1 /* $NetBSD: com.c,v 1.388 2025/02/12 05:15:39 imil Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Copyright (c) 1991 The Regents of the University of California.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. Neither the name of the University nor the names of its contributors
45 * may be used to endorse or promote products derived from this software
46 * without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
58 * SUCH DAMAGE.
59 *
60 * @(#)com.c 7.5 (Berkeley) 5/16/91
61 */
62
63 /*
64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART
65 * Supports automatic hardware flow control on StarTech ST16C650A UART
66 *
67 * Lock order:
68 * ttylock (IPL_VM)
69 * -> sc->sc_lock (IPL_HIGH)
70 * -> timecounter_lock (IPL_HIGH)
71 */
72
73 #include <sys/cdefs.h>
74 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.388 2025/02/12 05:15:39 imil Exp $");
75
76 #include "opt_com.h"
77 #include "opt_ddb.h"
78 #include "opt_kgdb.h"
79 #include "opt_lockdebug.h"
80 #include "opt_multiprocessor.h"
81 #include "opt_ntp.h"
82
83 /* The COM16650 option was renamed to COM_16650. */
84 #ifdef COM16650
85 #error Obsolete COM16650 option; use COM_16650 instead.
86 #endif
87
88 /*
89 * Override cnmagic(9) macro before including <sys/systm.h>.
90 * We need to know if cn_check_magic triggered debugger, so set a flag.
91 * Callers of cn_check_magic must declare int cn_trapped = 0;
92 * XXX: this is *ugly*!
93 */
94 #define cn_trap() \
95 do { \
96 console_debugger(); \
97 cn_trapped = 1; \
98 (void)cn_trapped; \
99 } while (/* CONSTCOND */ 0)
100
101 #include <sys/param.h>
102 #include <sys/systm.h>
103 #include <sys/ioctl.h>
104 #include <sys/select.h>
105 #include <sys/poll.h>
106 #include <sys/tty.h>
107 #include <sys/proc.h>
108 #include <sys/conf.h>
109 #include <sys/file.h>
110 #include <sys/uio.h>
111 #include <sys/kernel.h>
112 #include <sys/syslog.h>
113 #include <sys/device.h>
114 #include <sys/malloc.h>
115 #include <sys/timepps.h>
116 #include <sys/vnode.h>
117 #include <sys/kauth.h>
118 #include <sys/intr.h>
119 #ifdef RND_COM
120 #include <sys/rndsource.h>
121 #endif
122
123 #include <sys/bus.h>
124
125 #include <ddb/db_active.h>
126
127 #include <dev/ic/comreg.h>
128 #include <dev/ic/comvar.h>
129 #include <dev/ic/ns16550reg.h>
130 #include <dev/ic/st16650reg.h>
131 #include <dev/ic/hayespreg.h>
132 #define com_lcr com_cfcr
133 #include <dev/cons.h>
134
135 #include "ioconf.h"
136
137 #define CSR_READ_1(r, o) \
138 (r)->cr_read((r), (r)->cr_map[o])
139 #define CSR_WRITE_1(r, o, v) \
140 (r)->cr_write((r), (r)->cr_map[o], (v))
141 #define CSR_WRITE_MULTI(r, o, p, n) \
142 (r)->cr_write_multi((r), (r)->cr_map[o], (p), (n))
143
144 /*
145 * XXX COM_TYPE_AU1x00 specific
146 */
147 #define CSR_WRITE_2(r, o, v) \
148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v)
149 #define CSR_READ_2(r, o) \
150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o])
151
152 static void com_enable_debugport(struct com_softc *);
153
154 void com_config(struct com_softc *);
155 void com_shutdown(struct com_softc *);
156 int comspeed(long, long, int);
157 static u_char cflag2lcr(tcflag_t);
158 int comparam(struct tty *, struct termios *);
159 void comstart(struct tty *);
160 int comhwiflow(struct tty *, int);
161
162 void com_loadchannelregs(struct com_softc *);
163 void com_hwiflow(struct com_softc *);
164 void com_break(struct com_softc *, int);
165 void com_modem(struct com_softc *, int);
166 void tiocm_to_com(struct com_softc *, u_long, int);
167 int com_to_tiocm(struct com_softc *);
168 void com_iflush(struct com_softc *);
169
170 int com_common_getc(dev_t, struct com_regs *);
171 static void com_common_putc(dev_t, struct com_regs *, int, int);
172
173 int cominit(struct com_regs *, int, int, int, tcflag_t);
174
175 static int comcnreattach(void);
176
177 int comcngetc(dev_t);
178 void comcnputc(dev_t, int);
179 void comcnpollc(dev_t, int);
180
181 void comsoft(void *);
182 static inline void com_rxsoft(struct com_softc *, struct tty *);
183 static inline void com_txsoft(struct com_softc *, struct tty *);
184 static inline void com_stsoft(struct com_softc *, struct tty *);
185 static inline void com_schedrx(struct com_softc *);
186 void comdiag(void *);
187
188 dev_type_open(comopen);
189 dev_type_close(comclose);
190 dev_type_read(comread);
191 dev_type_write(comwrite);
192 dev_type_ioctl(comioctl);
193 dev_type_stop(comstop);
194 dev_type_tty(comtty);
195 dev_type_poll(compoll);
196
197 static struct comcons_info comcons_info;
198
199 /*
200 * Following are all routines needed for COM to act as console
201 */
202 static struct consdev comcons = {
203 .cn_getc = comcngetc,
204 .cn_putc = comcnputc,
205 .cn_pollc = comcnpollc,
206 .cn_dev = NODEV,
207 .cn_pri = CN_NORMAL
208 };
209
210
211 const struct cdevsw com_cdevsw = {
212 .d_open = comopen,
213 .d_close = comclose,
214 .d_read = comread,
215 .d_write = comwrite,
216 .d_ioctl = comioctl,
217 .d_stop = comstop,
218 .d_tty = comtty,
219 .d_poll = compoll,
220 .d_mmap = nommap,
221 .d_kqfilter = ttykqfilter,
222 .d_discard = nodiscard,
223 .d_flag = D_TTY
224 };
225
226 /*
227 * Make this an option variable one can patch.
228 * But be warned: this must be a power of 2!
229 */
230 u_int com_rbuf_size = COM_RING_SIZE;
231
232 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
233 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4;
234 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4;
235
236 static int comconsattached;
237 static struct cnm_state com_cnm_state;
238
239 #ifdef KGDB
240 #include <sys/kgdb.h>
241
242 static struct com_regs comkgdbregs;
243 static int com_kgdb_attached;
244
245 int com_kgdb_getc(void *);
246 void com_kgdb_putc(void *, int);
247 #endif /* KGDB */
248
249 /* initializer for typical 16550-ish hardware */
250 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = {
251 [COM_REG_RXDATA] = com_data,
252 [COM_REG_TXDATA] = com_data,
253 [COM_REG_DLBL] = com_dlbl,
254 [COM_REG_DLBH] = com_dlbh,
255 [COM_REG_IER] = com_ier,
256 [COM_REG_IIR] = com_iir,
257 [COM_REG_FIFO] = com_fifo,
258 [COM_REG_TCR] = com_fifo,
259 [COM_REG_EFR] = com_efr,
260 [COM_REG_TLR] = com_efr,
261 [COM_REG_LCR] = com_lcr,
262 [COM_REG_MCR] = com_mcr,
263 [COM_REG_LSR] = com_lsr,
264 [COM_REG_MSR] = com_msr,
265 [COM_REG_USR] = com_usr,
266 [COM_REG_TFL] = com_tfl,
267 [COM_REG_RFL] = com_rfl,
268 [COM_REG_HALT] = com_halt,
269 [COM_REG_MDR1] = com_mdr1,
270 };
271
272 #define COMDIALOUT_MASK TTDIALOUT_MASK
273
274 #define COMUNIT(x) TTUNIT(x)
275 #define COMDIALOUT(x) TTDIALOUT(x)
276
277 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \
278 device_is_active((sc)->sc_dev))
279
280 #define BR BUS_SPACE_BARRIER_READ
281 #define BW BUS_SPACE_BARRIER_WRITE
282 #define COM_BARRIER(r, f) \
283 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f))
284
285 /*
286 * com_read_1 --
287 * Default register read callback using single byte accesses.
288 */
289 static uint8_t
com_read_1(struct com_regs * regs,u_int reg)290 com_read_1(struct com_regs *regs, u_int reg)
291 {
292 return bus_space_read_1(regs->cr_iot, regs->cr_ioh, reg);
293 }
294
295 /*
296 * com_write_1 --
297 * Default register write callback using single byte accesses.
298 */
299 static void
com_write_1(struct com_regs * regs,u_int reg,uint8_t val)300 com_write_1(struct com_regs *regs, u_int reg, uint8_t val)
301 {
302 bus_space_write_1(regs->cr_iot, regs->cr_ioh, reg, val);
303 }
304
305 /*
306 * com_write_multi_1 --
307 * Default register multi write callback using single byte accesses.
308 */
309 static void
com_write_multi_1(struct com_regs * regs,u_int reg,const uint8_t * datap,bus_size_t count)310 com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap,
311 bus_size_t count)
312 {
313 bus_space_write_multi_1(regs->cr_iot, regs->cr_ioh, reg, datap, count);
314 }
315
316 /*
317 * com_read_4 --
318 * Default register read callback using dword accesses.
319 */
320 static uint8_t
com_read_4(struct com_regs * regs,u_int reg)321 com_read_4(struct com_regs *regs, u_int reg)
322 {
323 return bus_space_read_4(regs->cr_iot, regs->cr_ioh, reg) & 0xff;
324 }
325
326 /*
327 * com_write_4 --
328 * Default register write callback using dword accesses.
329 */
330 static void
com_write_4(struct com_regs * regs,u_int reg,uint8_t val)331 com_write_4(struct com_regs *regs, u_int reg, uint8_t val)
332 {
333 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, val);
334 }
335
336 /*
337 * com_write_multi_4 --
338 * Default register multi write callback using dword accesses.
339 */
340 static void
com_write_multi_4(struct com_regs * regs,u_int reg,const uint8_t * datap,bus_size_t count)341 com_write_multi_4(struct com_regs *regs, u_int reg, const uint8_t *datap,
342 bus_size_t count)
343 {
344 while (count-- > 0) {
345 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, *datap++);
346 }
347 }
348
349 /*
350 * com_init_regs --
351 * Driver front-ends use this to initialize our register map
352 * in the standard fashion. They may then tailor the map to
353 * their own particular requirements.
354 */
355 void
com_init_regs(struct com_regs * regs,bus_space_tag_t st,bus_space_handle_t sh,bus_addr_t addr)356 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh,
357 bus_addr_t addr)
358 {
359
360 memset(regs, 0, sizeof(*regs));
361 regs->cr_iot = st;
362 regs->cr_ioh = sh;
363 regs->cr_iobase = addr;
364 regs->cr_nports = COM_NPORTS;
365 regs->cr_read = com_read_1;
366 regs->cr_write = com_write_1;
367 regs->cr_write_multi = com_write_multi_1;
368 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map));
369 }
370
371 /*
372 * com_init_regs_stride --
373 * Convenience function for front-ends that have a stride between
374 * registers.
375 */
376 void
com_init_regs_stride(struct com_regs * regs,bus_space_tag_t st,bus_space_handle_t sh,bus_addr_t addr,u_int regshift)377 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st,
378 bus_space_handle_t sh, bus_addr_t addr, u_int regshift)
379 {
380
381 com_init_regs(regs, st, sh, addr);
382 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) {
383 regs->cr_map[i] <<= regshift;
384 }
385 regs->cr_nports <<= regshift;
386 }
387
388 /*
389 * com_init_regs_stride_width --
390 * Convenience function for front-ends that have a stride between
391 * registers and specific I/O width requirements.
392 */
393 void
com_init_regs_stride_width(struct com_regs * regs,bus_space_tag_t st,bus_space_handle_t sh,bus_addr_t addr,u_int regshift,u_int width)394 com_init_regs_stride_width(struct com_regs *regs, bus_space_tag_t st,
395 bus_space_handle_t sh, bus_addr_t addr,
396 u_int regshift, u_int width)
397 {
398
399 com_init_regs(regs, st, sh, addr);
400 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) {
401 regs->cr_map[i] <<= regshift;
402 }
403 regs->cr_nports <<= regshift;
404
405 switch (width) {
406 case 1:
407 /* Already set by com_init_regs */
408 break;
409 case 4:
410 regs->cr_read = com_read_4;
411 regs->cr_write = com_write_4;
412 regs->cr_write_multi = com_write_multi_4;
413 break;
414 default:
415 panic("com: unsupported I/O width %d", width);
416 }
417 }
418
419 /*ARGSUSED*/
420 int
comspeed(long speed,long frequency,int type)421 comspeed(long speed, long frequency, int type)
422 {
423 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
424
425 int x, err;
426 int divisor = 16;
427
428 if ((type == COM_TYPE_OMAP) && (speed > 230400)) {
429 divisor = 13;
430 }
431
432 if (speed == 0)
433 return (0);
434 if (speed < 0)
435 return (-1);
436 x = divrnd(frequency / divisor, speed);
437 if (x <= 0)
438 return (-1);
439 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000;
440 if (err < 0)
441 err = -err;
442 if (err > COM_TOLERANCE)
443 return (-1);
444 return (x);
445
446 #undef divrnd
447 }
448
449 #ifdef COM_DEBUG
450 int com_debug = 0;
451
452 void comstatus(struct com_softc *, const char *);
453 void
comstatus(struct com_softc * sc,const char * str)454 comstatus(struct com_softc *sc, const char *str)
455 {
456 struct tty *tp = sc->sc_tty;
457
458 aprint_normal_dev(sc->sc_dev,
459 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n",
460 str,
461 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-',
462 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-',
463 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-',
464 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-',
465 sc->sc_tx_stopped ? '+' : '-');
466
467 aprint_normal_dev(sc->sc_dev,
468 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n",
469 str,
470 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-',
471 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-',
472 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-',
473 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-',
474 sc->sc_rx_flags);
475 }
476 #endif
477
478 int
com_probe_subr(struct com_regs * regs)479 com_probe_subr(struct com_regs *regs)
480 {
481
482 /* force access to id reg */
483 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS);
484 CSR_WRITE_1(regs, COM_REG_IIR, 0);
485 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) ||
486 (CSR_READ_1(regs, COM_REG_IIR) & 0x38))
487 return (0);
488
489 return (1);
490 }
491
492 int
comprobe1(bus_space_tag_t iot,bus_space_handle_t ioh)493 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh)
494 {
495 struct com_regs regs;
496
497 com_init_regs(®s, iot, ioh, 0/*XXX*/);
498
499 return com_probe_subr(®s);
500 }
501
502 /*
503 * No locking in this routine; it is only called during attach,
504 * or with the port already locked.
505 */
506 static void
com_enable_debugport(struct com_softc * sc)507 com_enable_debugport(struct com_softc *sc)
508 {
509
510 /* Turn on line break interrupt, set carrier. */
511 sc->sc_ier = IER_ERLS;
512 if (sc->sc_type == COM_TYPE_PXA2x0)
513 sc->sc_ier |= IER_EUART | IER_ERXTOUT;
514 if (sc->sc_type == COM_TYPE_INGENIC ||
515 sc->sc_type == COM_TYPE_TEGRA)
516 sc->sc_ier |= IER_ERXTOUT;
517 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
518 SET(sc->sc_mcr, MCR_DTR | MCR_RTS);
519 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr);
520 }
521
522 static void
com_intr_poll(void * arg)523 com_intr_poll(void *arg)
524 {
525 struct com_softc * const sc = arg;
526
527 comintr(sc);
528
529 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks);
530 }
531
532 void
com_attach_subr(struct com_softc * sc)533 com_attach_subr(struct com_softc *sc)
534 {
535 struct com_regs *regsp = &sc->sc_regs;
536 struct tty *tp;
537 uint32_t cpr;
538 uint8_t lcr;
539 const char *fifo_msg = NULL;
540 prop_dictionary_t dict;
541 bool is_console = true;
542 bool force_console = false;
543 bool skip_attach_delay = false;
544
545 aprint_naive("\n");
546
547 dict = device_properties(sc->sc_dev);
548 prop_dictionary_get_bool(dict, "is_console", &is_console);
549 prop_dictionary_get_bool(dict, "force_console", &force_console);
550 prop_dictionary_get_bool(dict, "skip_attach_delay", &skip_attach_delay);
551 callout_init(&sc->sc_diag_callout, 0);
552 callout_init(&sc->sc_poll_callout, 0);
553 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc);
554 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
555
556 #if defined(COM_16650)
557 sc->sc_type = COM_TYPE_16650;
558 #elif defined(COM_16750)
559 sc->sc_type = COM_TYPE_16750;
560 #elif defined(COM_HAYESP)
561 sc->sc_type = COM_TYPE_HAYESP;
562 #elif defined(COM_PXA2X0)
563 sc->sc_type = COM_TYPE_PXA2x0;
564 #endif
565
566 /* Disable interrupts before configuring the device. */
567 if (sc->sc_type == COM_TYPE_PXA2x0)
568 sc->sc_ier = IER_EUART;
569 else
570 sc->sc_ier = 0;
571
572 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
573
574 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) &&
575 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) {
576 comconsattached = 1;
577
578 if (force_console)
579 memcpy(regsp, &comcons_info.regs, sizeof(*regsp));
580
581 if (cn_tab == NULL && comcnreattach() != 0) {
582 printf("can't re-init serial console @%lx\n",
583 (u_long)comcons_info.regs.cr_iobase);
584 }
585
586 switch (sc->sc_type) {
587 case COM_TYPE_16750:
588 case COM_TYPE_DW_APB:
589 /* Use in comintr(). */
590 sc->sc_lcr = cflag2lcr(comcons_info.cflag);
591 break;
592 }
593
594 /* No need for a delay on virtual machines. */
595 if (!skip_attach_delay)
596 delay(10000); /* wait for output to finish */
597
598 /* Make sure the console is always "hardwired". */
599 if (is_console) {
600 SET(sc->sc_hwflags, COM_HW_CONSOLE);
601 }
602
603 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
604 }
605
606 /* Probe for FIFO */
607 switch (sc->sc_type) {
608 case COM_TYPE_HAYESP:
609 goto fifodone;
610
611 case COM_TYPE_AU1x00:
612 sc->sc_fifolen = 16;
613 fifo_msg = "Au1X00 UART";
614 SET(sc->sc_hwflags, COM_HW_FIFO);
615 goto fifodelay;
616
617 case COM_TYPE_16550_NOERS:
618 sc->sc_fifolen = 16;
619 fifo_msg = "ns16650, no ERS";
620 SET(sc->sc_hwflags, COM_HW_FIFO);
621 goto fifodelay;
622
623 case COM_TYPE_OMAP:
624 sc->sc_fifolen = 64;
625 fifo_msg = "OMAP UART";
626 SET(sc->sc_hwflags, COM_HW_FIFO);
627 goto fifodelay;
628
629 case COM_TYPE_INGENIC:
630 sc->sc_fifolen = 16;
631 fifo_msg = "Ingenic UART";
632 SET(sc->sc_hwflags, COM_HW_FIFO);
633 SET(sc->sc_hwflags, COM_HW_NOIEN);
634 goto fifodelay;
635
636 case COM_TYPE_TEGRA:
637 sc->sc_fifolen = 8;
638 fifo_msg = "Tegra UART";
639 SET(sc->sc_hwflags, COM_HW_FIFO);
640 CSR_WRITE_1(regsp, COM_REG_FIFO,
641 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
642 goto fifodelay;
643
644 case COM_TYPE_BCMAUXUART:
645 sc->sc_fifolen = 1;
646 fifo_msg = "BCM AUX UART";
647 SET(sc->sc_hwflags, COM_HW_FIFO);
648 CSR_WRITE_1(regsp, COM_REG_FIFO,
649 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
650 goto fifodelay;
651
652 case COM_TYPE_DW_APB:
653 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) {
654 cpr = bus_space_read_4(sc->sc_regs.cr_iot,
655 sc->sc_regs.cr_ioh, DW_APB_UART_CPR);
656 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16;
657 }
658 if (sc->sc_fifolen == 0) {
659 sc->sc_fifolen = 1;
660 fifo_msg = "DesignWare APB UART, no fifo";
661 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
662 } else {
663 fifo_msg = "DesignWare APB UART";
664 SET(sc->sc_hwflags, COM_HW_FIFO);
665 CSR_WRITE_1(regsp, COM_REG_FIFO,
666 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
667 }
668 goto fifodelay;
669 }
670
671 sc->sc_fifolen = 1;
672 /* look for a NS 16550AF UART with FIFOs */
673 if (sc->sc_type == COM_TYPE_INGENIC) {
674 CSR_WRITE_1(regsp, COM_REG_FIFO,
675 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
676 FIFO_TRIGGER_14 | FIFO_UART_ON);
677 } else
678 CSR_WRITE_1(regsp, COM_REG_FIFO,
679 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
680 delay(100);
681 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)
682 == IIR_FIFO_MASK)
683 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14)
684 == FIFO_TRIGGER_14) {
685 SET(sc->sc_hwflags, COM_HW_FIFO);
686
687 fifo_msg = "ns16550a";
688 sc->sc_fifolen = 16;
689
690 /*
691 * IIR changes into the EFR if LCR is set to LCR_EERS
692 * on 16650s. We also know IIR != 0 at this point.
693 * Write 0 into the EFR, and read it. If the result
694 * is 0, we have a 16650.
695 *
696 * Older 16650s were broken; the test to detect them
697 * is taken from the Linux driver. Apparently
698 * setting DLAB enable gives access to the EFR on
699 * these chips.
700 */
701 if (sc->sc_type == COM_TYPE_16650) {
702 lcr = CSR_READ_1(regsp, COM_REG_LCR);
703 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
704 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
705 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
706 CSR_WRITE_1(regsp, COM_REG_LCR,
707 lcr | LCR_DLAB);
708 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
709 CLR(sc->sc_hwflags, COM_HW_FIFO);
710 sc->sc_fifolen = 0;
711 } else {
712 SET(sc->sc_hwflags, COM_HW_FLOW);
713 sc->sc_fifolen = 32;
714 }
715 } else
716 sc->sc_fifolen = 16;
717
718 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
719 if (sc->sc_fifolen == 0)
720 fifo_msg = "st16650, broken fifo";
721 else if (sc->sc_fifolen == 32)
722 fifo_msg = "st16650a";
723 else
724 fifo_msg = "ns16550a";
725 }
726
727 /*
728 * TL16C750 can enable 64byte FIFO, only when DLAB
729 * is 1. However, some 16750 may always enable. For
730 * example, restrictions according to DLAB in a data
731 * sheet for SC16C750 were not described.
732 * Please enable 'options COM_16650', supposing you
733 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW
734 * should become effective.
735 */
736 if (sc->sc_type == COM_TYPE_16750) {
737 uint8_t iir1, iir2;
738 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14;
739
740 lcr = CSR_READ_1(regsp, COM_REG_LCR);
741 CSR_WRITE_1(regsp, COM_REG_LCR,
742 lcr & ~LCR_DLAB);
743 CSR_WRITE_1(regsp, COM_REG_FIFO,
744 fcr | FIFO_64B_ENABLE);
745 iir1 = CSR_READ_1(regsp, COM_REG_IIR);
746 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
747 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
748 CSR_WRITE_1(regsp, COM_REG_FIFO,
749 fcr | FIFO_64B_ENABLE);
750 iir2 = CSR_READ_1(regsp, COM_REG_IIR);
751
752 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
753
754 if (!ISSET(iir1, IIR_64B_FIFO) &&
755 ISSET(iir2, IIR_64B_FIFO)) {
756 /* It is TL16C750. */
757 sc->sc_fifolen = 64;
758 SET(sc->sc_hwflags, COM_HW_AFE);
759 } else
760 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
761
762 if (sc->sc_fifolen == 64)
763 fifo_msg = "tl16c750";
764 else
765 fifo_msg = "ns16750";
766 }
767 } else
768 fifo_msg = "ns16550, broken fifo";
769 else
770 fifo_msg = "ns8250 or ns16450, no fifo";
771 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
772
773 fifodelay:
774 /*
775 * Some chips will clear down both Tx and Rx FIFOs when zero is
776 * written to com_fifo. If this chip is the console, writing zero
777 * results in some of the chip/FIFO description being lost, so delay
778 * printing it until now.
779 */
780 delay(10);
781 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) {
782 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen);
783 } else {
784 aprint_normal(": %s\n", fifo_msg);
785 }
786 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) {
787 sc->sc_fifolen = 1;
788 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n");
789 }
790
791 fifodone:
792
793 tp = tty_alloc();
794 tp->t_oproc = comstart;
795 tp->t_param = comparam;
796 tp->t_hwiflow = comhwiflow;
797 tp->t_softc = sc;
798
799 sc->sc_tty = tp;
800 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK);
801 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
802 sc->sc_rbavail = com_rbuf_size;
803 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1);
804
805 tty_attach(tp);
806
807 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
808 SET(sc->sc_mcr, MCR_IENABLE);
809
810 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
811 int maj;
812
813 /* locate the major number */
814 maj = cdevsw_lookup_major(&com_cdevsw);
815
816 tp->t_dev = cn_tab->cn_dev = makedev(maj,
817 device_unit(sc->sc_dev));
818
819 aprint_normal_dev(sc->sc_dev, "console\n");
820 }
821
822 #ifdef KGDB
823 /*
824 * Allow kgdb to "take over" this port. If this is
825 * not the console and is the kgdb device, it has
826 * exclusive use. If it's the console _and_ the
827 * kgdb device, it doesn't.
828 */
829 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) &&
830 regsp->cr_iobase == comkgdbregs.cr_iobase) {
831 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
832 com_kgdb_attached = 1;
833
834 SET(sc->sc_hwflags, COM_HW_KGDB);
835 }
836 aprint_normal_dev(sc->sc_dev, "kgdb\n");
837 }
838 #endif
839
840 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc);
841
842 #ifdef RND_COM
843 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
844 RND_TYPE_TTY, RND_FLAG_DEFAULT);
845 #endif
846
847 /* if there are no enable/disable functions, assume the device
848 is always enabled */
849 if (!sc->enable)
850 sc->enabled = 1;
851
852 com_config(sc);
853
854 SET(sc->sc_hwflags, COM_HW_DEV_OK);
855
856 if (sc->sc_poll_ticks != 0)
857 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks);
858 }
859
860 void
com_config(struct com_softc * sc)861 com_config(struct com_softc *sc)
862 {
863 struct com_regs *regsp = &sc->sc_regs;
864
865 /* Disable interrupts before configuring the device. */
866 if (sc->sc_type == COM_TYPE_PXA2x0)
867 sc->sc_ier = IER_EUART;
868 else
869 sc->sc_ier = 0;
870 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
871 (void) CSR_READ_1(regsp, COM_REG_IIR);
872
873 /* Look for a Hayes ESP board. */
874 if (sc->sc_type == COM_TYPE_HAYESP) {
875
876 /* Set 16550 compatibility mode */
877 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
878 HAYESP_SETMODE);
879 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
880 HAYESP_MODE_FIFO|HAYESP_MODE_RTS|
881 HAYESP_MODE_SCALE);
882
883 /* Set RTS/CTS flow control */
884 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
885 HAYESP_SETFLOWTYPE);
886 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
887 HAYESP_FLOW_RTS);
888 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
889 HAYESP_FLOW_CTS);
890
891 /* Set flow control levels */
892 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
893 HAYESP_SETRXFLOW);
894 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
895 HAYESP_HIBYTE(HAYESP_RXHIWMARK));
896 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
897 HAYESP_LOBYTE(HAYESP_RXHIWMARK));
898 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
899 HAYESP_HIBYTE(HAYESP_RXLOWMARK));
900 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
901 HAYESP_LOBYTE(HAYESP_RXLOWMARK));
902 }
903
904 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB))
905 com_enable_debugport(sc);
906 }
907
908 int
com_detach(device_t self,int flags)909 com_detach(device_t self, int flags)
910 {
911 struct com_softc *sc = device_private(self);
912 int maj, mn;
913
914 if (ISSET(sc->sc_hwflags, COM_HW_KGDB))
915 return EBUSY;
916
917 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) &&
918 (flags & DETACH_SHUTDOWN) != 0)
919 return EBUSY;
920
921 if (sc->disable != NULL && sc->enabled != 0) {
922 (*sc->disable)(sc);
923 sc->enabled = 0;
924 }
925
926 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
927 comconsattached = 0;
928 cn_tab = NULL;
929 }
930
931 /* locate the major number */
932 maj = cdevsw_lookup_major(&com_cdevsw);
933
934 /* Nuke the vnodes for any open instances. */
935 mn = device_unit(self);
936 vdevgone(maj, mn, mn, VCHR);
937
938 mn |= COMDIALOUT_MASK;
939 vdevgone(maj, mn, mn, VCHR);
940
941 if (sc->sc_rbuf == NULL) {
942 /*
943 * Ring buffer allocation failed in the com_attach_subr,
944 * only the tty is allocated, and nothing else.
945 */
946 tty_free(sc->sc_tty);
947 return 0;
948 }
949
950 /* Free the receive buffer. */
951 free(sc->sc_rbuf, M_DEVBUF);
952
953 /* Detach and free the tty. */
954 tty_detach(sc->sc_tty);
955 tty_free(sc->sc_tty);
956
957 /* Unhook the soft interrupt handler. */
958 softint_disestablish(sc->sc_si);
959
960 #ifdef RND_COM
961 /* Unhook the entropy source. */
962 rnd_detach_source(&sc->rnd_source);
963 #endif
964 callout_destroy(&sc->sc_diag_callout);
965
966 /* Destroy the lock. */
967 mutex_destroy(&sc->sc_lock);
968
969 return (0);
970 }
971
972 void
com_shutdown(struct com_softc * sc)973 com_shutdown(struct com_softc *sc)
974 {
975 struct tty *tp = sc->sc_tty;
976
977 mutex_spin_enter(&sc->sc_lock);
978
979 /* If we were asserting flow control, then deassert it. */
980 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
981 com_hwiflow(sc);
982
983 /* Clear any break condition set with TIOCSBRK. */
984 com_break(sc, 0);
985
986 /*
987 * Hang up if necessary. Record when we hung up, so if we
988 * immediately open the port again, we will wait a bit until
989 * the other side has had time to notice that we hung up.
990 */
991 if (ISSET(tp->t_cflag, HUPCL)) {
992 com_modem(sc, 0);
993 microuptime(&sc->sc_hup_pending);
994 sc->sc_hup_pending.tv_sec++;
995 }
996
997 /* Turn off interrupts. */
998 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
999 sc->sc_ier = IER_ERLS; /* interrupt on line break */
1000 if ((sc->sc_type == COM_TYPE_PXA2x0) ||
1001 (sc->sc_type == COM_TYPE_INGENIC) ||
1002 (sc->sc_type == COM_TYPE_TEGRA))
1003 sc->sc_ier |= IER_ERXTOUT;
1004 } else
1005 sc->sc_ier = 0;
1006
1007 if (sc->sc_type == COM_TYPE_PXA2x0)
1008 sc->sc_ier |= IER_EUART;
1009
1010 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
1011
1012 mutex_spin_exit(&sc->sc_lock);
1013
1014 if (sc->disable) {
1015 #ifdef DIAGNOSTIC
1016 if (!sc->enabled)
1017 panic("com_shutdown: not enabled?");
1018 #endif
1019 (*sc->disable)(sc);
1020 sc->enabled = 0;
1021 }
1022 }
1023
1024 int
comopen(dev_t dev,int flag,int mode,struct lwp * l)1025 comopen(dev_t dev, int flag, int mode, struct lwp *l)
1026 {
1027 struct com_softc *sc;
1028 struct tty *tp;
1029 int s;
1030 int error;
1031
1032 sc = device_lookup_private(&com_cd, COMUNIT(dev));
1033 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) ||
1034 sc->sc_rbuf == NULL)
1035 return (ENXIO);
1036
1037 if (!device_is_active(sc->sc_dev))
1038 return (ENXIO);
1039
1040 #ifdef KGDB
1041 /*
1042 * If this is the kgdb port, no other use is permitted.
1043 */
1044 if (ISSET(sc->sc_hwflags, COM_HW_KGDB))
1045 return (EBUSY);
1046 #endif
1047
1048 tp = sc->sc_tty;
1049
1050 /*
1051 * If the device is exclusively for kernel use, deny userland
1052 * open.
1053 */
1054 if (ISSET(tp->t_state, TS_KERN_ONLY))
1055 return (EBUSY);
1056
1057 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
1058 return (EBUSY);
1059
1060 s = spltty();
1061
1062 /*
1063 * Do the following iff this is a first open.
1064 */
1065 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
1066 struct termios t;
1067 struct timeval now, diff;
1068
1069 tp->t_dev = dev;
1070
1071 if (sc->enable) {
1072 if ((*sc->enable)(sc)) {
1073 splx(s);
1074 aprint_error_dev(sc->sc_dev,
1075 "device enable failed\n");
1076 return (EIO);
1077 }
1078 mutex_spin_enter(&sc->sc_lock);
1079 sc->enabled = 1;
1080 com_config(sc);
1081 } else {
1082 mutex_spin_enter(&sc->sc_lock);
1083 }
1084
1085 if (timerisset(&sc->sc_hup_pending)) {
1086 microuptime(&now);
1087 while (timercmp(&now, &sc->sc_hup_pending, <)) {
1088 timersub(&sc->sc_hup_pending, &now, &diff);
1089 const int ms = diff.tv_sec * 1000 +
1090 diff.tv_usec / 1000;
1091 kpause(ttclos, false, uimax(mstohz(ms), 1),
1092 &sc->sc_lock);
1093 microuptime(&now);
1094 }
1095 timerclear(&sc->sc_hup_pending);
1096 }
1097
1098 /* Turn on interrupts. */
1099 sc->sc_ier = IER_ERXRDY | IER_ERLS;
1100 if (!ISSET(tp->t_cflag, CLOCAL))
1101 sc->sc_ier |= IER_EMSC;
1102
1103 if (sc->sc_type == COM_TYPE_PXA2x0)
1104 sc->sc_ier |= IER_EUART | IER_ERXTOUT;
1105 else if (sc->sc_type == COM_TYPE_INGENIC ||
1106 sc->sc_type == COM_TYPE_TEGRA)
1107 sc->sc_ier |= IER_ERXTOUT;
1108 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
1109
1110 /* Fetch the current modem control status, needed later. */
1111 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR);
1112
1113 /* Clear PPS capture state on first open. */
1114 mutex_spin_enter(&timecounter_lock);
1115 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state));
1116 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1117 pps_init(&sc->sc_pps_state);
1118 mutex_spin_exit(&timecounter_lock);
1119
1120 mutex_spin_exit(&sc->sc_lock);
1121
1122 /*
1123 * Initialize the termios status to the defaults. Add in the
1124 * sticky bits from TIOCSFLAGS.
1125 */
1126 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
1127 t.c_ospeed = comcons_info.rate;
1128 t.c_cflag = comcons_info.cflag;
1129 } else {
1130 t.c_ospeed = TTYDEF_SPEED;
1131 t.c_cflag = TTYDEF_CFLAG;
1132 }
1133 t.c_ispeed = t.c_ospeed;
1134 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
1135 SET(t.c_cflag, CLOCAL);
1136 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
1137 SET(t.c_cflag, CRTSCTS);
1138 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
1139 SET(t.c_cflag, MDMBUF);
1140 /* Make sure comparam() will do something. */
1141 tp->t_ospeed = 0;
1142 (void) comparam(tp, &t);
1143 tp->t_iflag = TTYDEF_IFLAG;
1144 tp->t_oflag = TTYDEF_OFLAG;
1145 tp->t_lflag = TTYDEF_LFLAG;
1146 ttychars(tp);
1147 ttsetwater(tp);
1148
1149 mutex_spin_enter(&sc->sc_lock);
1150
1151 /*
1152 * Turn on DTR. We must always do this, even if carrier is not
1153 * present, because otherwise we'd have to use TIOCSDTR
1154 * immediately after setting CLOCAL, which applications do not
1155 * expect. We always assert DTR while the device is open
1156 * unless explicitly requested to deassert it.
1157 */
1158 com_modem(sc, 1);
1159
1160 /* Clear the input ring, and unblock. */
1161 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
1162 sc->sc_rbavail = com_rbuf_size;
1163 com_iflush(sc);
1164 CLR(sc->sc_rx_flags, RX_ANY_BLOCK);
1165 com_hwiflow(sc);
1166
1167 #ifdef COM_DEBUG
1168 if (com_debug)
1169 comstatus(sc, "comopen ");
1170 #endif
1171
1172 mutex_spin_exit(&sc->sc_lock);
1173 }
1174
1175 splx(s);
1176
1177 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK));
1178 if (error)
1179 goto bad;
1180
1181 error = (*tp->t_linesw->l_open)(dev, tp);
1182 if (error)
1183 goto bad;
1184
1185 return (0);
1186
1187 bad:
1188 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
1189 /*
1190 * We failed to open the device, and nobody else had it opened.
1191 * Clean up the state as appropriate.
1192 */
1193 com_shutdown(sc);
1194 }
1195
1196 return (error);
1197 }
1198
1199 int
comclose(dev_t dev,int flag,int mode,struct lwp * l)1200 comclose(dev_t dev, int flag, int mode, struct lwp *l)
1201 {
1202 struct com_softc *sc =
1203 device_lookup_private(&com_cd, COMUNIT(dev));
1204 struct tty *tp = sc->sc_tty;
1205
1206 /* XXX This is for cons.c. */
1207 if (!ISSET(tp->t_state, TS_ISOPEN))
1208 return (0);
1209 /*
1210 * If the device is exclusively for kernel use, deny userland
1211 * close.
1212 */
1213 if (ISSET(tp->t_state, TS_KERN_ONLY))
1214 return (0);
1215
1216 (*tp->t_linesw->l_close)(tp, flag);
1217 ttyclose(tp);
1218
1219 if (COM_ISALIVE(sc) == 0)
1220 return (0);
1221
1222 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
1223 /*
1224 * Although we got a last close, the device may still be in
1225 * use; e.g. if this was the dialout node, and there are still
1226 * processes waiting for carrier on the non-dialout node.
1227 */
1228 com_shutdown(sc);
1229 }
1230
1231 return (0);
1232 }
1233
1234 int
comread(dev_t dev,struct uio * uio,int flag)1235 comread(dev_t dev, struct uio *uio, int flag)
1236 {
1237 struct com_softc *sc =
1238 device_lookup_private(&com_cd, COMUNIT(dev));
1239 struct tty *tp = sc->sc_tty;
1240
1241 if (COM_ISALIVE(sc) == 0)
1242 return (EIO);
1243
1244 return ((*tp->t_linesw->l_read)(tp, uio, flag));
1245 }
1246
1247 int
comwrite(dev_t dev,struct uio * uio,int flag)1248 comwrite(dev_t dev, struct uio *uio, int flag)
1249 {
1250 struct com_softc *sc =
1251 device_lookup_private(&com_cd, COMUNIT(dev));
1252 struct tty *tp = sc->sc_tty;
1253
1254 if (COM_ISALIVE(sc) == 0)
1255 return (EIO);
1256
1257 return ((*tp->t_linesw->l_write)(tp, uio, flag));
1258 }
1259
1260 int
compoll(dev_t dev,int events,struct lwp * l)1261 compoll(dev_t dev, int events, struct lwp *l)
1262 {
1263 struct com_softc *sc =
1264 device_lookup_private(&com_cd, COMUNIT(dev));
1265 struct tty *tp = sc->sc_tty;
1266
1267 if (COM_ISALIVE(sc) == 0)
1268 return (POLLHUP);
1269
1270 return ((*tp->t_linesw->l_poll)(tp, events, l));
1271 }
1272
1273 struct tty *
comtty(dev_t dev)1274 comtty(dev_t dev)
1275 {
1276 struct com_softc *sc =
1277 device_lookup_private(&com_cd, COMUNIT(dev));
1278 struct tty *tp = sc->sc_tty;
1279
1280 return (tp);
1281 }
1282
1283 int
comioctl(dev_t dev,u_long cmd,void * data,int flag,struct lwp * l)1284 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
1285 {
1286 struct com_softc *sc;
1287 struct tty *tp;
1288 int error;
1289
1290 sc = device_lookup_private(&com_cd, COMUNIT(dev));
1291 if (sc == NULL)
1292 return ENXIO;
1293 if (COM_ISALIVE(sc) == 0)
1294 return (EIO);
1295
1296 tp = sc->sc_tty;
1297
1298 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
1299 if (error != EPASSTHROUGH)
1300 return (error);
1301
1302 error = ttioctl(tp, cmd, data, flag, l);
1303 if (error != EPASSTHROUGH)
1304 return (error);
1305
1306 error = 0;
1307 switch (cmd) {
1308 case TIOCSFLAGS:
1309 error = kauth_authorize_device_tty(l->l_cred,
1310 KAUTH_DEVICE_TTY_PRIVSET, tp);
1311 break;
1312 default:
1313 /* nothing */
1314 break;
1315 }
1316 if (error) {
1317 return error;
1318 }
1319
1320 mutex_spin_enter(&sc->sc_lock);
1321
1322 switch (cmd) {
1323 case TIOCSBRK:
1324 com_break(sc, 1);
1325 break;
1326
1327 case TIOCCBRK:
1328 com_break(sc, 0);
1329 break;
1330
1331 case TIOCSDTR:
1332 com_modem(sc, 1);
1333 break;
1334
1335 case TIOCCDTR:
1336 com_modem(sc, 0);
1337 break;
1338
1339 case TIOCGFLAGS:
1340 *(int *)data = sc->sc_swflags;
1341 break;
1342
1343 case TIOCSFLAGS:
1344 sc->sc_swflags = *(int *)data;
1345 break;
1346
1347 case TIOCMSET:
1348 case TIOCMBIS:
1349 case TIOCMBIC:
1350 tiocm_to_com(sc, cmd, *(int *)data);
1351 break;
1352
1353 case TIOCMGET:
1354 *(int *)data = com_to_tiocm(sc);
1355 break;
1356
1357 case PPS_IOC_CREATE:
1358 case PPS_IOC_DESTROY:
1359 case PPS_IOC_GETPARAMS:
1360 case PPS_IOC_SETPARAMS:
1361 case PPS_IOC_GETCAP:
1362 case PPS_IOC_FETCH:
1363 #ifdef PPS_SYNC
1364 case PPS_IOC_KCBIND:
1365 #endif
1366 mutex_spin_enter(&timecounter_lock);
1367 error = pps_ioctl(cmd, data, &sc->sc_pps_state);
1368 mutex_spin_exit(&timecounter_lock);
1369 break;
1370
1371 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */
1372 mutex_spin_enter(&timecounter_lock);
1373 #ifndef PPS_TRAILING_EDGE
1374 TIMESPEC_TO_TIMEVAL((struct timeval *)data,
1375 &sc->sc_pps_state.ppsinfo.assert_timestamp);
1376 #else
1377 TIMESPEC_TO_TIMEVAL((struct timeval *)data,
1378 &sc->sc_pps_state.ppsinfo.clear_timestamp);
1379 #endif
1380 mutex_spin_exit(&timecounter_lock);
1381 break;
1382
1383 default:
1384 error = EPASSTHROUGH;
1385 break;
1386 }
1387
1388 mutex_spin_exit(&sc->sc_lock);
1389
1390 #ifdef COM_DEBUG
1391 if (com_debug)
1392 comstatus(sc, "comioctl ");
1393 #endif
1394
1395 return (error);
1396 }
1397
1398 static inline void
com_schedrx(struct com_softc * sc)1399 com_schedrx(struct com_softc *sc)
1400 {
1401
1402 sc->sc_rx_ready = 1;
1403
1404 /* Wake up the poller. */
1405 softint_schedule(sc->sc_si);
1406 }
1407
1408 void
com_break(struct com_softc * sc,int onoff)1409 com_break(struct com_softc *sc, int onoff)
1410 {
1411
1412 if (onoff)
1413 SET(sc->sc_lcr, LCR_SBREAK);
1414 else
1415 CLR(sc->sc_lcr, LCR_SBREAK);
1416
1417 if (!sc->sc_heldchange) {
1418 if (sc->sc_tx_busy) {
1419 sc->sc_heldtbc = sc->sc_tbc;
1420 sc->sc_tbc = 0;
1421 sc->sc_heldchange = 1;
1422 } else
1423 com_loadchannelregs(sc);
1424 }
1425 }
1426
1427 void
com_modem(struct com_softc * sc,int onoff)1428 com_modem(struct com_softc *sc, int onoff)
1429 {
1430
1431 if (sc->sc_mcr_dtr == 0)
1432 return;
1433
1434 if (onoff)
1435 SET(sc->sc_mcr, sc->sc_mcr_dtr);
1436 else
1437 CLR(sc->sc_mcr, sc->sc_mcr_dtr);
1438
1439 if (!sc->sc_heldchange) {
1440 if (sc->sc_tx_busy) {
1441 sc->sc_heldtbc = sc->sc_tbc;
1442 sc->sc_tbc = 0;
1443 sc->sc_heldchange = 1;
1444 } else
1445 com_loadchannelregs(sc);
1446 }
1447 }
1448
1449 void
tiocm_to_com(struct com_softc * sc,u_long how,int ttybits)1450 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits)
1451 {
1452 u_char combits;
1453
1454 combits = 0;
1455 if (ISSET(ttybits, TIOCM_DTR))
1456 SET(combits, MCR_DTR);
1457 if (ISSET(ttybits, TIOCM_RTS))
1458 SET(combits, MCR_RTS);
1459
1460 switch (how) {
1461 case TIOCMBIC:
1462 CLR(sc->sc_mcr, combits);
1463 break;
1464
1465 case TIOCMBIS:
1466 SET(sc->sc_mcr, combits);
1467 break;
1468
1469 case TIOCMSET:
1470 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
1471 SET(sc->sc_mcr, combits);
1472 break;
1473 }
1474
1475 if (!sc->sc_heldchange) {
1476 if (sc->sc_tx_busy) {
1477 sc->sc_heldtbc = sc->sc_tbc;
1478 sc->sc_tbc = 0;
1479 sc->sc_heldchange = 1;
1480 } else
1481 com_loadchannelregs(sc);
1482 }
1483 }
1484
1485 int
com_to_tiocm(struct com_softc * sc)1486 com_to_tiocm(struct com_softc *sc)
1487 {
1488 u_char combits;
1489 int ttybits = 0;
1490
1491 combits = sc->sc_mcr;
1492 if (ISSET(combits, MCR_DTR))
1493 SET(ttybits, TIOCM_DTR);
1494 if (ISSET(combits, MCR_RTS))
1495 SET(ttybits, TIOCM_RTS);
1496
1497 combits = sc->sc_msr;
1498 if (sc->sc_type == COM_TYPE_INGENIC) {
1499 SET(ttybits, TIOCM_CD);
1500 } else {
1501 if (ISSET(combits, MSR_DCD))
1502 SET(ttybits, TIOCM_CD);
1503 }
1504 if (ISSET(combits, MSR_CTS))
1505 SET(ttybits, TIOCM_CTS);
1506 if (ISSET(combits, MSR_DSR))
1507 SET(ttybits, TIOCM_DSR);
1508 if (ISSET(combits, MSR_RI | MSR_TERI))
1509 SET(ttybits, TIOCM_RI);
1510
1511 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC))
1512 SET(ttybits, TIOCM_LE);
1513
1514 return (ttybits);
1515 }
1516
1517 static u_char
cflag2lcr(tcflag_t cflag)1518 cflag2lcr(tcflag_t cflag)
1519 {
1520 u_char lcr = 0;
1521
1522 switch (ISSET(cflag, CSIZE)) {
1523 case CS5:
1524 SET(lcr, LCR_5BITS);
1525 break;
1526 case CS6:
1527 SET(lcr, LCR_6BITS);
1528 break;
1529 case CS7:
1530 SET(lcr, LCR_7BITS);
1531 break;
1532 case CS8:
1533 SET(lcr, LCR_8BITS);
1534 break;
1535 }
1536 if (ISSET(cflag, PARENB)) {
1537 SET(lcr, LCR_PENAB);
1538 if (!ISSET(cflag, PARODD))
1539 SET(lcr, LCR_PEVEN);
1540 }
1541 if (ISSET(cflag, CSTOPB))
1542 SET(lcr, LCR_STOPB);
1543
1544 return (lcr);
1545 }
1546
1547 int
comparam(struct tty * tp,struct termios * t)1548 comparam(struct tty *tp, struct termios *t)
1549 {
1550 struct com_softc *sc =
1551 device_lookup_private(&com_cd, COMUNIT(tp->t_dev));
1552 int ospeed;
1553 u_char lcr;
1554
1555 if (COM_ISALIVE(sc) == 0)
1556 return (EIO);
1557
1558 if (sc->sc_type == COM_TYPE_HAYESP) {
1559 int prescaler, speed;
1560
1561 /*
1562 * Calculate UART clock prescaler. It should be in
1563 * range of 0 .. 3.
1564 */
1565 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4;
1566 prescaler++, speed /= 2)
1567 if ((ospeed = comspeed(speed, sc->sc_frequency,
1568 sc->sc_type)) > 0)
1569 break;
1570
1571 if (prescaler == 4)
1572 return (EINVAL);
1573 sc->sc_prescaler = prescaler;
1574 } else
1575 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type);
1576
1577 /* Check requested parameters. */
1578 if (ospeed < 0)
1579 return (EINVAL);
1580 if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
1581 return (EINVAL);
1582
1583 /*
1584 * For the console, always force CLOCAL and !HUPCL, so that the port
1585 * is always active.
1586 */
1587 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
1588 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
1589 SET(t->c_cflag, CLOCAL);
1590 CLR(t->c_cflag, HUPCL);
1591 }
1592
1593 /*
1594 * If there were no changes, don't do anything. This avoids dropping
1595 * input and improves performance when all we did was frob things like
1596 * VMIN and VTIME.
1597 */
1598 if (tp->t_ospeed == t->c_ospeed &&
1599 tp->t_cflag == t->c_cflag)
1600 return (0);
1601
1602 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag);
1603
1604 mutex_spin_enter(&sc->sc_lock);
1605
1606 sc->sc_lcr = lcr;
1607
1608 /*
1609 * If we're not in a mode that assumes a connection is present, then
1610 * ignore carrier changes.
1611 */
1612 if (ISSET(t->c_cflag, CLOCAL | MDMBUF))
1613 sc->sc_msr_dcd = 0;
1614 else
1615 sc->sc_msr_dcd = MSR_DCD;
1616 /*
1617 * Set the flow control pins depending on the current flow control
1618 * mode.
1619 */
1620 if (ISSET(t->c_cflag, CRTSCTS)) {
1621 sc->sc_mcr_dtr = MCR_DTR;
1622 sc->sc_mcr_rts = MCR_RTS;
1623 sc->sc_msr_cts = MSR_CTS;
1624 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) {
1625 SET(sc->sc_mcr, MCR_AFE);
1626 } else {
1627 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS;
1628 }
1629 } else if (ISSET(t->c_cflag, MDMBUF)) {
1630 /*
1631 * For DTR/DCD flow control, make sure we don't toggle DTR for
1632 * carrier detection.
1633 */
1634 sc->sc_mcr_dtr = 0;
1635 sc->sc_mcr_rts = MCR_DTR;
1636 sc->sc_msr_cts = MSR_DCD;
1637 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) {
1638 CLR(sc->sc_mcr, MCR_AFE);
1639 } else {
1640 sc->sc_efr = 0;
1641 }
1642 } else {
1643 /*
1644 * If no flow control, then always set RTS. This will make
1645 * the other side happy if it mistakenly thinks we're doing
1646 * RTS/CTS flow control.
1647 */
1648 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
1649 sc->sc_mcr_rts = 0;
1650 sc->sc_msr_cts = 0;
1651 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) {
1652 CLR(sc->sc_mcr, MCR_AFE);
1653 } else {
1654 sc->sc_efr = 0;
1655 }
1656 if (ISSET(sc->sc_mcr, MCR_DTR))
1657 SET(sc->sc_mcr, MCR_RTS);
1658 else
1659 CLR(sc->sc_mcr, MCR_RTS);
1660 }
1661 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd;
1662
1663 if (t->c_ospeed == 0 && tp->t_ospeed != 0)
1664 CLR(sc->sc_mcr, sc->sc_mcr_dtr);
1665 else if (t->c_ospeed != 0 && tp->t_ospeed == 0)
1666 SET(sc->sc_mcr, sc->sc_mcr_dtr);
1667
1668 sc->sc_dlbl = ospeed;
1669 sc->sc_dlbh = ospeed >> 8;
1670
1671 /*
1672 * Set the FIFO threshold based on the receive speed.
1673 *
1674 * * If it's a low speed, it's probably a mouse or some other
1675 * interactive device, so set the threshold low.
1676 * * If it's a high speed, trim the trigger level down to prevent
1677 * overflows.
1678 * * Otherwise set it a bit higher.
1679 */
1680 if (sc->sc_type == COM_TYPE_HAYESP) {
1681 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
1682 } else if (sc->sc_type == COM_TYPE_TEGRA) {
1683 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1;
1684 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) {
1685 if (t->c_ospeed <= 1200)
1686 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1;
1687 else if (t->c_ospeed <= 38400)
1688 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8;
1689 else
1690 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4;
1691 } else {
1692 sc->sc_fifo = 0;
1693 }
1694
1695 if (sc->sc_type == COM_TYPE_INGENIC)
1696 sc->sc_fifo |= FIFO_UART_ON;
1697
1698 /* And copy to tty. */
1699 tp->t_ispeed = t->c_ospeed;
1700 tp->t_ospeed = t->c_ospeed;
1701 tp->t_cflag = t->c_cflag;
1702
1703 if (!sc->sc_heldchange) {
1704 if (sc->sc_tx_busy) {
1705 sc->sc_heldtbc = sc->sc_tbc;
1706 sc->sc_tbc = 0;
1707 sc->sc_heldchange = 1;
1708 } else
1709 com_loadchannelregs(sc);
1710 }
1711
1712 if (!ISSET(t->c_cflag, CHWFLOW)) {
1713 /* Disable the high water mark. */
1714 sc->sc_r_hiwat = 0;
1715 sc->sc_r_lowat = 0;
1716 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
1717 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1718 com_schedrx(sc);
1719 }
1720 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) {
1721 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED);
1722 com_hwiflow(sc);
1723 }
1724 } else {
1725 sc->sc_r_hiwat = com_rbuf_hiwat;
1726 sc->sc_r_lowat = com_rbuf_lowat;
1727 }
1728
1729 mutex_spin_exit(&sc->sc_lock);
1730
1731 /*
1732 * Update the tty layer's idea of the carrier bit, in case we changed
1733 * CLOCAL or MDMBUF. We don't hang up here; we only do that by
1734 * explicit request.
1735 */
1736 if (sc->sc_type == COM_TYPE_INGENIC) {
1737 /* no DCD here */
1738 (void) (*tp->t_linesw->l_modem)(tp, 1);
1739 } else
1740 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD));
1741
1742 #ifdef COM_DEBUG
1743 if (com_debug)
1744 comstatus(sc, "comparam ");
1745 #endif
1746
1747 if (!ISSET(t->c_cflag, CHWFLOW)) {
1748 if (sc->sc_tx_stopped) {
1749 sc->sc_tx_stopped = 0;
1750 comstart(tp);
1751 }
1752 }
1753
1754 return (0);
1755 }
1756
1757 void
com_iflush(struct com_softc * sc)1758 com_iflush(struct com_softc *sc)
1759 {
1760 struct com_regs *regsp = &sc->sc_regs;
1761 uint8_t fifo;
1762 #ifdef DIAGNOSTIC
1763 int reg;
1764 #endif
1765 int timo;
1766
1767 #ifdef DIAGNOSTIC
1768 reg = 0xffff;
1769 #endif
1770 timo = 50000;
1771 /* flush any pending I/O */
1772 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)
1773 && --timo)
1774 #ifdef DIAGNOSTIC
1775 reg =
1776 #else
1777 (void)
1778 #endif
1779 CSR_READ_1(regsp, COM_REG_RXDATA);
1780 #ifdef DIAGNOSTIC
1781 if (!timo)
1782 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg);
1783 #endif
1784
1785 switch (sc->sc_type) {
1786 case COM_TYPE_16750:
1787 case COM_TYPE_DW_APB:
1788 /*
1789 * Reset all Rx/Tx FIFO, preserve current FIFO length.
1790 * This should prevent triggering busy interrupt while
1791 * manipulating divisors.
1792 */
1793 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
1794 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14);
1795 CSR_WRITE_1(regsp, COM_REG_FIFO,
1796 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST);
1797 delay(100);
1798 break;
1799 }
1800 }
1801
1802 void
com_loadchannelregs(struct com_softc * sc)1803 com_loadchannelregs(struct com_softc *sc)
1804 {
1805 struct com_regs *regsp = &sc->sc_regs;
1806
1807 /* XXXXX necessary? */
1808 com_iflush(sc);
1809
1810 if (sc->sc_type == COM_TYPE_PXA2x0)
1811 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
1812 else
1813 CSR_WRITE_1(regsp, COM_REG_IER, 0);
1814
1815 if (sc->sc_type == COM_TYPE_OMAP) {
1816 /* disable before changing settings */
1817 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
1818 }
1819
1820 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) {
1821 KASSERT(sc->sc_type != COM_TYPE_AU1x00);
1822 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS);
1823 /* no EFR on alchemy */
1824 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1825 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1826 }
1827 if (sc->sc_type == COM_TYPE_AU1x00) {
1828 /* alchemy has single separate 16-bit clock divisor register */
1829 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +
1830 (sc->sc_dlbh << 8));
1831 } else {
1832 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
1833 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
1834 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
1835 }
1836 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1837 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
1838 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
1839 if (sc->sc_type == COM_TYPE_HAYESP) {
1840 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
1841 HAYESP_SETPRESCALER);
1842 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
1843 sc->sc_prescaler);
1844 }
1845 if (sc->sc_type == COM_TYPE_OMAP) {
1846 /* setup the fifos. the FCR value is not used as long
1847 as SCR[6] and SCR[7] are 0, which they are at reset
1848 and we never touch the SCR register */
1849 uint8_t rx_fifo_trig = 40;
1850 uint8_t tx_fifo_trig = 60;
1851 uint8_t rx_start = 8;
1852 uint8_t rx_halt = 60;
1853 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2);
1854 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2);
1855
1856 /* enable access to TCR & TLR */
1857 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR);
1858
1859 /* write tcr and tlr values */
1860 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
1861 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
1862
1863 /* disable access to TCR & TLR */
1864 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr);
1865
1866 /* enable again, but mode is based on speed */
1867 if (sc->sc_tty->t_termios.c_ospeed > 230400) {
1868 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
1869 } else {
1870 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
1871 }
1872 }
1873
1874 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1875 }
1876
1877 int
comhwiflow(struct tty * tp,int block)1878 comhwiflow(struct tty *tp, int block)
1879 {
1880 struct com_softc *sc =
1881 device_lookup_private(&com_cd, COMUNIT(tp->t_dev));
1882
1883 if (COM_ISALIVE(sc) == 0)
1884 return (0);
1885
1886 if (sc->sc_mcr_rts == 0)
1887 return (0);
1888
1889 mutex_spin_enter(&sc->sc_lock);
1890
1891 if (block) {
1892 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1893 SET(sc->sc_rx_flags, RX_TTY_BLOCKED);
1894 com_hwiflow(sc);
1895 }
1896 } else {
1897 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
1898 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1899 com_schedrx(sc);
1900 }
1901 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1902 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED);
1903 com_hwiflow(sc);
1904 }
1905 }
1906
1907 mutex_spin_exit(&sc->sc_lock);
1908 return (1);
1909 }
1910
1911 /*
1912 * (un)block input via hw flowcontrol
1913 */
1914 void
com_hwiflow(struct com_softc * sc)1915 com_hwiflow(struct com_softc *sc)
1916 {
1917 struct com_regs *regsp= &sc->sc_regs;
1918
1919 if (sc->sc_mcr_rts == 0)
1920 return;
1921
1922 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) {
1923 CLR(sc->sc_mcr, sc->sc_mcr_rts);
1924 CLR(sc->sc_mcr_active, sc->sc_mcr_rts);
1925 } else {
1926 SET(sc->sc_mcr, sc->sc_mcr_rts);
1927 SET(sc->sc_mcr_active, sc->sc_mcr_rts);
1928 }
1929 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active);
1930 }
1931
1932
1933 void
comstart(struct tty * tp)1934 comstart(struct tty *tp)
1935 {
1936 struct com_softc *sc =
1937 device_lookup_private(&com_cd, COMUNIT(tp->t_dev));
1938 struct com_regs *regsp = &sc->sc_regs;
1939
1940 if (COM_ISALIVE(sc) == 0)
1941 return;
1942
1943 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
1944 return;
1945 if (sc->sc_tx_stopped)
1946 return;
1947 if (!ttypull(tp))
1948 return;
1949
1950 /* Grab the first contiguous region of buffer space. */
1951 {
1952 u_char *tba;
1953 int tbc;
1954
1955 tba = tp->t_outq.c_cf;
1956 tbc = ndqb(&tp->t_outq, 0);
1957
1958 mutex_spin_enter(&sc->sc_lock);
1959
1960 sc->sc_tba = tba;
1961 sc->sc_tbc = tbc;
1962 }
1963
1964 SET(tp->t_state, TS_BUSY);
1965 sc->sc_tx_busy = 1;
1966
1967 /* Enable transmit completion interrupts if necessary. */
1968 if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
1969 SET(sc->sc_ier, IER_ETXRDY);
1970 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1971 }
1972
1973 /* Output the first chunk of the contiguous buffer. */
1974 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) {
1975 u_int n;
1976
1977 n = sc->sc_tbc;
1978 if (n > sc->sc_fifolen)
1979 n = sc->sc_fifolen;
1980 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
1981 sc->sc_tbc -= n;
1982 sc->sc_tba += n;
1983 }
1984
1985 mutex_spin_exit(&sc->sc_lock);
1986 }
1987
1988 /*
1989 * Stop output on a line.
1990 */
1991 void
comstop(struct tty * tp,int flag)1992 comstop(struct tty *tp, int flag)
1993 {
1994 struct com_softc *sc =
1995 device_lookup_private(&com_cd, COMUNIT(tp->t_dev));
1996
1997 mutex_spin_enter(&sc->sc_lock);
1998 if (ISSET(tp->t_state, TS_BUSY)) {
1999 /* Stop transmitting at the next chunk. */
2000 sc->sc_tbc = 0;
2001 sc->sc_heldtbc = 0;
2002 if (!ISSET(tp->t_state, TS_TTSTOP))
2003 SET(tp->t_state, TS_FLUSH);
2004 }
2005 mutex_spin_exit(&sc->sc_lock);
2006 }
2007
2008 void
comdiag(void * arg)2009 comdiag(void *arg)
2010 {
2011 struct com_softc *sc = arg;
2012 int overflows, floods;
2013
2014 mutex_spin_enter(&sc->sc_lock);
2015 overflows = sc->sc_overflows;
2016 sc->sc_overflows = 0;
2017 floods = sc->sc_floods;
2018 sc->sc_floods = 0;
2019 sc->sc_errors = 0;
2020 mutex_spin_exit(&sc->sc_lock);
2021
2022 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
2023 device_xname(sc->sc_dev),
2024 overflows, overflows == 1 ? "" : "s",
2025 floods, floods == 1 ? "" : "s");
2026 }
2027
2028 static inline void
com_rxsoft(struct com_softc * sc,struct tty * tp)2029 com_rxsoft(struct com_softc *sc, struct tty *tp)
2030 {
2031 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint;
2032 u_char *get, *end;
2033 u_int cc, scc;
2034 u_char lsr;
2035 int code;
2036
2037 end = sc->sc_ebuf;
2038 get = sc->sc_rbget;
2039 scc = cc = com_rbuf_size - sc->sc_rbavail;
2040
2041 if (cc == com_rbuf_size) {
2042 sc->sc_floods++;
2043 if (sc->sc_errors++ == 0)
2044 callout_reset(&sc->sc_diag_callout, 60 * hz,
2045 comdiag, sc);
2046 }
2047
2048 /* If not yet open, drop the entire buffer content here */
2049 if (!ISSET(tp->t_state, TS_ISOPEN)) {
2050 get += cc << 1;
2051 if (get >= end)
2052 get -= com_rbuf_size << 1;
2053 cc = 0;
2054 }
2055 while (cc) {
2056 code = get[0];
2057 lsr = get[1];
2058 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) {
2059 if (ISSET(lsr, LSR_OE)) {
2060 sc->sc_overflows++;
2061 if (sc->sc_errors++ == 0)
2062 callout_reset(&sc->sc_diag_callout,
2063 60 * hz, comdiag, sc);
2064 }
2065 if (ISSET(lsr, LSR_BI | LSR_FE))
2066 SET(code, TTY_FE);
2067 if (ISSET(lsr, LSR_PE))
2068 SET(code, TTY_PE);
2069 }
2070 if ((*rint)(code, tp) == -1) {
2071 /*
2072 * The line discipline's buffer is out of space.
2073 */
2074 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
2075 /*
2076 * We're either not using flow control, or the
2077 * line discipline didn't tell us to block for
2078 * some reason. Either way, we have no way to
2079 * know when there's more space available, so
2080 * just drop the rest of the data.
2081 */
2082 get += cc << 1;
2083 if (get >= end)
2084 get -= com_rbuf_size << 1;
2085 cc = 0;
2086 } else {
2087 /*
2088 * Don't schedule any more receive processing
2089 * until the line discipline tells us there's
2090 * space available (through comhwiflow()).
2091 * Leave the rest of the data in the input
2092 * buffer.
2093 */
2094 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
2095 }
2096 break;
2097 }
2098 get += 2;
2099 if (get >= end)
2100 get = sc->sc_rbuf;
2101 cc--;
2102 }
2103
2104 if (cc != scc) {
2105 sc->sc_rbget = get;
2106 mutex_spin_enter(&sc->sc_lock);
2107
2108 cc = sc->sc_rbavail += scc - cc;
2109 /* Buffers should be ok again, release possible block. */
2110 if (cc >= sc->sc_r_lowat) {
2111 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
2112 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
2113 SET(sc->sc_ier, IER_ERXRDY);
2114 if (sc->sc_type == COM_TYPE_PXA2x0)
2115 SET(sc->sc_ier, IER_ERXTOUT);
2116 if (sc->sc_type == COM_TYPE_INGENIC ||
2117 sc->sc_type == COM_TYPE_TEGRA)
2118 SET(sc->sc_ier, IER_ERXTOUT);
2119
2120 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER,
2121 sc->sc_ier);
2122 }
2123 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
2124 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED);
2125 com_hwiflow(sc);
2126 }
2127 }
2128 mutex_spin_exit(&sc->sc_lock);
2129 }
2130 }
2131
2132 static inline void
com_txsoft(struct com_softc * sc,struct tty * tp)2133 com_txsoft(struct com_softc *sc, struct tty *tp)
2134 {
2135
2136 CLR(tp->t_state, TS_BUSY);
2137 if (ISSET(tp->t_state, TS_FLUSH))
2138 CLR(tp->t_state, TS_FLUSH);
2139 else
2140 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
2141 (*tp->t_linesw->l_start)(tp);
2142 }
2143
2144 static inline void
com_stsoft(struct com_softc * sc,struct tty * tp)2145 com_stsoft(struct com_softc *sc, struct tty *tp)
2146 {
2147 u_char msr, delta;
2148
2149 mutex_spin_enter(&sc->sc_lock);
2150 msr = sc->sc_msr;
2151 delta = sc->sc_msr_delta;
2152 sc->sc_msr_delta = 0;
2153 mutex_spin_exit(&sc->sc_lock);
2154
2155 if (ISSET(delta, sc->sc_msr_dcd)) {
2156 /*
2157 * Inform the tty layer that carrier detect changed.
2158 */
2159 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD));
2160 }
2161
2162 if (ISSET(delta, sc->sc_msr_cts)) {
2163 /* Block or unblock output according to flow control. */
2164 if (ISSET(msr, sc->sc_msr_cts)) {
2165 sc->sc_tx_stopped = 0;
2166 (*tp->t_linesw->l_start)(tp);
2167 } else {
2168 sc->sc_tx_stopped = 1;
2169 }
2170 }
2171
2172 #ifdef COM_DEBUG
2173 if (com_debug)
2174 comstatus(sc, "com_stsoft");
2175 #endif
2176 }
2177
2178 void
comsoft(void * arg)2179 comsoft(void *arg)
2180 {
2181 struct com_softc *sc = arg;
2182 struct tty *tp;
2183
2184 if (COM_ISALIVE(sc) == 0)
2185 return;
2186
2187 tp = sc->sc_tty;
2188
2189 if (sc->sc_rx_ready) {
2190 sc->sc_rx_ready = 0;
2191 com_rxsoft(sc, tp);
2192 }
2193
2194 if (sc->sc_st_check) {
2195 sc->sc_st_check = 0;
2196 com_stsoft(sc, tp);
2197 }
2198
2199 if (sc->sc_tx_done) {
2200 sc->sc_tx_done = 0;
2201 com_txsoft(sc, tp);
2202 }
2203 }
2204
2205 int
comintr(void * arg)2206 comintr(void *arg)
2207 {
2208 struct com_softc *sc = arg;
2209 struct com_regs *regsp = &sc->sc_regs;
2210
2211 u_char *put, *end;
2212 u_int cc;
2213 u_char lsr, iir;
2214
2215 if (COM_ISALIVE(sc) == 0)
2216 return (0);
2217
2218 KASSERT(regsp != NULL);
2219
2220 mutex_spin_enter(&sc->sc_lock);
2221 iir = CSR_READ_1(regsp, COM_REG_IIR);
2222
2223 /* Handle ns16750-specific busy interrupt. */
2224 if (sc->sc_type == COM_TYPE_16750 &&
2225 (iir & IIR_BUSY) == IIR_BUSY) {
2226 for (int timeout = 10000;
2227 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--)
2228 if (timeout <= 0) {
2229 aprint_error_dev(sc->sc_dev,
2230 "timeout while waiting for BUSY interrupt "
2231 "acknowledge\n");
2232 mutex_spin_exit(&sc->sc_lock);
2233 return (0);
2234 }
2235
2236 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2237 iir = CSR_READ_1(regsp, COM_REG_IIR);
2238 }
2239
2240 /* DesignWare APB UART BUSY interrupt */
2241 if (sc->sc_type == COM_TYPE_DW_APB &&
2242 (iir & IIR_BUSY) == IIR_BUSY) {
2243 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
2244 (void)CSR_READ_1(regsp, COM_REG_USR);
2245 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) {
2246 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN);
2247 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2248 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2249 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2250 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2251 CSR_WRITE_1(regsp, COM_REG_HALT,
2252 HALT_CHCFG_EN | HALT_CHCFG_UD);
2253 for (int timeout = 10000000;
2254 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0;
2255 timeout--) {
2256 if (timeout <= 0) {
2257 aprint_error_dev(sc->sc_dev,
2258 "timeout while waiting for HALT "
2259 "update acknowledge 0x%x 0x%x\n",
2260 CSR_READ_1(regsp, COM_REG_HALT),
2261 CSR_READ_1(regsp, COM_REG_USR));
2262 break;
2263 }
2264 }
2265 CSR_WRITE_1(regsp, COM_REG_HALT, 0);
2266 (void)CSR_READ_1(regsp, COM_REG_USR);
2267 } else {
2268 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2269 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2270 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2271 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2272 }
2273 }
2274
2275 end = sc->sc_ebuf;
2276 put = sc->sc_rbput;
2277 cc = sc->sc_rbavail;
2278
2279 if (ISSET(iir, IIR_NOPEND)) {
2280 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY))
2281 goto do_tx;
2282 mutex_spin_exit(&sc->sc_lock);
2283 return (0);
2284 }
2285
2286 again: do {
2287 u_char msr, delta;
2288
2289 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2290 if (ISSET(lsr, LSR_BI)) {
2291 int cn_trapped = 0; /* see above: cn_trap() */
2292
2293 cn_check_magic(sc->sc_tty->t_dev,
2294 CNC_BREAK, com_cnm_state);
2295 if (cn_trapped)
2296 continue;
2297 #if defined(KGDB) && !defined(DDB)
2298 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) {
2299 kgdb_connect(1);
2300 continue;
2301 }
2302 #endif
2303 }
2304
2305 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY))
2306 lsr |= LSR_RXRDY;
2307
2308 if (ISSET(lsr, LSR_RCV_MASK) &&
2309 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
2310 while (cc > 0) {
2311 int cn_trapped = 0;
2312 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA);
2313 put[1] = lsr;
2314 cn_check_magic(sc->sc_tty->t_dev,
2315 put[0], com_cnm_state);
2316 if (cn_trapped)
2317 goto next;
2318 put += 2;
2319 if (put >= end)
2320 put = sc->sc_rbuf;
2321 cc--;
2322 next:
2323 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2324 if (!ISSET(lsr, LSR_RCV_MASK))
2325 break;
2326 }
2327
2328 /*
2329 * Current string of incoming characters ended because
2330 * no more data was available or we ran out of space.
2331 * Schedule a receive event if any data was received.
2332 * If we're out of space, turn off receive interrupts.
2333 */
2334 sc->sc_rbput = put;
2335 sc->sc_rbavail = cc;
2336 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
2337 sc->sc_rx_ready = 1;
2338
2339 /*
2340 * See if we are in danger of overflowing a buffer. If
2341 * so, use hardware flow control to ease the pressure.
2342 */
2343 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
2344 cc < sc->sc_r_hiwat) {
2345 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
2346 com_hwiflow(sc);
2347 }
2348
2349 /*
2350 * If we're out of space, disable receive interrupts
2351 * until the queue has drained a bit.
2352 */
2353 if (!cc) {
2354 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
2355 switch (sc->sc_type) {
2356 case COM_TYPE_PXA2x0:
2357 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT);
2358 break;
2359 case COM_TYPE_INGENIC:
2360 case COM_TYPE_TEGRA:
2361 CLR(sc->sc_ier,
2362 IER_ERXRDY | IER_ERXTOUT);
2363 break;
2364 default:
2365 CLR(sc->sc_ier, IER_ERXRDY);
2366 break;
2367 }
2368 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2369 }
2370 } else {
2371 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) {
2372 (void) CSR_READ_1(regsp, COM_REG_RXDATA);
2373 continue;
2374 }
2375 }
2376
2377 msr = CSR_READ_1(regsp, COM_REG_MSR);
2378 delta = msr ^ sc->sc_msr;
2379 sc->sc_msr = msr;
2380 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) &&
2381 (delta & MSR_DCD)) {
2382 mutex_spin_enter(&timecounter_lock);
2383 pps_capture(&sc->sc_pps_state);
2384 pps_event(&sc->sc_pps_state,
2385 (msr & MSR_DCD) ?
2386 PPS_CAPTUREASSERT :
2387 PPS_CAPTURECLEAR);
2388 mutex_spin_exit(&timecounter_lock);
2389 }
2390
2391 /*
2392 * Process normal status changes
2393 */
2394 if (ISSET(delta, sc->sc_msr_mask)) {
2395 SET(sc->sc_msr_delta, delta);
2396
2397 /*
2398 * Stop output immediately if we lose the output
2399 * flow control signal or carrier detect.
2400 */
2401 if (ISSET(~msr, sc->sc_msr_mask)) {
2402 sc->sc_tbc = 0;
2403 sc->sc_heldtbc = 0;
2404 #ifdef COM_DEBUG
2405 if (com_debug)
2406 comstatus(sc, "comintr ");
2407 #endif
2408 }
2409
2410 sc->sc_st_check = 1;
2411 }
2412 } while (!ISSET((iir =
2413 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) &&
2414 /*
2415 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY
2416 * by IIR read, so we can't do this way: `process all interrupts,
2417 * then do TX if possible'.
2418 */
2419 (iir & IIR_IMASK) != IIR_TXRDY);
2420
2421 do_tx:
2422 /*
2423 * Read LSR again, since there may be an interrupt between
2424 * the last LSR read and IIR read above.
2425 */
2426 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2427
2428 /*
2429 * See if data can be transmitted as well.
2430 * Schedule tx done event if no data left
2431 * and tty was marked busy.
2432 */
2433 if (ISSET(lsr, LSR_TXRDY)) {
2434 /*
2435 * If we've delayed a parameter change, do it now, and restart
2436 * output.
2437 */
2438 if (sc->sc_heldchange) {
2439 com_loadchannelregs(sc);
2440 sc->sc_heldchange = 0;
2441 sc->sc_tbc = sc->sc_heldtbc;
2442 sc->sc_heldtbc = 0;
2443 }
2444
2445 /* Output the next chunk of the contiguous buffer, if any. */
2446 if (sc->sc_tbc > 0) {
2447 u_int n;
2448
2449 n = sc->sc_tbc;
2450 if (n > sc->sc_fifolen)
2451 n = sc->sc_fifolen;
2452 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
2453 sc->sc_tbc -= n;
2454 sc->sc_tba += n;
2455 } else {
2456 /* Disable transmit completion interrupts if necessary. */
2457 if (ISSET(sc->sc_ier, IER_ETXRDY)) {
2458 CLR(sc->sc_ier, IER_ETXRDY);
2459 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2460 }
2461 if (sc->sc_tx_busy) {
2462 sc->sc_tx_busy = 0;
2463 sc->sc_tx_done = 1;
2464 }
2465 }
2466 }
2467
2468 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND))
2469 goto again;
2470
2471 mutex_spin_exit(&sc->sc_lock);
2472
2473 /* Wake up the poller. */
2474 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0)
2475 softint_schedule(sc->sc_si);
2476
2477 #ifdef RND_COM
2478 rnd_add_uint32(&sc->rnd_source, iir | lsr);
2479 #endif
2480
2481 return (1);
2482 }
2483
2484 /*
2485 * The following functions are polled getc and putc routines, shared
2486 * by the console and kgdb glue.
2487 *
2488 * The read-ahead code is so that you can detect pending in-band
2489 * cn_magic in polled mode while doing output rather than having to
2490 * wait until the kernel decides it needs input.
2491 */
2492
2493 #define MAX_READAHEAD 20
2494 static int com_readahead[MAX_READAHEAD];
2495 static int com_readaheadcount = 0;
2496
2497 int
com_common_getc(dev_t dev,struct com_regs * regsp)2498 com_common_getc(dev_t dev, struct com_regs *regsp)
2499 {
2500 int s = splserial();
2501 u_char stat, c;
2502
2503 /* got a character from reading things earlier */
2504 if (com_readaheadcount > 0) {
2505 int i;
2506
2507 c = com_readahead[0];
2508 for (i = 1; i < com_readaheadcount; i++) {
2509 com_readahead[i-1] = com_readahead[i];
2510 }
2511 com_readaheadcount--;
2512 splx(s);
2513 return (c);
2514 }
2515
2516 /* don't block until a character becomes available */
2517 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2518 splx(s);
2519 return -1;
2520 }
2521
2522 c = CSR_READ_1(regsp, COM_REG_RXDATA);
2523 stat = CSR_READ_1(regsp, COM_REG_IIR);
2524 {
2525 int cn_trapped = 0; /* required by cn_trap, see above */
2526 if (!db_active)
2527 cn_check_magic(dev, c, com_cnm_state);
2528 }
2529 splx(s);
2530 return (c);
2531 }
2532
2533 static void
com_common_putc(dev_t dev,struct com_regs * regsp,int c,int with_readahead)2534 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead)
2535 {
2536 int s = splserial();
2537 int cin, stat, timo;
2538
2539 if (with_readahead && com_readaheadcount < MAX_READAHEAD
2540 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2541 int cn_trapped = 0;
2542 cin = CSR_READ_1(regsp, COM_REG_RXDATA);
2543 stat = CSR_READ_1(regsp, COM_REG_IIR);
2544 cn_check_magic(dev, cin, com_cnm_state);
2545 com_readahead[com_readaheadcount++] = cin;
2546 }
2547
2548 /* wait for any pending transmission to finish */
2549 timo = 150000;
2550 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo)
2551 continue;
2552
2553 CSR_WRITE_1(regsp, COM_REG_TXDATA, c);
2554 COM_BARRIER(regsp, BR | BW);
2555
2556 splx(s);
2557 }
2558
2559 /*
2560 * Initialize UART for use as console or KGDB line.
2561 */
2562 int
cominit(struct com_regs * regsp,int rate,int frequency,int type,tcflag_t cflag)2563 cominit(struct com_regs *regsp, int rate, int frequency, int type,
2564 tcflag_t cflag)
2565 {
2566
2567 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0,
2568 ®sp->cr_ioh))
2569 return (ENOMEM); /* ??? */
2570
2571 if (type == COM_TYPE_OMAP) {
2572 /* disable before changing settings */
2573 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
2574 }
2575
2576 rate = comspeed(rate, frequency, type);
2577 if (rate != -1) {
2578 if (type == COM_TYPE_AU1x00) {
2579 /* no EFR on alchemy */
2580 CSR_WRITE_2(regsp, COM_REG_DLBL, rate);
2581 } else {
2582 if ((type != COM_TYPE_16550_NOERS) &&
2583 (type != COM_TYPE_INGENIC)) {
2584 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
2585 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
2586 }
2587 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
2588 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
2589 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);
2590 }
2591 }
2592 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));
2593 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2594
2595 if (type == COM_TYPE_INGENIC) {
2596 CSR_WRITE_1(regsp, COM_REG_FIFO,
2597 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
2598 FIFO_TRIGGER_1 | FIFO_UART_ON);
2599 } else {
2600 CSR_WRITE_1(regsp, COM_REG_FIFO,
2601 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
2602 FIFO_TRIGGER_1);
2603 }
2604
2605 if (type == COM_TYPE_OMAP) {
2606 /* setup the fifos. the FCR value is not used as long
2607 as SCR[6] and SCR[7] are 0, which they are at reset
2608 and we never touch the SCR register */
2609 uint8_t rx_fifo_trig = 40;
2610 uint8_t tx_fifo_trig = 60;
2611 uint8_t rx_start = 8;
2612 uint8_t rx_halt = 60;
2613 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2);
2614 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2);
2615
2616 /* enable access to TCR & TLR */
2617 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);
2618
2619 /* write tcr and tlr values */
2620 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
2621 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
2622
2623 /* disable access to TCR & TLR */
2624 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2625
2626 /* enable again, but mode is based on speed */
2627 if (rate > 230400) {
2628 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
2629 } else {
2630 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
2631 }
2632 }
2633
2634 if (type == COM_TYPE_PXA2x0)
2635 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
2636 else
2637 CSR_WRITE_1(regsp, COM_REG_IER, 0);
2638
2639 return (0);
2640 }
2641
2642 int
comcnattach1(struct com_regs * regsp,int rate,int frequency,int type,tcflag_t cflag)2643 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type,
2644 tcflag_t cflag)
2645 {
2646 int res;
2647
2648 comcons_info.regs = *regsp;
2649
2650 res = cominit(&comcons_info.regs, rate, frequency, type, cflag);
2651 if (res)
2652 return (res);
2653
2654 cn_tab = &comcons;
2655 cn_init_magic(&com_cnm_state);
2656 cn_set_magic("\047\001"); /* default magic is BREAK */
2657
2658 comcons_info.frequency = frequency;
2659 comcons_info.type = type;
2660 comcons_info.rate = rate;
2661 comcons_info.cflag = cflag;
2662
2663 return (0);
2664 }
2665
2666 int
comcnattach(bus_space_tag_t iot,bus_addr_t iobase,int rate,int frequency,int type,tcflag_t cflag)2667 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency,
2668 int type, tcflag_t cflag)
2669 {
2670 struct com_regs regs;
2671
2672 /*XXX*/
2673 bus_space_handle_t dummy_bsh;
2674 memset(&dummy_bsh, 0, sizeof(dummy_bsh));
2675
2676 /*
2677 * dummy_bsh required because com_init_regs() wants it. A
2678 * real bus_space_handle will be filled in by cominit() later.
2679 * XXXJRT Detangle this mess eventually, plz.
2680 */
2681 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase);
2682
2683 return comcnattach1(®s, rate, frequency, type, cflag);
2684 }
2685
2686 static int
comcnreattach(void)2687 comcnreattach(void)
2688 {
2689 return comcnattach1(&comcons_info.regs, comcons_info.rate,
2690 comcons_info.frequency, comcons_info.type, comcons_info.cflag);
2691 }
2692
2693 int
comcngetc(dev_t dev)2694 comcngetc(dev_t dev)
2695 {
2696
2697 return (com_common_getc(dev, &comcons_info.regs));
2698 }
2699
2700 /*
2701 * Console kernel output character routine.
2702 */
2703 void
comcnputc(dev_t dev,int c)2704 comcnputc(dev_t dev, int c)
2705 {
2706
2707 com_common_putc(dev, &comcons_info.regs, c, cold);
2708 }
2709
2710 void
comcnpollc(dev_t dev,int on)2711 comcnpollc(dev_t dev, int on)
2712 {
2713
2714 com_readaheadcount = 0;
2715 }
2716
2717 #ifdef KGDB
2718 int
com_kgdb_attach1(struct com_regs * regsp,int rate,int frequency,int type,tcflag_t cflag)2719 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type,
2720 tcflag_t cflag)
2721 {
2722 int res;
2723
2724 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) &&
2725 regsp->cr_iobase == comcons_info.regs.cr_iobase) {
2726 #if !defined(DDB)
2727 return (EBUSY); /* cannot share with console */
2728 #else
2729 comkgdbregs = *regsp;
2730 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh;
2731 #endif
2732 } else {
2733 comkgdbregs = *regsp;
2734 res = cominit(&comkgdbregs, rate, frequency, type, cflag);
2735 if (res)
2736 return (res);
2737
2738 /*
2739 * XXXfvdl this shouldn't be needed, but the cn_magic goo
2740 * expects this to be initialized
2741 */
2742 cn_init_magic(&com_cnm_state);
2743 cn_set_magic("\047\001");
2744 }
2745
2746 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL);
2747 kgdb_dev = 123; /* unneeded, only to satisfy some tests */
2748
2749 return (0);
2750 }
2751
2752 int
com_kgdb_attach(bus_space_tag_t iot,bus_addr_t iobase,int rate,int frequency,int type,tcflag_t cflag)2753 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate,
2754 int frequency, int type, tcflag_t cflag)
2755 {
2756 struct com_regs regs;
2757
2758 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase);
2759
2760 return com_kgdb_attach1(®s, rate, frequency, type, cflag);
2761 }
2762
2763 /* ARGSUSED */
2764 int
com_kgdb_getc(void * arg)2765 com_kgdb_getc(void *arg)
2766 {
2767
2768 return (com_common_getc(NODEV, &comkgdbregs));
2769 }
2770
2771 /* ARGSUSED */
2772 void
com_kgdb_putc(void * arg,int c)2773 com_kgdb_putc(void *arg, int c)
2774 {
2775
2776 com_common_putc(NODEV, &comkgdbregs, c, 0);
2777 }
2778 #endif /* KGDB */
2779
2780 /*
2781 * helper function to identify the com ports used by
2782 * console or KGDB (and not yet autoconf attached)
2783 */
2784 int
com_is_console(bus_space_tag_t iot,bus_addr_t iobase,bus_space_handle_t * ioh)2785 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh)
2786 {
2787 bus_space_handle_t help;
2788
2789 if (!comconsattached &&
2790 bus_space_is_equal(iot, comcons_info.regs.cr_iot) &&
2791 iobase == comcons_info.regs.cr_iobase)
2792 help = comcons_info.regs.cr_ioh;
2793 #ifdef KGDB
2794 else if (!com_kgdb_attached &&
2795 bus_space_is_equal(iot, comkgdbregs.cr_iot) &&
2796 iobase == comkgdbregs.cr_iobase)
2797 help = comkgdbregs.cr_ioh;
2798 #endif
2799 else
2800 return (0);
2801
2802 if (ioh)
2803 *ioh = help;
2804 return (1);
2805 }
2806
2807 /*
2808 * this routine exists to serve as a shutdown hook for systems that
2809 * have firmware which doesn't interact properly with a com device in
2810 * FIFO mode.
2811 */
2812 bool
com_cleanup(device_t self,int how)2813 com_cleanup(device_t self, int how)
2814 {
2815 struct com_softc *sc = device_private(self);
2816
2817 if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
2818 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0);
2819
2820 return true;
2821 }
2822
2823 bool
com_suspend(device_t self,const pmf_qual_t * qual)2824 com_suspend(device_t self, const pmf_qual_t *qual)
2825 {
2826 struct com_softc *sc = device_private(self);
2827
2828 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0);
2829 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR);
2830
2831 return true;
2832 }
2833
2834 bool
com_resume(device_t self,const pmf_qual_t * qual)2835 com_resume(device_t self, const pmf_qual_t *qual)
2836 {
2837 struct com_softc *sc = device_private(self);
2838
2839 mutex_spin_enter(&sc->sc_lock);
2840 com_loadchannelregs(sc);
2841 mutex_spin_exit(&sc->sc_lock);
2842
2843 return true;
2844 }
2845