1 /*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include "intel_guc.h"
26 #include "i915_drv.h"
27
gen8_guc_raise_irq(struct intel_guc * guc)28 static void gen8_guc_raise_irq(struct intel_guc *guc)
29 {
30 struct drm_i915_private *dev_priv = guc_to_i915(guc);
31
32 I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
33 }
34
guc_send_reg(struct intel_guc * guc,u32 i)35 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
36 {
37 GEM_BUG_ON(!guc->send_regs.base);
38 GEM_BUG_ON(!guc->send_regs.count);
39 GEM_BUG_ON(i >= guc->send_regs.count);
40
41 return _MMIO(guc->send_regs.base + 4 * i);
42 }
43
intel_guc_init_send_regs(struct intel_guc * guc)44 void intel_guc_init_send_regs(struct intel_guc *guc)
45 {
46 struct drm_i915_private *dev_priv = guc_to_i915(guc);
47 enum forcewake_domains fw_domains = 0;
48 unsigned int i;
49
50 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
51 guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
52
53 for (i = 0; i < guc->send_regs.count; i++) {
54 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
55 guc_send_reg(guc, i),
56 FW_REG_READ | FW_REG_WRITE);
57 }
58 guc->send_regs.fw_domains = fw_domains;
59 }
60
intel_guc_init_early(struct intel_guc * guc)61 void intel_guc_init_early(struct intel_guc *guc)
62 {
63 intel_guc_ct_init_early(&guc->ct);
64
65 lockinit(&guc->send_mutex, "i9pgsm", 0, LK_CANRECURSE);
66 guc->send = intel_guc_send_nop;
67 guc->notify = gen8_guc_raise_irq;
68 }
69
get_gt_type(struct drm_i915_private * dev_priv)70 static u32 get_gt_type(struct drm_i915_private *dev_priv)
71 {
72 /* XXX: GT type based on PCI device ID? field seems unused by fw */
73 return 0;
74 }
75
get_core_family(struct drm_i915_private * dev_priv)76 static u32 get_core_family(struct drm_i915_private *dev_priv)
77 {
78 u32 gen = INTEL_GEN(dev_priv);
79
80 switch (gen) {
81 case 9:
82 return GUC_CORE_FAMILY_GEN9;
83
84 default:
85 MISSING_CASE(gen);
86 return GUC_CORE_FAMILY_UNKNOWN;
87 }
88 }
89
90 /*
91 * Initialise the GuC parameter block before starting the firmware
92 * transfer. These parameters are read by the firmware on startup
93 * and cannot be changed thereafter.
94 */
intel_guc_init_params(struct intel_guc * guc)95 void intel_guc_init_params(struct intel_guc *guc)
96 {
97 struct drm_i915_private *dev_priv = guc_to_i915(guc);
98 u32 params[GUC_CTL_MAX_DWORDS];
99 int i;
100
101 memset(params, 0, sizeof(params));
102
103 params[GUC_CTL_DEVICE_INFO] |=
104 (get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |
105 (get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);
106
107 /*
108 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
109 * second. This ARAR is calculated by:
110 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
111 */
112 params[GUC_CTL_ARAT_HIGH] = 0;
113 params[GUC_CTL_ARAT_LOW] = 100000000;
114
115 params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
116
117 params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
118 GUC_CTL_VCS2_ENABLED;
119
120 params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
121
122 if (i915_modparams.guc_log_level >= 0) {
123 params[GUC_CTL_DEBUG] =
124 i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
125 } else {
126 params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
127 }
128
129 /* If GuC submission is enabled, set up additional parameters here */
130 if (i915_modparams.enable_guc_submission) {
131 u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
132 u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
133 u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
134
135 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
136 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
137
138 pgs >>= PAGE_SHIFT;
139 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
140 (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
141
142 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
143
144 /* Unmask this bit to enable the GuC's internal scheduler */
145 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
146 }
147
148 /*
149 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
150 * they are power context saved so it's ok to release forcewake
151 * when we are done here and take it again at xfer time.
152 */
153 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
154
155 I915_WRITE(SOFT_SCRATCH(0), 0);
156
157 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
158 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
159
160 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
161 }
162
intel_guc_send_nop(struct intel_guc * guc,const u32 * action,u32 len)163 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
164 {
165 WARN(1, "Unexpected send: action=%#x\n", *action);
166 return -ENODEV;
167 }
168
169 /*
170 * This function implements the MMIO based host to GuC interface.
171 */
intel_guc_send_mmio(struct intel_guc * guc,const u32 * action,u32 len)172 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
173 {
174 struct drm_i915_private *dev_priv = guc_to_i915(guc);
175 u32 status;
176 int i;
177 int ret;
178
179 GEM_BUG_ON(!len);
180 GEM_BUG_ON(len > guc->send_regs.count);
181
182 /* If CT is available, we expect to use MMIO only during init/fini */
183 GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
184 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
185 *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
186
187 mutex_lock(&guc->send_mutex);
188 intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
189
190 for (i = 0; i < len; i++)
191 I915_WRITE(guc_send_reg(guc, i), action[i]);
192
193 POSTING_READ(guc_send_reg(guc, i - 1));
194
195 intel_guc_notify(guc);
196
197 /*
198 * No GuC command should ever take longer than 10ms.
199 * Fast commands should still complete in 10us.
200 */
201 ret = __intel_wait_for_register_fw(dev_priv,
202 guc_send_reg(guc, 0),
203 INTEL_GUC_RECV_MASK,
204 INTEL_GUC_RECV_MASK,
205 10, 10, &status);
206 if (status != INTEL_GUC_STATUS_SUCCESS) {
207 /*
208 * Either the GuC explicitly returned an error (which
209 * we convert to -EIO here) or no response at all was
210 * received within the timeout limit (-ETIMEDOUT)
211 */
212 if (ret != -ETIMEDOUT)
213 ret = -EIO;
214
215 DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
216 " ret=%d status=0x%08X response=0x%08X\n",
217 action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
218 }
219
220 intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
221 mutex_unlock(&guc->send_mutex);
222
223 return ret;
224 }
225
intel_guc_sample_forcewake(struct intel_guc * guc)226 int intel_guc_sample_forcewake(struct intel_guc *guc)
227 {
228 struct drm_i915_private *dev_priv = guc_to_i915(guc);
229 u32 action[2];
230
231 action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
232 /* WaRsDisableCoarsePowerGating:skl,bxt */
233 if (!intel_rc6_enabled() ||
234 NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
235 action[1] = 0;
236 else
237 /* bit 0 and 1 are for Render and Media domain separately */
238 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
239
240 return intel_guc_send(guc, action, ARRAY_SIZE(action));
241 }
242
243 /**
244 * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
245 * @guc: intel_guc structure
246 * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
247 *
248 * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
249 * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
250 * intel_huc_auth().
251 *
252 * Return: non-zero code on error
253 */
intel_guc_auth_huc(struct intel_guc * guc,u32 rsa_offset)254 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
255 {
256 u32 action[] = {
257 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
258 rsa_offset
259 };
260
261 return intel_guc_send(guc, action, ARRAY_SIZE(action));
262 }
263
264 /**
265 * intel_guc_suspend() - notify GuC entering suspend state
266 * @dev_priv: i915 device private
267 */
intel_guc_suspend(struct drm_i915_private * dev_priv)268 int intel_guc_suspend(struct drm_i915_private *dev_priv)
269 {
270 struct intel_guc *guc = &dev_priv->guc;
271 struct i915_gem_context *ctx;
272 u32 data[3];
273
274 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
275 return 0;
276
277 gen9_disable_guc_interrupts(dev_priv);
278
279 ctx = dev_priv->kernel_context;
280
281 data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
282 /* any value greater than GUC_POWER_D0 */
283 data[1] = GUC_POWER_D1;
284 /* first page is shared data with GuC */
285 data[2] = guc_ggtt_offset(ctx->engine[RCS].state) +
286 LRC_GUCSHR_PN * PAGE_SIZE;
287
288 return intel_guc_send(guc, data, ARRAY_SIZE(data));
289 }
290
291 /**
292 * intel_guc_resume() - notify GuC resuming from suspend state
293 * @dev_priv: i915 device private
294 */
intel_guc_resume(struct drm_i915_private * dev_priv)295 int intel_guc_resume(struct drm_i915_private *dev_priv)
296 {
297 struct intel_guc *guc = &dev_priv->guc;
298 struct i915_gem_context *ctx;
299 u32 data[3];
300
301 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
302 return 0;
303
304 if (i915_modparams.guc_log_level >= 0)
305 gen9_enable_guc_interrupts(dev_priv);
306
307 ctx = dev_priv->kernel_context;
308
309 data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
310 data[1] = GUC_POWER_D0;
311 /* first page is shared data with GuC */
312 data[2] = guc_ggtt_offset(ctx->engine[RCS].state) +
313 LRC_GUCSHR_PN * PAGE_SIZE;
314
315 return intel_guc_send(guc, data, ARRAY_SIZE(data));
316 }
317
318 /**
319 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
320 * @guc: the guc
321 * @size: size of area to allocate (both virtual space and memory)
322 *
323 * This is a wrapper to create an object for use with the GuC. In order to
324 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
325 * both some backing storage and a range inside the Global GTT. We must pin
326 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
327 * range is reserved inside GuC.
328 *
329 * Return: A i915_vma if successful, otherwise an ERR_PTR.
330 */
intel_guc_allocate_vma(struct intel_guc * guc,u32 size)331 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
332 {
333 struct drm_i915_private *dev_priv = guc_to_i915(guc);
334 struct drm_i915_gem_object *obj;
335 struct i915_vma *vma;
336 int ret;
337
338 obj = i915_gem_object_create(dev_priv, size);
339 if (IS_ERR(obj))
340 return ERR_CAST(obj);
341
342 vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
343 if (IS_ERR(vma))
344 goto err;
345
346 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
347 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
348 if (ret) {
349 vma = ERR_PTR(ret);
350 goto err;
351 }
352
353 return vma;
354
355 err:
356 i915_gem_object_put(obj);
357 return vma;
358 }
359
intel_guc_wopcm_size(struct drm_i915_private * dev_priv)360 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
361 {
362 u32 wopcm_size = GUC_WOPCM_TOP;
363
364 /* On BXT, the top of WOPCM is reserved for RC6 context */
365 if (IS_GEN9_LP(dev_priv))
366 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
367
368 return wopcm_size;
369 }
370