1 /*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "intel_drv.h"
30 #include "i915_reg.h"
31
i915_save_display(struct drm_i915_private * dev_priv)32 static void i915_save_display(struct drm_i915_private *dev_priv)
33 {
34 /* Display arbitration control */
35 if (INTEL_GEN(dev_priv) <= 4)
36 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
37
38 /* save FBC interval */
39 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
40 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
41 }
42
i915_restore_display(struct drm_i915_private * dev_priv)43 static void i915_restore_display(struct drm_i915_private *dev_priv)
44 {
45 /* Display arbitration */
46 if (INTEL_GEN(dev_priv) <= 4)
47 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
48
49 /* only restore FBC info on the platform that supports FBC*/
50 intel_fbc_global_disable(dev_priv);
51
52 /* restore FBC interval */
53 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
54 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
55
56 i915_redisable_vga(dev_priv);
57 }
58
i915_save_state(struct drm_i915_private * dev_priv)59 int i915_save_state(struct drm_i915_private *dev_priv)
60 {
61 struct pci_dev *pdev = dev_priv->drm.pdev;
62 int i;
63
64 mutex_lock(&dev_priv->drm.struct_mutex);
65
66 i915_save_display(dev_priv);
67
68 if (IS_GEN4(dev_priv))
69 pci_read_config_word(pdev, GCDGMBUS,
70 &dev_priv->regfile.saveGCDGMBUS);
71
72 /* Cache mode state */
73 if (INTEL_GEN(dev_priv) < 7)
74 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
75
76 /* Memory Arbitration state */
77 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
78
79 /* Scratch space */
80 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
81 for (i = 0; i < 7; i++) {
82 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
83 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
84 }
85 for (i = 0; i < 3; i++)
86 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
87 } else if (IS_GEN2(dev_priv)) {
88 for (i = 0; i < 7; i++)
89 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
90 } else if (HAS_GMCH_DISPLAY(dev_priv)) {
91 for (i = 0; i < 16; i++) {
92 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
93 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
94 }
95 for (i = 0; i < 3; i++)
96 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
97 }
98
99 mutex_unlock(&dev_priv->drm.struct_mutex);
100
101 return 0;
102 }
103
i915_restore_state(struct drm_i915_private * dev_priv)104 int i915_restore_state(struct drm_i915_private *dev_priv)
105 {
106 struct pci_dev *pdev = dev_priv->drm.pdev;
107 int i;
108
109 mutex_lock(&dev_priv->drm.struct_mutex);
110
111 if (IS_GEN4(dev_priv))
112 pci_write_config_word(pdev, GCDGMBUS,
113 dev_priv->regfile.saveGCDGMBUS);
114 i915_restore_display(dev_priv);
115
116 /* Cache mode state */
117 if (INTEL_GEN(dev_priv) < 7)
118 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
119 0xffff0000);
120
121 /* Memory arbitration state */
122 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
123
124 /* Scratch space */
125 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
126 for (i = 0; i < 7; i++) {
127 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
128 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
129 }
130 for (i = 0; i < 3; i++)
131 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
132 } else if (IS_GEN2(dev_priv)) {
133 for (i = 0; i < 7; i++)
134 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
135 } else if (HAS_GMCH_DISPLAY(dev_priv)) {
136 for (i = 0; i < 16; i++) {
137 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
138 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
139 }
140 for (i = 0; i < 3; i++)
141 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
142 }
143
144 mutex_unlock(&dev_priv->drm.struct_mutex);
145
146 intel_i2c_reset(dev_priv);
147
148 return 0;
149 }
150