1 /*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 static int ata_promise_chipinit(device_t dev);
55 static int ata_promise_ch_attach(device_t dev);
56 static int ata_promise_status(device_t dev);
57 static int ata_promise_dmastart(struct ata_request *request);
58 static int ata_promise_dmastop(struct ata_request *request);
59 static void ata_promise_dmareset(device_t dev);
60 static int ata_promise_setmode(device_t dev, int target, int mode);
61 static int ata_promise_tx2_ch_attach(device_t dev);
62 static int ata_promise_tx2_status(device_t dev);
63 static int ata_promise_mio_ch_attach(device_t dev);
64 static int ata_promise_mio_ch_detach(device_t dev);
65 static void ata_promise_mio_intr(void *data);
66 static int ata_promise_mio_status(device_t dev);
67 static int ata_promise_mio_command(struct ata_request *request);
68 static void ata_promise_mio_reset(device_t dev);
69 static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result);
70 static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result);
71 static u_int32_t ata_promise_mio_softreset(device_t dev, int port);
72 static void ata_promise_mio_dmainit(device_t dev);
73 static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
74 static int ata_promise_mio_setmode(device_t dev, int target, int mode);
75 static int ata_promise_mio_getrev(device_t dev, int target);
76 static void ata_promise_sx4_intr(void *data);
77 static int ata_promise_sx4_command(struct ata_request *request);
78 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
79 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
80 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
81
82 /* misc defines */
83 #define PR_OLD 0
84 #define PR_NEW 1
85 #define PR_TX 2
86 #define PR_MIO 3
87 #define PR_TX4 0x01
88 #define PR_SX4X 0x02
89 #define PR_SX6K 0x04
90 #define PR_PATA 0x08
91 #define PR_CMBO 0x10
92 #define PR_CMBO2 0x20
93 #define PR_SATA 0x40
94 #define PR_SATA2 0x80
95
96 /*
97 * Promise chipset support functions
98 */
99 #define ATA_PDC_APKT_OFFSET 0x00000010
100 #define ATA_PDC_HPKT_OFFSET 0x00000040
101 #define ATA_PDC_ASG_OFFSET 0x00000080
102 #define ATA_PDC_LSG_OFFSET 0x000000c0
103 #define ATA_PDC_HSG_OFFSET 0x00000100
104 #define ATA_PDC_CHN_OFFSET 0x00000400
105 #define ATA_PDC_BUF_BASE 0x00400000
106 #define ATA_PDC_BUF_OFFSET 0x00100000
107 #define ATA_PDC_MAX_HPKT 8
108 #define ATA_PDC_WRITE_REG 0x00
109 #define ATA_PDC_WRITE_CTL 0x0e
110 #define ATA_PDC_WRITE_END 0x08
111 #define ATA_PDC_WAIT_NBUSY 0x10
112 #define ATA_PDC_WAIT_READY 0x18
113 #define ATA_PDC_1B 0x20
114 #define ATA_PDC_2B 0x40
115
116 struct host_packet {
117 u_int32_t addr;
118 TAILQ_ENTRY(host_packet) chain;
119 };
120
121 struct ata_promise_sx4 {
122 struct mtx mtx;
123 TAILQ_HEAD(, host_packet) queue;
124 int busy;
125 };
126
127 static int
ata_promise_probe(device_t dev)128 ata_promise_probe(device_t dev)
129 {
130 struct ata_pci_controller *ctlr = device_get_softc(dev);
131 const struct ata_chip_id *idx;
132 static const struct ata_chip_id ids[] =
133 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" },
134 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" },
135 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" },
136 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" },
137 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" },
138 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" },
139 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" },
140 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" },
141 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" },
142 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" },
143 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" },
144 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" },
145 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" },
146 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" },
147 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" },
148 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" },
149 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" },
150 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" },
151 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" },
152 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" },
153 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" },
154 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" },
155 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" },
156 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" },
157 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" },
158 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" },
159 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" },
160 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" },
161 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" },
162 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" },
163 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" },
164 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" },
165 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" },
166 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" },
167 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" },
168 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" },
169 { 0, 0, 0, 0, 0, 0}};
170 char buffer[64];
171 uintptr_t devid = 0;
172
173 if (pci_get_vendor(dev) != ATA_PROMISE_ID)
174 return ENXIO;
175
176 if (!(idx = ata_match_chip(dev, ids)))
177 return ENXIO;
178
179 /* if we are on a SuperTrak SX6000 dont attach */
180 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
181 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
182 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
183 devid == ATA_I960RM)
184 return ENXIO;
185
186 strcpy(buffer, "Promise ");
187 strcat(buffer, idx->text);
188
189 /* if we are on a FastTrak TX4, adjust the interrupt resource */
190 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
191 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
192 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
193 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
194 static rman_res_t start = 0, end = 0;
195
196 if (pci_get_slot(dev) == 1) {
197 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
198 strcat(buffer, " (channel 0+1)");
199 }
200 else if (pci_get_slot(dev) == 2 && start && end) {
201 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
202 strcat(buffer, " (channel 2+3)");
203 }
204 else {
205 start = end = 0;
206 }
207 }
208 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
209 device_set_desc_copy(dev, buffer);
210 ctlr->chip = idx;
211 ctlr->chipinit = ata_promise_chipinit;
212 return (BUS_PROBE_LOW_PRIORITY);
213 }
214
215 static int
ata_promise_chipinit(device_t dev)216 ata_promise_chipinit(device_t dev)
217 {
218 struct ata_pci_controller *ctlr = device_get_softc(dev);
219 int stat_reg;
220
221 if (ata_setup_interrupt(dev, ata_generic_intr))
222 return ENXIO;
223
224 switch (ctlr->chip->cfg1) {
225 case PR_NEW:
226 /* setup clocks */
227 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
228 /* FALLTHROUGH */
229
230 case PR_OLD:
231 /* enable burst mode */
232 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
233 ctlr->ch_attach = ata_promise_ch_attach;
234 ctlr->ch_detach = ata_pci_ch_detach;
235 ctlr->setmode = ata_promise_setmode;
236 return 0;
237
238 case PR_TX:
239 ctlr->ch_attach = ata_promise_tx2_ch_attach;
240 ctlr->ch_detach = ata_pci_ch_detach;
241 ctlr->setmode = ata_promise_setmode;
242 return 0;
243
244 case PR_MIO:
245 ctlr->r_type1 = SYS_RES_MEMORY;
246 ctlr->r_rid1 = PCIR_BAR(4);
247 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
248 &ctlr->r_rid1, RF_ACTIVE)))
249 goto failnfree;
250
251 #ifdef __sparc64__
252 if (ctlr->chip->cfg2 == PR_SX4X &&
253 !bus_space_map(rman_get_bustag(ctlr->r_res1),
254 rman_get_bushandle(ctlr->r_res1), rman_get_size(ctlr->r_res1),
255 BUS_SPACE_MAP_LINEAR, NULL))
256 goto failnfree;
257 #endif
258
259 ctlr->r_type2 = SYS_RES_MEMORY;
260 ctlr->r_rid2 = PCIR_BAR(3);
261 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
262 &ctlr->r_rid2, RF_ACTIVE)))
263 goto failnfree;
264
265 if (ctlr->chip->cfg2 == PR_SX4X) {
266 struct ata_promise_sx4 *hpkt;
267 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
268
269 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
270 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
271 ata_promise_sx4_intr, ctlr, &ctlr->handle)) {
272 device_printf(dev, "unable to setup interrupt\n");
273 goto failnfree;
274 }
275
276 /* print info about cache memory */
277 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
278 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
279 ((dimm >> 24) & 0xff),
280 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
281 " ECC enabled" : "" );
282
283 /* adjust cache memory parameters */
284 ATA_OUTL(ctlr->r_res2, 0x000c000c,
285 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
286
287 /* setup host packet controls */
288 hpkt = malloc(sizeof(struct ata_promise_sx4),
289 M_ATAPCI, M_NOWAIT | M_ZERO);
290 if (hpkt == NULL) {
291 device_printf(dev, "Cannot allocate HPKT\n");
292 goto failnfree;
293 }
294 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
295 TAILQ_INIT(&hpkt->queue);
296 hpkt->busy = 0;
297 ctlr->chipset_data = hpkt;
298 ctlr->ch_attach = ata_promise_mio_ch_attach;
299 ctlr->ch_detach = ata_promise_mio_ch_detach;
300 ctlr->reset = ata_promise_mio_reset;
301 ctlr->setmode = ata_promise_setmode;
302 ctlr->channels = 4;
303 return 0;
304 }
305
306 /* mio type controllers need an interrupt intercept */
307 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
308 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
309 ata_promise_mio_intr, ctlr, &ctlr->handle)) {
310 device_printf(dev, "unable to setup interrupt\n");
311 goto failnfree;
312 }
313
314 switch (ctlr->chip->cfg2) {
315 case PR_PATA:
316 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
317 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
318 goto sata150;
319 case PR_CMBO:
320 ctlr->channels = 3;
321 goto sata150;
322 case PR_SATA:
323 ctlr->channels = 4;
324 sata150:
325 stat_reg = 0x6c;
326 break;
327
328 case PR_CMBO2:
329 ctlr->channels = 3;
330 goto sataii;
331 case PR_SATA2:
332 default:
333 ctlr->channels = 4;
334 sataii:
335 stat_reg = 0x60;
336 break;
337 }
338
339 /* prime fake interrupt register */
340 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff;
341
342 /* clear SATA status and unmask interrupts */
343 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
344
345 /* enable "long burst length" on gen2 chips */
346 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2))
347 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000);
348
349 ctlr->ch_attach = ata_promise_mio_ch_attach;
350 ctlr->ch_detach = ata_promise_mio_ch_detach;
351 ctlr->reset = ata_promise_mio_reset;
352 ctlr->setmode = ata_promise_mio_setmode;
353 ctlr->getrev = ata_promise_mio_getrev;
354
355 return 0;
356 }
357
358 failnfree:
359 if (ctlr->r_res2)
360 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
361 if (ctlr->r_res1)
362 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
363 return ENXIO;
364 }
365
366 static int
ata_promise_ch_attach(device_t dev)367 ata_promise_ch_attach(device_t dev)
368 {
369 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
370 struct ata_channel *ch = device_get_softc(dev);
371
372 if (ata_pci_ch_attach(dev))
373 return ENXIO;
374
375 if (ctlr->chip->cfg1 == PR_NEW) {
376 ch->dma.start = ata_promise_dmastart;
377 ch->dma.stop = ata_promise_dmastop;
378 ch->dma.reset = ata_promise_dmareset;
379 }
380
381 ch->hw.status = ata_promise_status;
382 ch->flags |= ATA_NO_ATAPI_DMA;
383 ch->flags |= ATA_CHECKS_CABLE;
384 return 0;
385 }
386
387 static int
ata_promise_status(device_t dev)388 ata_promise_status(device_t dev)
389 {
390 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
391 struct ata_channel *ch = device_get_softc(dev);
392
393 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
394 return ata_pci_status(dev);
395 }
396 return 0;
397 }
398
399 static int
ata_promise_dmastart(struct ata_request * request)400 ata_promise_dmastart(struct ata_request *request)
401 {
402 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
403 struct ata_channel *ch = device_get_softc(request->parent);
404
405 if (request->flags & ATA_R_48BIT) {
406 ATA_OUTB(ctlr->r_res1, 0x11,
407 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
408 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
409 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) |
410 (request->bytecount >> 1));
411 }
412 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
413 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
414 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus);
415 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
416 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) |
417 ATA_BMCMD_START_STOP);
418 ch->dma.flags |= ATA_DMA_ACTIVE;
419 return 0;
420 }
421
422 static int
ata_promise_dmastop(struct ata_request * request)423 ata_promise_dmastop(struct ata_request *request)
424 {
425 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
426 struct ata_channel *ch = device_get_softc(request->parent);
427 int error;
428
429 if (request->flags & ATA_R_48BIT) {
430 ATA_OUTB(ctlr->r_res1, 0x11,
431 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
432 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
433 }
434 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
435 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
436 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
437 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
438 ch->dma.flags &= ~ATA_DMA_ACTIVE;
439 return error;
440 }
441
442 static void
ata_promise_dmareset(device_t dev)443 ata_promise_dmareset(device_t dev)
444 {
445 struct ata_channel *ch = device_get_softc(dev);
446
447 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
448 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
449 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
450 ch->flags &= ~ATA_DMA_ACTIVE;
451 }
452
453 static int
ata_promise_setmode(device_t dev,int target,int mode)454 ata_promise_setmode(device_t dev, int target, int mode)
455 {
456 device_t parent = device_get_parent(dev);
457 struct ata_pci_controller *ctlr = device_get_softc(parent);
458 struct ata_channel *ch = device_get_softc(dev);
459 int devno = (ch->unit << 1) + target;
460 static const uint32_t timings[][2] = {
461 /* PR_OLD PR_NEW mode */
462 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
463 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
464 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
465 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
466 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
467 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
468 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
469 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
470 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
471 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
472 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
473 { 0, 0x00424ef6 }, /* UDMA 3 */
474 { 0, 0x004127f3 }, /* UDMA 4 */
475 { 0, 0x004127f3 } /* UDMA 5 */
476 };
477
478 mode = min(mode, ctlr->chip->max_dma);
479
480 switch (ctlr->chip->cfg1) {
481 case PR_OLD:
482 case PR_NEW:
483 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
484 (pci_read_config(parent, 0x50, 2) &
485 (ch->unit ? 1 << 11 : 1 << 10))) {
486 ata_print_cable(dev, "controller");
487 mode = ATA_UDMA2;
488 }
489 break;
490
491 case PR_TX:
492 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
493 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
494 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
495 ata_print_cable(dev, "controller");
496 mode = ATA_UDMA2;
497 }
498 break;
499
500 case PR_MIO:
501 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
502 (ATA_INL(ctlr->r_res2,
503 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) +
504 (ch->unit << 7)) & 0x01000000)) {
505 ata_print_cable(dev, "controller");
506 mode = ATA_UDMA2;
507 }
508 break;
509 }
510
511 if (ctlr->chip->cfg1 < PR_TX)
512 pci_write_config(parent, 0x60 + (devno << 2),
513 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
514 return (mode);
515 }
516
517 static int
ata_promise_tx2_ch_attach(device_t dev)518 ata_promise_tx2_ch_attach(device_t dev)
519 {
520 struct ata_channel *ch = device_get_softc(dev);
521
522 if (ata_pci_ch_attach(dev))
523 return ENXIO;
524
525 ch->hw.status = ata_promise_tx2_status;
526 ch->flags |= ATA_CHECKS_CABLE;
527 return 0;
528 }
529
530 static int
ata_promise_tx2_status(device_t dev)531 ata_promise_tx2_status(device_t dev)
532 {
533 struct ata_channel *ch = device_get_softc(dev);
534
535 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
536 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
537 return ata_pci_status(dev);
538 }
539 return 0;
540 }
541
542 static int
ata_promise_mio_ch_attach(device_t dev)543 ata_promise_mio_ch_attach(device_t dev)
544 {
545 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
546 struct ata_channel *ch = device_get_softc(dev);
547 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0;
548 int i;
549
550 ata_promise_mio_dmainit(dev);
551
552 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
553 ch->r_io[i].res = ctlr->r_res2;
554 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
555 }
556 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
557 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
558 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
559 ata_default_registers(dev);
560 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) ||
561 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) {
562 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
563 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
564 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
565 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
566 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
567 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
568 ch->flags |= ATA_NO_SLAVE;
569 ch->flags |= ATA_SATA;
570 }
571 ch->flags |= ATA_USE_16BIT;
572 ch->flags |= ATA_CHECKS_CABLE;
573
574 ata_generic_hw(dev);
575 if (ctlr->chip->cfg2 & PR_SX4X) {
576 ch->hw.command = ata_promise_sx4_command;
577 }
578 else {
579 ch->hw.command = ata_promise_mio_command;
580 ch->hw.status = ata_promise_mio_status;
581 ch->hw.softreset = ata_promise_mio_softreset;
582 ch->hw.pm_read = ata_promise_mio_pm_read;
583 ch->hw.pm_write = ata_promise_mio_pm_write;
584 }
585 return 0;
586 }
587
588 static int
ata_promise_mio_ch_detach(device_t dev)589 ata_promise_mio_ch_detach(device_t dev)
590 {
591
592 ata_dmafini(dev);
593 return (0);
594 }
595
596 static void
ata_promise_mio_intr(void * data)597 ata_promise_mio_intr(void *data)
598 {
599 struct ata_pci_controller *ctlr = data;
600 struct ata_channel *ch;
601 u_int32_t vector;
602 int unit;
603
604 /*
605 * since reading interrupt status register on early "mio" chips
606 * clears the status bits we cannot read it for each channel later on
607 * in the generic interrupt routine.
608 */
609 vector = ATA_INL(ctlr->r_res2, 0x040);
610 ATA_OUTL(ctlr->r_res2, 0x040, vector);
611 ctlr->chipset_data = (void *)(uintptr_t)vector;
612
613 for (unit = 0; unit < ctlr->channels; unit++) {
614 if ((ch = ctlr->interrupt[unit].argument))
615 ctlr->interrupt[unit].function(ch);
616 }
617
618 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff;
619 }
620
621 static int
ata_promise_mio_status(device_t dev)622 ata_promise_mio_status(device_t dev)
623 {
624 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
625 struct ata_channel *ch = device_get_softc(dev);
626 u_int32_t stat_reg, vector, status;
627
628 switch (ctlr->chip->cfg2) {
629 case PR_PATA:
630 case PR_CMBO:
631 case PR_SATA:
632 stat_reg = 0x6c;
633 break;
634 case PR_CMBO2:
635 case PR_SATA2:
636 default:
637 stat_reg = 0x60;
638 break;
639 }
640
641 /* read and acknowledge interrupt */
642 vector = (uint32_t)(uintptr_t)ctlr->chipset_data;
643
644 /* read and clear interface status */
645 status = ATA_INL(ctlr->r_res2, stat_reg);
646 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
647
648 /* check for and handle disconnect events */
649 if (status & (0x00000001 << ch->unit)) {
650 if (bootverbose)
651 device_printf(dev, "DISCONNECT requested\n");
652 taskqueue_enqueue(taskqueue_thread, &ch->conntask);
653 }
654
655 /* check for and handle connect events */
656 if (status & (0x00000010 << ch->unit)) {
657 if (bootverbose)
658 device_printf(dev, "CONNECT requested\n");
659 taskqueue_enqueue(taskqueue_thread, &ch->conntask);
660 }
661
662 /* do we have any device action ? */
663 return (vector & (1 << (ch->unit + 1)));
664 }
665
666 static int
ata_promise_mio_command(struct ata_request * request)667 ata_promise_mio_command(struct ata_request *request)
668 {
669 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
670 struct ata_channel *ch = device_get_softc(request->parent);
671
672 u_int32_t *wordp = (u_int32_t *)ch->dma.work;
673
674 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
675
676 if ((ctlr->chip->cfg2 == PR_SATA2) ||
677 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) {
678 /* set portmultiplier port */
679 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f);
680 }
681
682 /* XXX SOS add ATAPI commands support later */
683 switch (request->u.ata.command) {
684 default:
685 return ata_generic_command(request);
686
687 case ATA_READ_DMA:
688 case ATA_READ_DMA48:
689 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
690 break;
691
692 case ATA_WRITE_DMA:
693 case ATA_WRITE_DMA48:
694 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
695 break;
696 }
697 wordp[1] = htole32(request->dma->sg_bus);
698 wordp[2] = 0;
699 ata_promise_apkt((u_int8_t*)wordp, request);
700
701 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus);
702 return 0;
703 }
704
705 static void
ata_promise_mio_reset(device_t dev)706 ata_promise_mio_reset(device_t dev)
707 {
708 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
709 struct ata_channel *ch = device_get_softc(dev);
710 struct ata_promise_sx4 *hpktp;
711
712 switch (ctlr->chip->cfg2) {
713 case PR_SX4X:
714
715 /* softreset channel ATA module */
716 hpktp = ctlr->chipset_data;
717 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
718 ata_udelay(1000);
719 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
720 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
721 ~0x00003f9f) | (ch->unit + 1));
722
723 /* softreset HOST module */ /* XXX SOS what about other outstandings */
724 mtx_lock(&hpktp->mtx);
725 ATA_OUTL(ctlr->r_res2, 0xc012c,
726 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
727 DELAY(10);
728 ATA_OUTL(ctlr->r_res2, 0xc012c,
729 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
730 hpktp->busy = 0;
731 mtx_unlock(&hpktp->mtx);
732 ata_generic_reset(dev);
733 break;
734
735 case PR_PATA:
736 case PR_CMBO:
737 case PR_SATA:
738 if ((ctlr->chip->cfg2 == PR_SATA) ||
739 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) {
740
741 /* mask plug/unplug intr */
742 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
743 }
744
745 /* softreset channels ATA module */
746 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
747 ata_udelay(10000);
748 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
749 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
750 ~0x00003f9f) | (ch->unit + 1));
751
752 if ((ctlr->chip->cfg2 == PR_SATA) ||
753 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) {
754
755 if (ata_sata_phy_reset(dev, -1, 1))
756 ata_generic_reset(dev);
757 else
758 ch->devices = 0;
759
760 /* reset and enable plug/unplug intr */
761 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
762 }
763 else
764 ata_generic_reset(dev);
765 break;
766
767 case PR_CMBO2:
768 case PR_SATA2:
769 if ((ctlr->chip->cfg2 == PR_SATA2) ||
770 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) {
771 /* set portmultiplier port */
772 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
773
774 /* mask plug/unplug intr */
775 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
776 }
777
778 /* softreset channels ATA module */
779 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
780 ata_udelay(10000);
781 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
782 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
783 ~0x00003f9f) | (ch->unit + 1));
784
785 if ((ctlr->chip->cfg2 == PR_SATA2) ||
786 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) {
787
788 /* set PHY mode to "improved" */
789 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
790 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
791 ~0x00000003) | 0x00000001);
792
793 if (ata_sata_phy_reset(dev, -1, 1)) {
794 u_int32_t signature = ch->hw.softreset(dev, ATA_PM);
795
796 if (bootverbose)
797 device_printf(dev, "SIGNATURE: %08x\n", signature);
798
799 switch (signature >> 16) {
800 case 0x0000:
801 ch->devices = ATA_ATA_MASTER;
802 break;
803 case 0x9669:
804 ch->devices = ATA_PORTMULTIPLIER;
805 ata_pm_identify(dev);
806 break;
807 case 0xeb14:
808 ch->devices = ATA_ATAPI_MASTER;
809 break;
810 default: /* SOS XXX */
811 if (bootverbose)
812 device_printf(dev,
813 "No signature, assuming disk device\n");
814 ch->devices = ATA_ATA_MASTER;
815 }
816 if (bootverbose)
817 device_printf(dev, "promise_mio_reset devices=%08x\n",
818 ch->devices);
819
820 } else
821 ch->devices = 0;
822
823 /* reset and enable plug/unplug intr */
824 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
825
826 ///* set portmultiplier port */
827 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
828 }
829 else
830 ata_generic_reset(dev);
831 break;
832
833 }
834 }
835
836 static int
ata_promise_mio_pm_read(device_t dev,int port,int reg,u_int32_t * result)837 ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result)
838 {
839 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
840 struct ata_channel *ch = device_get_softc(dev);
841 int timeout = 0;
842
843 if (port < 0) {
844 *result = ATA_IDX_INL(ch, reg);
845 return (0);
846 }
847 if (port < ATA_PM) {
848 switch (reg) {
849 case ATA_SSTATUS:
850 reg = 0;
851 break;
852 case ATA_SERROR:
853 reg = 1;
854 break;
855 case ATA_SCONTROL:
856 reg = 2;
857 break;
858 default:
859 return (EINVAL);
860 }
861 }
862 /* set portmultiplier port */
863 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
864
865 ATA_IDX_OUTB(ch, ATA_FEATURE, reg);
866 ATA_IDX_OUTB(ch, ATA_DRIVE, port);
867
868 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM);
869
870 while (timeout < 1000000) {
871 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS);
872 if (!(status & ATA_S_BUSY))
873 break;
874 timeout += 1000;
875 DELAY(1000);
876 }
877 if (timeout >= 1000000)
878 return ATA_E_ABORT;
879
880 *result = ATA_IDX_INB(ch, ATA_COUNT) |
881 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) |
882 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) |
883 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24);
884 return 0;
885 }
886
887 static int
ata_promise_mio_pm_write(device_t dev,int port,int reg,u_int32_t value)888 ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value)
889 {
890 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
891 struct ata_channel *ch = device_get_softc(dev);
892 int timeout = 0;
893
894 if (port < 0) {
895 ATA_IDX_OUTL(ch, reg, value);
896 return (0);
897 }
898 if (port < ATA_PM) {
899 switch (reg) {
900 case ATA_SSTATUS:
901 reg = 0;
902 break;
903 case ATA_SERROR:
904 reg = 1;
905 break;
906 case ATA_SCONTROL:
907 reg = 2;
908 break;
909 default:
910 return (EINVAL);
911 }
912 }
913 /* set portmultiplier port */
914 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
915
916 ATA_IDX_OUTB(ch, ATA_FEATURE, reg);
917 ATA_IDX_OUTB(ch, ATA_DRIVE, port);
918 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff);
919 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff);
920 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff);
921 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff);
922
923 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM);
924
925 while (timeout < 1000000) {
926 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS);
927 if (!(status & ATA_S_BUSY))
928 break;
929 timeout += 1000;
930 DELAY(1000);
931 }
932 if (timeout >= 1000000)
933 return ATA_E_ABORT;
934
935 return ATA_IDX_INB(ch, ATA_ERROR);
936 }
937
938 /* must be called with ATA channel locked and state_mtx held */
939 static u_int32_t
ata_promise_mio_softreset(device_t dev,int port)940 ata_promise_mio_softreset(device_t dev, int port)
941 {
942 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
943 struct ata_channel *ch = device_get_softc(dev);
944 int timeout;
945
946 /* set portmultiplier port */
947 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f);
948
949 /* softreset device on this channel */
950 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
951 DELAY(10);
952 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
953 ata_udelay(10000);
954 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
955 ata_udelay(150000);
956 ATA_IDX_INB(ch, ATA_ERROR);
957
958 /* wait for BUSY to go inactive */
959 for (timeout = 0; timeout < 100; timeout++) {
960 u_int8_t /* err, */ stat;
961
962 /* err = */ ATA_IDX_INB(ch, ATA_ERROR);
963 stat = ATA_IDX_INB(ch, ATA_STATUS);
964
965 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10))
966 //break;
967
968 if (!(stat & ATA_S_BUSY)) {
969 //if ((err & 0x7f) == ATA_E_ILI) {
970 return ATA_IDX_INB(ch, ATA_COUNT) |
971 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) |
972 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) |
973 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24);
974 //}
975 //else if (stat & 0x0f) {
976 //stat |= ATA_S_BUSY;
977 //}
978 }
979
980 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10))
981 break;
982 ata_udelay(100000);
983 }
984 return -1;
985 }
986
987 static void
ata_promise_mio_dmainit(device_t dev)988 ata_promise_mio_dmainit(device_t dev)
989 {
990 struct ata_channel *ch = device_get_softc(dev);
991
992 /* note start and stop are not used here */
993 ch->dma.setprd = ata_promise_mio_setprd;
994 ch->dma.max_iosize = 65536;
995 ata_dmainit(dev);
996 }
997
998 #define MAXLASTSGSIZE (32 * sizeof(u_int32_t))
999 static void
ata_promise_mio_setprd(void * xsc,bus_dma_segment_t * segs,int nsegs,int error)1000 ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1001 {
1002 struct ata_dmasetprd_args *args = xsc;
1003 struct ata_dma_prdentry *prd = args->dmatab;
1004 int i;
1005
1006 if ((args->error = error))
1007 return;
1008
1009 for (i = 0; i < nsegs; i++) {
1010 prd[i].addr = htole32(segs[i].ds_addr);
1011 prd[i].count = htole32(segs[i].ds_len);
1012 }
1013 if (segs[i - 1].ds_len > MAXLASTSGSIZE) {
1014 //printf("split last SG element of %u\n", segs[i - 1].ds_len);
1015 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE);
1016 prd[i].count = htole32(MAXLASTSGSIZE);
1017 prd[i].addr = htole32(segs[i - 1].ds_addr +
1018 (segs[i - 1].ds_len - MAXLASTSGSIZE));
1019 nsegs++;
1020 i++;
1021 }
1022 prd[i - 1].count |= htole32(ATA_DMA_EOT);
1023 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
1024 args->nsegs = nsegs;
1025 }
1026
1027 static int
ata_promise_mio_setmode(device_t dev,int target,int mode)1028 ata_promise_mio_setmode(device_t dev, int target, int mode)
1029 {
1030 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1031 struct ata_channel *ch = device_get_softc(dev);
1032
1033 if ( (ctlr->chip->cfg2 == PR_SATA) ||
1034 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) ||
1035 (ctlr->chip->cfg2 == PR_SATA2) ||
1036 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2)))
1037 mode = ata_sata_setmode(dev, target, mode);
1038 else
1039 mode = ata_promise_setmode(dev, target, mode);
1040 return (mode);
1041 }
1042
1043 static int
ata_promise_mio_getrev(device_t dev,int target)1044 ata_promise_mio_getrev(device_t dev, int target)
1045 {
1046 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1047 struct ata_channel *ch = device_get_softc(dev);
1048
1049 if ( (ctlr->chip->cfg2 == PR_SATA) ||
1050 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) ||
1051 (ctlr->chip->cfg2 == PR_SATA2) ||
1052 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2)))
1053 return (ata_sata_getrev(dev, target));
1054 else
1055 return (0);
1056 }
1057
1058 static void
ata_promise_sx4_intr(void * data)1059 ata_promise_sx4_intr(void *data)
1060 {
1061 struct ata_pci_controller *ctlr = data;
1062 struct ata_channel *ch;
1063 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
1064 int unit;
1065
1066 for (unit = 0; unit < ctlr->channels; unit++) {
1067 if (vector & (1 << (unit + 1)))
1068 if ((ch = ctlr->interrupt[unit].argument))
1069 ctlr->interrupt[unit].function(ch);
1070 if (vector & (1 << (unit + 5)))
1071 if ((ch = ctlr->interrupt[unit].argument))
1072 ata_promise_queue_hpkt(ctlr,
1073 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
1074 ATA_PDC_HPKT_OFFSET));
1075 if (vector & (1 << (unit + 9))) {
1076 ata_promise_next_hpkt(ctlr);
1077 if ((ch = ctlr->interrupt[unit].argument))
1078 ctlr->interrupt[unit].function(ch);
1079 }
1080 if (vector & (1 << (unit + 13))) {
1081 ata_promise_next_hpkt(ctlr);
1082 if ((ch = ctlr->interrupt[unit].argument))
1083 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1084 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
1085 ATA_PDC_APKT_OFFSET));
1086 }
1087 }
1088 }
1089
1090 static int
ata_promise_sx4_command(struct ata_request * request)1091 ata_promise_sx4_command(struct ata_request *request)
1092 {
1093 device_t gparent = device_get_parent(request->parent);
1094 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1095 struct ata_channel *ch = device_get_softc(request->parent);
1096 struct ata_dma_prdentry *prd;
1097 caddr_t window = rman_get_virtual(ctlr->r_res1);
1098 u_int32_t *wordp;
1099 int i, idx, length = 0;
1100
1101 /* XXX SOS add ATAPI commands support later */
1102 switch (request->u.ata.command) {
1103
1104 default:
1105 return -1;
1106
1107 case ATA_ATA_IDENTIFY:
1108 case ATA_READ:
1109 case ATA_READ48:
1110 case ATA_READ_MUL:
1111 case ATA_READ_MUL48:
1112 case ATA_WRITE:
1113 case ATA_WRITE48:
1114 case ATA_WRITE_MUL:
1115 case ATA_WRITE_MUL48:
1116 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
1117 return ata_generic_command(request);
1118
1119 case ATA_SETFEATURES:
1120 case ATA_FLUSHCACHE:
1121 case ATA_FLUSHCACHE48:
1122 case ATA_SLEEP:
1123 case ATA_SET_MULTI:
1124 wordp = (u_int32_t *)
1125 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
1126 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
1127 wordp[1] = 0;
1128 wordp[2] = 0;
1129 ata_promise_apkt((u_int8_t *)wordp, request);
1130 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
1131 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
1132 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1133 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
1134 return 0;
1135
1136 case ATA_READ_DMA:
1137 case ATA_READ_DMA48:
1138 case ATA_WRITE_DMA:
1139 case ATA_WRITE_DMA48:
1140 prd = request->dma->sg;
1141 wordp = (u_int32_t *)
1142 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
1143 i = idx = 0;
1144 do {
1145 wordp[idx++] = prd[i].addr;
1146 wordp[idx++] = prd[i].count;
1147 length += (prd[i].count & ~ATA_DMA_EOT);
1148 } while (!(prd[i++].count & ATA_DMA_EOT));
1149
1150 wordp = (u_int32_t *)
1151 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
1152 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
1153 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
1154
1155 wordp = (u_int32_t *)
1156 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
1157 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
1158 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
1159
1160 wordp = (u_int32_t *)
1161 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
1162 if (request->flags & ATA_R_READ)
1163 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
1164 if (request->flags & ATA_R_WRITE)
1165 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
1166 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
1167 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
1168 wordp[3] = 0;
1169
1170 wordp = (u_int32_t *)
1171 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
1172 if (request->flags & ATA_R_READ)
1173 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
1174 if (request->flags & ATA_R_WRITE)
1175 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
1176 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
1177 wordp[2] = 0;
1178 ata_promise_apkt((u_int8_t *)wordp, request);
1179 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
1180
1181 if (request->flags & ATA_R_READ) {
1182 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
1183 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
1184 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
1185 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
1186 }
1187 if (request->flags & ATA_R_WRITE) {
1188 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
1189 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
1190 ata_promise_queue_hpkt(ctlr,
1191 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
1192 }
1193 return 0;
1194 }
1195 }
1196
1197 static int
ata_promise_apkt(u_int8_t * bytep,struct ata_request * request)1198 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
1199 {
1200 int i = 12;
1201
1202 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
1203 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit);
1204 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
1205 bytep[i++] = ATA_A_4BIT;
1206
1207 if (request->flags & ATA_R_48BIT) {
1208 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
1209 bytep[i++] = request->u.ata.feature >> 8;
1210 bytep[i++] = request->u.ata.feature;
1211 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
1212 bytep[i++] = request->u.ata.count >> 8;
1213 bytep[i++] = request->u.ata.count;
1214 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
1215 bytep[i++] = request->u.ata.lba >> 24;
1216 bytep[i++] = request->u.ata.lba;
1217 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
1218 bytep[i++] = request->u.ata.lba >> 32;
1219 bytep[i++] = request->u.ata.lba >> 8;
1220 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
1221 bytep[i++] = request->u.ata.lba >> 40;
1222 bytep[i++] = request->u.ata.lba >> 16;
1223 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
1224 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit);
1225 }
1226 else {
1227 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
1228 bytep[i++] = request->u.ata.feature;
1229 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
1230 bytep[i++] = request->u.ata.count;
1231 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
1232 bytep[i++] = request->u.ata.lba;
1233 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
1234 bytep[i++] = request->u.ata.lba >> 8;
1235 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
1236 bytep[i++] = request->u.ata.lba >> 16;
1237 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
1238 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) |
1239 ((request->u.ata.lba >> 24)&0xf);
1240 }
1241 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
1242 bytep[i++] = request->u.ata.command;
1243 return i;
1244 }
1245
1246 static void
ata_promise_queue_hpkt(struct ata_pci_controller * ctlr,u_int32_t hpkt)1247 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
1248 {
1249 struct ata_promise_sx4 *hpktp = ctlr->chipset_data;
1250
1251 mtx_lock(&hpktp->mtx);
1252 if (hpktp->busy) {
1253 struct host_packet *hp =
1254 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO);
1255 hp->addr = hpkt;
1256 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
1257 }
1258 else {
1259 hpktp->busy = 1;
1260 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
1261 }
1262 mtx_unlock(&hpktp->mtx);
1263 }
1264
1265 static void
ata_promise_next_hpkt(struct ata_pci_controller * ctlr)1266 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
1267 {
1268 struct ata_promise_sx4 *hpktp = ctlr->chipset_data;
1269 struct host_packet *hp;
1270
1271 mtx_lock(&hpktp->mtx);
1272 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
1273 TAILQ_REMOVE(&hpktp->queue, hp, chain);
1274 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
1275 free(hp, M_TEMP);
1276 }
1277 else
1278 hpktp->busy = 0;
1279 mtx_unlock(&hpktp->mtx);
1280 }
1281
1282 ATA_DECLARE_DRIVER(ata_promise);
1283