1 /*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/mbuf.h>
40 #include <sys/rman.h>
41 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
47
48 #include <net/bpf.h>
49 #include <net/if.h>
50 #include <net/if_var.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
57
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
62
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68
69 #include <machine/bus.h>
70 #include <machine/in_cksum.h>
71
72 #include <dev/age/if_agereg.h>
73 #include <dev/age/if_agevar.h>
74
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
77
78 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
79
80 MODULE_DEPEND(age, pci, 1, 1, 1);
81 MODULE_DEPEND(age, ether, 1, 1, 1);
82 MODULE_DEPEND(age, miibus, 1, 1, 1);
83
84 /* Tunables. */
85 static int msi_disable = 0;
86 static int msix_disable = 0;
87 TUNABLE_INT("hw.age.msi_disable", &msi_disable);
88 TUNABLE_INT("hw.age.msix_disable", &msix_disable);
89
90 /*
91 * Devices supported by this driver.
92 */
93 static struct age_dev {
94 uint16_t age_vendorid;
95 uint16_t age_deviceid;
96 const char *age_name;
97 } age_devs[] = {
98 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
99 "Attansic Technology Corp, L1 Gigabit Ethernet" },
100 };
101
102 static int age_miibus_readreg(device_t, int, int);
103 static int age_miibus_writereg(device_t, int, int, int);
104 static void age_miibus_statchg(device_t);
105 static void age_mediastatus(struct ifnet *, struct ifmediareq *);
106 static int age_mediachange(struct ifnet *);
107 static int age_probe(device_t);
108 static void age_get_macaddr(struct age_softc *);
109 static void age_phy_reset(struct age_softc *);
110 static int age_attach(device_t);
111 static int age_detach(device_t);
112 static void age_sysctl_node(struct age_softc *);
113 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
114 static int age_check_boundary(struct age_softc *);
115 static int age_dma_alloc(struct age_softc *);
116 static void age_dma_free(struct age_softc *);
117 static int age_shutdown(device_t);
118 static void age_setwol(struct age_softc *);
119 static int age_suspend(device_t);
120 static int age_resume(device_t);
121 static int age_encap(struct age_softc *, struct mbuf **);
122 static void age_start(struct ifnet *);
123 static void age_start_locked(struct ifnet *);
124 static void age_watchdog(struct age_softc *);
125 static int age_ioctl(struct ifnet *, u_long, caddr_t);
126 static void age_mac_config(struct age_softc *);
127 static void age_link_task(void *, int);
128 static void age_stats_update(struct age_softc *);
129 static int age_intr(void *);
130 static void age_int_task(void *, int);
131 static void age_txintr(struct age_softc *, int);
132 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
133 static int age_rxintr(struct age_softc *, int, int);
134 static void age_tick(void *);
135 static void age_reset(struct age_softc *);
136 static void age_init(void *);
137 static void age_init_locked(struct age_softc *);
138 static void age_stop(struct age_softc *);
139 static void age_stop_txmac(struct age_softc *);
140 static void age_stop_rxmac(struct age_softc *);
141 static void age_init_tx_ring(struct age_softc *);
142 static int age_init_rx_ring(struct age_softc *);
143 static void age_init_rr_ring(struct age_softc *);
144 static void age_init_cmb_block(struct age_softc *);
145 static void age_init_smb_block(struct age_softc *);
146 #ifndef __NO_STRICT_ALIGNMENT
147 static struct mbuf *age_fixup_rx(struct ifnet *, struct mbuf *);
148 #endif
149 static int age_newbuf(struct age_softc *, struct age_rxdesc *);
150 static void age_rxvlan(struct age_softc *);
151 static void age_rxfilter(struct age_softc *);
152 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
154 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
155 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
156
157
158 static device_method_t age_methods[] = {
159 /* Device interface. */
160 DEVMETHOD(device_probe, age_probe),
161 DEVMETHOD(device_attach, age_attach),
162 DEVMETHOD(device_detach, age_detach),
163 DEVMETHOD(device_shutdown, age_shutdown),
164 DEVMETHOD(device_suspend, age_suspend),
165 DEVMETHOD(device_resume, age_resume),
166
167 /* MII interface. */
168 DEVMETHOD(miibus_readreg, age_miibus_readreg),
169 DEVMETHOD(miibus_writereg, age_miibus_writereg),
170 DEVMETHOD(miibus_statchg, age_miibus_statchg),
171
172 { NULL, NULL }
173 };
174
175 static driver_t age_driver = {
176 "age",
177 age_methods,
178 sizeof(struct age_softc)
179 };
180
181 static devclass_t age_devclass;
182
183 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0);
184 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0);
185
186 static struct resource_spec age_res_spec_mem[] = {
187 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
188 { -1, 0, 0 }
189 };
190
191 static struct resource_spec age_irq_spec_legacy[] = {
192 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
193 { -1, 0, 0 }
194 };
195
196 static struct resource_spec age_irq_spec_msi[] = {
197 { SYS_RES_IRQ, 1, RF_ACTIVE },
198 { -1, 0, 0 }
199 };
200
201 static struct resource_spec age_irq_spec_msix[] = {
202 { SYS_RES_IRQ, 1, RF_ACTIVE },
203 { -1, 0, 0 }
204 };
205
206 /*
207 * Read a PHY register on the MII of the L1.
208 */
209 static int
age_miibus_readreg(device_t dev,int phy,int reg)210 age_miibus_readreg(device_t dev, int phy, int reg)
211 {
212 struct age_softc *sc;
213 uint32_t v;
214 int i;
215
216 sc = device_get_softc(dev);
217
218 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
219 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
220 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
221 DELAY(1);
222 v = CSR_READ_4(sc, AGE_MDIO);
223 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
224 break;
225 }
226
227 if (i == 0) {
228 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
229 return (0);
230 }
231
232 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
233 }
234
235 /*
236 * Write a PHY register on the MII of the L1.
237 */
238 static int
age_miibus_writereg(device_t dev,int phy,int reg,int val)239 age_miibus_writereg(device_t dev, int phy, int reg, int val)
240 {
241 struct age_softc *sc;
242 uint32_t v;
243 int i;
244
245 sc = device_get_softc(dev);
246
247 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
248 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
249 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
250 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
251 DELAY(1);
252 v = CSR_READ_4(sc, AGE_MDIO);
253 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
254 break;
255 }
256
257 if (i == 0)
258 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
259
260 return (0);
261 }
262
263 /*
264 * Callback from MII layer when media changes.
265 */
266 static void
age_miibus_statchg(device_t dev)267 age_miibus_statchg(device_t dev)
268 {
269 struct age_softc *sc;
270
271 sc = device_get_softc(dev);
272 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
273 }
274
275 /*
276 * Get the current interface media status.
277 */
278 static void
age_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)279 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
280 {
281 struct age_softc *sc;
282 struct mii_data *mii;
283
284 sc = ifp->if_softc;
285 AGE_LOCK(sc);
286 mii = device_get_softc(sc->age_miibus);
287
288 mii_pollstat(mii);
289 ifmr->ifm_status = mii->mii_media_status;
290 ifmr->ifm_active = mii->mii_media_active;
291 AGE_UNLOCK(sc);
292 }
293
294 /*
295 * Set hardware to newly-selected media.
296 */
297 static int
age_mediachange(struct ifnet * ifp)298 age_mediachange(struct ifnet *ifp)
299 {
300 struct age_softc *sc;
301 struct mii_data *mii;
302 struct mii_softc *miisc;
303 int error;
304
305 sc = ifp->if_softc;
306 AGE_LOCK(sc);
307 mii = device_get_softc(sc->age_miibus);
308 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
309 PHY_RESET(miisc);
310 error = mii_mediachg(mii);
311 AGE_UNLOCK(sc);
312
313 return (error);
314 }
315
316 static int
age_probe(device_t dev)317 age_probe(device_t dev)
318 {
319 struct age_dev *sp;
320 int i;
321 uint16_t vendor, devid;
322
323 vendor = pci_get_vendor(dev);
324 devid = pci_get_device(dev);
325 sp = age_devs;
326 for (i = 0; i < nitems(age_devs); i++, sp++) {
327 if (vendor == sp->age_vendorid &&
328 devid == sp->age_deviceid) {
329 device_set_desc(dev, sp->age_name);
330 return (BUS_PROBE_DEFAULT);
331 }
332 }
333
334 return (ENXIO);
335 }
336
337 static void
age_get_macaddr(struct age_softc * sc)338 age_get_macaddr(struct age_softc *sc)
339 {
340 uint32_t ea[2], reg;
341 int i, vpdc;
342
343 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
344 if ((reg & SPI_VPD_ENB) != 0) {
345 /* Get VPD stored in TWSI EEPROM. */
346 reg &= ~SPI_VPD_ENB;
347 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
348 }
349
350 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
351 /*
352 * PCI VPD capability found, let TWSI reload EEPROM.
353 * This will set ethernet address of controller.
354 */
355 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
356 TWSI_CTRL_SW_LD_START);
357 for (i = 100; i > 0; i--) {
358 DELAY(1000);
359 reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
360 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
361 break;
362 }
363 if (i == 0)
364 device_printf(sc->age_dev,
365 "reloading EEPROM timeout!\n");
366 } else {
367 if (bootverbose)
368 device_printf(sc->age_dev,
369 "PCI VPD capability not found!\n");
370 }
371
372 ea[0] = CSR_READ_4(sc, AGE_PAR0);
373 ea[1] = CSR_READ_4(sc, AGE_PAR1);
374 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
375 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
376 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
377 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
378 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
379 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
380 }
381
382 static void
age_phy_reset(struct age_softc * sc)383 age_phy_reset(struct age_softc *sc)
384 {
385 uint16_t reg, pn;
386 int i, linkup;
387
388 /* Reset PHY. */
389 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
390 DELAY(2000);
391 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
392 DELAY(2000);
393
394 #define ATPHY_DBG_ADDR 0x1D
395 #define ATPHY_DBG_DATA 0x1E
396 #define ATPHY_CDTC 0x16
397 #define PHY_CDTC_ENB 0x0001
398 #define PHY_CDTC_POFF 8
399 #define ATPHY_CDTS 0x1C
400 #define PHY_CDTS_STAT_OK 0x0000
401 #define PHY_CDTS_STAT_SHORT 0x0100
402 #define PHY_CDTS_STAT_OPEN 0x0200
403 #define PHY_CDTS_STAT_INVAL 0x0300
404 #define PHY_CDTS_STAT_MASK 0x0300
405
406 /* Check power saving mode. Magic from Linux. */
407 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
408 for (linkup = 0, pn = 0; pn < 4; pn++) {
409 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
410 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
411 for (i = 200; i > 0; i--) {
412 DELAY(1000);
413 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
414 ATPHY_CDTC);
415 if ((reg & PHY_CDTC_ENB) == 0)
416 break;
417 }
418 DELAY(1000);
419 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
420 ATPHY_CDTS);
421 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
422 linkup++;
423 break;
424 }
425 }
426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
427 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
428 if (linkup == 0) {
429 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
430 ATPHY_DBG_ADDR, 0);
431 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
432 ATPHY_DBG_DATA, 0x124E);
433 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
434 ATPHY_DBG_ADDR, 1);
435 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
436 ATPHY_DBG_DATA);
437 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
438 ATPHY_DBG_DATA, reg | 0x03);
439 /* XXX */
440 DELAY(1500 * 1000);
441 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
442 ATPHY_DBG_ADDR, 0);
443 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
444 ATPHY_DBG_DATA, 0x024E);
445 }
446
447 #undef ATPHY_DBG_ADDR
448 #undef ATPHY_DBG_DATA
449 #undef ATPHY_CDTC
450 #undef PHY_CDTC_ENB
451 #undef PHY_CDTC_POFF
452 #undef ATPHY_CDTS
453 #undef PHY_CDTS_STAT_OK
454 #undef PHY_CDTS_STAT_SHORT
455 #undef PHY_CDTS_STAT_OPEN
456 #undef PHY_CDTS_STAT_INVAL
457 #undef PHY_CDTS_STAT_MASK
458 }
459
460 static int
age_attach(device_t dev)461 age_attach(device_t dev)
462 {
463 struct age_softc *sc;
464 struct ifnet *ifp;
465 uint16_t burst;
466 int error, i, msic, msixc, pmc;
467
468 error = 0;
469 sc = device_get_softc(dev);
470 sc->age_dev = dev;
471
472 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
473 MTX_DEF);
474 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
475 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
476 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
477
478 /* Map the device. */
479 pci_enable_busmaster(dev);
480 sc->age_res_spec = age_res_spec_mem;
481 sc->age_irq_spec = age_irq_spec_legacy;
482 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
483 if (error != 0) {
484 device_printf(dev, "cannot allocate memory resources.\n");
485 goto fail;
486 }
487
488 /* Set PHY address. */
489 sc->age_phyaddr = AGE_PHY_ADDR;
490
491 /* Reset PHY. */
492 age_phy_reset(sc);
493
494 /* Reset the ethernet controller. */
495 age_reset(sc);
496
497 /* Get PCI and chip id/revision. */
498 sc->age_rev = pci_get_revid(dev);
499 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
500 MASTER_CHIP_REV_SHIFT;
501 if (bootverbose) {
502 device_printf(dev, "PCI device revision : 0x%04x\n",
503 sc->age_rev);
504 device_printf(dev, "Chip id/revision : 0x%04x\n",
505 sc->age_chip_rev);
506 }
507
508 /*
509 * XXX
510 * Unintialized hardware returns an invalid chip id/revision
511 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
512 * unplugged cable results in putting hardware into automatic
513 * power down mode which in turn returns invalld chip revision.
514 */
515 if (sc->age_chip_rev == 0xFFFF) {
516 device_printf(dev,"invalid chip revision : 0x%04x -- "
517 "not initialized?\n", sc->age_chip_rev);
518 error = ENXIO;
519 goto fail;
520 }
521
522 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
523 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
524 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
525
526 /* Allocate IRQ resources. */
527 msixc = pci_msix_count(dev);
528 msic = pci_msi_count(dev);
529 if (bootverbose) {
530 device_printf(dev, "MSIX count : %d\n", msixc);
531 device_printf(dev, "MSI count : %d\n", msic);
532 }
533
534 /* Prefer MSIX over MSI. */
535 if (msix_disable == 0 || msi_disable == 0) {
536 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
537 pci_alloc_msix(dev, &msixc) == 0) {
538 if (msic == AGE_MSIX_MESSAGES) {
539 device_printf(dev, "Using %d MSIX messages.\n",
540 msixc);
541 sc->age_flags |= AGE_FLAG_MSIX;
542 sc->age_irq_spec = age_irq_spec_msix;
543 } else
544 pci_release_msi(dev);
545 }
546 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
547 msic == AGE_MSI_MESSAGES &&
548 pci_alloc_msi(dev, &msic) == 0) {
549 if (msic == AGE_MSI_MESSAGES) {
550 device_printf(dev, "Using %d MSI messages.\n",
551 msic);
552 sc->age_flags |= AGE_FLAG_MSI;
553 sc->age_irq_spec = age_irq_spec_msi;
554 } else
555 pci_release_msi(dev);
556 }
557 }
558
559 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
560 if (error != 0) {
561 device_printf(dev, "cannot allocate IRQ resources.\n");
562 goto fail;
563 }
564
565
566 /* Get DMA parameters from PCIe device control register. */
567 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
568 sc->age_flags |= AGE_FLAG_PCIE;
569 burst = pci_read_config(dev, i + 0x08, 2);
570 /* Max read request size. */
571 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
572 DMA_CFG_RD_BURST_SHIFT;
573 /* Max payload size. */
574 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
575 DMA_CFG_WR_BURST_SHIFT;
576 if (bootverbose) {
577 device_printf(dev, "Read request size : %d bytes.\n",
578 128 << ((burst >> 12) & 0x07));
579 device_printf(dev, "TLP payload size : %d bytes.\n",
580 128 << ((burst >> 5) & 0x07));
581 }
582 } else {
583 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
584 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
585 }
586
587 /* Create device sysctl node. */
588 age_sysctl_node(sc);
589
590 if ((error = age_dma_alloc(sc)) != 0)
591 goto fail;
592
593 /* Load station address. */
594 age_get_macaddr(sc);
595
596 ifp = sc->age_ifp = if_alloc(IFT_ETHER);
597 if (ifp == NULL) {
598 device_printf(dev, "cannot allocate ifnet structure.\n");
599 error = ENXIO;
600 goto fail;
601 }
602
603 ifp->if_softc = sc;
604 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
606 ifp->if_ioctl = age_ioctl;
607 ifp->if_start = age_start;
608 ifp->if_init = age_init;
609 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1;
610 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
611 IFQ_SET_READY(&ifp->if_snd);
612 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
613 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO;
614 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
615 sc->age_flags |= AGE_FLAG_PMCAP;
616 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
617 }
618 ifp->if_capenable = ifp->if_capabilities;
619
620 /* Set up MII bus. */
621 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange,
622 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
623 0);
624 if (error != 0) {
625 device_printf(dev, "attaching PHYs failed\n");
626 goto fail;
627 }
628
629 ether_ifattach(ifp, sc->age_eaddr);
630
631 /* VLAN capability setup. */
632 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
633 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
634 ifp->if_capenable = ifp->if_capabilities;
635
636 /* Tell the upper layer(s) we support long frames. */
637 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
638
639 /* Create local taskq. */
640 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
641 taskqueue_thread_enqueue, &sc->age_tq);
642 if (sc->age_tq == NULL) {
643 device_printf(dev, "could not create taskqueue.\n");
644 ether_ifdetach(ifp);
645 error = ENXIO;
646 goto fail;
647 }
648 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
649 device_get_nameunit(sc->age_dev));
650
651 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
652 msic = AGE_MSIX_MESSAGES;
653 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
654 msic = AGE_MSI_MESSAGES;
655 else
656 msic = 1;
657 for (i = 0; i < msic; i++) {
658 error = bus_setup_intr(dev, sc->age_irq[i],
659 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
660 &sc->age_intrhand[i]);
661 if (error != 0)
662 break;
663 }
664 if (error != 0) {
665 device_printf(dev, "could not set up interrupt handler.\n");
666 taskqueue_free(sc->age_tq);
667 sc->age_tq = NULL;
668 ether_ifdetach(ifp);
669 goto fail;
670 }
671
672 fail:
673 if (error != 0)
674 age_detach(dev);
675
676 return (error);
677 }
678
679 static int
age_detach(device_t dev)680 age_detach(device_t dev)
681 {
682 struct age_softc *sc;
683 struct ifnet *ifp;
684 int i, msic;
685
686 sc = device_get_softc(dev);
687
688 ifp = sc->age_ifp;
689 if (device_is_attached(dev)) {
690 AGE_LOCK(sc);
691 sc->age_flags |= AGE_FLAG_DETACH;
692 age_stop(sc);
693 AGE_UNLOCK(sc);
694 callout_drain(&sc->age_tick_ch);
695 taskqueue_drain(sc->age_tq, &sc->age_int_task);
696 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
697 ether_ifdetach(ifp);
698 }
699
700 if (sc->age_tq != NULL) {
701 taskqueue_drain(sc->age_tq, &sc->age_int_task);
702 taskqueue_free(sc->age_tq);
703 sc->age_tq = NULL;
704 }
705
706 if (sc->age_miibus != NULL) {
707 device_delete_child(dev, sc->age_miibus);
708 sc->age_miibus = NULL;
709 }
710 bus_generic_detach(dev);
711 age_dma_free(sc);
712
713 if (ifp != NULL) {
714 if_free(ifp);
715 sc->age_ifp = NULL;
716 }
717
718 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
719 msic = AGE_MSIX_MESSAGES;
720 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
721 msic = AGE_MSI_MESSAGES;
722 else
723 msic = 1;
724 for (i = 0; i < msic; i++) {
725 if (sc->age_intrhand[i] != NULL) {
726 bus_teardown_intr(dev, sc->age_irq[i],
727 sc->age_intrhand[i]);
728 sc->age_intrhand[i] = NULL;
729 }
730 }
731
732 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
733 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
734 pci_release_msi(dev);
735 bus_release_resources(dev, sc->age_res_spec, sc->age_res);
736 mtx_destroy(&sc->age_mtx);
737
738 return (0);
739 }
740
741 static void
age_sysctl_node(struct age_softc * sc)742 age_sysctl_node(struct age_softc *sc)
743 {
744 int error;
745
746 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
747 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
748 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats,
749 "I", "Statistics");
750
751 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
752 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
753 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0,
754 sysctl_hw_age_int_mod, "I", "age interrupt moderation");
755
756 /* Pull in device tunables. */
757 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
758 error = resource_int_value(device_get_name(sc->age_dev),
759 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
760 if (error == 0) {
761 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
762 sc->age_int_mod > AGE_IM_TIMER_MAX) {
763 device_printf(sc->age_dev,
764 "int_mod value out of range; using default: %d\n",
765 AGE_IM_TIMER_DEFAULT);
766 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
767 }
768 }
769
770 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
771 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
772 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit,
773 0, sysctl_hw_age_proc_limit, "I",
774 "max number of Rx events to process");
775
776 /* Pull in device tunables. */
777 sc->age_process_limit = AGE_PROC_DEFAULT;
778 error = resource_int_value(device_get_name(sc->age_dev),
779 device_get_unit(sc->age_dev), "process_limit",
780 &sc->age_process_limit);
781 if (error == 0) {
782 if (sc->age_process_limit < AGE_PROC_MIN ||
783 sc->age_process_limit > AGE_PROC_MAX) {
784 device_printf(sc->age_dev,
785 "process_limit value out of range; "
786 "using default: %d\n", AGE_PROC_DEFAULT);
787 sc->age_process_limit = AGE_PROC_DEFAULT;
788 }
789 }
790 }
791
792 struct age_dmamap_arg {
793 bus_addr_t age_busaddr;
794 };
795
796 static void
age_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)797 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
798 {
799 struct age_dmamap_arg *ctx;
800
801 if (error != 0)
802 return;
803
804 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
805
806 ctx = (struct age_dmamap_arg *)arg;
807 ctx->age_busaddr = segs[0].ds_addr;
808 }
809
810 /*
811 * Attansic L1 controller have single register to specify high
812 * address part of DMA blocks. So all descriptor structures and
813 * DMA memory blocks should have the same high address of given
814 * 4GB address space(i.e. crossing 4GB boundary is not allowed).
815 */
816 static int
age_check_boundary(struct age_softc * sc)817 age_check_boundary(struct age_softc *sc)
818 {
819 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
820 bus_addr_t cmb_block_end, smb_block_end;
821
822 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
823 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
824 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
825 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
826 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
827 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
828
829 if ((AGE_ADDR_HI(tx_ring_end) !=
830 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
831 (AGE_ADDR_HI(rx_ring_end) !=
832 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
833 (AGE_ADDR_HI(rr_ring_end) !=
834 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
835 (AGE_ADDR_HI(cmb_block_end) !=
836 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
837 (AGE_ADDR_HI(smb_block_end) !=
838 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
839 return (EFBIG);
840
841 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
842 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
843 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
844 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
845 return (EFBIG);
846
847 return (0);
848 }
849
850 static int
age_dma_alloc(struct age_softc * sc)851 age_dma_alloc(struct age_softc *sc)
852 {
853 struct age_txdesc *txd;
854 struct age_rxdesc *rxd;
855 bus_addr_t lowaddr;
856 struct age_dmamap_arg ctx;
857 int error, i;
858
859 lowaddr = BUS_SPACE_MAXADDR;
860
861 again:
862 /* Create parent ring/DMA block tag. */
863 error = bus_dma_tag_create(
864 bus_get_dma_tag(sc->age_dev), /* parent */
865 1, 0, /* alignment, boundary */
866 lowaddr, /* lowaddr */
867 BUS_SPACE_MAXADDR, /* highaddr */
868 NULL, NULL, /* filter, filterarg */
869 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
870 0, /* nsegments */
871 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
872 0, /* flags */
873 NULL, NULL, /* lockfunc, lockarg */
874 &sc->age_cdata.age_parent_tag);
875 if (error != 0) {
876 device_printf(sc->age_dev,
877 "could not create parent DMA tag.\n");
878 goto fail;
879 }
880
881 /* Create tag for Tx ring. */
882 error = bus_dma_tag_create(
883 sc->age_cdata.age_parent_tag, /* parent */
884 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */
885 BUS_SPACE_MAXADDR, /* lowaddr */
886 BUS_SPACE_MAXADDR, /* highaddr */
887 NULL, NULL, /* filter, filterarg */
888 AGE_TX_RING_SZ, /* maxsize */
889 1, /* nsegments */
890 AGE_TX_RING_SZ, /* maxsegsize */
891 0, /* flags */
892 NULL, NULL, /* lockfunc, lockarg */
893 &sc->age_cdata.age_tx_ring_tag);
894 if (error != 0) {
895 device_printf(sc->age_dev,
896 "could not create Tx ring DMA tag.\n");
897 goto fail;
898 }
899
900 /* Create tag for Rx ring. */
901 error = bus_dma_tag_create(
902 sc->age_cdata.age_parent_tag, /* parent */
903 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */
904 BUS_SPACE_MAXADDR, /* lowaddr */
905 BUS_SPACE_MAXADDR, /* highaddr */
906 NULL, NULL, /* filter, filterarg */
907 AGE_RX_RING_SZ, /* maxsize */
908 1, /* nsegments */
909 AGE_RX_RING_SZ, /* maxsegsize */
910 0, /* flags */
911 NULL, NULL, /* lockfunc, lockarg */
912 &sc->age_cdata.age_rx_ring_tag);
913 if (error != 0) {
914 device_printf(sc->age_dev,
915 "could not create Rx ring DMA tag.\n");
916 goto fail;
917 }
918
919 /* Create tag for Rx return ring. */
920 error = bus_dma_tag_create(
921 sc->age_cdata.age_parent_tag, /* parent */
922 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */
923 BUS_SPACE_MAXADDR, /* lowaddr */
924 BUS_SPACE_MAXADDR, /* highaddr */
925 NULL, NULL, /* filter, filterarg */
926 AGE_RR_RING_SZ, /* maxsize */
927 1, /* nsegments */
928 AGE_RR_RING_SZ, /* maxsegsize */
929 0, /* flags */
930 NULL, NULL, /* lockfunc, lockarg */
931 &sc->age_cdata.age_rr_ring_tag);
932 if (error != 0) {
933 device_printf(sc->age_dev,
934 "could not create Rx return ring DMA tag.\n");
935 goto fail;
936 }
937
938 /* Create tag for coalesing message block. */
939 error = bus_dma_tag_create(
940 sc->age_cdata.age_parent_tag, /* parent */
941 AGE_CMB_ALIGN, 0, /* alignment, boundary */
942 BUS_SPACE_MAXADDR, /* lowaddr */
943 BUS_SPACE_MAXADDR, /* highaddr */
944 NULL, NULL, /* filter, filterarg */
945 AGE_CMB_BLOCK_SZ, /* maxsize */
946 1, /* nsegments */
947 AGE_CMB_BLOCK_SZ, /* maxsegsize */
948 0, /* flags */
949 NULL, NULL, /* lockfunc, lockarg */
950 &sc->age_cdata.age_cmb_block_tag);
951 if (error != 0) {
952 device_printf(sc->age_dev,
953 "could not create CMB DMA tag.\n");
954 goto fail;
955 }
956
957 /* Create tag for statistics message block. */
958 error = bus_dma_tag_create(
959 sc->age_cdata.age_parent_tag, /* parent */
960 AGE_SMB_ALIGN, 0, /* alignment, boundary */
961 BUS_SPACE_MAXADDR, /* lowaddr */
962 BUS_SPACE_MAXADDR, /* highaddr */
963 NULL, NULL, /* filter, filterarg */
964 AGE_SMB_BLOCK_SZ, /* maxsize */
965 1, /* nsegments */
966 AGE_SMB_BLOCK_SZ, /* maxsegsize */
967 0, /* flags */
968 NULL, NULL, /* lockfunc, lockarg */
969 &sc->age_cdata.age_smb_block_tag);
970 if (error != 0) {
971 device_printf(sc->age_dev,
972 "could not create SMB DMA tag.\n");
973 goto fail;
974 }
975
976 /* Allocate DMA'able memory and load the DMA map. */
977 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
978 (void **)&sc->age_rdata.age_tx_ring,
979 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
980 &sc->age_cdata.age_tx_ring_map);
981 if (error != 0) {
982 device_printf(sc->age_dev,
983 "could not allocate DMA'able memory for Tx ring.\n");
984 goto fail;
985 }
986 ctx.age_busaddr = 0;
987 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
988 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
989 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
990 if (error != 0 || ctx.age_busaddr == 0) {
991 device_printf(sc->age_dev,
992 "could not load DMA'able memory for Tx ring.\n");
993 goto fail;
994 }
995 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
996 /* Rx ring */
997 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
998 (void **)&sc->age_rdata.age_rx_ring,
999 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1000 &sc->age_cdata.age_rx_ring_map);
1001 if (error != 0) {
1002 device_printf(sc->age_dev,
1003 "could not allocate DMA'able memory for Rx ring.\n");
1004 goto fail;
1005 }
1006 ctx.age_busaddr = 0;
1007 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
1008 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
1009 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
1010 if (error != 0 || ctx.age_busaddr == 0) {
1011 device_printf(sc->age_dev,
1012 "could not load DMA'able memory for Rx ring.\n");
1013 goto fail;
1014 }
1015 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
1016 /* Rx return ring */
1017 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
1018 (void **)&sc->age_rdata.age_rr_ring,
1019 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1020 &sc->age_cdata.age_rr_ring_map);
1021 if (error != 0) {
1022 device_printf(sc->age_dev,
1023 "could not allocate DMA'able memory for Rx return ring.\n");
1024 goto fail;
1025 }
1026 ctx.age_busaddr = 0;
1027 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1028 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1029 AGE_RR_RING_SZ, age_dmamap_cb,
1030 &ctx, 0);
1031 if (error != 0 || ctx.age_busaddr == 0) {
1032 device_printf(sc->age_dev,
1033 "could not load DMA'able memory for Rx return ring.\n");
1034 goto fail;
1035 }
1036 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1037 /* CMB block */
1038 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1039 (void **)&sc->age_rdata.age_cmb_block,
1040 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1041 &sc->age_cdata.age_cmb_block_map);
1042 if (error != 0) {
1043 device_printf(sc->age_dev,
1044 "could not allocate DMA'able memory for CMB block.\n");
1045 goto fail;
1046 }
1047 ctx.age_busaddr = 0;
1048 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1049 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1050 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1051 if (error != 0 || ctx.age_busaddr == 0) {
1052 device_printf(sc->age_dev,
1053 "could not load DMA'able memory for CMB block.\n");
1054 goto fail;
1055 }
1056 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1057 /* SMB block */
1058 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1059 (void **)&sc->age_rdata.age_smb_block,
1060 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1061 &sc->age_cdata.age_smb_block_map);
1062 if (error != 0) {
1063 device_printf(sc->age_dev,
1064 "could not allocate DMA'able memory for SMB block.\n");
1065 goto fail;
1066 }
1067 ctx.age_busaddr = 0;
1068 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1069 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1070 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1071 if (error != 0 || ctx.age_busaddr == 0) {
1072 device_printf(sc->age_dev,
1073 "could not load DMA'able memory for SMB block.\n");
1074 goto fail;
1075 }
1076 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1077
1078 /*
1079 * All ring buffer and DMA blocks should have the same
1080 * high address part of 64bit DMA address space.
1081 */
1082 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1083 (error = age_check_boundary(sc)) != 0) {
1084 device_printf(sc->age_dev, "4GB boundary crossed, "
1085 "switching to 32bit DMA addressing mode.\n");
1086 age_dma_free(sc);
1087 /* Limit DMA address space to 32bit and try again. */
1088 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1089 goto again;
1090 }
1091
1092 /*
1093 * Create Tx/Rx buffer parent tag.
1094 * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1095 * so it needs separate parent DMA tag.
1096 * XXX
1097 * It seems enabling 64bit DMA causes data corruption. Limit
1098 * DMA address space to 32bit.
1099 */
1100 error = bus_dma_tag_create(
1101 bus_get_dma_tag(sc->age_dev), /* parent */
1102 1, 0, /* alignment, boundary */
1103 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1104 BUS_SPACE_MAXADDR, /* highaddr */
1105 NULL, NULL, /* filter, filterarg */
1106 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1107 0, /* nsegments */
1108 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1109 0, /* flags */
1110 NULL, NULL, /* lockfunc, lockarg */
1111 &sc->age_cdata.age_buffer_tag);
1112 if (error != 0) {
1113 device_printf(sc->age_dev,
1114 "could not create parent buffer DMA tag.\n");
1115 goto fail;
1116 }
1117
1118 /* Create tag for Tx buffers. */
1119 error = bus_dma_tag_create(
1120 sc->age_cdata.age_buffer_tag, /* parent */
1121 1, 0, /* alignment, boundary */
1122 BUS_SPACE_MAXADDR, /* lowaddr */
1123 BUS_SPACE_MAXADDR, /* highaddr */
1124 NULL, NULL, /* filter, filterarg */
1125 AGE_TSO_MAXSIZE, /* maxsize */
1126 AGE_MAXTXSEGS, /* nsegments */
1127 AGE_TSO_MAXSEGSIZE, /* maxsegsize */
1128 0, /* flags */
1129 NULL, NULL, /* lockfunc, lockarg */
1130 &sc->age_cdata.age_tx_tag);
1131 if (error != 0) {
1132 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1133 goto fail;
1134 }
1135
1136 /* Create tag for Rx buffers. */
1137 error = bus_dma_tag_create(
1138 sc->age_cdata.age_buffer_tag, /* parent */
1139 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */
1140 BUS_SPACE_MAXADDR, /* lowaddr */
1141 BUS_SPACE_MAXADDR, /* highaddr */
1142 NULL, NULL, /* filter, filterarg */
1143 MCLBYTES, /* maxsize */
1144 1, /* nsegments */
1145 MCLBYTES, /* maxsegsize */
1146 0, /* flags */
1147 NULL, NULL, /* lockfunc, lockarg */
1148 &sc->age_cdata.age_rx_tag);
1149 if (error != 0) {
1150 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1151 goto fail;
1152 }
1153
1154 /* Create DMA maps for Tx buffers. */
1155 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1156 txd = &sc->age_cdata.age_txdesc[i];
1157 txd->tx_m = NULL;
1158 txd->tx_dmamap = NULL;
1159 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1160 &txd->tx_dmamap);
1161 if (error != 0) {
1162 device_printf(sc->age_dev,
1163 "could not create Tx dmamap.\n");
1164 goto fail;
1165 }
1166 }
1167 /* Create DMA maps for Rx buffers. */
1168 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1169 &sc->age_cdata.age_rx_sparemap)) != 0) {
1170 device_printf(sc->age_dev,
1171 "could not create spare Rx dmamap.\n");
1172 goto fail;
1173 }
1174 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1175 rxd = &sc->age_cdata.age_rxdesc[i];
1176 rxd->rx_m = NULL;
1177 rxd->rx_dmamap = NULL;
1178 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1179 &rxd->rx_dmamap);
1180 if (error != 0) {
1181 device_printf(sc->age_dev,
1182 "could not create Rx dmamap.\n");
1183 goto fail;
1184 }
1185 }
1186
1187 fail:
1188 return (error);
1189 }
1190
1191 static void
age_dma_free(struct age_softc * sc)1192 age_dma_free(struct age_softc *sc)
1193 {
1194 struct age_txdesc *txd;
1195 struct age_rxdesc *rxd;
1196 int i;
1197
1198 /* Tx buffers */
1199 if (sc->age_cdata.age_tx_tag != NULL) {
1200 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1201 txd = &sc->age_cdata.age_txdesc[i];
1202 if (txd->tx_dmamap != NULL) {
1203 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1204 txd->tx_dmamap);
1205 txd->tx_dmamap = NULL;
1206 }
1207 }
1208 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1209 sc->age_cdata.age_tx_tag = NULL;
1210 }
1211 /* Rx buffers */
1212 if (sc->age_cdata.age_rx_tag != NULL) {
1213 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1214 rxd = &sc->age_cdata.age_rxdesc[i];
1215 if (rxd->rx_dmamap != NULL) {
1216 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1217 rxd->rx_dmamap);
1218 rxd->rx_dmamap = NULL;
1219 }
1220 }
1221 if (sc->age_cdata.age_rx_sparemap != NULL) {
1222 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1223 sc->age_cdata.age_rx_sparemap);
1224 sc->age_cdata.age_rx_sparemap = NULL;
1225 }
1226 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1227 sc->age_cdata.age_rx_tag = NULL;
1228 }
1229 /* Tx ring. */
1230 if (sc->age_cdata.age_tx_ring_tag != NULL) {
1231 if (sc->age_rdata.age_tx_ring_paddr != 0)
1232 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1233 sc->age_cdata.age_tx_ring_map);
1234 if (sc->age_rdata.age_tx_ring != NULL)
1235 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1236 sc->age_rdata.age_tx_ring,
1237 sc->age_cdata.age_tx_ring_map);
1238 sc->age_rdata.age_tx_ring_paddr = 0;
1239 sc->age_rdata.age_tx_ring = NULL;
1240 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1241 sc->age_cdata.age_tx_ring_tag = NULL;
1242 }
1243 /* Rx ring. */
1244 if (sc->age_cdata.age_rx_ring_tag != NULL) {
1245 if (sc->age_rdata.age_rx_ring_paddr != 0)
1246 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1247 sc->age_cdata.age_rx_ring_map);
1248 if (sc->age_rdata.age_rx_ring != NULL)
1249 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1250 sc->age_rdata.age_rx_ring,
1251 sc->age_cdata.age_rx_ring_map);
1252 sc->age_rdata.age_rx_ring_paddr = 0;
1253 sc->age_rdata.age_rx_ring = NULL;
1254 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1255 sc->age_cdata.age_rx_ring_tag = NULL;
1256 }
1257 /* Rx return ring. */
1258 if (sc->age_cdata.age_rr_ring_tag != NULL) {
1259 if (sc->age_rdata.age_rr_ring_paddr != 0)
1260 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1261 sc->age_cdata.age_rr_ring_map);
1262 if (sc->age_rdata.age_rr_ring != NULL)
1263 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1264 sc->age_rdata.age_rr_ring,
1265 sc->age_cdata.age_rr_ring_map);
1266 sc->age_rdata.age_rr_ring_paddr = 0;
1267 sc->age_rdata.age_rr_ring = NULL;
1268 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1269 sc->age_cdata.age_rr_ring_tag = NULL;
1270 }
1271 /* CMB block */
1272 if (sc->age_cdata.age_cmb_block_tag != NULL) {
1273 if (sc->age_rdata.age_cmb_block_paddr != 0)
1274 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1275 sc->age_cdata.age_cmb_block_map);
1276 if (sc->age_rdata.age_cmb_block != NULL)
1277 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1278 sc->age_rdata.age_cmb_block,
1279 sc->age_cdata.age_cmb_block_map);
1280 sc->age_rdata.age_cmb_block_paddr = 0;
1281 sc->age_rdata.age_cmb_block = NULL;
1282 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1283 sc->age_cdata.age_cmb_block_tag = NULL;
1284 }
1285 /* SMB block */
1286 if (sc->age_cdata.age_smb_block_tag != NULL) {
1287 if (sc->age_rdata.age_smb_block_paddr != 0)
1288 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1289 sc->age_cdata.age_smb_block_map);
1290 if (sc->age_rdata.age_smb_block != NULL)
1291 bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1292 sc->age_rdata.age_smb_block,
1293 sc->age_cdata.age_smb_block_map);
1294 sc->age_rdata.age_smb_block_paddr = 0;
1295 sc->age_rdata.age_smb_block = NULL;
1296 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1297 sc->age_cdata.age_smb_block_tag = NULL;
1298 }
1299
1300 if (sc->age_cdata.age_buffer_tag != NULL) {
1301 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1302 sc->age_cdata.age_buffer_tag = NULL;
1303 }
1304 if (sc->age_cdata.age_parent_tag != NULL) {
1305 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1306 sc->age_cdata.age_parent_tag = NULL;
1307 }
1308 }
1309
1310 /*
1311 * Make sure the interface is stopped at reboot time.
1312 */
1313 static int
age_shutdown(device_t dev)1314 age_shutdown(device_t dev)
1315 {
1316
1317 return (age_suspend(dev));
1318 }
1319
1320 static void
age_setwol(struct age_softc * sc)1321 age_setwol(struct age_softc *sc)
1322 {
1323 struct ifnet *ifp;
1324 struct mii_data *mii;
1325 uint32_t reg, pmcs;
1326 uint16_t pmstat;
1327 int aneg, i, pmc;
1328
1329 AGE_LOCK_ASSERT(sc);
1330
1331 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1332 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1333 /*
1334 * No PME capability, PHY power down.
1335 * XXX
1336 * Due to an unknown reason powering down PHY resulted
1337 * in unexpected results such as inaccessbility of
1338 * hardware of freshly rebooted system. Disable
1339 * powering down PHY until I got more information for
1340 * Attansic/Atheros PHY hardwares.
1341 */
1342 #ifdef notyet
1343 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1344 MII_BMCR, BMCR_PDOWN);
1345 #endif
1346 return;
1347 }
1348
1349 ifp = sc->age_ifp;
1350 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1351 /*
1352 * Note, this driver resets the link speed to 10/100Mbps with
1353 * auto-negotiation but we don't know whether that operation
1354 * would succeed or not as it have no control after powering
1355 * off. If the renegotiation fail WOL may not work. Running
1356 * at 1Gbps will draw more power than 375mA at 3.3V which is
1357 * specified in PCI specification and that would result in
1358 * complete shutdowning power to ethernet controller.
1359 *
1360 * TODO
1361 * Save current negotiated media speed/duplex/flow-control
1362 * to softc and restore the same link again after resuming.
1363 * PHY handling such as power down/resetting to 100Mbps
1364 * may be better handled in suspend method in phy driver.
1365 */
1366 mii = device_get_softc(sc->age_miibus);
1367 mii_pollstat(mii);
1368 aneg = 0;
1369 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1370 switch IFM_SUBTYPE(mii->mii_media_active) {
1371 case IFM_10_T:
1372 case IFM_100_TX:
1373 goto got_link;
1374 case IFM_1000_T:
1375 aneg++;
1376 default:
1377 break;
1378 }
1379 }
1380 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1381 MII_100T2CR, 0);
1382 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1383 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1384 ANAR_10 | ANAR_CSMA);
1385 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1386 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1387 DELAY(1000);
1388 if (aneg != 0) {
1389 /* Poll link state until age(4) get a 10/100 link. */
1390 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1391 mii_pollstat(mii);
1392 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1393 switch (IFM_SUBTYPE(
1394 mii->mii_media_active)) {
1395 case IFM_10_T:
1396 case IFM_100_TX:
1397 age_mac_config(sc);
1398 goto got_link;
1399 default:
1400 break;
1401 }
1402 }
1403 AGE_UNLOCK(sc);
1404 pause("agelnk", hz);
1405 AGE_LOCK(sc);
1406 }
1407 if (i == MII_ANEGTICKS_GIGE)
1408 device_printf(sc->age_dev,
1409 "establishing link failed, "
1410 "WOL may not work!");
1411 }
1412 /*
1413 * No link, force MAC to have 100Mbps, full-duplex link.
1414 * This is the last resort and may/may not work.
1415 */
1416 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1417 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1418 age_mac_config(sc);
1419 }
1420
1421 got_link:
1422 pmcs = 0;
1423 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1424 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1425 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1426 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1427 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1428 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1429 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1430 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1431 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1432 reg |= MAC_CFG_RX_ENB;
1433 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1434 }
1435
1436 /* Request PME. */
1437 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1438 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1439 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1440 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1441 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1442 #ifdef notyet
1443 /* See above for powering down PHY issues. */
1444 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1445 /* No WOL, PHY power down. */
1446 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1447 MII_BMCR, BMCR_PDOWN);
1448 }
1449 #endif
1450 }
1451
1452 static int
age_suspend(device_t dev)1453 age_suspend(device_t dev)
1454 {
1455 struct age_softc *sc;
1456
1457 sc = device_get_softc(dev);
1458
1459 AGE_LOCK(sc);
1460 age_stop(sc);
1461 age_setwol(sc);
1462 AGE_UNLOCK(sc);
1463
1464 return (0);
1465 }
1466
1467 static int
age_resume(device_t dev)1468 age_resume(device_t dev)
1469 {
1470 struct age_softc *sc;
1471 struct ifnet *ifp;
1472
1473 sc = device_get_softc(dev);
1474
1475 AGE_LOCK(sc);
1476 age_phy_reset(sc);
1477 ifp = sc->age_ifp;
1478 if ((ifp->if_flags & IFF_UP) != 0)
1479 age_init_locked(sc);
1480
1481 AGE_UNLOCK(sc);
1482
1483 return (0);
1484 }
1485
1486 static int
age_encap(struct age_softc * sc,struct mbuf ** m_head)1487 age_encap(struct age_softc *sc, struct mbuf **m_head)
1488 {
1489 struct age_txdesc *txd, *txd_last;
1490 struct tx_desc *desc;
1491 struct mbuf *m;
1492 struct ip *ip;
1493 struct tcphdr *tcp;
1494 bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1495 bus_dmamap_t map;
1496 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1497 int error, i, nsegs, prod, si;
1498
1499 AGE_LOCK_ASSERT(sc);
1500
1501 M_ASSERTPKTHDR((*m_head));
1502
1503 m = *m_head;
1504 ip = NULL;
1505 tcp = NULL;
1506 cflags = vtag = 0;
1507 ip_off = poff = 0;
1508 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1509 /*
1510 * L1 requires offset of TCP/UDP payload in its Tx
1511 * descriptor to perform hardware Tx checksum offload.
1512 * Additionally, TSO requires IP/TCP header size and
1513 * modification of IP/TCP header in order to make TSO
1514 * engine work. This kind of operation takes many CPU
1515 * cycles on FreeBSD so fast host CPU is needed to get
1516 * smooth TSO performance.
1517 */
1518 struct ether_header *eh;
1519
1520 if (M_WRITABLE(m) == 0) {
1521 /* Get a writable copy. */
1522 m = m_dup(*m_head, M_NOWAIT);
1523 /* Release original mbufs. */
1524 m_freem(*m_head);
1525 if (m == NULL) {
1526 *m_head = NULL;
1527 return (ENOBUFS);
1528 }
1529 *m_head = m;
1530 }
1531 ip_off = sizeof(struct ether_header);
1532 m = m_pullup(m, ip_off);
1533 if (m == NULL) {
1534 *m_head = NULL;
1535 return (ENOBUFS);
1536 }
1537 eh = mtod(m, struct ether_header *);
1538 /*
1539 * Check if hardware VLAN insertion is off.
1540 * Additional check for LLC/SNAP frame?
1541 */
1542 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1543 ip_off = sizeof(struct ether_vlan_header);
1544 m = m_pullup(m, ip_off);
1545 if (m == NULL) {
1546 *m_head = NULL;
1547 return (ENOBUFS);
1548 }
1549 }
1550 m = m_pullup(m, ip_off + sizeof(struct ip));
1551 if (m == NULL) {
1552 *m_head = NULL;
1553 return (ENOBUFS);
1554 }
1555 ip = (struct ip *)(mtod(m, char *) + ip_off);
1556 poff = ip_off + (ip->ip_hl << 2);
1557 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1558 m = m_pullup(m, poff + sizeof(struct tcphdr));
1559 if (m == NULL) {
1560 *m_head = NULL;
1561 return (ENOBUFS);
1562 }
1563 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1564 m = m_pullup(m, poff + (tcp->th_off << 2));
1565 if (m == NULL) {
1566 *m_head = NULL;
1567 return (ENOBUFS);
1568 }
1569 /*
1570 * L1 requires IP/TCP header size and offset as
1571 * well as TCP pseudo checksum which complicates
1572 * TSO configuration. I guess this comes from the
1573 * adherence to Microsoft NDIS Large Send
1574 * specification which requires insertion of
1575 * pseudo checksum by upper stack. The pseudo
1576 * checksum that NDIS refers to doesn't include
1577 * TCP payload length so age(4) should recompute
1578 * the pseudo checksum here. Hopefully this wouldn't
1579 * be much burden on modern CPUs.
1580 * Reset IP checksum and recompute TCP pseudo
1581 * checksum as NDIS specification said.
1582 */
1583 ip = (struct ip *)(mtod(m, char *) + ip_off);
1584 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1585 ip->ip_sum = 0;
1586 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1587 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1588 }
1589 *m_head = m;
1590 }
1591
1592 si = prod = sc->age_cdata.age_tx_prod;
1593 txd = &sc->age_cdata.age_txdesc[prod];
1594 txd_last = txd;
1595 map = txd->tx_dmamap;
1596
1597 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1598 *m_head, txsegs, &nsegs, 0);
1599 if (error == EFBIG) {
1600 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS);
1601 if (m == NULL) {
1602 m_freem(*m_head);
1603 *m_head = NULL;
1604 return (ENOMEM);
1605 }
1606 *m_head = m;
1607 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1608 *m_head, txsegs, &nsegs, 0);
1609 if (error != 0) {
1610 m_freem(*m_head);
1611 *m_head = NULL;
1612 return (error);
1613 }
1614 } else if (error != 0)
1615 return (error);
1616 if (nsegs == 0) {
1617 m_freem(*m_head);
1618 *m_head = NULL;
1619 return (EIO);
1620 }
1621
1622 /* Check descriptor overrun. */
1623 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1624 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1625 return (ENOBUFS);
1626 }
1627
1628 m = *m_head;
1629 /* Configure VLAN hardware tag insertion. */
1630 if ((m->m_flags & M_VLANTAG) != 0) {
1631 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1632 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1633 cflags |= AGE_TD_INSERT_VLAN_TAG;
1634 }
1635
1636 desc = NULL;
1637 i = 0;
1638 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1639 /* Request TSO and set MSS. */
1640 cflags |= AGE_TD_TSO_IPV4;
1641 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1642 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1643 AGE_TD_TSO_MSS_SHIFT);
1644 /* Set IP/TCP header size. */
1645 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1646 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1647 /*
1648 * L1 requires the first buffer should only hold IP/TCP
1649 * header data. TCP payload should be handled in other
1650 * descriptors.
1651 */
1652 hdrlen = poff + (tcp->th_off << 2);
1653 desc = &sc->age_rdata.age_tx_ring[prod];
1654 desc->addr = htole64(txsegs[0].ds_addr);
1655 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag);
1656 desc->flags = htole32(cflags);
1657 sc->age_cdata.age_tx_cnt++;
1658 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1659 if (m->m_len - hdrlen > 0) {
1660 /* Handle remaining payload of the 1st fragment. */
1661 desc = &sc->age_rdata.age_tx_ring[prod];
1662 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
1663 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) |
1664 vtag);
1665 desc->flags = htole32(cflags);
1666 sc->age_cdata.age_tx_cnt++;
1667 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1668 }
1669 /* Handle remaining fragments. */
1670 i = 1;
1671 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1672 /* Configure Tx IP/TCP/UDP checksum offload. */
1673 cflags |= AGE_TD_CSUM;
1674 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1675 cflags |= AGE_TD_TCPCSUM;
1676 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1677 cflags |= AGE_TD_UDPCSUM;
1678 /* Set checksum start offset. */
1679 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1680 /* Set checksum insertion position of TCP/UDP. */
1681 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1682 AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1683 }
1684 for (; i < nsegs; i++) {
1685 desc = &sc->age_rdata.age_tx_ring[prod];
1686 desc->addr = htole64(txsegs[i].ds_addr);
1687 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1688 desc->flags = htole32(cflags);
1689 sc->age_cdata.age_tx_cnt++;
1690 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1691 }
1692 /* Update producer index. */
1693 sc->age_cdata.age_tx_prod = prod;
1694
1695 /* Set EOP on the last descriptor. */
1696 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1697 desc = &sc->age_rdata.age_tx_ring[prod];
1698 desc->flags |= htole32(AGE_TD_EOP);
1699
1700 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1701 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1702 desc = &sc->age_rdata.age_tx_ring[si];
1703 desc->flags |= htole32(AGE_TD_TSO_HDR);
1704 }
1705
1706 /* Swap dmamap of the first and the last. */
1707 txd = &sc->age_cdata.age_txdesc[prod];
1708 map = txd_last->tx_dmamap;
1709 txd_last->tx_dmamap = txd->tx_dmamap;
1710 txd->tx_dmamap = map;
1711 txd->tx_m = m;
1712
1713 /* Sync descriptors. */
1714 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1715 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1716 sc->age_cdata.age_tx_ring_map,
1717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1718
1719 return (0);
1720 }
1721
1722 static void
age_start(struct ifnet * ifp)1723 age_start(struct ifnet *ifp)
1724 {
1725 struct age_softc *sc;
1726
1727 sc = ifp->if_softc;
1728 AGE_LOCK(sc);
1729 age_start_locked(ifp);
1730 AGE_UNLOCK(sc);
1731 }
1732
1733 static void
age_start_locked(struct ifnet * ifp)1734 age_start_locked(struct ifnet *ifp)
1735 {
1736 struct age_softc *sc;
1737 struct mbuf *m_head;
1738 int enq;
1739
1740 sc = ifp->if_softc;
1741
1742 AGE_LOCK_ASSERT(sc);
1743
1744 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1745 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0)
1746 return;
1747
1748 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1749 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1750 if (m_head == NULL)
1751 break;
1752 /*
1753 * Pack the data into the transmit ring. If we
1754 * don't have room, set the OACTIVE flag and wait
1755 * for the NIC to drain the ring.
1756 */
1757 if (age_encap(sc, &m_head)) {
1758 if (m_head == NULL)
1759 break;
1760 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1761 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1762 break;
1763 }
1764
1765 enq++;
1766 /*
1767 * If there's a BPF listener, bounce a copy of this frame
1768 * to him.
1769 */
1770 ETHER_BPF_MTAP(ifp, m_head);
1771 }
1772
1773 if (enq > 0) {
1774 /* Update mbox. */
1775 AGE_COMMIT_MBOX(sc);
1776 /* Set a timeout in case the chip goes out to lunch. */
1777 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1778 }
1779 }
1780
1781 static void
age_watchdog(struct age_softc * sc)1782 age_watchdog(struct age_softc *sc)
1783 {
1784 struct ifnet *ifp;
1785
1786 AGE_LOCK_ASSERT(sc);
1787
1788 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1789 return;
1790
1791 ifp = sc->age_ifp;
1792 if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1793 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1794 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1795 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1796 age_init_locked(sc);
1797 return;
1798 }
1799 if (sc->age_cdata.age_tx_cnt == 0) {
1800 if_printf(sc->age_ifp,
1801 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1802 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1803 age_start_locked(ifp);
1804 return;
1805 }
1806 if_printf(sc->age_ifp, "watchdog timeout\n");
1807 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1808 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1809 age_init_locked(sc);
1810 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1811 age_start_locked(ifp);
1812 }
1813
1814 static int
age_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1815 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1816 {
1817 struct age_softc *sc;
1818 struct ifreq *ifr;
1819 struct mii_data *mii;
1820 uint32_t reg;
1821 int error, mask;
1822
1823 sc = ifp->if_softc;
1824 ifr = (struct ifreq *)data;
1825 error = 0;
1826 switch (cmd) {
1827 case SIOCSIFMTU:
1828 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1829 error = EINVAL;
1830 else if (ifp->if_mtu != ifr->ifr_mtu) {
1831 AGE_LOCK(sc);
1832 ifp->if_mtu = ifr->ifr_mtu;
1833 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1834 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1835 age_init_locked(sc);
1836 }
1837 AGE_UNLOCK(sc);
1838 }
1839 break;
1840 case SIOCSIFFLAGS:
1841 AGE_LOCK(sc);
1842 if ((ifp->if_flags & IFF_UP) != 0) {
1843 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1844 if (((ifp->if_flags ^ sc->age_if_flags)
1845 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1846 age_rxfilter(sc);
1847 } else {
1848 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1849 age_init_locked(sc);
1850 }
1851 } else {
1852 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1853 age_stop(sc);
1854 }
1855 sc->age_if_flags = ifp->if_flags;
1856 AGE_UNLOCK(sc);
1857 break;
1858 case SIOCADDMULTI:
1859 case SIOCDELMULTI:
1860 AGE_LOCK(sc);
1861 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1862 age_rxfilter(sc);
1863 AGE_UNLOCK(sc);
1864 break;
1865 case SIOCSIFMEDIA:
1866 case SIOCGIFMEDIA:
1867 mii = device_get_softc(sc->age_miibus);
1868 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1869 break;
1870 case SIOCSIFCAP:
1871 AGE_LOCK(sc);
1872 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1873 if ((mask & IFCAP_TXCSUM) != 0 &&
1874 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1875 ifp->if_capenable ^= IFCAP_TXCSUM;
1876 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1877 ifp->if_hwassist |= AGE_CSUM_FEATURES;
1878 else
1879 ifp->if_hwassist &= ~AGE_CSUM_FEATURES;
1880 }
1881 if ((mask & IFCAP_RXCSUM) != 0 &&
1882 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1883 ifp->if_capenable ^= IFCAP_RXCSUM;
1884 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1885 reg &= ~MAC_CFG_RXCSUM_ENB;
1886 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1887 reg |= MAC_CFG_RXCSUM_ENB;
1888 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1889 }
1890 if ((mask & IFCAP_TSO4) != 0 &&
1891 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1892 ifp->if_capenable ^= IFCAP_TSO4;
1893 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1894 ifp->if_hwassist |= CSUM_TSO;
1895 else
1896 ifp->if_hwassist &= ~CSUM_TSO;
1897 }
1898
1899 if ((mask & IFCAP_WOL_MCAST) != 0 &&
1900 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
1901 ifp->if_capenable ^= IFCAP_WOL_MCAST;
1902 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1903 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1904 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1905 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1906 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1907 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1908 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1909 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1910 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1911 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1912 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1913 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1914 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1915 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
1916 age_rxvlan(sc);
1917 }
1918 AGE_UNLOCK(sc);
1919 VLAN_CAPABILITIES(ifp);
1920 break;
1921 default:
1922 error = ether_ioctl(ifp, cmd, data);
1923 break;
1924 }
1925
1926 return (error);
1927 }
1928
1929 static void
age_mac_config(struct age_softc * sc)1930 age_mac_config(struct age_softc *sc)
1931 {
1932 struct mii_data *mii;
1933 uint32_t reg;
1934
1935 AGE_LOCK_ASSERT(sc);
1936
1937 mii = device_get_softc(sc->age_miibus);
1938 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1939 reg &= ~MAC_CFG_FULL_DUPLEX;
1940 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1941 reg &= ~MAC_CFG_SPEED_MASK;
1942 /* Reprogram MAC with resolved speed/duplex. */
1943 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1944 case IFM_10_T:
1945 case IFM_100_TX:
1946 reg |= MAC_CFG_SPEED_10_100;
1947 break;
1948 case IFM_1000_T:
1949 reg |= MAC_CFG_SPEED_1000;
1950 break;
1951 }
1952 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1953 reg |= MAC_CFG_FULL_DUPLEX;
1954 #ifdef notyet
1955 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1956 reg |= MAC_CFG_TX_FC;
1957 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1958 reg |= MAC_CFG_RX_FC;
1959 #endif
1960 }
1961
1962 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1963 }
1964
1965 static void
age_link_task(void * arg,int pending)1966 age_link_task(void *arg, int pending)
1967 {
1968 struct age_softc *sc;
1969 struct mii_data *mii;
1970 struct ifnet *ifp;
1971 uint32_t reg;
1972
1973 sc = (struct age_softc *)arg;
1974
1975 AGE_LOCK(sc);
1976 mii = device_get_softc(sc->age_miibus);
1977 ifp = sc->age_ifp;
1978 if (mii == NULL || ifp == NULL ||
1979 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1980 AGE_UNLOCK(sc);
1981 return;
1982 }
1983
1984 sc->age_flags &= ~AGE_FLAG_LINK;
1985 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1986 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1987 case IFM_10_T:
1988 case IFM_100_TX:
1989 case IFM_1000_T:
1990 sc->age_flags |= AGE_FLAG_LINK;
1991 break;
1992 default:
1993 break;
1994 }
1995 }
1996
1997 /* Stop Rx/Tx MACs. */
1998 age_stop_rxmac(sc);
1999 age_stop_txmac(sc);
2000
2001 /* Program MACs with resolved speed/duplex/flow-control. */
2002 if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
2003 age_mac_config(sc);
2004 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2005 /* Restart DMA engine and Tx/Rx MAC. */
2006 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
2007 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
2008 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2009 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2010 }
2011
2012 AGE_UNLOCK(sc);
2013 }
2014
2015 static void
age_stats_update(struct age_softc * sc)2016 age_stats_update(struct age_softc *sc)
2017 {
2018 struct age_stats *stat;
2019 struct smb *smb;
2020 struct ifnet *ifp;
2021
2022 AGE_LOCK_ASSERT(sc);
2023
2024 stat = &sc->age_stat;
2025
2026 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2027 sc->age_cdata.age_smb_block_map,
2028 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2029
2030 smb = sc->age_rdata.age_smb_block;
2031 if (smb->updated == 0)
2032 return;
2033
2034 ifp = sc->age_ifp;
2035 /* Rx stats. */
2036 stat->rx_frames += smb->rx_frames;
2037 stat->rx_bcast_frames += smb->rx_bcast_frames;
2038 stat->rx_mcast_frames += smb->rx_mcast_frames;
2039 stat->rx_pause_frames += smb->rx_pause_frames;
2040 stat->rx_control_frames += smb->rx_control_frames;
2041 stat->rx_crcerrs += smb->rx_crcerrs;
2042 stat->rx_lenerrs += smb->rx_lenerrs;
2043 stat->rx_bytes += smb->rx_bytes;
2044 stat->rx_runts += smb->rx_runts;
2045 stat->rx_fragments += smb->rx_fragments;
2046 stat->rx_pkts_64 += smb->rx_pkts_64;
2047 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2048 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2049 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2050 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2051 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2052 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2053 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2054 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2055 stat->rx_desc_oflows += smb->rx_desc_oflows;
2056 stat->rx_alignerrs += smb->rx_alignerrs;
2057 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2058 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2059 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2060
2061 /* Tx stats. */
2062 stat->tx_frames += smb->tx_frames;
2063 stat->tx_bcast_frames += smb->tx_bcast_frames;
2064 stat->tx_mcast_frames += smb->tx_mcast_frames;
2065 stat->tx_pause_frames += smb->tx_pause_frames;
2066 stat->tx_excess_defer += smb->tx_excess_defer;
2067 stat->tx_control_frames += smb->tx_control_frames;
2068 stat->tx_deferred += smb->tx_deferred;
2069 stat->tx_bytes += smb->tx_bytes;
2070 stat->tx_pkts_64 += smb->tx_pkts_64;
2071 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2072 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2073 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2074 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2075 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2076 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2077 stat->tx_single_colls += smb->tx_single_colls;
2078 stat->tx_multi_colls += smb->tx_multi_colls;
2079 stat->tx_late_colls += smb->tx_late_colls;
2080 stat->tx_excess_colls += smb->tx_excess_colls;
2081 stat->tx_underrun += smb->tx_underrun;
2082 stat->tx_desc_underrun += smb->tx_desc_underrun;
2083 stat->tx_lenerrs += smb->tx_lenerrs;
2084 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2085 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2086 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2087
2088 /* Update counters in ifnet. */
2089 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2090
2091 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2092 smb->tx_multi_colls + smb->tx_late_colls +
2093 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2094
2095 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls +
2096 smb->tx_late_colls + smb->tx_underrun +
2097 smb->tx_pkts_truncated);
2098
2099 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2100
2101 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs +
2102 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated +
2103 smb->rx_fifo_oflows + smb->rx_desc_oflows +
2104 smb->rx_alignerrs);
2105
2106 /* Update done, clear. */
2107 smb->updated = 0;
2108
2109 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2110 sc->age_cdata.age_smb_block_map,
2111 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2112 }
2113
2114 static int
age_intr(void * arg)2115 age_intr(void *arg)
2116 {
2117 struct age_softc *sc;
2118 uint32_t status;
2119
2120 sc = (struct age_softc *)arg;
2121
2122 status = CSR_READ_4(sc, AGE_INTR_STATUS);
2123 if (status == 0 || (status & AGE_INTRS) == 0)
2124 return (FILTER_STRAY);
2125 /* Disable interrupts. */
2126 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2127 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2128
2129 return (FILTER_HANDLED);
2130 }
2131
2132 static void
age_int_task(void * arg,int pending)2133 age_int_task(void *arg, int pending)
2134 {
2135 struct age_softc *sc;
2136 struct ifnet *ifp;
2137 struct cmb *cmb;
2138 uint32_t status;
2139
2140 sc = (struct age_softc *)arg;
2141
2142 AGE_LOCK(sc);
2143
2144 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2145 sc->age_cdata.age_cmb_block_map,
2146 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2147 cmb = sc->age_rdata.age_cmb_block;
2148 status = le32toh(cmb->intr_status);
2149 if (sc->age_morework != 0)
2150 status |= INTR_CMB_RX;
2151 if ((status & AGE_INTRS) == 0)
2152 goto done;
2153
2154 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2155 TPD_CONS_SHIFT;
2156 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2157 RRD_PROD_SHIFT;
2158 /* Let hardware know CMB was served. */
2159 cmb->intr_status = 0;
2160 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2161 sc->age_cdata.age_cmb_block_map,
2162 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2163
2164 #if 0
2165 printf("INTR: 0x%08x\n", status);
2166 status &= ~INTR_DIS_DMA;
2167 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2168 #endif
2169 ifp = sc->age_ifp;
2170 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2171 if ((status & INTR_CMB_RX) != 0)
2172 sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2173 sc->age_process_limit);
2174 if ((status & INTR_CMB_TX) != 0)
2175 age_txintr(sc, sc->age_tpd_cons);
2176 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2177 if ((status & INTR_DMA_RD_TO_RST) != 0)
2178 device_printf(sc->age_dev,
2179 "DMA read error! -- resetting\n");
2180 if ((status & INTR_DMA_WR_TO_RST) != 0)
2181 device_printf(sc->age_dev,
2182 "DMA write error! -- resetting\n");
2183 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2184 age_init_locked(sc);
2185 }
2186 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2187 age_start_locked(ifp);
2188 if ((status & INTR_SMB) != 0)
2189 age_stats_update(sc);
2190 }
2191
2192 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2193 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2194 sc->age_cdata.age_cmb_block_map,
2195 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2196 status = le32toh(cmb->intr_status);
2197 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2198 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2199 AGE_UNLOCK(sc);
2200 return;
2201 }
2202
2203 done:
2204 /* Re-enable interrupts. */
2205 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2206 AGE_UNLOCK(sc);
2207 }
2208
2209 static void
age_txintr(struct age_softc * sc,int tpd_cons)2210 age_txintr(struct age_softc *sc, int tpd_cons)
2211 {
2212 struct ifnet *ifp;
2213 struct age_txdesc *txd;
2214 int cons, prog;
2215
2216 AGE_LOCK_ASSERT(sc);
2217
2218 ifp = sc->age_ifp;
2219
2220 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2221 sc->age_cdata.age_tx_ring_map,
2222 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2223
2224 /*
2225 * Go through our Tx list and free mbufs for those
2226 * frames which have been transmitted.
2227 */
2228 cons = sc->age_cdata.age_tx_cons;
2229 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2230 if (sc->age_cdata.age_tx_cnt <= 0)
2231 break;
2232 prog++;
2233 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2234 sc->age_cdata.age_tx_cnt--;
2235 txd = &sc->age_cdata.age_txdesc[cons];
2236 /*
2237 * Clear Tx descriptors, it's not required but would
2238 * help debugging in case of Tx issues.
2239 */
2240 txd->tx_desc->addr = 0;
2241 txd->tx_desc->len = 0;
2242 txd->tx_desc->flags = 0;
2243
2244 if (txd->tx_m == NULL)
2245 continue;
2246 /* Reclaim transmitted mbufs. */
2247 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2248 BUS_DMASYNC_POSTWRITE);
2249 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2250 m_freem(txd->tx_m);
2251 txd->tx_m = NULL;
2252 }
2253
2254 if (prog > 0) {
2255 sc->age_cdata.age_tx_cons = cons;
2256
2257 /*
2258 * Unarm watchdog timer only when there are no pending
2259 * Tx descriptors in queue.
2260 */
2261 if (sc->age_cdata.age_tx_cnt == 0)
2262 sc->age_watchdog_timer = 0;
2263 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2264 sc->age_cdata.age_tx_ring_map,
2265 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2266 }
2267 }
2268
2269 #ifndef __NO_STRICT_ALIGNMENT
2270 static struct mbuf *
age_fixup_rx(struct ifnet * ifp,struct mbuf * m)2271 age_fixup_rx(struct ifnet *ifp, struct mbuf *m)
2272 {
2273 struct mbuf *n;
2274 int i;
2275 uint16_t *src, *dst;
2276
2277 src = mtod(m, uint16_t *);
2278 dst = src - 3;
2279
2280 if (m->m_next == NULL) {
2281 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2282 *dst++ = *src++;
2283 m->m_data -= 6;
2284 return (m);
2285 }
2286 /*
2287 * Append a new mbuf to received mbuf chain and copy ethernet
2288 * header from the mbuf chain. This can save lots of CPU
2289 * cycles for jumbo frame.
2290 */
2291 MGETHDR(n, M_NOWAIT, MT_DATA);
2292 if (n == NULL) {
2293 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2294 m_freem(m);
2295 return (NULL);
2296 }
2297 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2298 m->m_data += ETHER_HDR_LEN;
2299 m->m_len -= ETHER_HDR_LEN;
2300 n->m_len = ETHER_HDR_LEN;
2301 M_MOVE_PKTHDR(n, m);
2302 n->m_next = m;
2303 return (n);
2304 }
2305 #endif
2306
2307 /* Receive a frame. */
2308 static void
age_rxeof(struct age_softc * sc,struct rx_rdesc * rxrd)2309 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2310 {
2311 struct age_rxdesc *rxd;
2312 struct ifnet *ifp;
2313 struct mbuf *mp, *m;
2314 uint32_t status, index, vtag;
2315 int count, nsegs;
2316 int rx_cons;
2317
2318 AGE_LOCK_ASSERT(sc);
2319
2320 ifp = sc->age_ifp;
2321 status = le32toh(rxrd->flags);
2322 index = le32toh(rxrd->index);
2323 rx_cons = AGE_RX_CONS(index);
2324 nsegs = AGE_RX_NSEGS(index);
2325
2326 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2327 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) {
2328 /*
2329 * We want to pass the following frames to upper
2330 * layer regardless of error status of Rx return
2331 * ring.
2332 *
2333 * o IP/TCP/UDP checksum is bad.
2334 * o frame length and protocol specific length
2335 * does not match.
2336 */
2337 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK;
2338 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2339 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0)
2340 return;
2341 }
2342
2343 for (count = 0; count < nsegs; count++,
2344 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2345 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2346 mp = rxd->rx_m;
2347 /* Add a new receive buffer to the ring. */
2348 if (age_newbuf(sc, rxd) != 0) {
2349 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2350 /* Reuse Rx buffers. */
2351 if (sc->age_cdata.age_rxhead != NULL)
2352 m_freem(sc->age_cdata.age_rxhead);
2353 break;
2354 }
2355
2356 /*
2357 * Assume we've received a full sized frame.
2358 * Actual size is fixed when we encounter the end of
2359 * multi-segmented frame.
2360 */
2361 mp->m_len = AGE_RX_BUF_SIZE;
2362
2363 /* Chain received mbufs. */
2364 if (sc->age_cdata.age_rxhead == NULL) {
2365 sc->age_cdata.age_rxhead = mp;
2366 sc->age_cdata.age_rxtail = mp;
2367 } else {
2368 mp->m_flags &= ~M_PKTHDR;
2369 sc->age_cdata.age_rxprev_tail =
2370 sc->age_cdata.age_rxtail;
2371 sc->age_cdata.age_rxtail->m_next = mp;
2372 sc->age_cdata.age_rxtail = mp;
2373 }
2374
2375 if (count == nsegs - 1) {
2376 /* Last desc. for this frame. */
2377 m = sc->age_cdata.age_rxhead;
2378 m->m_flags |= M_PKTHDR;
2379 /*
2380 * It seems that L1 controller has no way
2381 * to tell hardware to strip CRC bytes.
2382 */
2383 m->m_pkthdr.len = sc->age_cdata.age_rxlen -
2384 ETHER_CRC_LEN;
2385 if (nsegs > 1) {
2386 /* Set last mbuf size. */
2387 mp->m_len = sc->age_cdata.age_rxlen -
2388 ((nsegs - 1) * AGE_RX_BUF_SIZE);
2389 /* Remove the CRC bytes in chained mbufs. */
2390 if (mp->m_len <= ETHER_CRC_LEN) {
2391 sc->age_cdata.age_rxtail =
2392 sc->age_cdata.age_rxprev_tail;
2393 sc->age_cdata.age_rxtail->m_len -=
2394 (ETHER_CRC_LEN - mp->m_len);
2395 sc->age_cdata.age_rxtail->m_next = NULL;
2396 m_freem(mp);
2397 } else {
2398 mp->m_len -= ETHER_CRC_LEN;
2399 }
2400 } else
2401 m->m_len = m->m_pkthdr.len;
2402 m->m_pkthdr.rcvif = ifp;
2403 /*
2404 * Set checksum information.
2405 * It seems that L1 controller can compute partial
2406 * checksum. The partial checksum value can be used
2407 * to accelerate checksum computation for fragmented
2408 * TCP/UDP packets. Upper network stack already
2409 * takes advantage of the partial checksum value in
2410 * IP reassembly stage. But I'm not sure the
2411 * correctness of the partial hardware checksum
2412 * assistance due to lack of data sheet. If it is
2413 * proven to work on L1 I'll enable it.
2414 */
2415 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2416 (status & AGE_RRD_IPV4) != 0) {
2417 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2418 m->m_pkthdr.csum_flags |=
2419 CSUM_IP_CHECKED | CSUM_IP_VALID;
2420 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2421 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2422 m->m_pkthdr.csum_flags |=
2423 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2424 m->m_pkthdr.csum_data = 0xffff;
2425 }
2426 /*
2427 * Don't mark bad checksum for TCP/UDP frames
2428 * as fragmented frames may always have set
2429 * bad checksummed bit of descriptor status.
2430 */
2431 }
2432
2433 /* Check for VLAN tagged frames. */
2434 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2435 (status & AGE_RRD_VLAN) != 0) {
2436 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2437 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2438 m->m_flags |= M_VLANTAG;
2439 }
2440 #ifndef __NO_STRICT_ALIGNMENT
2441 m = age_fixup_rx(ifp, m);
2442 if (m != NULL)
2443 #endif
2444 {
2445 /* Pass it on. */
2446 AGE_UNLOCK(sc);
2447 (*ifp->if_input)(ifp, m);
2448 AGE_LOCK(sc);
2449 }
2450 }
2451 }
2452
2453 /* Reset mbuf chains. */
2454 AGE_RXCHAIN_RESET(sc);
2455 }
2456
2457 static int
age_rxintr(struct age_softc * sc,int rr_prod,int count)2458 age_rxintr(struct age_softc *sc, int rr_prod, int count)
2459 {
2460 struct rx_rdesc *rxrd;
2461 int rr_cons, nsegs, pktlen, prog;
2462
2463 AGE_LOCK_ASSERT(sc);
2464
2465 rr_cons = sc->age_cdata.age_rr_cons;
2466 if (rr_cons == rr_prod)
2467 return (0);
2468
2469 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2470 sc->age_cdata.age_rr_ring_map,
2471 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2472 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2473 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2474
2475 for (prog = 0; rr_cons != rr_prod; prog++) {
2476 if (count-- <= 0)
2477 break;
2478 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2479 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2480 if (nsegs == 0)
2481 break;
2482 /*
2483 * Check number of segments against received bytes.
2484 * Non-matching value would indicate that hardware
2485 * is still trying to update Rx return descriptors.
2486 * I'm not sure whether this check is really needed.
2487 */
2488 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2489 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE))
2490 break;
2491
2492 /* Received a frame. */
2493 age_rxeof(sc, rxrd);
2494 /* Clear return ring. */
2495 rxrd->index = 0;
2496 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2497 sc->age_cdata.age_rx_cons += nsegs;
2498 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2499 }
2500
2501 if (prog > 0) {
2502 /* Update the consumer index. */
2503 sc->age_cdata.age_rr_cons = rr_cons;
2504
2505 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2506 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
2507 /* Sync descriptors. */
2508 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2509 sc->age_cdata.age_rr_ring_map,
2510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2511
2512 /* Notify hardware availability of new Rx buffers. */
2513 AGE_COMMIT_MBOX(sc);
2514 }
2515
2516 return (count > 0 ? 0 : EAGAIN);
2517 }
2518
2519 static void
age_tick(void * arg)2520 age_tick(void *arg)
2521 {
2522 struct age_softc *sc;
2523 struct mii_data *mii;
2524
2525 sc = (struct age_softc *)arg;
2526
2527 AGE_LOCK_ASSERT(sc);
2528
2529 mii = device_get_softc(sc->age_miibus);
2530 mii_tick(mii);
2531 age_watchdog(sc);
2532 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2533 }
2534
2535 static void
age_reset(struct age_softc * sc)2536 age_reset(struct age_softc *sc)
2537 {
2538 uint32_t reg;
2539 int i;
2540
2541 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2542 CSR_READ_4(sc, AGE_MASTER_CFG);
2543 DELAY(1000);
2544 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2545 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2546 break;
2547 DELAY(10);
2548 }
2549
2550 if (i == 0)
2551 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2552 /* Initialize PCIe module. From Linux. */
2553 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2554 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2555 }
2556
2557 static void
age_init(void * xsc)2558 age_init(void *xsc)
2559 {
2560 struct age_softc *sc;
2561
2562 sc = (struct age_softc *)xsc;
2563 AGE_LOCK(sc);
2564 age_init_locked(sc);
2565 AGE_UNLOCK(sc);
2566 }
2567
2568 static void
age_init_locked(struct age_softc * sc)2569 age_init_locked(struct age_softc *sc)
2570 {
2571 struct ifnet *ifp;
2572 struct mii_data *mii;
2573 uint8_t eaddr[ETHER_ADDR_LEN];
2574 bus_addr_t paddr;
2575 uint32_t reg, fsize;
2576 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2577 int error;
2578
2579 AGE_LOCK_ASSERT(sc);
2580
2581 ifp = sc->age_ifp;
2582 mii = device_get_softc(sc->age_miibus);
2583
2584 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2585 return;
2586
2587 /*
2588 * Cancel any pending I/O.
2589 */
2590 age_stop(sc);
2591
2592 /*
2593 * Reset the chip to a known state.
2594 */
2595 age_reset(sc);
2596
2597 /* Initialize descriptors. */
2598 error = age_init_rx_ring(sc);
2599 if (error != 0) {
2600 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2601 age_stop(sc);
2602 return;
2603 }
2604 age_init_rr_ring(sc);
2605 age_init_tx_ring(sc);
2606 age_init_cmb_block(sc);
2607 age_init_smb_block(sc);
2608
2609 /* Reprogram the station address. */
2610 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2611 CSR_WRITE_4(sc, AGE_PAR0,
2612 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2613 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2614
2615 /* Set descriptor base addresses. */
2616 paddr = sc->age_rdata.age_tx_ring_paddr;
2617 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2618 paddr = sc->age_rdata.age_rx_ring_paddr;
2619 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2620 paddr = sc->age_rdata.age_rr_ring_paddr;
2621 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2622 paddr = sc->age_rdata.age_tx_ring_paddr;
2623 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2624 paddr = sc->age_rdata.age_cmb_block_paddr;
2625 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2626 paddr = sc->age_rdata.age_smb_block_paddr;
2627 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2628 /* Set Rx/Rx return descriptor counter. */
2629 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2630 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2631 DESC_RRD_CNT_MASK) |
2632 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2633 /* Set Tx descriptor counter. */
2634 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2635 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2636
2637 /* Tell hardware that we're ready to load descriptors. */
2638 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2639
2640 /*
2641 * Initialize mailbox register.
2642 * Updated producer/consumer index information is exchanged
2643 * through this mailbox register. However Tx producer and
2644 * Rx return consumer/Rx producer are all shared such that
2645 * it's hard to separate code path between Tx and Rx without
2646 * locking. If L1 hardware have a separate mail box register
2647 * for Tx and Rx consumer/producer management we could have
2648 * indepent Tx/Rx handler which in turn Rx handler could have
2649 * been run without any locking.
2650 */
2651 AGE_COMMIT_MBOX(sc);
2652
2653 /* Configure IPG/IFG parameters. */
2654 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2655 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2656 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2657 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2658 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2659
2660 /* Set parameters for half-duplex media. */
2661 CSR_WRITE_4(sc, AGE_HDPX_CFG,
2662 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2663 HDPX_CFG_LCOL_MASK) |
2664 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2665 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2666 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2667 HDPX_CFG_ABEBT_MASK) |
2668 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2669 HDPX_CFG_JAMIPG_MASK));
2670
2671 /* Configure interrupt moderation timer. */
2672 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2673 reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2674 reg &= ~MASTER_MTIMER_ENB;
2675 if (AGE_USECS(sc->age_int_mod) == 0)
2676 reg &= ~MASTER_ITIMER_ENB;
2677 else
2678 reg |= MASTER_ITIMER_ENB;
2679 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2680 if (bootverbose)
2681 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2682 sc->age_int_mod);
2683 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2684
2685 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2686 if (ifp->if_mtu < ETHERMTU)
2687 sc->age_max_frame_size = ETHERMTU;
2688 else
2689 sc->age_max_frame_size = ifp->if_mtu;
2690 sc->age_max_frame_size += ETHER_HDR_LEN +
2691 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2692 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2693 /* Configure jumbo frame. */
2694 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2695 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2696 (((fsize / sizeof(uint64_t)) <<
2697 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2698 ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2699 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2700 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2701 RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2702
2703 /* Configure flow-control parameters. From Linux. */
2704 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2705 /*
2706 * Magic workaround for old-L1.
2707 * Don't know which hw revision requires this magic.
2708 */
2709 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2710 /*
2711 * Another magic workaround for flow-control mode
2712 * change. From Linux.
2713 */
2714 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2715 }
2716 /*
2717 * TODO
2718 * Should understand pause parameter relationships between FIFO
2719 * size and number of Rx descriptors and Rx return descriptors.
2720 *
2721 * Magic parameters came from Linux.
2722 */
2723 switch (sc->age_chip_rev) {
2724 case 0x8001:
2725 case 0x9001:
2726 case 0x9002:
2727 case 0x9003:
2728 rxf_hi = AGE_RX_RING_CNT / 16;
2729 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2730 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2731 rrd_lo = AGE_RR_RING_CNT / 16;
2732 break;
2733 default:
2734 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2735 rxf_lo = reg / 16;
2736 if (rxf_lo < 192)
2737 rxf_lo = 192;
2738 rxf_hi = (reg * 7) / 8;
2739 if (rxf_hi < rxf_lo)
2740 rxf_hi = rxf_lo + 16;
2741 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2742 rrd_lo = reg / 8;
2743 rrd_hi = (reg * 7) / 8;
2744 if (rrd_lo < 2)
2745 rrd_lo = 2;
2746 if (rrd_hi < rrd_lo)
2747 rrd_hi = rrd_lo + 3;
2748 break;
2749 }
2750 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2751 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2752 RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2753 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2754 RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2755 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2756 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2757 RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2758 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2759 RXQ_RRD_PAUSE_THRESH_HI_MASK));
2760
2761 /* Configure RxQ. */
2762 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2763 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2764 RXQ_CFG_RD_BURST_MASK) |
2765 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2766 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2767 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2768 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2769 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2770
2771 /* Configure TxQ. */
2772 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2773 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2774 TXQ_CFG_TPD_BURST_MASK) |
2775 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2776 TXQ_CFG_TX_FIFO_BURST_MASK) |
2777 ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2778 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2779 TXQ_CFG_ENB);
2780
2781 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2782 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2783 TX_JUMBO_TPD_TH_MASK) |
2784 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2785 TX_JUMBO_TPD_IPG_MASK));
2786 /* Configure DMA parameters. */
2787 CSR_WRITE_4(sc, AGE_DMA_CFG,
2788 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2789 sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2790 sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2791
2792 /* Configure CMB DMA write threshold. */
2793 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2794 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2795 CMB_WR_THRESH_RRD_MASK) |
2796 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2797 CMB_WR_THRESH_TPD_MASK));
2798
2799 /* Set CMB/SMB timer and enable them. */
2800 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2801 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2802 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2803 /* Request SMB updates for every seconds. */
2804 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2805 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2806
2807 /*
2808 * Disable all WOL bits as WOL can interfere normal Rx
2809 * operation.
2810 */
2811 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2812
2813 /*
2814 * Configure Tx/Rx MACs.
2815 * - Auto-padding for short frames.
2816 * - Enable CRC generation.
2817 * Start with full-duplex/1000Mbps media. Actual reconfiguration
2818 * of MAC is followed after link establishment.
2819 */
2820 CSR_WRITE_4(sc, AGE_MAC_CFG,
2821 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2822 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2823 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2824 MAC_CFG_PREAMBLE_MASK));
2825 /* Set up the receive filter. */
2826 age_rxfilter(sc);
2827 age_rxvlan(sc);
2828
2829 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2830 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2831 reg |= MAC_CFG_RXCSUM_ENB;
2832
2833 /* Ack all pending interrupts and clear it. */
2834 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2835 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2836
2837 /* Finally enable Tx/Rx MAC. */
2838 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2839
2840 sc->age_flags &= ~AGE_FLAG_LINK;
2841 /* Switch to the current media. */
2842 mii_mediachg(mii);
2843
2844 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2845
2846 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2847 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2848 }
2849
2850 static void
age_stop(struct age_softc * sc)2851 age_stop(struct age_softc *sc)
2852 {
2853 struct ifnet *ifp;
2854 struct age_txdesc *txd;
2855 struct age_rxdesc *rxd;
2856 uint32_t reg;
2857 int i;
2858
2859 AGE_LOCK_ASSERT(sc);
2860 /*
2861 * Mark the interface down and cancel the watchdog timer.
2862 */
2863 ifp = sc->age_ifp;
2864 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2865 sc->age_flags &= ~AGE_FLAG_LINK;
2866 callout_stop(&sc->age_tick_ch);
2867 sc->age_watchdog_timer = 0;
2868
2869 /*
2870 * Disable interrupts.
2871 */
2872 CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2873 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2874 /* Stop CMB/SMB updates. */
2875 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2876 /* Stop Rx/Tx MAC. */
2877 age_stop_rxmac(sc);
2878 age_stop_txmac(sc);
2879 /* Stop DMA. */
2880 CSR_WRITE_4(sc, AGE_DMA_CFG,
2881 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2882 /* Stop TxQ/RxQ. */
2883 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2884 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2885 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2886 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2887 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2888 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2889 break;
2890 DELAY(10);
2891 }
2892 if (i == 0)
2893 device_printf(sc->age_dev,
2894 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2895
2896 /* Reclaim Rx buffers that have been processed. */
2897 if (sc->age_cdata.age_rxhead != NULL)
2898 m_freem(sc->age_cdata.age_rxhead);
2899 AGE_RXCHAIN_RESET(sc);
2900 /*
2901 * Free RX and TX mbufs still in the queues.
2902 */
2903 for (i = 0; i < AGE_RX_RING_CNT; i++) {
2904 rxd = &sc->age_cdata.age_rxdesc[i];
2905 if (rxd->rx_m != NULL) {
2906 bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2907 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2908 bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2909 rxd->rx_dmamap);
2910 m_freem(rxd->rx_m);
2911 rxd->rx_m = NULL;
2912 }
2913 }
2914 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2915 txd = &sc->age_cdata.age_txdesc[i];
2916 if (txd->tx_m != NULL) {
2917 bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2918 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2919 bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2920 txd->tx_dmamap);
2921 m_freem(txd->tx_m);
2922 txd->tx_m = NULL;
2923 }
2924 }
2925 }
2926
2927 static void
age_stop_txmac(struct age_softc * sc)2928 age_stop_txmac(struct age_softc *sc)
2929 {
2930 uint32_t reg;
2931 int i;
2932
2933 AGE_LOCK_ASSERT(sc);
2934
2935 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2936 if ((reg & MAC_CFG_TX_ENB) != 0) {
2937 reg &= ~MAC_CFG_TX_ENB;
2938 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2939 }
2940 /* Stop Tx DMA engine. */
2941 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2942 if ((reg & DMA_CFG_RD_ENB) != 0) {
2943 reg &= ~DMA_CFG_RD_ENB;
2944 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2945 }
2946 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2947 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2948 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2949 break;
2950 DELAY(10);
2951 }
2952 if (i == 0)
2953 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2954 }
2955
2956 static void
age_stop_rxmac(struct age_softc * sc)2957 age_stop_rxmac(struct age_softc *sc)
2958 {
2959 uint32_t reg;
2960 int i;
2961
2962 AGE_LOCK_ASSERT(sc);
2963
2964 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2965 if ((reg & MAC_CFG_RX_ENB) != 0) {
2966 reg &= ~MAC_CFG_RX_ENB;
2967 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2968 }
2969 /* Stop Rx DMA engine. */
2970 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2971 if ((reg & DMA_CFG_WR_ENB) != 0) {
2972 reg &= ~DMA_CFG_WR_ENB;
2973 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2974 }
2975 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2976 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2977 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2978 break;
2979 DELAY(10);
2980 }
2981 if (i == 0)
2982 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2983 }
2984
2985 static void
age_init_tx_ring(struct age_softc * sc)2986 age_init_tx_ring(struct age_softc *sc)
2987 {
2988 struct age_ring_data *rd;
2989 struct age_txdesc *txd;
2990 int i;
2991
2992 AGE_LOCK_ASSERT(sc);
2993
2994 sc->age_cdata.age_tx_prod = 0;
2995 sc->age_cdata.age_tx_cons = 0;
2996 sc->age_cdata.age_tx_cnt = 0;
2997
2998 rd = &sc->age_rdata;
2999 bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
3000 for (i = 0; i < AGE_TX_RING_CNT; i++) {
3001 txd = &sc->age_cdata.age_txdesc[i];
3002 txd->tx_desc = &rd->age_tx_ring[i];
3003 txd->tx_m = NULL;
3004 }
3005
3006 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
3007 sc->age_cdata.age_tx_ring_map,
3008 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3009 }
3010
3011 static int
age_init_rx_ring(struct age_softc * sc)3012 age_init_rx_ring(struct age_softc *sc)
3013 {
3014 struct age_ring_data *rd;
3015 struct age_rxdesc *rxd;
3016 int i;
3017
3018 AGE_LOCK_ASSERT(sc);
3019
3020 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
3021 sc->age_morework = 0;
3022 rd = &sc->age_rdata;
3023 bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
3024 for (i = 0; i < AGE_RX_RING_CNT; i++) {
3025 rxd = &sc->age_cdata.age_rxdesc[i];
3026 rxd->rx_m = NULL;
3027 rxd->rx_desc = &rd->age_rx_ring[i];
3028 if (age_newbuf(sc, rxd) != 0)
3029 return (ENOBUFS);
3030 }
3031
3032 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
3033 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
3034
3035 return (0);
3036 }
3037
3038 static void
age_init_rr_ring(struct age_softc * sc)3039 age_init_rr_ring(struct age_softc *sc)
3040 {
3041 struct age_ring_data *rd;
3042
3043 AGE_LOCK_ASSERT(sc);
3044
3045 sc->age_cdata.age_rr_cons = 0;
3046 AGE_RXCHAIN_RESET(sc);
3047
3048 rd = &sc->age_rdata;
3049 bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3050 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3051 sc->age_cdata.age_rr_ring_map,
3052 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3053 }
3054
3055 static void
age_init_cmb_block(struct age_softc * sc)3056 age_init_cmb_block(struct age_softc *sc)
3057 {
3058 struct age_ring_data *rd;
3059
3060 AGE_LOCK_ASSERT(sc);
3061
3062 rd = &sc->age_rdata;
3063 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3064 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3065 sc->age_cdata.age_cmb_block_map,
3066 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3067 }
3068
3069 static void
age_init_smb_block(struct age_softc * sc)3070 age_init_smb_block(struct age_softc *sc)
3071 {
3072 struct age_ring_data *rd;
3073
3074 AGE_LOCK_ASSERT(sc);
3075
3076 rd = &sc->age_rdata;
3077 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3078 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3079 sc->age_cdata.age_smb_block_map,
3080 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3081 }
3082
3083 static int
age_newbuf(struct age_softc * sc,struct age_rxdesc * rxd)3084 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3085 {
3086 struct rx_desc *desc;
3087 struct mbuf *m;
3088 bus_dma_segment_t segs[1];
3089 bus_dmamap_t map;
3090 int nsegs;
3091
3092 AGE_LOCK_ASSERT(sc);
3093
3094 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3095 if (m == NULL)
3096 return (ENOBUFS);
3097 m->m_len = m->m_pkthdr.len = MCLBYTES;
3098 #ifndef __NO_STRICT_ALIGNMENT
3099 m_adj(m, AGE_RX_BUF_ALIGN);
3100 #endif
3101
3102 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3103 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3104 m_freem(m);
3105 return (ENOBUFS);
3106 }
3107 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3108
3109 if (rxd->rx_m != NULL) {
3110 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3111 BUS_DMASYNC_POSTREAD);
3112 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3113 }
3114 map = rxd->rx_dmamap;
3115 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3116 sc->age_cdata.age_rx_sparemap = map;
3117 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3118 BUS_DMASYNC_PREREAD);
3119 rxd->rx_m = m;
3120
3121 desc = rxd->rx_desc;
3122 desc->addr = htole64(segs[0].ds_addr);
3123 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3124 AGE_RD_LEN_SHIFT);
3125 return (0);
3126 }
3127
3128 static void
age_rxvlan(struct age_softc * sc)3129 age_rxvlan(struct age_softc *sc)
3130 {
3131 struct ifnet *ifp;
3132 uint32_t reg;
3133
3134 AGE_LOCK_ASSERT(sc);
3135
3136 ifp = sc->age_ifp;
3137 reg = CSR_READ_4(sc, AGE_MAC_CFG);
3138 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3139 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3140 reg |= MAC_CFG_VLAN_TAG_STRIP;
3141 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3142 }
3143
3144 static void
age_rxfilter(struct age_softc * sc)3145 age_rxfilter(struct age_softc *sc)
3146 {
3147 struct ifnet *ifp;
3148 struct ifmultiaddr *ifma;
3149 uint32_t crc;
3150 uint32_t mchash[2];
3151 uint32_t rxcfg;
3152
3153 AGE_LOCK_ASSERT(sc);
3154
3155 ifp = sc->age_ifp;
3156
3157 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3158 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3159 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3160 rxcfg |= MAC_CFG_BCAST;
3161 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3162 if ((ifp->if_flags & IFF_PROMISC) != 0)
3163 rxcfg |= MAC_CFG_PROMISC;
3164 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3165 rxcfg |= MAC_CFG_ALLMULTI;
3166 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3167 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3168 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3169 return;
3170 }
3171
3172 /* Program new filter. */
3173 bzero(mchash, sizeof(mchash));
3174
3175 if_maddr_rlock(ifp);
3176 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) {
3177 if (ifma->ifma_addr->sa_family != AF_LINK)
3178 continue;
3179 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3180 ifma->ifma_addr), ETHER_ADDR_LEN);
3181 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3182 }
3183 if_maddr_runlock(ifp);
3184
3185 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3186 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3187 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3188 }
3189
3190 static int
sysctl_age_stats(SYSCTL_HANDLER_ARGS)3191 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3192 {
3193 struct age_softc *sc;
3194 struct age_stats *stats;
3195 int error, result;
3196
3197 result = -1;
3198 error = sysctl_handle_int(oidp, &result, 0, req);
3199
3200 if (error != 0 || req->newptr == NULL)
3201 return (error);
3202
3203 if (result != 1)
3204 return (error);
3205
3206 sc = (struct age_softc *)arg1;
3207 stats = &sc->age_stat;
3208 printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3209 printf("Transmit good frames : %ju\n",
3210 (uintmax_t)stats->tx_frames);
3211 printf("Transmit good broadcast frames : %ju\n",
3212 (uintmax_t)stats->tx_bcast_frames);
3213 printf("Transmit good multicast frames : %ju\n",
3214 (uintmax_t)stats->tx_mcast_frames);
3215 printf("Transmit pause control frames : %u\n",
3216 stats->tx_pause_frames);
3217 printf("Transmit control frames : %u\n",
3218 stats->tx_control_frames);
3219 printf("Transmit frames with excessive deferrals : %u\n",
3220 stats->tx_excess_defer);
3221 printf("Transmit deferrals : %u\n",
3222 stats->tx_deferred);
3223 printf("Transmit good octets : %ju\n",
3224 (uintmax_t)stats->tx_bytes);
3225 printf("Transmit good broadcast octets : %ju\n",
3226 (uintmax_t)stats->tx_bcast_bytes);
3227 printf("Transmit good multicast octets : %ju\n",
3228 (uintmax_t)stats->tx_mcast_bytes);
3229 printf("Transmit frames 64 bytes : %ju\n",
3230 (uintmax_t)stats->tx_pkts_64);
3231 printf("Transmit frames 65 to 127 bytes : %ju\n",
3232 (uintmax_t)stats->tx_pkts_65_127);
3233 printf("Transmit frames 128 to 255 bytes : %ju\n",
3234 (uintmax_t)stats->tx_pkts_128_255);
3235 printf("Transmit frames 256 to 511 bytes : %ju\n",
3236 (uintmax_t)stats->tx_pkts_256_511);
3237 printf("Transmit frames 512 to 1024 bytes : %ju\n",
3238 (uintmax_t)stats->tx_pkts_512_1023);
3239 printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3240 (uintmax_t)stats->tx_pkts_1024_1518);
3241 printf("Transmit frames 1519 to MTU bytes : %ju\n",
3242 (uintmax_t)stats->tx_pkts_1519_max);
3243 printf("Transmit single collisions : %u\n",
3244 stats->tx_single_colls);
3245 printf("Transmit multiple collisions : %u\n",
3246 stats->tx_multi_colls);
3247 printf("Transmit late collisions : %u\n",
3248 stats->tx_late_colls);
3249 printf("Transmit abort due to excessive collisions : %u\n",
3250 stats->tx_excess_colls);
3251 printf("Transmit underruns due to FIFO underruns : %u\n",
3252 stats->tx_underrun);
3253 printf("Transmit descriptor write-back errors : %u\n",
3254 stats->tx_desc_underrun);
3255 printf("Transmit frames with length mismatched frame size : %u\n",
3256 stats->tx_lenerrs);
3257 printf("Transmit frames with truncated due to MTU size : %u\n",
3258 stats->tx_lenerrs);
3259
3260 printf("Receive good frames : %ju\n",
3261 (uintmax_t)stats->rx_frames);
3262 printf("Receive good broadcast frames : %ju\n",
3263 (uintmax_t)stats->rx_bcast_frames);
3264 printf("Receive good multicast frames : %ju\n",
3265 (uintmax_t)stats->rx_mcast_frames);
3266 printf("Receive pause control frames : %u\n",
3267 stats->rx_pause_frames);
3268 printf("Receive control frames : %u\n",
3269 stats->rx_control_frames);
3270 printf("Receive CRC errors : %u\n",
3271 stats->rx_crcerrs);
3272 printf("Receive frames with length errors : %u\n",
3273 stats->rx_lenerrs);
3274 printf("Receive good octets : %ju\n",
3275 (uintmax_t)stats->rx_bytes);
3276 printf("Receive good broadcast octets : %ju\n",
3277 (uintmax_t)stats->rx_bcast_bytes);
3278 printf("Receive good multicast octets : %ju\n",
3279 (uintmax_t)stats->rx_mcast_bytes);
3280 printf("Receive frames too short : %u\n",
3281 stats->rx_runts);
3282 printf("Receive fragmented frames : %ju\n",
3283 (uintmax_t)stats->rx_fragments);
3284 printf("Receive frames 64 bytes : %ju\n",
3285 (uintmax_t)stats->rx_pkts_64);
3286 printf("Receive frames 65 to 127 bytes : %ju\n",
3287 (uintmax_t)stats->rx_pkts_65_127);
3288 printf("Receive frames 128 to 255 bytes : %ju\n",
3289 (uintmax_t)stats->rx_pkts_128_255);
3290 printf("Receive frames 256 to 511 bytes : %ju\n",
3291 (uintmax_t)stats->rx_pkts_256_511);
3292 printf("Receive frames 512 to 1024 bytes : %ju\n",
3293 (uintmax_t)stats->rx_pkts_512_1023);
3294 printf("Receive frames 1024 to 1518 bytes : %ju\n",
3295 (uintmax_t)stats->rx_pkts_1024_1518);
3296 printf("Receive frames 1519 to MTU bytes : %ju\n",
3297 (uintmax_t)stats->rx_pkts_1519_max);
3298 printf("Receive frames too long : %ju\n",
3299 (uint64_t)stats->rx_pkts_truncated);
3300 printf("Receive frames with FIFO overflow : %u\n",
3301 stats->rx_fifo_oflows);
3302 printf("Receive frames with return descriptor overflow : %u\n",
3303 stats->rx_desc_oflows);
3304 printf("Receive frames with alignment errors : %u\n",
3305 stats->rx_alignerrs);
3306 printf("Receive frames dropped due to address filtering : %ju\n",
3307 (uint64_t)stats->rx_pkts_filtered);
3308
3309 return (error);
3310 }
3311
3312 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3313 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3314 {
3315 int error, value;
3316
3317 if (arg1 == NULL)
3318 return (EINVAL);
3319 value = *(int *)arg1;
3320 error = sysctl_handle_int(oidp, &value, 0, req);
3321 if (error || req->newptr == NULL)
3322 return (error);
3323 if (value < low || value > high)
3324 return (EINVAL);
3325 *(int *)arg1 = value;
3326
3327 return (0);
3328 }
3329
3330 static int
sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)3331 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3332 {
3333 return (sysctl_int_range(oidp, arg1, arg2, req,
3334 AGE_PROC_MIN, AGE_PROC_MAX));
3335 }
3336
3337 static int
sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)3338 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3339 {
3340
3341 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
3342 AGE_IM_TIMER_MAX));
3343 }
3344