1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
3 *
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28
29
30 #include "stream_encoder.h"
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce120_resource.h"
34 #include "dce112/dce112_resource.h"
35
36 #include "dce110/dce110_resource.h"
37 #include "../virtual/virtual_stream_encoder.h"
38 #include "dce120_timing_generator.h"
39 #include "irq/dce120/irq_service_dce120.h"
40 #include "dce/dce_opp.h"
41 #include "dce/dce_clock_source.h"
42 #include "dce/dce_clocks.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_mem_input.h"
45
46 #include "dce110/dce110_hw_sequencer.h"
47 #include "dce120/dce120_hw_sequencer.h"
48 #include "dce/dce_transform.h"
49
50 #include "dce/dce_audio.h"
51 #include "dce/dce_link_encoder.h"
52 #include "dce/dce_stream_encoder.h"
53 #include "dce/dce_hwseq.h"
54 #include "dce/dce_abm.h"
55 #include "dce/dce_dmcu.h"
56 #include "dce/dce_aux.h"
57
58 #include "dce/dce_12_0_offset.h"
59 #include "dce/dce_12_0_sh_mask.h"
60 #include "soc15_hw_ip.h"
61 #include "vega10_ip_offset.h"
62 #include "nbio/nbio_6_1_offset.h"
63 #include "reg_helper.h"
64
65 #include "dce100/dce100_resource.h"
66
67 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
68 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
69 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
70 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
71 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
72 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
73 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
74 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
75 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
76 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
77 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
79 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
80 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
81 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
82 #endif
83
84 enum dce120_clk_src_array_id {
85 DCE120_CLK_SRC_PLL0,
86 DCE120_CLK_SRC_PLL1,
87 DCE120_CLK_SRC_PLL2,
88 DCE120_CLK_SRC_PLL3,
89 DCE120_CLK_SRC_PLL4,
90 DCE120_CLK_SRC_PLL5,
91
92 DCE120_CLK_SRC_TOTAL
93 };
94
95 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
96 {
97 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
98 },
99 {
100 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
101 },
102 {
103 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
104 },
105 {
106 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
107 },
108 {
109 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
110 },
111 {
112 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
113 }
114 };
115
116 /* begin *********************
117 * macros to expend register list macro defined in HW object header file */
118
119 #define BASE_INNER(seg) \
120 DCE_BASE__INST0_SEG ## seg
121
122 #define NBIO_BASE_INNER(seg) \
123 NBIF_BASE__INST0_SEG ## seg
124
125 #define NBIO_BASE(seg) \
126 NBIO_BASE_INNER(seg)
127
128 /* compile time expand base address. */
129 #define BASE(seg) \
130 BASE_INNER(seg)
131
132 #define SR(reg_name)\
133 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
134 mm ## reg_name
135
136 #define SRI(reg_name, block, id)\
137 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 mm ## block ## id ## _ ## reg_name
139
140 /* macros to expend register list macro defined in HW object header file
141 * end *********************/
142
143
144 static const struct dce_dmcu_registers dmcu_regs = {
145 DMCU_DCE110_COMMON_REG_LIST()
146 };
147
148 static const struct dce_dmcu_shift dmcu_shift = {
149 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
150 };
151
152 static const struct dce_dmcu_mask dmcu_mask = {
153 DMCU_MASK_SH_LIST_DCE110(_MASK)
154 };
155
156 static const struct dce_abm_registers abm_regs = {
157 ABM_DCE110_COMMON_REG_LIST()
158 };
159
160 static const struct dce_abm_shift abm_shift = {
161 ABM_MASK_SH_LIST_DCE110(__SHIFT)
162 };
163
164 static const struct dce_abm_mask abm_mask = {
165 ABM_MASK_SH_LIST_DCE110(_MASK)
166 };
167
168 #define ipp_regs(id)\
169 [id] = {\
170 IPP_DCE110_REG_LIST_DCE_BASE(id)\
171 }
172
173 static const struct dce_ipp_registers ipp_regs[] = {
174 ipp_regs(0),
175 ipp_regs(1),
176 ipp_regs(2),
177 ipp_regs(3),
178 ipp_regs(4),
179 ipp_regs(5)
180 };
181
182 static const struct dce_ipp_shift ipp_shift = {
183 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
184 };
185
186 static const struct dce_ipp_mask ipp_mask = {
187 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
188 };
189
190 #define transform_regs(id)\
191 [id] = {\
192 XFM_COMMON_REG_LIST_DCE110(id)\
193 }
194
195 static const struct dce_transform_registers xfm_regs[] = {
196 transform_regs(0),
197 transform_regs(1),
198 transform_regs(2),
199 transform_regs(3),
200 transform_regs(4),
201 transform_regs(5)
202 };
203
204 static const struct dce_transform_shift xfm_shift = {
205 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
206 };
207
208 static const struct dce_transform_mask xfm_mask = {
209 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
210 };
211
212 #define aux_regs(id)\
213 [id] = {\
214 AUX_REG_LIST(id)\
215 }
216
217 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
218 aux_regs(0),
219 aux_regs(1),
220 aux_regs(2),
221 aux_regs(3),
222 aux_regs(4),
223 aux_regs(5)
224 };
225
226 #define hpd_regs(id)\
227 [id] = {\
228 HPD_REG_LIST(id)\
229 }
230
231 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
232 hpd_regs(0),
233 hpd_regs(1),
234 hpd_regs(2),
235 hpd_regs(3),
236 hpd_regs(4),
237 hpd_regs(5)
238 };
239
240 #define link_regs(id)\
241 [id] = {\
242 LE_DCE120_REG_LIST(id), \
243 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
244 }
245
246 static const struct dce110_link_enc_registers link_enc_regs[] = {
247 link_regs(0),
248 link_regs(1),
249 link_regs(2),
250 link_regs(3),
251 link_regs(4),
252 link_regs(5),
253 link_regs(6),
254 };
255
256
257 #define stream_enc_regs(id)\
258 [id] = {\
259 SE_COMMON_REG_LIST(id),\
260 .TMDS_CNTL = 0,\
261 }
262
263 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
264 stream_enc_regs(0),
265 stream_enc_regs(1),
266 stream_enc_regs(2),
267 stream_enc_regs(3),
268 stream_enc_regs(4),
269 stream_enc_regs(5)
270 };
271
272 static const struct dce_stream_encoder_shift se_shift = {
273 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
274 };
275
276 static const struct dce_stream_encoder_mask se_mask = {
277 SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
278 };
279
280 #define opp_regs(id)\
281 [id] = {\
282 OPP_DCE_120_REG_LIST(id),\
283 }
284
285 static const struct dce_opp_registers opp_regs[] = {
286 opp_regs(0),
287 opp_regs(1),
288 opp_regs(2),
289 opp_regs(3),
290 opp_regs(4),
291 opp_regs(5)
292 };
293
294 static const struct dce_opp_shift opp_shift = {
295 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
296 };
297
298 static const struct dce_opp_mask opp_mask = {
299 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
300 };
301 #define aux_engine_regs(id)\
302 [id] = {\
303 AUX_COMMON_REG_LIST(id), \
304 .AUX_RESET_MASK = 0 \
305 }
306
307 static const struct dce110_aux_registers aux_engine_regs[] = {
308 aux_engine_regs(0),
309 aux_engine_regs(1),
310 aux_engine_regs(2),
311 aux_engine_regs(3),
312 aux_engine_regs(4),
313 aux_engine_regs(5)
314 };
315
316 #define audio_regs(id)\
317 [id] = {\
318 AUD_COMMON_REG_LIST(id)\
319 }
320
321 static const struct dce_audio_registers audio_regs[] = {
322 audio_regs(0),
323 audio_regs(1),
324 audio_regs(2),
325 audio_regs(3),
326 audio_regs(4),
327 audio_regs(5)
328 };
329
330 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
331 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
332 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
333 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
334
335 static const struct dce_audio_shift audio_shift = {
336 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
337 };
338
339 static const struct dce_aduio_mask audio_mask = {
340 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
341 };
342
343 #define clk_src_regs(index, id)\
344 [index] = {\
345 CS_COMMON_REG_LIST_DCE_112(id),\
346 }
347
348 static const struct dce110_clk_src_regs clk_src_regs[] = {
349 clk_src_regs(0, A),
350 clk_src_regs(1, B),
351 clk_src_regs(2, C),
352 clk_src_regs(3, D),
353 clk_src_regs(4, E),
354 clk_src_regs(5, F)
355 };
356
357 static const struct dce110_clk_src_shift cs_shift = {
358 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
359 };
360
361 static const struct dce110_clk_src_mask cs_mask = {
362 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
363 };
364
365 static
dce120_opp_create(struct dc_context * ctx,uint32_t inst)366 struct output_pixel_processor *dce120_opp_create(
367 struct dc_context *ctx,
368 uint32_t inst)
369 {
370 struct dce110_opp *opp =
371 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
372
373 if (!opp)
374 return NULL;
375
376 dce110_opp_construct(opp,
377 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
378 return &opp->base;
379 }
380
381 static
dce120_aux_engine_create(struct dc_context * ctx,uint32_t inst)382 struct aux_engine *dce120_aux_engine_create(
383 struct dc_context *ctx,
384 uint32_t inst)
385 {
386 struct aux_engine_dce110 *aux_engine =
387 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
388
389 if (!aux_engine)
390 return NULL;
391
392 dce110_aux_engine_construct(aux_engine, ctx, inst,
393 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
394 &aux_engine_regs[inst]);
395
396 return &aux_engine->base;
397 }
398
399 static const struct bios_registers bios_regs = {
400 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
401 };
402
403 static const struct resource_caps res_cap = {
404 .num_timing_generator = 6,
405 .num_audio = 7,
406 .num_stream_encoder = 6,
407 .num_pll = 6,
408 };
409
410 static const struct dc_debug_options debug_defaults = {
411 .disable_clock_gate = true,
412 };
413
414 static
dce120_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)415 struct clock_source *dce120_clock_source_create(
416 struct dc_context *ctx,
417 struct dc_bios *bios,
418 enum clock_source_id id,
419 const struct dce110_clk_src_regs *regs,
420 bool dp_clk_src)
421 {
422 struct dce110_clk_src *clk_src =
423 kzalloc(sizeof(*clk_src), GFP_KERNEL);
424
425 if (!clk_src)
426 return NULL;
427
428 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
429 regs, &cs_shift, &cs_mask)) {
430 clk_src->base.dp_clk_src = dp_clk_src;
431 return &clk_src->base;
432 }
433
434 BREAK_TO_DEBUGGER();
435 return NULL;
436 }
437
438 static
dce120_clock_source_destroy(struct clock_source ** clk_src)439 void dce120_clock_source_destroy(struct clock_source **clk_src)
440 {
441 kfree(TO_DCE110_CLK_SRC(*clk_src));
442 *clk_src = NULL;
443 }
444
445 static
dce120_hw_sequencer_create(struct dc * dc)446 bool dce120_hw_sequencer_create(struct dc *dc)
447 {
448 /* All registers used by dce11.2 match those in dce11 in offset and
449 * structure
450 */
451 dce120_hw_sequencer_construct(dc);
452
453 /*TODO Move to separate file and Override what is needed */
454
455 return true;
456 }
457
dce120_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)458 static struct timing_generator *dce120_timing_generator_create(
459 struct dc_context *ctx,
460 uint32_t instance,
461 const struct dce110_timing_generator_offsets *offsets)
462 {
463 struct dce110_timing_generator *tg110 =
464 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
465
466 if (!tg110)
467 return NULL;
468
469 dce120_timing_generator_construct(tg110, ctx, instance, offsets);
470 return &tg110->base;
471 }
472
dce120_transform_destroy(struct transform ** xfm)473 static void dce120_transform_destroy(struct transform **xfm)
474 {
475 kfree(TO_DCE_TRANSFORM(*xfm));
476 *xfm = NULL;
477 }
478
destruct(struct dce110_resource_pool * pool)479 static void destruct(struct dce110_resource_pool *pool)
480 {
481 unsigned int i;
482
483 for (i = 0; i < pool->base.pipe_count; i++) {
484 if (pool->base.opps[i] != NULL)
485 dce110_opp_destroy(&pool->base.opps[i]);
486
487 if (pool->base.transforms[i] != NULL)
488 dce120_transform_destroy(&pool->base.transforms[i]);
489
490 if (pool->base.ipps[i] != NULL)
491 dce_ipp_destroy(&pool->base.ipps[i]);
492
493 if (pool->base.mis[i] != NULL) {
494 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
495 pool->base.mis[i] = NULL;
496 }
497
498 if (pool->base.irqs != NULL) {
499 dal_irq_service_destroy(&pool->base.irqs);
500 }
501
502 if (pool->base.timing_generators[i] != NULL) {
503 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
504 pool->base.timing_generators[i] = NULL;
505 }
506
507 if (pool->base.engines[i] != NULL)
508 dce110_engine_destroy(&pool->base.engines[i]);
509
510 }
511
512 for (i = 0; i < pool->base.audio_count; i++) {
513 if (pool->base.audios[i])
514 dce_aud_destroy(&pool->base.audios[i]);
515 }
516
517 for (i = 0; i < pool->base.stream_enc_count; i++) {
518 if (pool->base.stream_enc[i] != NULL)
519 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
520 }
521
522 for (i = 0; i < pool->base.clk_src_count; i++) {
523 if (pool->base.clock_sources[i] != NULL)
524 dce120_clock_source_destroy(
525 &pool->base.clock_sources[i]);
526 }
527
528 if (pool->base.dp_clock_source != NULL)
529 dce120_clock_source_destroy(&pool->base.dp_clock_source);
530
531 if (pool->base.abm != NULL)
532 dce_abm_destroy(&pool->base.abm);
533
534 if (pool->base.dmcu != NULL)
535 dce_dmcu_destroy(&pool->base.dmcu);
536
537 if (pool->base.dccg != NULL)
538 dce_dccg_destroy(&pool->base.dccg);
539 }
540
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)541 static void read_dce_straps(
542 struct dc_context *ctx,
543 struct resource_straps *straps)
544 {
545 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
546
547 straps->audio_stream_number = get_reg_field_value(reg_val,
548 CC_DC_MISC_STRAPS,
549 AUDIO_STREAM_NUMBER);
550 straps->hdmi_disable = get_reg_field_value(reg_val,
551 CC_DC_MISC_STRAPS,
552 HDMI_DISABLE);
553
554 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
555 straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
556 DC_PINSTRAPS,
557 DC_PINSTRAPS_AUDIO);
558 }
559
create_audio(struct dc_context * ctx,unsigned int inst)560 static struct audio *create_audio(
561 struct dc_context *ctx, unsigned int inst)
562 {
563 return dce_audio_create(ctx, inst,
564 &audio_regs[inst], &audio_shift, &audio_mask);
565 }
566
567 static const struct encoder_feature_support link_enc_feature = {
568 .max_hdmi_deep_color = COLOR_DEPTH_121212,
569 .max_hdmi_pixel_clock = 600000,
570 .ycbcr420_supported = true,
571 .flags.bits.IS_HBR2_CAPABLE = true,
572 .flags.bits.IS_HBR3_CAPABLE = true,
573 .flags.bits.IS_TPS3_CAPABLE = true,
574 .flags.bits.IS_TPS4_CAPABLE = true,
575 .flags.bits.IS_YCBCR_CAPABLE = true
576 };
577
dce120_link_encoder_create(const struct encoder_init_data * enc_init_data)578 static struct link_encoder *dce120_link_encoder_create(
579 const struct encoder_init_data *enc_init_data)
580 {
581 struct dce110_link_encoder *enc110 =
582 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
583
584 if (!enc110)
585 return NULL;
586
587 dce110_link_encoder_construct(enc110,
588 enc_init_data,
589 &link_enc_feature,
590 &link_enc_regs[enc_init_data->transmitter],
591 &link_enc_aux_regs[enc_init_data->channel - 1],
592 &link_enc_hpd_regs[enc_init_data->hpd_source]);
593
594 return &enc110->base;
595 }
596
dce120_ipp_create(struct dc_context * ctx,uint32_t inst)597 static struct input_pixel_processor *dce120_ipp_create(
598 struct dc_context *ctx, uint32_t inst)
599 {
600 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
601
602 if (!ipp) {
603 BREAK_TO_DEBUGGER();
604 return NULL;
605 }
606
607 dce_ipp_construct(ipp, ctx, inst,
608 &ipp_regs[inst], &ipp_shift, &ipp_mask);
609 return &ipp->base;
610 }
611
dce120_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)612 static struct stream_encoder *dce120_stream_encoder_create(
613 enum engine_id eng_id,
614 struct dc_context *ctx)
615 {
616 struct dce110_stream_encoder *enc110 =
617 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
618
619 if (!enc110)
620 return NULL;
621
622 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
623 &stream_enc_regs[eng_id],
624 &se_shift, &se_mask);
625 return &enc110->base;
626 }
627
628 #define SRII(reg_name, block, id)\
629 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
630 mm ## block ## id ## _ ## reg_name
631
632 static const struct dce_hwseq_registers hwseq_reg = {
633 HWSEQ_DCE120_REG_LIST()
634 };
635
636 static const struct dce_hwseq_shift hwseq_shift = {
637 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
638 };
639
640 static const struct dce_hwseq_mask hwseq_mask = {
641 HWSEQ_DCE12_MASK_SH_LIST(_MASK)
642 };
643
dce120_hwseq_create(struct dc_context * ctx)644 static struct dce_hwseq *dce120_hwseq_create(
645 struct dc_context *ctx)
646 {
647 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
648
649 if (hws) {
650 hws->ctx = ctx;
651 hws->regs = &hwseq_reg;
652 hws->shifts = &hwseq_shift;
653 hws->masks = &hwseq_mask;
654 }
655 return hws;
656 }
657
658 static const struct resource_create_funcs res_create_funcs = {
659 .read_dce_straps = read_dce_straps,
660 .create_audio = create_audio,
661 .create_stream_encoder = dce120_stream_encoder_create,
662 .create_hwseq = dce120_hwseq_create,
663 };
664
665 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
666 static const struct dce_mem_input_registers mi_regs[] = {
667 mi_inst_regs(0),
668 mi_inst_regs(1),
669 mi_inst_regs(2),
670 mi_inst_regs(3),
671 mi_inst_regs(4),
672 mi_inst_regs(5),
673 };
674
675 static const struct dce_mem_input_shift mi_shifts = {
676 MI_DCE12_MASK_SH_LIST(__SHIFT)
677 };
678
679 static const struct dce_mem_input_mask mi_masks = {
680 MI_DCE12_MASK_SH_LIST(_MASK)
681 };
682
dce120_mem_input_create(struct dc_context * ctx,uint32_t inst)683 static struct mem_input *dce120_mem_input_create(
684 struct dc_context *ctx,
685 uint32_t inst)
686 {
687 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
688 GFP_KERNEL);
689
690 if (!dce_mi) {
691 BREAK_TO_DEBUGGER();
692 return NULL;
693 }
694
695 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
696 return &dce_mi->base;
697 }
698
dce120_transform_create(struct dc_context * ctx,uint32_t inst)699 static struct transform *dce120_transform_create(
700 struct dc_context *ctx,
701 uint32_t inst)
702 {
703 struct dce_transform *transform =
704 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
705
706 if (!transform)
707 return NULL;
708
709 dce_transform_construct(transform, ctx, inst,
710 &xfm_regs[inst], &xfm_shift, &xfm_mask);
711 transform->lb_memory_size = 0x1404; /*5124*/
712 return &transform->base;
713 }
714
dce120_destroy_resource_pool(struct resource_pool ** pool)715 static void dce120_destroy_resource_pool(struct resource_pool **pool)
716 {
717 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
718
719 destruct(dce110_pool);
720 kfree(dce110_pool);
721 *pool = NULL;
722 }
723
724 static const struct resource_funcs dce120_res_pool_funcs = {
725 .destroy = dce120_destroy_resource_pool,
726 .link_enc_create = dce120_link_encoder_create,
727 .validate_bandwidth = dce112_validate_bandwidth,
728 .validate_plane = dce100_validate_plane,
729 .add_stream_to_ctx = dce112_add_stream_to_ctx
730 };
731
bw_calcs_data_update_from_pplib(struct dc * dc)732 static void bw_calcs_data_update_from_pplib(struct dc *dc)
733 {
734 struct dm_pp_clock_levels_with_latency eng_clks = {0};
735 struct dm_pp_clock_levels_with_latency mem_clks = {0};
736 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
737 int i;
738 unsigned int clk;
739 unsigned int latency;
740
741 /*do system clock*/
742 if (!dm_pp_get_clock_levels_by_type_with_latency(
743 dc->ctx,
744 DM_PP_CLOCK_TYPE_ENGINE_CLK,
745 &eng_clks) || eng_clks.num_levels == 0) {
746
747 eng_clks.num_levels = 8;
748 clk = 300000;
749
750 for (i = 0; i < eng_clks.num_levels; i++) {
751 eng_clks.data[i].clocks_in_khz = clk;
752 clk += 100000;
753 }
754 }
755
756 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
757 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
758 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
759 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
760 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
761 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
762 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
763 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
764 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
765 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
766 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
767 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
768 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
769 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
770 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
771 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
772 eng_clks.data[0].clocks_in_khz, 1000);
773
774 /*do memory clock*/
775 if (!dm_pp_get_clock_levels_by_type_with_latency(
776 dc->ctx,
777 DM_PP_CLOCK_TYPE_MEMORY_CLK,
778 &mem_clks) || mem_clks.num_levels == 0) {
779
780 mem_clks.num_levels = 3;
781 clk = 250000;
782 latency = 45;
783
784 for (i = 0; i < eng_clks.num_levels; i++) {
785 mem_clks.data[i].clocks_in_khz = clk;
786 mem_clks.data[i].latency_in_us = latency;
787 clk += 500000;
788 latency -= 5;
789 }
790
791 }
792
793 /* we don't need to call PPLIB for validation clock since they
794 * also give us the highest sclk and highest mclk (UMA clock).
795 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
796 * YCLK = UMACLK*m_memoryTypeMultiplier
797 */
798 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
799 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
800 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
801 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
802 1000);
803 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
804 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
805 1000);
806
807 /* Now notify PPLib/SMU about which Watermarks sets they should select
808 * depending on DPM state they are in. And update BW MGR GFX Engine and
809 * Memory clock member variables for Watermarks calculations for each
810 * Watermark Set
811 */
812 clk_ranges.num_wm_sets = 4;
813 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
814 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
815 eng_clks.data[0].clocks_in_khz;
816 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
817 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
818 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
819 mem_clks.data[0].clocks_in_khz;
820 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
821 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
822
823 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
824 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
825 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
826 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
827 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
828 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
829 mem_clks.data[0].clocks_in_khz;
830 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
831 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
832
833 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
834 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
835 eng_clks.data[0].clocks_in_khz;
836 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
837 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
838 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
839 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
840 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
841 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
842
843 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
844 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
845 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
846 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
847 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
848 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
849 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
850 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
851 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
852
853 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
854 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
855 }
856
read_pipe_fuses(struct dc_context * ctx)857 static uint32_t read_pipe_fuses(struct dc_context *ctx)
858 {
859 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
860 /* VG20 support max 6 pipes */
861 value = value & 0x3f;
862 return value;
863 }
864
construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)865 static bool construct(
866 uint8_t num_virtual_links,
867 struct dc *dc,
868 struct dce110_resource_pool *pool)
869 {
870 unsigned int i;
871 int j;
872 struct dc_context *ctx = dc->ctx;
873 struct irq_service_init_data irq_init_data;
874 bool harvest_enabled = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
875 uint32_t pipe_fuses;
876
877 ctx->dc_bios->regs = &bios_regs;
878
879 pool->base.res_cap = &res_cap;
880 pool->base.funcs = &dce120_res_pool_funcs;
881
882 /* TODO: Fill more data from GreenlandAsicCapability.cpp */
883 pool->base.pipe_count = res_cap.num_timing_generator;
884 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
885 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
886
887 dc->caps.max_downscale_ratio = 200;
888 dc->caps.i2c_speed_in_khz = 100;
889 dc->caps.max_cursor_size = 128;
890 dc->caps.dual_link_dvi = true;
891 dc->caps.psp_setup_panel_mode = true;
892
893 dc->debug = debug_defaults;
894
895 /*************************************************
896 * Create resources *
897 *************************************************/
898
899 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
900 dce120_clock_source_create(ctx, ctx->dc_bios,
901 CLOCK_SOURCE_COMBO_PHY_PLL0,
902 &clk_src_regs[0], false);
903 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
904 dce120_clock_source_create(ctx, ctx->dc_bios,
905 CLOCK_SOURCE_COMBO_PHY_PLL1,
906 &clk_src_regs[1], false);
907 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
908 dce120_clock_source_create(ctx, ctx->dc_bios,
909 CLOCK_SOURCE_COMBO_PHY_PLL2,
910 &clk_src_regs[2], false);
911 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
912 dce120_clock_source_create(ctx, ctx->dc_bios,
913 CLOCK_SOURCE_COMBO_PHY_PLL3,
914 &clk_src_regs[3], false);
915 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
916 dce120_clock_source_create(ctx, ctx->dc_bios,
917 CLOCK_SOURCE_COMBO_PHY_PLL4,
918 &clk_src_regs[4], false);
919 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
920 dce120_clock_source_create(ctx, ctx->dc_bios,
921 CLOCK_SOURCE_COMBO_PHY_PLL5,
922 &clk_src_regs[5], false);
923 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
924
925 pool->base.dp_clock_source =
926 dce120_clock_source_create(ctx, ctx->dc_bios,
927 CLOCK_SOURCE_ID_DP_DTO,
928 &clk_src_regs[0], true);
929
930 for (i = 0; i < pool->base.clk_src_count; i++) {
931 if (pool->base.clock_sources[i] == NULL) {
932 dm_error("DC: failed to create clock sources!\n");
933 BREAK_TO_DEBUGGER();
934 goto clk_src_create_fail;
935 }
936 }
937
938 pool->base.dccg = dce120_dccg_create(ctx);
939 if (pool->base.dccg == NULL) {
940 dm_error("DC: failed to create display clock!\n");
941 BREAK_TO_DEBUGGER();
942 goto dccg_create_fail;
943 }
944
945 pool->base.dmcu = dce_dmcu_create(ctx,
946 &dmcu_regs,
947 &dmcu_shift,
948 &dmcu_mask);
949 if (pool->base.dmcu == NULL) {
950 dm_error("DC: failed to create dmcu!\n");
951 BREAK_TO_DEBUGGER();
952 goto res_create_fail;
953 }
954
955 pool->base.abm = dce_abm_create(ctx,
956 &abm_regs,
957 &abm_shift,
958 &abm_mask);
959 if (pool->base.abm == NULL) {
960 dm_error("DC: failed to create abm!\n");
961 BREAK_TO_DEBUGGER();
962 goto res_create_fail;
963 }
964
965 irq_init_data.ctx = dc->ctx;
966 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
967 if (!pool->base.irqs)
968 goto irqs_create_fail;
969
970 /* retrieve valid pipe fuses */
971 if (harvest_enabled)
972 pipe_fuses = read_pipe_fuses(ctx);
973
974 /* index to valid pipe resource */
975 j = 0;
976 for (i = 0; i < pool->base.pipe_count; i++) {
977 if (harvest_enabled) {
978 if ((pipe_fuses & (1 << i)) != 0) {
979 dm_error("DC: skip invalid pipe %d!\n", i);
980 continue;
981 }
982 }
983
984 pool->base.timing_generators[j] =
985 dce120_timing_generator_create(
986 ctx,
987 i,
988 &dce120_tg_offsets[i]);
989 if (pool->base.timing_generators[j] == NULL) {
990 BREAK_TO_DEBUGGER();
991 dm_error("DC: failed to create tg!\n");
992 goto controller_create_fail;
993 }
994
995 pool->base.mis[j] = dce120_mem_input_create(ctx, i);
996
997 if (pool->base.mis[j] == NULL) {
998 BREAK_TO_DEBUGGER();
999 dm_error(
1000 "DC: failed to create memory input!\n");
1001 goto controller_create_fail;
1002 }
1003
1004 pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1005 if (pool->base.ipps[i] == NULL) {
1006 BREAK_TO_DEBUGGER();
1007 dm_error(
1008 "DC: failed to create input pixel processor!\n");
1009 goto controller_create_fail;
1010 }
1011
1012 pool->base.transforms[j] = dce120_transform_create(ctx, i);
1013 if (pool->base.transforms[i] == NULL) {
1014 BREAK_TO_DEBUGGER();
1015 dm_error(
1016 "DC: failed to create transform!\n");
1017 goto res_create_fail;
1018 }
1019
1020 pool->base.opps[j] = dce120_opp_create(
1021 ctx,
1022 i);
1023 if (pool->base.opps[j] == NULL) {
1024 BREAK_TO_DEBUGGER();
1025 dm_error(
1026 "DC: failed to create output pixel processor!\n");
1027 }
1028 pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1029 if (pool->base.engines[i] == NULL) {
1030 BREAK_TO_DEBUGGER();
1031 dm_error(
1032 "DC:failed to create aux engine!!\n");
1033 goto res_create_fail;
1034 }
1035
1036 /* check next valid pipe */
1037 j++;
1038 }
1039
1040 /* valid pipe num */
1041 pool->base.pipe_count = j;
1042 pool->base.timing_generator_count = j;
1043
1044 if (!resource_construct(num_virtual_links, dc, &pool->base,
1045 &res_create_funcs))
1046 goto res_create_fail;
1047
1048 /* Create hardware sequencer */
1049 if (!dce120_hw_sequencer_create(dc))
1050 goto controller_create_fail;
1051
1052 dc->caps.max_planes = pool->base.pipe_count;
1053
1054 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1055
1056 bw_calcs_data_update_from_pplib(dc);
1057
1058 return true;
1059
1060 irqs_create_fail:
1061 controller_create_fail:
1062 dccg_create_fail:
1063 clk_src_create_fail:
1064 res_create_fail:
1065
1066 destruct(pool);
1067
1068 return false;
1069 }
1070
dce120_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1071 struct resource_pool *dce120_create_resource_pool(
1072 uint8_t num_virtual_links,
1073 struct dc *dc)
1074 {
1075 struct dce110_resource_pool *pool =
1076 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1077
1078 if (!pool)
1079 return NULL;
1080
1081 if (construct(num_virtual_links, dc, pool))
1082 return &pool->base;
1083
1084 kfree(pool);
1085 BREAK_TO_DEBUGGER();
1086 return NULL;
1087 }
1088