1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 /*
24 * dc_debug.c
25 *
26 * Created on: Nov 3, 2016
27 * Author: yonsun
28 */
29
30 #include "dm_services.h"
31
32 #include "dc.h"
33
34 #include "core_status.h"
35 #include "core_types.h"
36 #include "hw_sequencer.h"
37
38 #include "resource.h"
39
40 #define DC_LOGGER_INIT(logger)
41
42
43 #define SURFACE_TRACE(...) do {\
44 if (dc->debug.surface_trace) \
45 DC_LOG_IF_TRACE(__VA_ARGS__); \
46 } while (0)
47
48 #define TIMING_TRACE(...) do {\
49 if (dc->debug.timing_trace) \
50 DC_LOG_SYNC(__VA_ARGS__); \
51 } while (0)
52
53 #define CLOCK_TRACE(...) do {\
54 if (dc->debug.clock_trace) \
55 DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \
56 } while (0)
57
pre_surface_trace(struct dc * dc,const struct dc_plane_state * const * plane_states,int surface_count)58 void pre_surface_trace(
59 struct dc *dc,
60 const struct dc_plane_state *const *plane_states,
61 int surface_count)
62 {
63 int i;
64 DC_LOGGER_INIT(dc->ctx->logger);
65
66 for (i = 0; i < surface_count; i++) {
67 const struct dc_plane_state *plane_state = plane_states[i];
68
69 SURFACE_TRACE("Planes %d:\n", i);
70
71 SURFACE_TRACE(
72 "plane_state->visible = %d;\n"
73 "plane_state->flip_immediate = %d;\n"
74 "plane_state->address.type = %d;\n"
75 "plane_state->address.grph.addr.quad_part = 0x%lX;\n"
76 "plane_state->address.grph.meta_addr.quad_part = 0x%lX;\n"
77 "plane_state->scaling_quality.h_taps = %d;\n"
78 "plane_state->scaling_quality.v_taps = %d;\n"
79 "plane_state->scaling_quality.h_taps_c = %d;\n"
80 "plane_state->scaling_quality.v_taps_c = %d;\n",
81 plane_state->visible,
82 plane_state->flip_immediate,
83 plane_state->address.type,
84 plane_state->address.grph.addr.quad_part,
85 plane_state->address.grph.meta_addr.quad_part,
86 plane_state->scaling_quality.h_taps,
87 plane_state->scaling_quality.v_taps,
88 plane_state->scaling_quality.h_taps_c,
89 plane_state->scaling_quality.v_taps_c);
90
91 SURFACE_TRACE(
92 "plane_state->src_rect.x = %d;\n"
93 "plane_state->src_rect.y = %d;\n"
94 "plane_state->src_rect.width = %d;\n"
95 "plane_state->src_rect.height = %d;\n"
96 "plane_state->dst_rect.x = %d;\n"
97 "plane_state->dst_rect.y = %d;\n"
98 "plane_state->dst_rect.width = %d;\n"
99 "plane_state->dst_rect.height = %d;\n"
100 "plane_state->clip_rect.x = %d;\n"
101 "plane_state->clip_rect.y = %d;\n"
102 "plane_state->clip_rect.width = %d;\n"
103 "plane_state->clip_rect.height = %d;\n",
104 plane_state->src_rect.x,
105 plane_state->src_rect.y,
106 plane_state->src_rect.width,
107 plane_state->src_rect.height,
108 plane_state->dst_rect.x,
109 plane_state->dst_rect.y,
110 plane_state->dst_rect.width,
111 plane_state->dst_rect.height,
112 plane_state->clip_rect.x,
113 plane_state->clip_rect.y,
114 plane_state->clip_rect.width,
115 plane_state->clip_rect.height);
116
117 SURFACE_TRACE(
118 "plane_state->plane_size.grph.surface_size.x = %d;\n"
119 "plane_state->plane_size.grph.surface_size.y = %d;\n"
120 "plane_state->plane_size.grph.surface_size.width = %d;\n"
121 "plane_state->plane_size.grph.surface_size.height = %d;\n"
122 "plane_state->plane_size.grph.surface_pitch = %d;\n",
123 plane_state->plane_size.grph.surface_size.x,
124 plane_state->plane_size.grph.surface_size.y,
125 plane_state->plane_size.grph.surface_size.width,
126 plane_state->plane_size.grph.surface_size.height,
127 plane_state->plane_size.grph.surface_pitch);
128
129
130 SURFACE_TRACE(
131 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
132 "plane_state->tiling_info.gfx8.bank_width = %d;\n"
133 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
134 "plane_state->tiling_info.gfx8.bank_height = %d;\n"
135 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
136 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
137 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
138 "plane_state->tiling_info.gfx8.tile_split = %d;\n"
139 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
140 "plane_state->tiling_info.gfx8.tile_mode = %d;\n"
141 "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
142 plane_state->tiling_info.gfx8.num_banks,
143 plane_state->tiling_info.gfx8.bank_width,
144 plane_state->tiling_info.gfx8.bank_width_c,
145 plane_state->tiling_info.gfx8.bank_height,
146 plane_state->tiling_info.gfx8.bank_height_c,
147 plane_state->tiling_info.gfx8.tile_aspect,
148 plane_state->tiling_info.gfx8.tile_aspect_c,
149 plane_state->tiling_info.gfx8.tile_split,
150 plane_state->tiling_info.gfx8.tile_split_c,
151 plane_state->tiling_info.gfx8.tile_mode,
152 plane_state->tiling_info.gfx8.tile_mode_c);
153
154 SURFACE_TRACE(
155 "plane_state->tiling_info.gfx8.pipe_config = %d;\n"
156 "plane_state->tiling_info.gfx8.array_mode = %d;\n"
157 "plane_state->color_space = %d;\n"
158 "plane_state->dcc.enable = %d;\n"
159 "plane_state->format = %d;\n"
160 "plane_state->rotation = %d;\n"
161 "plane_state->stereo_format = %d;\n",
162 plane_state->tiling_info.gfx8.pipe_config,
163 plane_state->tiling_info.gfx8.array_mode,
164 plane_state->color_space,
165 plane_state->dcc.enable,
166 plane_state->format,
167 plane_state->rotation,
168 plane_state->stereo_format);
169
170 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
171 plane_state->tiling_info.gfx9.swizzle);
172
173 SURFACE_TRACE("\n");
174 }
175 SURFACE_TRACE("\n");
176 }
177
update_surface_trace(struct dc * dc,const struct dc_surface_update * updates,int surface_count)178 void update_surface_trace(
179 struct dc *dc,
180 const struct dc_surface_update *updates,
181 int surface_count)
182 {
183 int i;
184 DC_LOGGER_INIT(dc->ctx->logger);
185
186 for (i = 0; i < surface_count; i++) {
187 const struct dc_surface_update *update = &updates[i];
188
189 SURFACE_TRACE("Update %d\n", i);
190 if (update->flip_addr) {
191 SURFACE_TRACE("flip_addr->address.type = %d;\n"
192 "flip_addr->address.grph.addr.quad_part = 0x%lX;\n"
193 "flip_addr->address.grph.meta_addr.quad_part = 0x%lX;\n"
194 "flip_addr->flip_immediate = %d;\n",
195 update->flip_addr->address.type,
196 update->flip_addr->address.grph.addr.quad_part,
197 update->flip_addr->address.grph.meta_addr.quad_part,
198 update->flip_addr->flip_immediate);
199 }
200
201 if (update->plane_info) {
202 SURFACE_TRACE(
203 "plane_info->color_space = %d;\n"
204 "plane_info->format = %d;\n"
205 "plane_info->plane_size.grph.surface_pitch = %d;\n"
206 "plane_info->plane_size.grph.surface_size.height = %d;\n"
207 "plane_info->plane_size.grph.surface_size.width = %d;\n"
208 "plane_info->plane_size.grph.surface_size.x = %d;\n"
209 "plane_info->plane_size.grph.surface_size.y = %d;\n"
210 "plane_info->rotation = %d;\n"
211 "plane_info->stereo_format = %d;\n",
212 update->plane_info->color_space,
213 update->plane_info->format,
214 update->plane_info->plane_size.grph.surface_pitch,
215 update->plane_info->plane_size.grph.surface_size.height,
216 update->plane_info->plane_size.grph.surface_size.width,
217 update->plane_info->plane_size.grph.surface_size.x,
218 update->plane_info->plane_size.grph.surface_size.y,
219 update->plane_info->rotation,
220 update->plane_info->stereo_format);
221
222 SURFACE_TRACE(
223 "plane_info->tiling_info.gfx8.num_banks = %d;\n"
224 "plane_info->tiling_info.gfx8.bank_width = %d;\n"
225 "plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
226 "plane_info->tiling_info.gfx8.bank_height = %d;\n"
227 "plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
228 "plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
229 "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
230 "plane_info->tiling_info.gfx8.tile_split = %d;\n"
231 "plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
232 "plane_info->tiling_info.gfx8.tile_mode = %d;\n"
233 "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
234 update->plane_info->tiling_info.gfx8.num_banks,
235 update->plane_info->tiling_info.gfx8.bank_width,
236 update->plane_info->tiling_info.gfx8.bank_width_c,
237 update->plane_info->tiling_info.gfx8.bank_height,
238 update->plane_info->tiling_info.gfx8.bank_height_c,
239 update->plane_info->tiling_info.gfx8.tile_aspect,
240 update->plane_info->tiling_info.gfx8.tile_aspect_c,
241 update->plane_info->tiling_info.gfx8.tile_split,
242 update->plane_info->tiling_info.gfx8.tile_split_c,
243 update->plane_info->tiling_info.gfx8.tile_mode,
244 update->plane_info->tiling_info.gfx8.tile_mode_c);
245
246 SURFACE_TRACE(
247 "plane_info->tiling_info.gfx8.pipe_config = %d;\n"
248 "plane_info->tiling_info.gfx8.array_mode = %d;\n"
249 "plane_info->visible = %d;\n"
250 "plane_info->per_pixel_alpha = %d;\n",
251 update->plane_info->tiling_info.gfx8.pipe_config,
252 update->plane_info->tiling_info.gfx8.array_mode,
253 update->plane_info->visible,
254 update->plane_info->per_pixel_alpha);
255
256 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
257 update->plane_info->tiling_info.gfx9.swizzle);
258 }
259
260 if (update->scaling_info) {
261 SURFACE_TRACE(
262 "scaling_info->src_rect.x = %d;\n"
263 "scaling_info->src_rect.y = %d;\n"
264 "scaling_info->src_rect.width = %d;\n"
265 "scaling_info->src_rect.height = %d;\n"
266 "scaling_info->dst_rect.x = %d;\n"
267 "scaling_info->dst_rect.y = %d;\n"
268 "scaling_info->dst_rect.width = %d;\n"
269 "scaling_info->dst_rect.height = %d;\n"
270 "scaling_info->clip_rect.x = %d;\n"
271 "scaling_info->clip_rect.y = %d;\n"
272 "scaling_info->clip_rect.width = %d;\n"
273 "scaling_info->clip_rect.height = %d;\n"
274 "scaling_info->scaling_quality.h_taps = %d;\n"
275 "scaling_info->scaling_quality.v_taps = %d;\n"
276 "scaling_info->scaling_quality.h_taps_c = %d;\n"
277 "scaling_info->scaling_quality.v_taps_c = %d;\n",
278 update->scaling_info->src_rect.x,
279 update->scaling_info->src_rect.y,
280 update->scaling_info->src_rect.width,
281 update->scaling_info->src_rect.height,
282 update->scaling_info->dst_rect.x,
283 update->scaling_info->dst_rect.y,
284 update->scaling_info->dst_rect.width,
285 update->scaling_info->dst_rect.height,
286 update->scaling_info->clip_rect.x,
287 update->scaling_info->clip_rect.y,
288 update->scaling_info->clip_rect.width,
289 update->scaling_info->clip_rect.height,
290 update->scaling_info->scaling_quality.h_taps,
291 update->scaling_info->scaling_quality.v_taps,
292 update->scaling_info->scaling_quality.h_taps_c,
293 update->scaling_info->scaling_quality.v_taps_c);
294 }
295 SURFACE_TRACE("\n");
296 }
297 SURFACE_TRACE("\n");
298 }
299
post_surface_trace(struct dc * dc)300 void post_surface_trace(struct dc *dc)
301 {
302 DC_LOGGER_INIT(dc->ctx->logger);
303
304 SURFACE_TRACE("post surface process.\n");
305
306 }
307
context_timing_trace(struct dc * dc,struct resource_context * res_ctx)308 void context_timing_trace(
309 struct dc *dc,
310 struct resource_context *res_ctx)
311 {
312 int i;
313 struct dc *core_dc = dc;
314 int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
315 struct crtc_position position;
316 unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
317 DC_LOGGER_INIT(dc->ctx->logger);
318
319
320 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
321 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
322 /* get_position() returns CRTC vertical/horizontal counter
323 * hence not applicable for underlay pipe
324 */
325 if (pipe_ctx->stream == NULL
326 || pipe_ctx->pipe_idx == underlay_idx)
327 continue;
328
329 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
330 h_pos[i] = position.horizontal_count;
331 v_pos[i] = position.vertical_count;
332 }
333 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
334 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
335
336 if (pipe_ctx->stream == NULL)
337 continue;
338
339 TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
340 pipe_ctx->stream_res.tg->inst,
341 pipe_ctx->stream->timing.h_total,
342 pipe_ctx->stream->timing.v_total,
343 h_pos[i], v_pos[i]);
344 }
345 }
346
context_clock_trace(struct dc * dc,struct dc_state * context)347 void context_clock_trace(
348 struct dc *dc,
349 struct dc_state *context)
350 {
351 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
352 DC_LOGGER_INIT(dc->ctx->logger);
353 CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
354 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
355 context->bw.dcn.clk.dispclk_khz,
356 context->bw.dcn.clk.dppclk_khz,
357 context->bw.dcn.clk.dcfclk_khz,
358 context->bw.dcn.clk.dcfclk_deep_sleep_khz,
359 context->bw.dcn.clk.fclk_khz,
360 context->bw.dcn.clk.socclk_khz);
361 CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
362 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
363 context->bw.dcn.clk.dispclk_khz,
364 context->bw.dcn.clk.dppclk_khz,
365 context->bw.dcn.clk.dcfclk_khz,
366 context->bw.dcn.clk.dcfclk_deep_sleep_khz,
367 context->bw.dcn.clk.fclk_khz,
368 context->bw.dcn.clk.socclk_khz);
369 #endif
370 }
371