1/* Definitions of target machine for GNU compiler, for IBM S/390
2   Copyright (C) 2002-2022 Free Software Foundation, Inc.
3   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4                  Ulrich Weigand (uweigand@de.ibm.com).
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 3, or (at your option) any later
11version.
12
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3.  If not see
20<http://www.gnu.org/licenses/>.  */
21
22/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
23INT_MODE (OI, 32);
24
25/* 128-bit float stored in a VR on z14+ or a FPR pair on older machines.  */
26FLOAT_MODE (TF, 16, ieee_quad_format);
27
28/* 128-bit float stored in a FPR pair.  */
29FLOAT_MODE (FPRX2, 16, ieee_quad_format);
30
31/* Add any extra modes needed to represent the condition code.  */
32
33/*
34
35Condition Codes
36
37      CC0         CC1          CC2         CC3
38
39Check for zero
40
41CCZ:  EQ          NE           NE          NE
42CCZ1: EQ          NE                                  (CS)
43
44Unsigned compares
45
46CCU:  EQ          LTU          GTU         NE         (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
47CCUR: EQ          GTU          LTU         NE         (CLGF/R)
48
49Signed compares
50
51CCS:  EQ          LT           GT          UNORDERED  (LTGFR, LTGR, LTR, ICM/Y,
52                                                       LTDBR, LTDR, LTEBR, LTER,
53                                                       CG/R, C/R/Y, CGHI, CHI,
54                                                       CDB/R, CD/R, CEB/R, CE/R,
55                                                       ADB/R, AEB/R, SDB/R, SEB/R,
56                                                       SRAG, SRA, SRDA)
57CCSR: EQ          GT           LT          UNORDERED  (CGF/R, CH/Y)
58CCSFPS: EQ        LT           GT          UNORDERED  (KEB/R, KDB/R, KXBR, KDTR,
59                                                                   KXTR, WFK)
60
61Condition codes resulting from add with overflow
62
63CCA:  EQ          LT           GT          Overflow
64CCAP: EQ          LT           GT          LT         (AGHI, AHI)
65CCAN: EQ          LT           GT          GT         (AGHI, AHI)
66
67Condition codes for overflow checking resulting from signed adds/subs/mults
68
69CCO:  EQ          EQ           EQ          NE         (AGR, AGHI, SGR, MSC, ...)
70
71Condition codes of unsigned adds and subs
72
73CCL:  EQ          NE           EQ          NE         (ALGF/R, ALG/R, AL/R/Y,
74                                                       ALCG/R, ALC/R,
75                                                       SLGF/R, SLG/R, SL/R/Y,
76                                                       SLBG/R, SLB/R)
77CCL1: GEU         GEU          LTU         LTU        (ALG/R, AL/R/Y)
78CCL2: GTU         GTU          LEU         LEU        (SLG/R, SL/R/Y)
79CCL3: EQ          LTU          EQ          GTU        (SLG/R, SL/R/Y)
80
81Test under mask checks
82
83CCT:  EQ          NE           NE          NE         (ICM/Y, TML, CG/R, CGHI,
84                                                       C/R/Y, CHI, NG/R, N/R/Y,
85                                                       OG/R, O/R/Y, XG/R, X/R/Y)
86CCT1: NE          EQ           NE          NE         (TMH, TML)
87CCT2: NE          NE           EQ          NE         (TMH, TML)
88CCT3: NE          NE           NE          EQ         (TMH, TML)
89
90CCA and CCT modes are request only modes. These modes are never returned by
91s390_select_cc_mode. They are only intended to match other modes.
92
93Requested mode            -> Destination CC register mode
94
95CCS, CCU, CCT, CCSR, CCUR -> CCZ
96CCA                       -> CCAP, CCAN
97
98
99
100*** Comments ***
101
102CCAP, CCAN
103
104The CC obtained from add instruction usually can't be used for comparisons
105because its coupling with overflow flag. In case of an overflow the
106less than/greater than data are lost. Nevertheless a comparison can be done
107whenever immediate values are involved because they are known at compile time.
108If you know whether the used constant is positive or negative you can predict
109the sign of the result even in case of an overflow.
110
111
112CCO
113
114This mode is used to check whether there was an overflow condition in
115a signed add, sub, or mul operation.  See (addv<mode>4, subv<mode>4,
116mulv<mode>4 patterns).
117
118
119CCT, CCT1, CCT2, CCT3
120
121If bits of an integer masked with an AND instruction are checked, the test under
122mask instructions turn out to be very handy for a set of special cases.
123The simple cases are checks whether all masked bits are zero or ones:
124
125  int a;
126  if ((a & (16 + 128)) == 0)          -> CCT/CCZ
127  if ((a & (16 + 128)) == 16 + 128)   -> CCT3
128
129Using two extra modes makes it possible to do complete checks on two bits of an
130integer (This is possible on register operands only. TM does not provide the
131information necessary for CCT1 and CCT2 modes.):
132
133  int a;
134  if ((a & (16 + 128)) == 16)         -> CCT1
135  if ((a & (16 + 128)) == 128)        -> CCT2
136
137
138CCSR, CCUR
139
140There are several instructions comparing 32 bit with 64-bit unsigned/signed
141values. Such instructions can be considered to have a builtin zero/sign_extend.
142The problem is that in the RTL (to be canonical) the zero/sign extended operand
143has to be the first one but the machine instructions like it the other way
144around. The following both modes can be considered as CCS and CCU modes with
145exchanged operands.
146
147
148CCSFPS
149
150This mode is used for signaling rtxes: LT, LE, GT, GE and LTGT.
151
152
153CCL1, CCL2
154
155These modes represent the result of overflow checks.
156
157if (a + b < a) -> CCL1 state of the carry bit   (CC2 | CC3)
158if (a - b > a) -> CCL2 state of the borrow bit  (CC0 | CC1)
159
160They are used when multi word numbers are computed dealing one SImode part after
161another or whenever manual overflow checks like the examples above are
162compiled.
163
164
165CCL3
166
167A logical subtract instruction sets the borrow bit in case of an overflow.
168The resulting condition code of those instructions is represented by the
169CCL3 mode. Together with the CCU mode this mode is used for jumpless
170implementations of several if-constructs - see s390_expand_addcc for more
171details.
172
173CCZ1
174
175The compare and swap instructions sets the condition code to 0/1 if the
176operands were equal/unequal. The CCZ1 mode ensures the result can be
177effectively placed into a register.
178
179CCVIH, CCVIHU, CCVFH, CCVFHE
180
181These are condition code modes used in instructions setting the
182condition code.  The mode determines which comparison to perform (H -
183high, HU - high unsigned, HE - high or equal) and whether it is a
184floating point comparison or not (I - int, F - float).
185
186The comparison operation to be performed needs to be encoded into the
187condition code mode since the comparison operator is not available in
188compare style patterns (set cc (compare (op0) (op1))).  So the
189condition code mode is the only information to determine the
190instruction to be used.
191
192CCVIALL, CCVIANY, CCVFALL, CCVFANY
193
194These modes are used in instructions reading the condition code.
195Opposed to the CC producer patterns the comparison operator is
196available.  Hence the comparison operation does not need to be part of
197the CC mode.  However, we still need to know whether CC has been
198generated by a float or an integer comparison in order to be able to
199invert the condition correctly (int: GT -> LE, float: GT -> UNLE).
200
201The ALL and ANY variants differ only in the usage of CC1 which
202indicates a mixed result across the vector elements.  Be aware that
203depending on the comparison code the ALL and ANY variants might
204actually refer to their opposite meaning.  I.e. while inverting the
205comparison in (EQ (reg:CCVIALL 33) (const_int 0)) results in (NE
206(reg:CCVIALL 33) (const_int 0)) it in fact describes an ANY comparison
207(inverting "all equal" should be "any not equal") However, the
208middle-end does invert only the comparison operator without touching
209the mode.
210Hence, the ALL/ANY in the mode names refer to the meaning in the
211context of EQ, GT, GE while for the inverted codes it actually means
212ANY/ALL.
213
214CCRAW
215
216The cc mode generated by a non-compare instruction.  The condition
217code mask for the CC consumer is determined by the comparison operator
218(only EQ and NE allowed) and the immediate value given as second
219operand to the operator.  For the other CC modes this value used to be
2200.
221
222*/
223
224
225CC_MODE (CCZ);
226CC_MODE (CCZ1);
227CC_MODE (CCA);
228CC_MODE (CCAP);
229CC_MODE (CCAN);
230CC_MODE (CCO);
231CC_MODE (CCL);
232CC_MODE (CCL1);
233CC_MODE (CCL2);
234CC_MODE (CCL3);
235CC_MODE (CCU);
236CC_MODE (CCUR);
237CC_MODE (CCS);
238CC_MODE (CCSR);
239CC_MODE (CCSFPS);
240CC_MODE (CCT);
241CC_MODE (CCT1);
242CC_MODE (CCT2);
243CC_MODE (CCT3);
244CC_MODE (CCRAW);
245
246CC_MODE (CCVEQ);
247
248CC_MODE (CCVIH);
249CC_MODE (CCVIHU);
250
251CC_MODE (CCVFH);
252CC_MODE (CCVFHE);
253
254CC_MODE (CCVIALL);
255CC_MODE (CCVIANY);
256
257CC_MODE (CCVFALL);
258CC_MODE (CCVFANY);
259
260/* Vector modes.  */
261
262VECTOR_MODES (INT, 2);        /*                       V2QI */
263VECTOR_MODES (INT, 4);        /*                  V4QI V2HI */
264VECTOR_MODES (INT, 8);        /*             V8QI V4HI V2SI */
265VECTOR_MODES (INT, 16);       /*       V16QI V8HI V4SI V2DI */
266VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI V2TI */
267
268VECTOR_MODE (FLOAT, SF, 2);   /* V2SF */
269VECTOR_MODE (FLOAT, SF, 4);   /* V4SF */
270VECTOR_MODE (FLOAT, SF, 8);   /* V8SF */
271VECTOR_MODE (FLOAT, DF, 2);   /* V2DF */
272VECTOR_MODE (FLOAT, DF, 4);   /* V4DF */
273
274VECTOR_MODE (INT, QI, 1);     /* V1QI */
275VECTOR_MODE (INT, HI, 1);     /* V1HI */
276VECTOR_MODE (INT, SI, 1);     /* V1SI */
277VECTOR_MODE (INT, DI, 1);     /* V1DI */
278VECTOR_MODE (INT, TI, 1);     /* V1TI */
279
280VECTOR_MODE (FLOAT, SF, 1);   /* V1SF */
281VECTOR_MODE (FLOAT, DF, 1);   /* V1DF */
282VECTOR_MODE (FLOAT, TF, 1);   /* V1TF */
283