1 /* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */
2
3 /*
4 * Copyright (c) 2003
5 * Ichiro FUKUHARA <ichiro@ichiro.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Ichiro FUKUHARA.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD: stable/10/sys/arm/xscale/ixp425/ixp425_pci.c 278613 2015-02-12 03:50:33Z ian $");
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #define _ARM32_BUS_DMA_PRIVATE
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/rman.h>
47
48 #include <dev/pci/pcivar.h>
49
50 #include <machine/armreg.h>
51 #include <machine/bus.h>
52 #include <machine/cpu.h>
53 #include <machine/pcb.h>
54
55 #include <vm/vm.h>
56 #include <vm/pmap.h>
57 #include <vm/vm_extern.h>
58
59 #include <arm/xscale/ixp425/ixp425reg.h>
60 #include <arm/xscale/ixp425/ixp425var.h>
61
62 #include <dev/pci/pcib_private.h>
63 #include "pcib_if.h"
64
65 #include <dev/pci/pcireg.h>
66 extern struct ixp425_softc *ixp425_softc;
67
68 #define PCI_CSR_WRITE_4(sc, reg, data) \
69 bus_write_4(sc->sc_csr, reg, data)
70
71 #define PCI_CSR_READ_4(sc, reg) \
72 bus_read_4(sc->sc_csr, reg)
73
74 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I)
75 #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
76
77 static device_probe_t ixppcib_probe;
78 static device_attach_t ixppcib_attach;
79 static bus_read_ivar_t ixppcib_read_ivar;
80 static bus_write_ivar_t ixppcib_write_ivar;
81 static bus_setup_intr_t ixppcib_setup_intr;
82 static bus_teardown_intr_t ixppcib_teardown_intr;
83 static bus_alloc_resource_t ixppcib_alloc_resource;
84 static bus_activate_resource_t ixppcib_activate_resource;
85 static bus_deactivate_resource_t ixppcib_deactivate_resource;
86 static bus_release_resource_t ixppcib_release_resource;
87 static pcib_maxslots_t ixppcib_maxslots;
88 static pcib_read_config_t ixppcib_read_config;
89 static pcib_write_config_t ixppcib_write_config;
90 static pcib_route_interrupt_t ixppcib_route_interrupt;
91
92 static int
ixppcib_probe(device_t dev)93 ixppcib_probe(device_t dev)
94 {
95 device_set_desc(dev, "IXP4XX PCI Bus");
96 return (0);
97 }
98
99 static void
ixp425_pci_conf_reg_write(struct ixppcib_softc * sc,uint32_t reg,uint32_t data)100 ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg,
101 uint32_t data)
102 {
103 PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
104 PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data);
105 }
106
107 static int
ixppcib_attach(device_t dev)108 ixppcib_attach(device_t dev)
109 {
110 int rid;
111 struct ixppcib_softc *sc;
112
113 sc = device_get_softc(dev);
114
115 rid = 0;
116 sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
117 IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE,
118 IXP425_PCI_SIZE, RF_ACTIVE);
119 if (sc->sc_csr == NULL)
120 panic("cannot allocate PCI CSR registers");
121
122 ixp425_md_attach(dev);
123 /* always setup the base, incase another OS messes w/ it */
124 PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
125
126 rid = 0;
127 sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
128 IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE,
129 IXP425_PCI_MEM_SIZE, RF_ACTIVE);
130 if (sc->sc_mem == NULL)
131 panic("cannot allocate PCI MEM space");
132
133 /* NB: PCI dma window is 64M so anything above must be bounced */
134 if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024,
135 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
136 NULL, NULL, &sc->sc_dmat))
137 panic("couldn't create the PCI dma tag !");
138 /*
139 * The PCI bus can only address 64MB. However, due to the way our
140 * implementation of busdma works, busdma can't tell if a device
141 * is a PCI device or not. So defaults to the PCI dma tag, which
142 * restrict the DMA'able memory to the first 64MB, and explicitely
143 * create less restrictive tags for non-PCI devices.
144 */
145 arm_root_dma_tag = sc->sc_dmat;
146 /*
147 * Initialize the bus space tags.
148 */
149 ixp425_io_bs_init(&sc->sc_pci_iot, sc);
150 ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
151
152 sc->sc_dev = dev;
153
154 /* Initialize memory and i/o rmans. */
155 sc->sc_io_rman.rm_type = RMAN_ARRAY;
156 sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports";
157 if (rman_init(&sc->sc_io_rman) != 0 ||
158 rman_manage_region(&sc->sc_io_rman, 0,
159 IXP425_PCI_IO_SIZE) != 0) {
160 panic("ixppcib_probe: failed to set up I/O rman");
161 }
162
163 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
164 sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory";
165 if (rman_init(&sc->sc_mem_rman) != 0 ||
166 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE,
167 IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) {
168 panic("ixppcib_probe: failed to set up memory rman");
169 }
170
171 /*
172 * PCI->AHB address translation
173 * begin at the physical memory start + OFFSET
174 */
175 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
176 (IXP425_AHB_OFFSET & 0xFF000000) +
177 ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) +
178 ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) +
179 ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) +
180 0x00010203);
181
182 #define IXPPCIB_WRITE_CONF(sc, reg, val) \
183 ixp425_pci_conf_reg_write(sc, reg, val)
184 /* Write Mapping registers PCI Configuration Registers */
185 /* Base Address 0 - 3 */
186 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000);
187 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000);
188 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000);
189 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000);
190
191 /* Base Address 4 */
192 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff);
193
194 /* Base Address 5 */
195 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000);
196
197 /* Assert some PCI errors */
198 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
199
200 #ifdef __ARMEB__
201 /*
202 * Set up byte lane swapping between little-endian PCI
203 * and the big-endian AHB bus
204 */
205 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
206 #else
207 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE);
208 #endif
209
210 /*
211 * Enable bus mastering and I/O,memory access
212 */
213 IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
214 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
215
216 /*
217 * Wait some more to ensure PCI devices have stabilised.
218 */
219 DELAY(50000);
220
221 device_add_child(dev, "pci", -1);
222 return (bus_generic_attach(dev));
223 }
224
225 static int
ixppcib_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)226 ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
227 {
228 struct ixppcib_softc *sc;
229
230 sc = device_get_softc(dev);
231 switch (which) {
232 case PCIB_IVAR_DOMAIN:
233 *result = 0;
234 return (0);
235 case PCIB_IVAR_BUS:
236 *result = sc->sc_bus;
237 return (0);
238 }
239
240 return (ENOENT);
241 }
242
243 static int
ixppcib_write_ivar(device_t dev,device_t child,int which,uintptr_t value)244 ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
245 {
246 struct ixppcib_softc *sc;
247
248 sc = device_get_softc(dev);
249 switch (which) {
250 case PCIB_IVAR_DOMAIN:
251 return (EINVAL);
252 case PCIB_IVAR_BUS:
253 sc->sc_bus = value;
254 return (0);
255 }
256
257 return (ENOENT);
258 }
259
260 static int
ixppcib_setup_intr(device_t dev,device_t child,struct resource * ires,int flags,driver_filter_t * filt,driver_intr_t * intr,void * arg,void ** cookiep)261 ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires,
262 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
263 void **cookiep)
264 {
265
266 return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
267 filt, intr, arg, cookiep));
268 }
269
270 static int
ixppcib_teardown_intr(device_t dev,device_t child,struct resource * vec,void * cookie)271 ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
272 void *cookie)
273 {
274
275 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie));
276 }
277
278 static struct resource *
ixppcib_alloc_resource(device_t bus,device_t child,int type,int * rid,u_long start,u_long end,u_long count,u_int flags)279 ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
280 u_long start, u_long end, u_long count, u_int flags)
281 {
282 struct ixppcib_softc *sc = device_get_softc(bus);
283 struct rman *rmanp;
284 struct resource *rv;
285
286 rv = NULL;
287 switch (type) {
288 case SYS_RES_IRQ:
289 rmanp = &sc->sc_irq_rman;
290 break;
291
292 case SYS_RES_IOPORT:
293 rmanp = &sc->sc_io_rman;
294 break;
295
296 case SYS_RES_MEMORY:
297 rmanp = &sc->sc_mem_rman;
298 break;
299
300 default:
301 return (rv);
302 }
303
304 rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE,
305 child);
306 if (rv == NULL)
307 return (NULL);
308 rman_set_rid(rv, *rid);
309 if (flags & RF_ACTIVE) {
310 if (bus_activate_resource(child, type, *rid, rv)) {
311 rman_release_resource(rv);
312 return (NULL);
313 }
314 }
315
316 return (rv);
317 }
318
319 static int
ixppcib_activate_resource(device_t bus,device_t child,int type,int rid,struct resource * r)320 ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
321 struct resource *r)
322 {
323
324 struct ixppcib_softc *sc = device_get_softc(bus);
325
326 switch (type) {
327 case SYS_RES_IOPORT:
328 rman_set_bustag(r, &sc->sc_pci_iot);
329 rman_set_bushandle(r, rman_get_start(r));
330 break;
331 case SYS_RES_MEMORY:
332 rman_set_bustag(r, &sc->sc_pci_memt);
333 rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) +
334 (rman_get_start(r) - IXP425_PCI_MEM_HWBASE));
335 break;
336 }
337
338 return (rman_activate_resource(r));
339 }
340
341 static int
ixppcib_deactivate_resource(device_t bus,device_t child,int type,int rid,struct resource * r)342 ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
343 struct resource *r)
344 {
345
346 device_printf(bus, "%s called deactivate_resource (unexpected)\n",
347 device_get_nameunit(child));
348 return (ENXIO);
349 }
350
351 static int
ixppcib_release_resource(device_t bus,device_t child,int type,int rid,struct resource * r)352 ixppcib_release_resource(device_t bus, device_t child, int type, int rid,
353 struct resource *r)
354 {
355
356 device_printf(bus, "%s called release_resource (unexpected)\n",
357 device_get_nameunit(child));
358 return (ENXIO);
359 }
360
361 static void
ixppcib_conf_setup(struct ixppcib_softc * sc,int bus,int slot,int func,int reg)362 ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func,
363 int reg)
364 {
365 if (bus == 0) {
366 /* configuration type 0 */
367 PCI_CSR_WRITE_4(sc, PCI_NP_AD,
368 (1U << (32 - (slot & 0x1f))) |
369 ((func & 0x7) << 8) | (reg & ~3));
370 } else {
371 /* configuration type 1 */
372 PCI_CSR_WRITE_4(sc, PCI_NP_AD,
373 (bus << 16) | (slot << 11) |
374 (func << 8) | (reg & ~3) | 1);
375 }
376
377 }
378
379 static int
ixppcib_maxslots(device_t dev)380 ixppcib_maxslots(device_t dev)
381 {
382
383 return (PCI_SLOTMAX);
384 }
385
386 static u_int32_t
ixppcib_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)387 ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
388 int bytes)
389 {
390 struct ixppcib_softc *sc = device_get_softc(dev);
391 u_int32_t data, ret;
392
393 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
394
395 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
396 ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
397 ret >>= (reg & 3) * 8;
398 ret &= 0xffffffff >> ((4 - bytes) * 8);
399 #if 0
400 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n",
401 __func__, bus, slot, func, reg, bytes, ret);
402 #endif
403 /* check & clear PCI abort */
404 data = PCI_CSR_READ_4(sc, PCI_ISR);
405 if (data & ISR_PFE) {
406 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
407 return (-1);
408 }
409 return (ret);
410 }
411
412 static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 };
413
414 static void
ixppcib_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,u_int32_t val,int bytes)415 ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
416 u_int32_t val, int bytes)
417 {
418 struct ixppcib_softc *sc = device_get_softc(dev);
419 u_int32_t data;
420
421 #if 0
422 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n",
423 __func__, bus, slot, func, reg, bytes, val);
424 #endif
425 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
426
427 /* Byte enables are active low, so not them first */
428 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE |
429 (~(byteenables[bytes] << (reg & 3)) & 0xf0));
430 PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8));
431
432 /* check & clear PCI abort */
433 data = PCI_CSR_READ_4(sc, PCI_ISR);
434 if (data & ISR_PFE)
435 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
436 }
437
438 static int
ixppcib_route_interrupt(device_t bridge,device_t device,int pin)439 ixppcib_route_interrupt(device_t bridge, device_t device, int pin)
440 {
441
442 return (ixp425_md_route_interrupt(bridge, device, pin));
443 }
444
445 static device_method_t ixppcib_methods[] = {
446 /* Device interface */
447 DEVMETHOD(device_probe, ixppcib_probe),
448 DEVMETHOD(device_attach, ixppcib_attach),
449
450 /* Bus interface */
451 DEVMETHOD(bus_read_ivar, ixppcib_read_ivar),
452 DEVMETHOD(bus_write_ivar, ixppcib_write_ivar),
453 DEVMETHOD(bus_setup_intr, ixppcib_setup_intr),
454 DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr),
455 DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource),
456 DEVMETHOD(bus_activate_resource, ixppcib_activate_resource),
457 DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource),
458 DEVMETHOD(bus_release_resource, ixppcib_release_resource),
459 /* DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), */
460
461 /* pcib interface */
462 DEVMETHOD(pcib_maxslots, ixppcib_maxslots),
463 DEVMETHOD(pcib_read_config, ixppcib_read_config),
464 DEVMETHOD(pcib_write_config, ixppcib_write_config),
465 DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt),
466
467 DEVMETHOD_END
468 };
469
470 static driver_t ixppcib_driver = {
471 "pcib",
472 ixppcib_methods,
473 sizeof(struct ixppcib_softc),
474 };
475 static devclass_t ixppcib_devclass;
476
477 DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);
478