1 /*-
2 * Copyright (c) 2011 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas of 3am Software Foundry.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #define LBC_PRIVATE
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: pq3nandfcm.c,v 1.5 2023/05/10 00:08:07 riastradh Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/device.h>
38 #include <sys/cpu.h>
39
40 #include <sys/bus.h>
41
42 #include <powerpc/booke/cpuvar.h>
43 #include <powerpc/booke/e500reg.h>
44 #include <powerpc/booke/obiovar.h>
45
46 #include <dev/nand/nand.h>
47 #include <dev/nand/onfi.h>
48
49 static int pq3nandfcm_match(device_t, cfdata_t, void *);
50 static void pq3nandfcm_attach(device_t, device_t, void *);
51 static int pq3nandfcm_detach(device_t, int);
52
53 static void pq3nandfcm_select(device_t, bool);
54 static void pq3nandfcm_command(device_t, uint8_t);
55 static void pq3nandfcm_address(device_t, uint8_t);
56 static void pq3nandfcm_busy(device_t);
57 static void pq3nandfcm_read_byte(device_t, uint8_t *);
58 static void pq3nandfcm_write_byte(device_t, uint8_t);
59 static void pq3nandfcm_read_buf(device_t, void *, size_t);
60 static void pq3nandfcm_write_buf(device_t, const void *, size_t);
61
62 struct pq3nandfcm_softc {
63 device_t sc_dev;
64 bus_space_tag_t sc_window_bst;
65 bus_space_handle_t sc_window_bsh;
66 bus_size_t sc_window_size;
67
68 struct nand_interface sc_nandif;
69 device_t sc_nanddev;
70
71 struct pq3obio_softc *sc_obio;
72 struct pq3lbc_softc *sc_lbc;
73
74 u_int sc_cs;
75
76 };
77
78 CFATTACH_DECL_NEW(pq3nandfcm, sizeof(struct pq3nandfcm_softc),
79 pq3nandfcm_match, pq3nandfcm_attach, pq3nandfcm_detach, NULL);
80
81 int
pq3nandfcm_match(device_t parent,cfdata_t cf,void * aux)82 pq3nandfcm_match(device_t parent, cfdata_t cf, void *aux)
83 {
84 struct generic_attach_args * const ga = aux;
85 struct pq3obio_softc * const psc = device_private(parent);
86 struct pq3lbc_softc * const lbc = &psc->sc_lbcs[ga->ga_cs];
87
88 if ((lbc->lbc_br & BR_V) == 0)
89 return 0;
90
91 if (__SHIFTOUT(lbc->lbc_br,BR_MSEL) != BR_MSEL_FCM)
92 return 0;
93
94 return 1;
95 }
96
97 void
pq3nandfcm_attach(device_t parent,device_t self,void * aux)98 pq3nandfcm_attach(device_t parent, device_t self, void *aux)
99 {
100 struct generic_attach_args * const ga = aux;
101 struct pq3nandfcm_softc * const sc = device_private(self);
102 struct pq3obio_softc * const psc = device_private(parent);
103 struct pq3lbc_softc * const lbc = &psc->sc_lbcs[ga->ga_cs];
104
105 sc->sc_dev = self;
106 sc->sc_obio = psc;
107 sc->sc_lbc = lbc;
108 }
109
110 int
pq3nandfcm_detach(device_t self,int flags)111 pq3nandfcm_detach(device_t self, int flags)
112 {
113 struct pq3nandfcm_softc * const sc = device_private(self);
114 int error;
115
116 error = config_detach_children(self, flags);
117 if (error)
118 return error;
119
120 pmf_device_deregister(self);
121
122 bus_space_unmap(sc->sc_window_bst, sc->sc_window_bsh,
123 sc->sc_window_size);
124 return 0;
125 }
126 void
pq3nandfcm_command(device_t self,uint8_t command)127 pq3nandfcm_command(device_t self, uint8_t command)
128 {
129 struct pq3nandfcm_softc * const sc = device_private(self);
130
131 lbc_lock(sc->sc_obio);
132 lbc_write_4(sc->sc_obio, FCR, __SHIFTIN(command, FCR_CMD0));
133 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_CM0, FIR_OP0));
134 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs);
135 lbc_unlock(sc->sc_obio);
136
137 }
138
139 void
pq3nandfcm_address(device_t self,uint8_t address)140 pq3nandfcm_address(device_t self, uint8_t address)
141 {
142 struct pq3nandfcm_softc * const sc = device_private(self);
143
144 lbc_lock(sc->sc_obio);
145 lbc_write_4(sc->sc_obio, MDR, __SHIFTIN(address, MDR_AS0));
146 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_UA, FIR_OP0));
147 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs);
148 lbc_unlock(sc->sc_obio);
149 }
150
151 void
pq3nandfcm_busy(device_t self)152 pq3nandfcm_busy(device_t self)
153 {
154 struct pq3nandfcm_softc * const sc = device_private(self);
155
156 lbc_lock(sc->sc_obio);
157 for (;;) {
158 uint32_t v = lbc_read_4(sc->sc_obio, LTESR);
159 if ((v & LTESR_CC) == 0) {
160 /*
161 * The command is done but the device might not
162 * be ready since the CC doesn't check for that.
163 */
164 break;
165 }
166 DELAY(1);
167 }
168 lbc_unlock(sc->sc_obio);
169 }
170
171 void
pq3nandfcm_read_byte(device_t self,uint8_t * valp)172 pq3nandfcm_read_byte(device_t self, uint8_t *valp)
173 {
174 struct pq3nandfcm_softc * const sc = device_private(self);
175
176 lbc_lock(sc->sc_obio);
177 /*
178 * Make sure the device is ready before reading the byte.
179 */
180 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_RSW, FIR_OP0));
181 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs);
182 uint32_t v = lbc_read_4(sc->sc_obio, MDR);
183 lbc_unlock(sc->sc_obio);
184
185 *valp = (uint8_t) v;
186 }
187
188 void
pq3nandfcm_write_byte(device_t self,uint8_t val)189 pq3nandfcm_write_byte(device_t self, uint8_t val)
190 {
191 struct pq3nandfcm_softc * const sc = device_private(self);
192
193 lbc_lock(sc->sc_obio);
194 lbc_write_4(sc->sc_obio, MDR, val);
195 /*
196 * Make sure the device is ready before writing the byte.
197 */
198 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_WS, FIR_OP0));
199 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs);
200 lbc_unlock(sc->sc_obio);
201 }
202
203 void
pq3nandfcm_read_buf(device_t self,void * buf,size_t len)204 pq3nandfcm_read_buf(device_t self, void *buf, size_t len)
205 {
206 struct pq3nandfcm_softc * const sc = device_private(self);
207 bus_size_t offset = 0;
208 uint32_t *dp32 = buf;
209
210 KASSERT(len < 4096);
211 KASSERT((len & 3) == 0);
212 KASSERT(((uintptr_t)dp32 & 3) == 0);
213
214 lbc_lock(sc->sc_obio);
215 lbc_write_4(sc->sc_obio, FCR, len);
216 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_RBW, FIR_OP0));
217 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs);
218
219 while (lbc_read_4(sc->sc_obio, LTESR) & LTESR_CC) {
220 DELAY(1);
221 }
222 for (offset = 0; len >= 4; offset += 4, len -= 4) {
223 *dp32++ = fcm_buf_read(sc, offset);
224 }
225 if (len) {
226 const uint32_t mask = ~0 >> (8 * len);
227 const uint32_t data = fcm_buf_read(sc, offset);
228 *dp32 = (data & ~mask) | (*dp32 & mask);
229 }
230 lbc_unlock(sc->sc_obio);
231 }
232
233 void
pq3nandfcm_write_buf(device_t self,const void * buf,size_t len)234 pq3nandfcm_write_buf(device_t self, const void *buf, size_t len)
235 {
236 struct pq3nandfcm_softc * const sc = device_private(self);
237 bus_size_t offset = 0;
238 const uint32_t *dp32 = buf;
239
240 KASSERT(len < 4096);
241 KASSERT((len & 3) == 0);
242 KASSERT(((uintptr_t)dp32 & 3) == 0);
243
244 lbc_lock(sc->sc_obio);
245 lbc_write_4(sc->sc_obio, FCR, len);
246
247 /*
248 * First we need to copy to the FCM buffer. There will be a few extra
249 * bytes at the end but we don't care.
250 */
251 for (len = roundup2(len, 4); offset < len; offset += 4, dp32++) {
252 fcm_buf_write(sc, offset, *dp32);
253 }
254
255 /*
256 * W
257 */
258 lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_WB, FIR_OP0));
259 lbc_write_4(sc->sc_obio, LSOR, sc->sc_cs);
260 while (lbc_read_4(sc->sc_obio, LTESR) & LTESR_CC) {
261 DELAY(1);
262 }
263 lbc_unlock(sc->sc_obio);
264 }
265