1 /* $NetBSD: pq3gpio.c,v 1.14 2021/08/07 16:19:02 thorpej Exp $ */
2 /*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 *
10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #define GLOBAL_PRIVATE
38 #define GPIO_PRIVATE
39
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.14 2021/08/07 16:19:02 thorpej Exp $");
42
43 #ifdef _KERNEL_OPT
44 #include "opt_mpc85xx.h"
45 #endif
46
47 #include <sys/param.h>
48 #include <sys/cpu.h>
49 #include <sys/device.h>
50 #include <sys/tty.h>
51 #include <sys/kmem.h>
52 #include <sys/gpio.h>
53 #include <sys/bitops.h>
54
55 #include "ioconf.h"
56
57 #include <sys/intr.h>
58 #include <sys/bus.h>
59
60 #include <dev/gpio/gpiovar.h>
61
62 #include <powerpc/booke/cpuvar.h>
63 #include <powerpc/booke/spr.h>
64 #include <powerpc/booke/e500var.h>
65 #include <powerpc/booke/e500reg.h>
66
67 struct pq3gpio_group {
68 struct gpio_chipset_tag gc_tag;
69 gpio_pin_t gc_pins[32];
70 bus_space_tag_t gc_bst;
71 bus_space_handle_t gc_bsh;
72 bus_size_t gc_reg;
73 };
74
75 struct pq3gpio_softc {
76 device_t sc_dev;
77 bus_space_tag_t sc_bst;
78 bus_space_handle_t sc_bsh;
79 SIMPLEQ_HEAD(,pq3gpio_group) sc_gpios;
80 };
81
82 static int
pq3gpio_pin_read(void * v,int num)83 pq3gpio_pin_read(void *v, int num)
84 {
85 struct pq3gpio_group * const gc = v;
86
87 uint32_t data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg);
88
89 return (data >> (gc->gc_pins[num].pin_num ^ 31)) & 1;
90 }
91
92 static void
pq3gpio_pin_write(void * v,int num,int val)93 pq3gpio_pin_write(void *v, int num, int val)
94 {
95 struct pq3gpio_group * const gc = v;
96 const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31);
97
98 val = val ? mask : 0;
99 u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg);
100 if ((data & mask) != val) {
101 data = (data & ~mask) | val;
102 bus_space_write_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg, data);
103 }
104 }
105
106 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8544)
107 static void
pq3gpio_null_pin_ctl(void * v,int num,int ctl)108 pq3gpio_null_pin_ctl(void *v, int num, int ctl)
109 {
110 }
111 #endif
112
113 #if defined(P1025)
114 /*
115 * P1025 has controllable input/output pins
116 */
117 static void
pq3gpio_pin_ctl(void * v,int num,int ctl)118 pq3gpio_pin_ctl(void *v, int num, int ctl)
119 {
120 struct pq3gpio_group * const gc = v;
121 const size_t shift = gc->gc_pins[num].pin_num ^ 31;
122
123 uint64_t old_dir =
124 ((uint64_t)bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR1) << 32)
125 | (bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR2) << 0);
126
127 uint32_t dir = 0;
128 switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
129 case GPIO_PIN_INPUT|GPIO_PIN_OUTPUT: dir = CPDIR_INOUT; break;
130 case GPIO_PIN_OUTPUT: dir = CPDIR_OUT; break;
131 case GPIO_PIN_INPUT: dir = CPDIR_INOUT; break;
132 case 0: dir = CPDIR_DIS; break;
133 }
134
135 uint64_t new_dir = (old_dir & (3ULL << (2 * shift)))
136 | ((uint64_t)dir << (2 * shift));
137
138 if ((uint32_t)old_dir != (uint32_t)new_dir)
139 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR2,
140 (uint32_t)new_dir);
141 new_dir >>= 32;
142 old_dir >>= 32;
143 if ((uint32_t)old_dir != (uint32_t)new_dir)
144 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR1,
145 (uint32_t)new_dir);
146
147 /*
148 * Now handle opendrain
149 */
150 uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPODR);
151 uint32_t new_odr = old_odr;
152 uint32_t odr_mask = 1UL << shift;
153
154 if (ctl & GPIO_PIN_OPENDRAIN) {
155 new_odr |= odr_mask;
156 } else {
157 new_odr &= ~odr_mask;
158 }
159
160 if (old_odr != new_odr)
161 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPODR, new_odr);
162 }
163 #endif
164
165 #if defined(MPC8536) || defined(P2020) || defined(P1023)
166 /*
167 * MPC8536 / P20x0 / P1023 have controllable input/output pins
168 */
169 static void
pq3gpio_pin_ctl(void * v,int num,int ctl)170 pq3gpio_pin_ctl(void *v, int num, int ctl)
171 {
172 struct pq3gpio_group * const gc = v;
173 const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31);
174
175 uint32_t old_dir = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPDIR);
176 uint32_t new_dir = old_dir;
177 switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
178 case GPIO_PIN_OUTPUT: new_dir |= mask; break;
179 case GPIO_PIN_INPUT: new_dir &= ~mask; break;
180 default: return;
181 }
182 if (old_dir != new_dir)
183 bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPDIR, new_dir);
184
185 /*
186 * Now handle opendrain
187 */
188 uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPODR);
189 uint32_t new_odr = old_odr;
190
191 if (ctl & GPIO_PIN_OPENDRAIN) {
192 new_odr |= mask;
193 } else {
194 new_odr &= ~mask;
195 }
196
197 if (old_odr != new_odr)
198 bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPODR, new_odr);
199 }
200 #endif
201
202 static void
pq3gpio_group_create(device_t self,bus_space_tag_t bst,bus_space_handle_t bsh,bus_size_t reg,uint32_t pinmask,int pincaps,void (* pin_ctl)(void *,int,int))203 pq3gpio_group_create(device_t self, bus_space_tag_t bst, bus_space_handle_t bsh,
204 bus_size_t reg, uint32_t pinmask, int pincaps,
205 void (*pin_ctl)(void *, int, int))
206 {
207 struct pq3gpio_group * const gc = kmem_zalloc(sizeof(*gc), KM_SLEEP);
208
209 gc->gc_bst = bst;
210 gc->gc_bsh = bsh;
211 gc->gc_reg = reg;
212 gc->gc_tag.gp_cookie = gc;
213 #if 0
214 gc->gc_tag.gp_gc_open = pq3gpio_gc_open;
215 gc->gc_tag.gp_gc_close = pq3gpio_gc_close;
216 #endif
217 gc->gc_tag.gp_pin_read = pq3gpio_pin_read;
218 gc->gc_tag.gp_pin_write = pq3gpio_pin_write;
219 gc->gc_tag.gp_pin_ctl = pin_ctl;
220
221 u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, reg);
222 u_int mask = __BIT(31);
223 gpio_pin_t *pin = gc->gc_pins;
224 for (u_int i = 0; mask != 0; i++, mask >>= 1) {
225 if (mask & pinmask) {
226 pin->pin_num = i;
227 pin->pin_caps = pincaps;
228 pin->pin_flags = pincaps;
229 pin->pin_state = (data & mask) != 0;
230 pin++;
231 }
232 }
233
234 struct gpiobus_attach_args gba = {
235 .gba_gc = &gc->gc_tag,
236 .gba_pins = gc->gc_pins,
237 .gba_npins = pin - gc->gc_pins,
238 };
239
240 config_found(self, &gba, gpiobus_print,
241 CFARGS(.iattr = "gpiobus"));
242 }
243
244 #ifdef MPC8536
245 static void
pq3gpio_mpc8536_attach(device_t self,bus_space_tag_t bst,bus_space_handle_t bsh,u_int svr)246 pq3gpio_mpc8536_attach(device_t self, bus_space_tag_t bst,
247 bus_space_handle_t bsh, u_int svr)
248 {
249 static const uint8_t gpio2pmuxcr_map[] = {
250 [0] = ilog2(PMUXCR_PCI_REQGNT3),
251 [1] = ilog2(PMUXCR_PCI_REQGNT4),
252 [2] = ilog2(PMUXCR_PCI_REQGNT3),
253 [3] = ilog2(PMUXCR_PCI_REQGNT4),
254 [4] = ilog2(PMUXCR_SDHC_CD),
255 [5] = ilog2(PMUXCR_SDHC_WP),
256 [6] = ilog2(PMUXCR_USB1),
257 [7] = ilog2(PMUXCR_USB1),
258 [8] = ilog2(PMUXCR_USB2),
259 [9] = ilog2(PMUXCR_USB2),
260 [10] = ilog2(PMUXCR_DMA0),
261 [11] = ilog2(PMUXCR_DMA1),
262 [12] = ilog2(PMUXCR_DMA0),
263 [13] = ilog2(PMUXCR_DMA1),
264 [14] = ilog2(PMUXCR_DMA0),
265 [15] = ilog2(PMUXCR_DMA1),
266 };
267
268 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */
269 uint32_t gpiomask = __BIT(31);
270 size_t pincnt = 16;
271 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR);
272 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map);
273 i++, gpiomask >>= 1) {
274 if (pmuxcr & __BIT(gpio2pmuxcr_map[i])) {
275 pinmask &= ~gpiomask;
276 pincnt--;
277 }
278 }
279
280 /*
281 * Create GPIO pin groups
282 */
283 aprint_normal_dev(self, "%zu input/output/opendrain pins\n",
284 pincnt);
285 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask,
286 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN,
287 pq3gpio_pin_ctl);
288 }
289 #endif /* MPC8536 */
290
291 #ifdef MPC8544
292 static void
pq3gpio_mpc8544_attach(device_t self,bus_space_tag_t bst,bus_space_handle_t bsh,u_int svr)293 pq3gpio_mpc8544_attach(device_t self, bus_space_tag_t bst,
294 bus_space_handle_t bsh, u_int svr)
295 {
296 /*
297 * Enable GPOUT
298 */
299 uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR);
300 gpiocr |= GPIOCR_GPOUT;
301 bus_space_write_4(bst, bsh, GPIOCR, gpiocr);
302
303 aprint_normal_dev(self, "8 input pins, 8 output pins\n");
304
305 /*
306 * Create GPIO pin groups
307 */
308 pq3gpio_group_create(self, bst, bsh, GPINDR, 0xff000000,
309 GPIO_PIN_INPUT, pq3gpio_null_pin_ctl);
310 pq3gpio_group_create(self, bst, bsh, GPOUTDR, 0xff000000,
311 GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl);
312 }
313 #endif /* MPC8544 */
314
315 #if defined(MPC8548) || defined(MPC8555)
316 static void
pq3gpio_mpc8548_attach(device_t self,bus_space_tag_t bst,bus_space_handle_t bsh,u_int svr)317 pq3gpio_mpc8548_attach(device_t self, bus_space_tag_t bst,
318 bus_space_handle_t bsh, u_int svr)
319 {
320 const uint32_t pordevsr = bus_space_read_4(bst, bsh, PORDEVSR);
321 const uint32_t devdisr = bus_space_read_4(bst, bsh, DEVDISR);
322 uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR);
323
324 uint32_t inmask = 0;
325 uint32_t outmask = 0;
326
327 size_t ipins = 0;
328 size_t opins = 0;
329
330 aprint_normal_dev(self, "GPIOCR %#x, DEVDISR %#x, PORDEVSR %#x\n",
331 gpiocr, devdisr, pordevsr);
332 aprint_normal_dev(self, "GPINDR %#x, GPOUTDR %#x, GPPORCR %#x\n",
333 bus_space_read_4(bst, bsh, GPINDR),
334 bus_space_read_4(bst, bsh, GPOUTDR),
335 bus_space_read_4(bst, bsh, GPPORCR));
336
337 /*
338 * Use PCI2 AD[15:0] as GPIO if PCI2 is disabled and
339 * PCI1 is either disabled or not 64bits wide.
340 */
341 if ((devdisr & DEVDISR_PCI2) &&
342 ((devdisr & DEVDISR_PCI1) || (pordevsr & PORDEVSR_PCI32))) {
343 gpiocr |= GPIOCR_PCIOUT;
344 gpiocr |= GPIOCR_PCIIN;
345 outmask |= 0x00ff0000;
346 inmask |= 0x00ff0000;
347 opins += 8;
348 ipins += 8;
349 }
350 if (devdisr & DEVDISR_TSEC2) {
351 gpiocr |= GPIOCR_TX2;
352 gpiocr |= GPIOCR_RX2;
353 outmask |= 0xff000000;
354 inmask |= 0xff000000;
355 opins += 8;
356 ipins += 8;
357 }
358 if (svr != (SVR_MPC8555v1 >> 16)) {
359 gpiocr |= GPIOCR_GPOUT;
360 outmask |= 0x000000ff;
361 opins += 8;
362 }
363 #if 1
364 aprint_normal_dev(self, "GPIOCR: %#x\n", gpiocr);
365 #else
366 bus_space_write_4(bst, bsh, GPIOCR, gpiocr);
367 #endif
368
369 /*
370 * Create GPIO pin groups
371 */
372 aprint_normal_dev(self, "%zu input pins, %zu output pins\n",
373 ipins, opins);
374
375 if (inmask)
376 pq3gpio_group_create(self, bst, bsh, GPINDR, inmask,
377 GPIO_PIN_INPUT, pq3gpio_null_pin_ctl);
378 if (outmask)
379 pq3gpio_group_create(self, bst, bsh, GPOUTDR, outmask,
380 GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl);
381 }
382 #endif /* MPC8548 */
383
384 #ifdef P1025
385 static void
pq3gpio_p1025_attach(device_t self,bus_space_tag_t bst,bus_space_handle_t bsh,u_int svr)386 pq3gpio_p1025_attach(device_t self, bus_space_tag_t bst,
387 bus_space_handle_t bsh, u_int svr)
388 {
389 static const uint32_t gpio2pmuxcr_map[][4] = {
390 { 0, __BIT(12), 0, PMUXCR_SDHC_WP },
391 { __BIT(15), __BIT(8), 0, PMUXCR_USB1 },
392 { __BITS(14,4)|__BIT(16)|__BITS(27,17)|__BIT(30),
393 __BIT(1)|__BITS(3,2), 0, PMUXCR_QE0 },
394 { __BITS(3,1), 0, 0, PMUXCR_QE3 },
395 { 0, __BITS(17,14), 0, PMUXCR_QE8 },
396 { __BIT(29), __BITS(19,18), 0, PMUXCR_QE9 },
397 { 0, __BITS(22,21), 0, PMUXCR_QE10 },
398 { 0, __BITS(28,23), 0, PMUXCR_QE11 },
399 { 0, __BIT(20), 0, PMUXCR_QE12 },
400 };
401
402 uint32_t pinmask[3] = {
403 0xffffffff, 0xffffffff, 0xffffffff
404 }; /* assume all bits are valid */
405 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR);
406 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) {
407 if (pmuxcr & gpio2pmuxcr_map[i][3]) {
408 pinmask[0] &= ~gpio2pmuxcr_map[i][0];
409 pinmask[1] &= ~gpio2pmuxcr_map[i][1];
410 pinmask[2] &= ~gpio2pmuxcr_map[i][2];
411 }
412 }
413
414 /*
415 * Create GPIO pin groups
416 */
417 for (size_t i = 0; i < 3; i++) {
418 if (pinmask[i]) {
419 bus_space_handle_t bsh2;
420 aprint_normal_dev(self,
421 "gpio[%c]: %zu input/output/opendrain pins\n",
422 "abc"[i], popcount32(pinmask[i]));
423 bus_space_subregion(bst, bsh, CPBASE(i), 0x20, &bsh2);
424 pq3gpio_group_create(self, bst, bsh2, CPDAT,
425 pinmask[0],
426 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN,
427 pq3gpio_pin_ctl);
428 }
429 }
430 }
431 #endif /* P1025 */
432
433 #ifdef P2020
434 static void
pq3gpio_p20x0_attach(device_t self,bus_space_tag_t bst,bus_space_handle_t bsh,u_int svr)435 pq3gpio_p20x0_attach(device_t self, bus_space_tag_t bst,
436 bus_space_handle_t bsh, u_int svr)
437 {
438 static const uint32_t gpio2pmuxcr_map[][2] = {
439 { __BIT(8), PMUXCR_SDHC_CD },
440 { __BIT(9), PMUXCR_SDHC_WP },
441 /*
442 * These are really two bits but the low bit MBZ so we ignore
443 * it.
444 */
445 { __BIT(10), PMUXCR_TSEC3_TS },
446 { __BIT(11), PMUXCR_TSEC3_TS },
447 };
448
449 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */
450 size_t pincnt = 16;
451 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR);
452 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) {
453 if (pmuxcr & gpio2pmuxcr_map[i][1]) {
454 pinmask &= ~gpio2pmuxcr_map[i][0];
455 pincnt--;
456 }
457 }
458
459 /*
460 * Create GPIO pin groups
461 */
462 aprint_normal_dev(self, "%zu input/output/opendrain pins\n",
463 pincnt);
464 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask,
465 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN,
466 pq3gpio_pin_ctl);
467 }
468 #endif /* P2020 */
469
470 #ifdef P1023
471 static void
pq3gpio_p1023_attach(device_t self,bus_space_tag_t bst,bus_space_handle_t bsh,u_int svr)472 pq3gpio_p1023_attach(device_t self, bus_space_tag_t bst,
473 bus_space_handle_t bsh, u_int svr)
474 {
475 static const uint32_t gpio2pmuxcr2_map[][3] = {
476 { __PPCBITS( 0, 1), __PPCBITS( 0, 1), 0 }, /* GPIO_1 */
477 { __PPCBIT(2), __PPCBITS( 2, 3), 0 }, /* GPUO_2 */
478 { __PPCBITS( 4, 5), __PPCBITS( 4, 5), 0 }, /* GPUO_3 */
479 { __PPCBITS( 6, 7), __PPCBITS( 6, 7), 0 }, /* GPUO_4 */
480 { __PPCBITS( 8, 9), __PPCBITS( 8, 9), 0 }, /* GPUO_5 */
481 { __PPCBITS(10,11), __PPCBITS(10,11), 0 }, /* GPUO_6 */
482 { __PPCBITS(12,13), __PPCBITS(12,13), 0 }, /* GPUO_7 */
483 { __PPCBITS(14,15), __PPCBITS(14,15), 0 }, /* GPUO_8 */
484 { __PPCBIT(3), __PPCBITS(18,19), 0 }, /* GPUO_9 */
485 };
486
487 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */
488 size_t pincnt = 16;
489 const uint32_t pmuxcr2 = cpu_read_4(GLOBAL_BASE + PMUXCR2);
490 for (size_t i = 0; i < __arraycount(gpio2pmuxcr2_map); i++) {
491 const uint32_t *map = gpio2pmuxcr2_map[i];
492 if ((pmuxcr2 & map[1]) != map[2]) {
493 pinmask &= ~map[0];
494 pincnt--;
495 }
496 }
497
498 /*
499 * Create GPIO pin groups
500 */
501 aprint_normal_dev(self, "%zu input/output/opendrain pins\n", pincnt);
502 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask,
503 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, pq3gpio_pin_ctl);
504 }
505 #endif /* P1023 */
506
507 static const struct pq3gpio_svr_info {
508 uint16_t si_svr;
509 void (*si_attach)(device_t, bus_space_tag_t, bus_space_handle_t, u_int);
510 bus_addr_t si_base;
511 bus_size_t si_size;
512 } pq3gpio_svrs[] = {
513 #ifdef MPC8548
514 { SVR_MPC8548v2 >> 16, pq3gpio_mpc8548_attach,
515 GLOBAL_BASE, GLOBAL_SIZE },
516 #endif
517 #ifdef MPC8555
518 { SVR_MPC8555v1 >> 16, pq3gpio_mpc8548_attach,
519 GLOBAL_BASE, GLOBAL_SIZE },
520 #endif
521 #ifdef MPC8544
522 { SVR_MPC8544v1 >> 16, pq3gpio_mpc8544_attach,
523 GLOBAL_BASE, GLOBAL_SIZE },
524 #endif
525 #ifdef MPC8536
526 { SVR_MPC8536v1 >> 16, pq3gpio_mpc8536_attach,
527 GPIO_BASE, GPIO_SIZE },
528 #endif
529 #ifdef P1025
530 { SVR_P1025v1 >> 16, pq3gpio_p1025_attach,
531 GLOBAL_BASE, GLOBAL_SIZE },
532 #endif
533 #ifdef P2020
534 { SVR_P2020v2 >> 16, pq3gpio_p20x0_attach,
535 GPIO_BASE, GPIO_SIZE },
536 #endif
537 #ifdef P1023
538 { SVR_P1023v1 >> 16, pq3gpio_p1023_attach,
539 GPIO_BASE, GPIO_SIZE },
540 #endif
541 };
542
543 void
pq3gpio_attach(device_t parent,device_t self,void * aux)544 pq3gpio_attach(device_t parent, device_t self, void *aux)
545 {
546 struct mainbus_attach_args * const ma = aux;
547 bus_space_tag_t bst = ma->ma_memt;
548 bus_space_handle_t bsh;
549
550 const uint16_t svr = e500_get_svr();
551 for (u_int i = 0; i < __arraycount(pq3gpio_svrs); i++) {
552 const struct pq3gpio_svr_info * const si = &pq3gpio_svrs[i];
553 if (si->si_svr == svr) {
554 int error = bus_space_map(bst, si->si_base,
555 si->si_size, 0, &bsh);
556 if (error) {
557 aprint_error_dev(self,
558 "can't map global registers for gpio: %d\n",
559 error);
560 return;
561 }
562 (*si->si_attach)(self, bst, bsh, svr);
563 return;
564 }
565 }
566 aprint_normal_dev(self,
567 "0 input groups, 0 output groups (unknown svr %#x)\n",
568 svr);
569 }
570