1 /*
2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: stable/10/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c 251655 2013-06-12 14:52:57Z adrian $
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23 #include "ah_devid.h"
24
25 #include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
26
27 #include "ar9002/ar9280.h"
28 #include "ar9002/ar9285.h"
29 #include "ar5416/ar5416reg.h"
30 #include "ar5416/ar5416phy.h"
31
32 #include "ar9002/ar9285.ini"
33 #include "ar9002/ar9285v2.ini"
34 #include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */
35
36 #include "ar9002/ar9285_cal.h"
37 #include "ar9002/ar9285_phy.h"
38 #include "ar9002/ar9285_diversity.h"
39
40 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
41 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
42 .calNumSamples = MIN_CAL_SAMPLES,
43 .calCountMax = PER_MAX_LOG_COUNT,
44 .calCollect = ar5416IQCalCollect,
45 .calPostProc = ar5416IQCalibration
46 };
47 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
48 .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
49 .calNumSamples = MIN_CAL_SAMPLES,
50 .calCountMax = PER_MIN_LOG_COUNT,
51 .calCollect = ar5416AdcGainCalCollect,
52 .calPostProc = ar5416AdcGainCalibration
53 };
54 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
55 .calName = "ADC DC", .calType = ADC_DC_CAL,
56 .calNumSamples = MIN_CAL_SAMPLES,
57 .calCountMax = PER_MIN_LOG_COUNT,
58 .calCollect = ar5416AdcDcCalCollect,
59 .calPostProc = ar5416AdcDcCalibration
60 };
61 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
62 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
63 .calNumSamples = MIN_CAL_SAMPLES,
64 .calCountMax = INIT_LOG_COUNT,
65 .calCollect = ar5416AdcDcCalCollect,
66 .calPostProc = ar5416AdcDcCalibration
67 };
68
69 static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
70 HAL_BOOL power_off);
71 static void ar9285DisablePCIE(struct ath_hal *ah);
72 static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
73 static void ar9285WriteIni(struct ath_hal *ah,
74 const struct ieee80211_channel *chan);
75
76 static void
ar9285AniSetup(struct ath_hal * ah)77 ar9285AniSetup(struct ath_hal *ah)
78 {
79 /*
80 * These are the parameters from the AR5416 ANI code;
81 * they likely need quite a bit of adjustment for the
82 * AR9285.
83 */
84 static const struct ar5212AniParams aniparams = {
85 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
86 .totalSizeDesired = { -55, -55, -55, -55, -62 },
87 .coarseHigh = { -14, -14, -14, -14, -12 },
88 .coarseLow = { -64, -64, -64, -64, -70 },
89 .firpwr = { -78, -78, -78, -78, -80 },
90 .maxSpurImmunityLevel = 7,
91 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
92 .maxFirstepLevel = 2, /* levels 0..2 */
93 .firstep = { 0, 4, 8 },
94 .ofdmTrigHigh = 500,
95 .ofdmTrigLow = 200,
96 .cckTrigHigh = 200,
97 .cckTrigLow = 100,
98 .rssiThrHigh = 40,
99 .rssiThrLow = 7,
100 .period = 100,
101 };
102 /* NB: disable ANI noise immmunity for reliable RIFS rx */
103 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
104
105 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
106 }
107
108 static const char * ar9285_lna_conf[] = {
109 "LNA1-LNA2",
110 "LNA2",
111 "LNA1",
112 "LNA1+LNA2",
113 };
114
115 static void
ar9285_eeprom_print_diversity_settings(struct ath_hal * ah)116 ar9285_eeprom_print_diversity_settings(struct ath_hal *ah)
117 {
118 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
119 const MODAL_EEP4K_HEADER *pModal = &ee->ee_base.modalHeader;
120
121 ath_hal_printf(ah, "[ath] AR9285 Main LNA config: %s\n",
122 ar9285_lna_conf[(pModal->antdiv_ctl2 >> 2) & 0x3]);
123 ath_hal_printf(ah, "[ath] AR9285 Alt LNA config: %s\n",
124 ar9285_lna_conf[pModal->antdiv_ctl2 & 0x3]);
125 ath_hal_printf(ah, "[ath] LNA diversity %s, Diversity %s\n",
126 ((pModal->antdiv_ctl1 & 0x1) ? "enabled" : "disabled"),
127 ((pModal->antdiv_ctl1 & 0x8) ? "enabled" : "disabled"));
128 }
129
130 /*
131 * Attach for an AR9285 part.
132 */
133 static struct ath_hal *
ar9285Attach(uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,uint16_t * eepromdata,HAL_STATUS * status)134 ar9285Attach(uint16_t devid, HAL_SOFTC sc,
135 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
136 HAL_STATUS *status)
137 {
138 struct ath_hal_9285 *ahp9285;
139 struct ath_hal_5212 *ahp;
140 struct ath_hal *ah;
141 uint32_t val;
142 HAL_STATUS ecode;
143 HAL_BOOL rfStatus;
144
145 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
146 __func__, sc, (void*) st, (void*) sh);
147
148 /* NB: memory is returned zero'd */
149 ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
150 if (ahp9285 == AH_NULL) {
151 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
152 "%s: cannot allocate memory for state block\n", __func__);
153 *status = HAL_ENOMEM;
154 return AH_NULL;
155 }
156 ahp = AH5212(ahp9285);
157 ah = &ahp->ah_priv.h;
158
159 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
160
161 /*
162 * Use the "local" EEPROM data given to us by the higher layers.
163 * This is a private copy out of system flash. The Linux ath9k
164 * commit for the initial AR9130 support mentions MMIO flash
165 * access is "unreliable." -adrian
166 */
167 if (eepromdata != AH_NULL) {
168 AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
169 AH_PRIVATE(ah)->ah_eepromWrite = NULL;
170 ah->ah_eepromdata = eepromdata;
171 }
172
173 /* override with 9285 specific state */
174 AH5416(ah)->ah_initPLL = ar9280InitPLL;
175 AH5416(ah)->ah_btCoexSetDiversity = ar9285BTCoexAntennaDiversity;
176
177 ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
178 ah->ah_configPCIE = ar9285ConfigPCIE;
179 ah->ah_disablePCIE = ar9285DisablePCIE;
180 ah->ah_setTxPower = ar9285SetTransmitPower;
181 ah->ah_setBoardValues = ar9285SetBoardValues;
182 ah->ah_btCoexSetParameter = ar9285BTCoexSetParameter;
183 ah->ah_divLnaConfGet = ar9285_antdiv_comb_conf_get;
184 ah->ah_divLnaConfSet = ar9285_antdiv_comb_conf_set;
185
186 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
187 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
188 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
189 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
190 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
191
192 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
193 AH5416(ah)->ah_writeIni = ar9285WriteIni;
194 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
195 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
196
197 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
198
199 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
200 /* reset chip */
201 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
202 __func__);
203 ecode = HAL_EIO;
204 goto bad;
205 }
206
207 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
208 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
209 __func__);
210 ecode = HAL_EIO;
211 goto bad;
212 }
213 /* Read Revisions from Chips before taking out of reset */
214 val = OS_REG_READ(ah, AR_SREV);
215 HALDEBUG(ah, HAL_DEBUG_ATTACH,
216 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
217 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
218 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
219 /* NB: include chip type to differentiate from pre-Sowl versions */
220 AH_PRIVATE(ah)->ah_macVersion =
221 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
222 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
223 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
224
225 /* setup common ini data; rf backends handle remainder */
226 if (AR_SREV_KITE_12_OR_LATER(ah)) {
227 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
228 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
229 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
230 ar9285PciePhy_clkreq_always_on_L1_v2, 2);
231 } else {
232 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
233 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
234 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
235 ar9285PciePhy_clkreq_always_on_L1, 2);
236 }
237 ar5416AttachPCIE(ah);
238
239 /* Attach methods that require MAC version/revision info */
240 if (AR_SREV_KITE_12_OR_LATER(ah))
241 AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
242 if (AR_SREV_KITE_11_OR_LATER(ah))
243 AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
244
245 ecode = ath_hal_v4kEepromAttach(ah);
246 if (ecode != HAL_OK)
247 goto bad;
248
249 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
250 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
251 __func__);
252 ecode = HAL_EIO;
253 goto bad;
254 }
255
256 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
257
258 if (!ar5212ChipTest(ah)) {
259 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
260 __func__);
261 ecode = HAL_ESELFTEST;
262 goto bad;
263 }
264
265 /*
266 * Set correct Baseband to analog shift
267 * setting to access analog chips.
268 */
269 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
270
271 /* Read Radio Chip Rev Extract */
272 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
273 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
274 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
275 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
276 break;
277 default:
278 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
279 AH_PRIVATE(ah)->ah_analog5GhzRev =
280 AR_RAD5133_SREV_MAJOR;
281 break;
282 }
283 #ifdef AH_DEBUG
284 HALDEBUG(ah, HAL_DEBUG_ANY,
285 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
286 "this driver\n", __func__,
287 AH_PRIVATE(ah)->ah_analog5GhzRev);
288 ecode = HAL_ENOTSUPP;
289 goto bad;
290 #endif
291 }
292 rfStatus = ar9285RfAttach(ah, &ecode);
293 if (!rfStatus) {
294 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
295 __func__, ecode);
296 goto bad;
297 }
298
299 HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
300 6);
301
302 if (AR_SREV_9285E_20(ah))
303 ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
304
305 /* setup txgain table */
306 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
307 case AR5416_EEP_TXGAIN_HIGH_POWER:
308 if (AR_SREV_9285E_20(ah))
309 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
310 ar9285Modes_XE2_0_high_power, 6);
311 else
312 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
313 ar9285Modes_high_power_tx_gain_v2, 6);
314 break;
315 case AR5416_EEP_TXGAIN_ORIG:
316 if (AR_SREV_9285E_20(ah))
317 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
318 ar9285Modes_XE2_0_normal_power, 6);
319 else
320 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
321 ar9285Modes_original_tx_gain_v2, 6);
322 break;
323 default:
324 HALASSERT(AH_FALSE);
325 goto bad; /* XXX ? try to continue */
326 }
327
328 /*
329 * Got everything we need now to setup the capabilities.
330 */
331 if (!ar9285FillCapabilityInfo(ah)) {
332 ecode = HAL_EEREAD;
333 goto bad;
334 }
335
336 /*
337 * Print out the EEPROM antenna configuration mapping.
338 * Some devices have a hard-coded LNA configuration profile;
339 * others enable diversity.
340 */
341 ar9285_eeprom_print_diversity_settings(ah);
342
343 /* Print out whether the EEPROM settings enable AR9285 diversity */
344 if (ar9285_check_div_comb(ah)) {
345 ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
346 }
347
348 /* Disable 11n for the AR2427 */
349 if (devid == AR2427_DEVID_PCIE)
350 AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
351
352 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
353 if (ecode != HAL_OK) {
354 HALDEBUG(ah, HAL_DEBUG_ANY,
355 "%s: error getting mac address from EEPROM\n", __func__);
356 goto bad;
357 }
358 /* XXX How about the serial number ? */
359 /* Read Reg Domain */
360 AH_PRIVATE(ah)->ah_currentRD =
361 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
362 /*
363 * For Kite and later chipsets, the following bits are not
364 * programmed in EEPROM and so are set as enabled always.
365 */
366 AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
367
368 /*
369 * ah_miscMode is populated by ar5416FillCapabilityInfo()
370 * starting from griffin. Set here to make sure that
371 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
372 * placed into hardware.
373 */
374 if (ahp->ah_miscMode != 0)
375 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
376
377 ar9285AniSetup(ah); /* Anti Noise Immunity */
378
379 /* Setup noise floor min/max/nominal values */
380 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
381 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
382 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
383 /* XXX no 5ghz values? */
384
385 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
386
387 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
388
389 return ah;
390 bad:
391 if (ah != AH_NULL)
392 ah->ah_detach(ah);
393 if (status)
394 *status = ecode;
395 return AH_NULL;
396 }
397
398 static void
ar9285ConfigPCIE(struct ath_hal * ah,HAL_BOOL restore,HAL_BOOL power_off)399 ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
400 {
401 uint32_t val;
402
403 /*
404 * This workaround needs some integration work with the HAL
405 * config parameters and the if_ath_pci.c glue.
406 * Specifically, read the value of the PCI register 0x70c
407 * (4 byte PCI config space register) and store it in ath_hal_war70c.
408 * Then if it's non-zero, the below WAR would override register
409 * 0x570c upon suspend/resume.
410 */
411 #if 0
412 if (AR_SREV_9285E_20(ah)) {
413 val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
414 if (val) {
415 val &= 0xffff00ff;
416 val |= 0x6f00;
417 OS_REG_WRITE(ah, 0x570c, val);
418 }
419 }
420 #endif
421
422 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
423 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
424 OS_DELAY(1000);
425 }
426
427 /*
428 * Set PCIe workaround bits
429 *
430 * NOTE:
431 *
432 * In Merlin and Kite, bit 14 in WA register (disable L1) should only
433 * be set when device enters D3 and be cleared when device comes back
434 * to D0.
435 */
436 if (power_off) { /* Power-off */
437 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
438
439 val = OS_REG_READ(ah, AR_WA);
440
441 /*
442 * Disable bit 6 and 7 before entering D3 to prevent
443 * system hang.
444 */
445 val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
446
447 /*
448 * See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
449 *
450 * XXX The reference HAL does it this way - it only sets
451 * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
452 * which it (currently) isn't. So the following statement
453 * is currently a NOP.
454 */
455 if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
456 val |= AR_WA_D3_L1_DISABLE;
457
458 if (AR_SREV_9285E_20(ah))
459 val |= AR_WA_BIT23;
460
461 OS_REG_WRITE(ah, AR_WA, val);
462 } else { /* Power-on */
463 val = AR9285_WA_DEFAULT;
464 /*
465 * See note above: make sure L1_DISABLE is not set.
466 */
467 val &= (~AR_WA_D3_L1_DISABLE);
468
469 /* Software workaroud for ASPM system hang. */
470 val |= (AR_WA_BIT6 | AR_WA_BIT7);
471
472 if (AR_SREV_9285E_20(ah))
473 val |= AR_WA_BIT23;
474
475 OS_REG_WRITE(ah, AR_WA, val);
476
477 /* set bit 19 to allow forcing of pcie core into L1 state */
478 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
479 }
480 }
481
482 static void
ar9285DisablePCIE(struct ath_hal * ah)483 ar9285DisablePCIE(struct ath_hal *ah)
484 {
485 }
486
487 static void
ar9285WriteIni(struct ath_hal * ah,const struct ieee80211_channel * chan)488 ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
489 {
490 u_int modesIndex, freqIndex;
491 int regWrites = 0;
492
493 /* Setup the indices for the next set of register array writes */
494 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
495 freqIndex = 2;
496 if (IEEE80211_IS_CHAN_HT40(chan))
497 modesIndex = 3;
498 else if (IEEE80211_IS_CHAN_108G(chan))
499 modesIndex = 5;
500 else
501 modesIndex = 4;
502
503 /* Set correct Baseband to analog shift setting to access analog chips. */
504 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
505 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
506 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
507 modesIndex, regWrites);
508 if (AR_SREV_KITE_12_OR_LATER(ah)) {
509 regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
510 modesIndex, regWrites);
511 }
512 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
513 1, regWrites);
514 }
515
516 /*
517 * Fill all software cached or static hardware state information.
518 * Return failure if capabilities are to come from EEPROM and
519 * cannot be read.
520 */
521 static HAL_BOOL
ar9285FillCapabilityInfo(struct ath_hal * ah)522 ar9285FillCapabilityInfo(struct ath_hal *ah)
523 {
524 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
525
526 if (!ar5416FillCapabilityInfo(ah))
527 return AH_FALSE;
528 pCap->halNumGpioPins = 12;
529 pCap->halWowSupport = AH_TRUE;
530 pCap->halWowMatchPatternExact = AH_TRUE;
531 #if 0
532 pCap->halWowMatchPatternDword = AH_TRUE;
533 #endif
534 /* AR9285 has 2 antennas but is a 1x1 stream device */
535 pCap->halTxStreams = 1;
536 pCap->halRxStreams = 1;
537
538 if (ar9285_check_div_comb(ah))
539 pCap->halAntDivCombSupport = AH_TRUE;
540
541 pCap->halCSTSupport = AH_TRUE;
542 pCap->halRifsRxSupport = AH_TRUE;
543 pCap->halRifsTxSupport = AH_TRUE;
544 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
545 pCap->halExtChanDfsSupport = AH_TRUE;
546 pCap->halUseCombinedRadarRssi = AH_TRUE;
547 #if 1
548 /* XXX bluetooth */
549 pCap->halBtCoexSupport = AH_TRUE;
550 #endif
551 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
552 pCap->hal4kbSplitTransSupport = AH_FALSE;
553 /* Disable this so Block-ACK works correctly */
554 pCap->halHasRxSelfLinkedTail = AH_FALSE;
555 pCap->halMbssidAggrSupport = AH_TRUE;
556 pCap->hal4AddrAggrSupport = AH_TRUE;
557 pCap->halSpectralScanSupport = AH_TRUE;
558 pCap->halRxUsingLnaMixing = AH_TRUE;
559
560 if (AR_SREV_KITE_12_OR_LATER(ah))
561 pCap->halPSPollBroken = AH_FALSE;
562
563 /* Only RX STBC supported */
564 pCap->halRxStbcSupport = 1;
565 pCap->halTxStbcSupport = 0;
566
567 return AH_TRUE;
568 }
569
570 static const char*
ar9285Probe(uint16_t vendorid,uint16_t devid)571 ar9285Probe(uint16_t vendorid, uint16_t devid)
572 {
573 if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
574 return "Atheros 9285";
575 if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE))
576 return "Atheros 2427";
577
578 return AH_NULL;
579 }
580 AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
581