1 /* $NetBSD: ahcisatareg.h,v 1.17 2025/01/07 20:24:10 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 /* SATA AHCI v1.0 register defines */ 29 30 /* misc defines */ 31 #define AHCI_MAX_PORTS 32 32 #define AHCI_MAX_CMDS 32 33 34 /* in-memory structures used by the controller */ 35 /* physical region descriptor: points to a region of data (max 4MB) */ 36 struct ahci_dma_prd { 37 uint64_t prd_dba; /* data base address */ 38 uint32_t prd_res; /* reserved */ 39 uint32_t prd_dbc; /* data byte count */ 40 #define AHCI_PRD_DBC_MASK 0x003fffff 41 #define AHCI_PRD_DBC_IPC 0x80000000 /* interrupt on completion */ 42 } __packed __aligned(8); 43 44 #define AHCI_NPRD ((MAXPHYS/PAGE_SIZE) + 1) 45 46 /* command table: describe a command to send to drive */ 47 struct ahci_cmd_tbl { 48 uint8_t cmdt_cfis[64]; /* command FIS */ 49 uint8_t cmdt_acmd[16]; /* ATAPI command */ 50 uint8_t cmdt_res[48]; /* reserved */ 51 struct ahci_dma_prd cmdt_prd[1]; /* extended to AHCI_NPRD */ 52 } __packed __aligned(8); 53 54 #define AHCI_CMDTBL_ALIGN 0x7f 55 56 #define AHCI_CMDTBL_SIZE ((sizeof(struct ahci_cmd_tbl) + \ 57 (sizeof(struct ahci_dma_prd) * (AHCI_NPRD - 1)) + (AHCI_CMDTBL_ALIGN)) \ 58 & ~AHCI_CMDTBL_ALIGN) 59 60 /* 61 * command header: points to a command table. The command list is an array 62 * of theses. 63 */ 64 struct ahci_cmd_header { 65 uint16_t cmdh_flags; 66 #define AHCI_CMDH_F_PMP_MASK 0xf000 /* port multiplier port */ 67 #define AHCI_CMDH_F_PMP_SHIFT 12 68 #define AHCI_CMDH_F_CBSY 0x0400 /* clear BSY on R_OK */ 69 #define AHCI_CMDH_F_BIST 0x0200 /* BIST FIS */ 70 #define AHCI_CMDH_F_RST 0x0100 /* Reset FIS */ 71 #define AHCI_CMDH_F_PRF 0x0080 /* prefetchable */ 72 #define AHCI_CMDH_F_WR 0x0040 /* write */ 73 #define AHCI_CMDH_F_A 0x0020 /* ATAPI */ 74 #define AHCI_CMDH_F_CFL_MASK 0x001f /* command FIS length (in dw) */ 75 #define AHCI_CMDH_F_CFL_SHIFT 0 76 uint16_t cmdh_prdtl; /* number of cmdt_prd */ 77 uint32_t cmdh_prdbc; /* physical region descriptor byte count */ 78 uint64_t cmdh_cmdtba; /* phys. addr. of cmd_tbl, 128bytes aligned */ 79 uint32_t cmdh_res[4]; /* reserved */ 80 } __packed __aligned(8); 81 82 #define AHCI_CMDH_SIZE (sizeof(struct ahci_cmd_header) * AHCI_MAX_CMDS) 83 84 /* received FIS: where the HBA stores various type of FIS it receives */ 85 struct ahci_r_fis { 86 uint8_t rfis_dsfis[32]; /* DMA setup FIS */ 87 uint8_t rfis_psfis[32]; /* PIO setup FIS */ 88 uint8_t rfis_rfis[24]; /* D2H register FIS */ 89 uint8_t rfis_sdbfis[8]; /* set device bit FIS */ 90 uint8_t rfis_ukfis[64]; /* unknown FIS */ 91 uint8_t rfis_res[96]; /* reserved */ 92 } __packed __aligned(8); 93 94 #define AHCI_RFIS_SIZE (sizeof(struct ahci_r_fis)) 95 96 /* PCI registers */ 97 /* class Mass storage, subclass SATA, interface AHCI */ 98 #define PCI_INTERFACE_SATA_AHCI 0x01 99 100 #define AHCI_PCI_ABAR 0x24 /* native AHCI registers (memory mapped) */ 101 102 /* ABAR registers */ 103 /* Global registers */ 104 #define AHCI_CAP 0x00 /* HBA capabilities */ 105 #define AHCI_CAP_NPMASK 0x0000001f /* Number of ports */ 106 #define AHCI_CAP_XS 0x00000020 /* External SATA */ 107 #define AHCI_CAP_EM 0x00000040 /* Enclosure Management */ 108 #define AHCI_CAP_CCC 0x00000080 /* command completion coalescing */ 109 #define AHCI_CAP_NCS 0x00001f00 /* number of command slots */ 110 #define AHCI_CAP_PS 0x00002000 /* Partial State */ 111 #define AHCI_CAP_SS 0x00004000 /* Slumber State */ 112 #define AHCI_CAP_PMD 0x00008000 /* PIO multiple DRQ blocks */ 113 #define AHCI_CAP_FBS 0x00010000 /* FIS-Based switching */ 114 #define AHCI_CAP_SPM 0x00020000 /* Port multipliers */ 115 #define AHCI_CAP_SAM 0x00040000 /* AHCI-only */ 116 #define AHCI_CAP_NZO 0x00080000 /* Non-zero DMA offset (reserved) */ 117 #define AHCI_CAP_IS 0x00f00000 /* Interface speed */ 118 #define AHCI_CAP_IS_GEN1 0x00100000 /* 1.5 Gb/s */ 119 #define AHCI_CAP_IS_GEN2 0x00200000 /* 3.0 Gb/s */ 120 #define AHCI_CAP_IS_GEN3 0x00300000 /* 6.0 Gb/s */ 121 #define AHCI_CAP_CLO 0x01000000 /* Command list override */ 122 #define AHCI_CAP_AL 0x02000000 /* Single Activity LED */ 123 #define AHCI_CAP_ALP 0x04000000 /* Aggressive link power management */ 124 #define AHCI_CAP_SSU 0x08000000 /* Staggered spin-up */ 125 #define AHCI_CAP_MPS 0x10000000 /* Mechanical switch */ 126 #define AHCI_CAP_NTF 0x20000000 /* Snotification */ 127 #define AHCI_CAP_NCQ 0x40000000 /* Native command queuing */ 128 #define AHCI_CAP_64BIT 0x80000000 /* 64bit addresses */ 129 130 #define AHCI_GHC 0x04 /* HBA control */ 131 #define AHCI_GHC_HR 0x00000001 /* HBA reset */ 132 #define AHCI_GHC_IE 0x00000002 /* Interrupt enable */ 133 #define AHCI_GHC_MRSM 0x00000004 /* MSI revert to single message */ 134 #define AHCI_GHC_AE 0x80000000 /* AHCI enable */ 135 136 #define AHCI_IS 0x08 /* Interrupt status register: one bit per port */ 137 138 #define AHCI_PI 0x0c /* Port implemented: one bit per port */ 139 140 #define AHCI_VS 0x10 /* AHCI version */ 141 #define AHCI_VS_095 0x00000905 /* AHCI spec 0.95 */ 142 #define AHCI_VS_100 0x00010000 /* AHCI spec 1.0 */ 143 #define AHCI_VS_110 0x00010100 /* AHCI spec 1.1 */ 144 #define AHCI_VS_120 0x00010200 /* AHCI spec 1.2 */ 145 #define AHCI_VS_130 0x00010300 /* AHCI spec 1.3 */ 146 #define AHCI_VS_MJR(v) ((unsigned int)__SHIFTOUT(v, __BITS(31, 16))) 147 #define AHCI_VS_MNR(v) ((unsigned int)__SHIFTOUT(v, __BITS(15, 8)) * 10 + (unsigned int)__SHIFTOUT(v, __BITS(7, 0) * 1)) 148 149 #define AHCI_CC_CTL 0x14 /* command completion coalescing control */ 150 #define AHCI_CC_TV_MASK 0xffff0000 /* timeout value */ 151 #define AHCI_CC_TV_SHIFT 16 152 #define AHCI_CC_CC_MASK 0x0000ff00 /* command completion */ 153 #define AHCI_CC_CC_SHIFT 8 154 #define AHCI_CC_INT_MASK 0x000000f8 /* interrupt */ 155 #define AHCI_CC_INT_SHIFT 3 156 #define AHCI_CC_EN 0x000000001 /* enable */ 157 158 #define AHCI_CC_PORTS 0x18 /* command completion coalescing ports (1b/port */ 159 160 #define AHCI_EM_LOC 0x1c /* enclosure management location */ 161 #define AHCI_EML_OFF_MASK 0xffff0000 /* offset in ABAR */ 162 #define AHCI_EML_OFF_SHIFT 16 163 #define AHCI_EML_SZ_MASK 0x0000ffff /* offset in ABAR */ 164 #define AHCI_EML_SZ_SHIFT 0 165 166 #define AHCI_EM_CTL 0x20 /* enclosure management control */ 167 #define AHCI_EMC_PM 0x08000000 /* port multiplier support */ 168 #define AHCI_EMC_ALHD 0x04000000 /* activity LED hardware driven */ 169 #define AHCI_EMC_XMIT 0x02000000 /* transmit messages only */ 170 #define AHCI_EMC_SMB 0x01000000 /* single message buffer */ 171 #define AHCI_EMC_SGPIO 0x00080000 /* enclosure management messages */ 172 #define AHCI_EMC_SES2 0x00040000 /* SeS-2 messages */ 173 #define AHCI_EMC_SAF 0x00020000 /* SAF_TE messages */ 174 #define AHCI_EMC_LED 0x00010000 /* LED messages */ 175 #define AHCI_EMC_RST 0x00000200 /* Reset */ 176 #define AHCI_EMC_TM 0x00000100 /* Transmit message */ 177 #define AHCI_EMC_MR 0x00000001 /* Message received */ 178 179 #define AHCI_CAP2 0x24 /* HBA Capabilities Extended */ 180 #define AHCI_CAP2_APST 0x00000004 181 #define AHCI_CAP2_NVMP 0x00000002 182 #define AHCI_CAP2_BOH 0x00000001 183 184 #define AHCI_BOHC 0x28 /* BIOS/OS Handoff Control and Status */ 185 #define AHCI_BOHC_BB 0x00000010 186 #define AHCI_BOHC_OOC 0x00000008 187 #define AHCI_BOHC_SOOE 0x00000004 188 #define AHCI_BOHC_OOS 0x00000002 189 #define AHCI_BOHC_BOS 0x00000001 190 191 /* Per-port registers */ 192 #define AHCI_P_OFFSET(port) (0x80 * (port)) 193 194 #define AHCI_P_CLB(p) (0x100 + AHCI_P_OFFSET(p)) /* command list addr */ 195 #define AHCI_P_CLBU(p) (0x104 + AHCI_P_OFFSET(p)) /* command list addr */ 196 #define AHCI_P_FB(p) (0x108 + AHCI_P_OFFSET(p)) /* FIS addr */ 197 #define AHCI_P_FBU(p) (0x10c + AHCI_P_OFFSET(p)) /* FIS addr */ 198 #define AHCI_P_IS(p) (0x110 + AHCI_P_OFFSET(p)) /* Interrupt status */ 199 #define AHCI_P_IE(p) (0x114 + AHCI_P_OFFSET(p)) /* Interrupt enable */ 200 #define AHCI_P_IX_CPDS 0x80000000 /* Cold port detect */ 201 #define AHCI_P_IX_TFES 0x40000000 /* Task file error */ 202 #define AHCI_P_IX_HBFS 0x20000000 /* Host bus fatal error */ 203 #define AHCI_P_IX_HBDS 0x10000000 /* Host bus data error */ 204 #define AHCI_P_IX_IFS 0x08000000 /* Interface fatal error */ 205 #define AHCI_P_IX_INFS 0x04000000 /* Interface non-fatal error */ 206 #define AHCI_P_IX_OFS 0x01000000 /* Overflow */ 207 #define AHCI_P_IX_IPMS 0x00800000 /* Incorrect port multiplier */ 208 #define AHCI_P_IX_PRCS 0x00400000 /* Phy Ready change */ 209 #define AHCI_P_IX_DMPS 0x00000080 /* Device Mechanical Presence */ 210 #define AHCI_P_IX_PCS 0x00000040 /* port Connect change */ 211 #define AHCI_P_IX_DPS 0x00000020 /* descriptor processed */ 212 #define AHCI_P_IX_UFS 0x00000010 /* Unknown FIS */ 213 #define AHCI_P_IX_SDBS 0x00000008 /* Set device bit */ 214 #define AHCI_P_IX_DSS 0x00000004 /* DMA setup FIS */ 215 #define AHCI_P_IX_PSS 0x00000002 /* PIO setup FIS */ 216 #define AHCI_P_IX_DHRS 0x00000001 /* Device to Host FIS */ 217 218 #define AHCI_P_CMD(p) (0x118 + AHCI_P_OFFSET(p)) /* Port command/status */ 219 #define AHCI_P_CMD_ICC_MASK 0xf0000000 /* Interface Comm. Control */ 220 #define AHCI_P_CMD_ICC_SL 0x60000000 /* State slumber */ 221 #define AHCI_P_CMD_ICC_PA 0x20000000 /* State partial */ 222 #define AHCI_P_CMD_ICC_AC 0x10000000 /* State active */ 223 #define AHCI_P_CMD_ICC_NO 0x00000000 /* State idle/NOP */ 224 #define AHCI_P_CMD_ASP 0x08000000 /* Aggressive Slumber/Partial */ 225 #define AHCI_P_CMD_ALPE 0x04000000 /* Aggressive link power management */ 226 #define AHCI_P_CMD_DLAE 0x02000000 /* drive LED on ATAPI */ 227 #define AHCI_P_CMD_ATAP 0x01000000 /* Device is ATAPI */ 228 #define AHCI_P_CMD_ESP 0x00200000 /* external SATA port */ 229 #define AHCI_P_CMD_CPD 0x00100000 /* Cold presence detection */ 230 #define AHCI_P_CMD_MPSP 0x00080000 /* Mechanical switch attached */ 231 #define AHCI_P_CMD_HPCP 0x00040000 /* hot-plug capable */ 232 #define AHCI_P_CMD_PMA 0x00020000 /* port multiplier attached */ 233 #define AHCI_P_CMD_CPS 0x00010000 /* cold presence state */ 234 #define AHCI_P_CMD_CR 0x00008000 /* command list running */ 235 #define AHCI_P_CMD_FR 0x00004000 /* FIS receive running */ 236 #define AHCI_P_CMD_MPSS 0x00002000 /* mechanical switch state */ 237 #define AHCI_P_CMD_CCS_MASK __BITS(12, 8) /* current command slot */ 238 #define AHCI_P_CMD_CCS_SHIFT 8 239 #define AHCI_P_CMD_FRE 0x00000010 /* FIS receive enable */ 240 #define AHCI_P_CMD_CLO 0x00000008 /* command list override */ 241 #define AHCI_P_CMD_POD 0x00000004 /* power on device */ 242 #define AHCI_P_CMD_SUD 0x00000002 /* spin up device */ 243 #define AHCI_P_CMD_ST 0x00000001 /* start */ 244 245 #define AHCI_P_TFD(p) (0x120 + AHCI_P_OFFSET(p)) /* Port task file data */ 246 #define AHCI_P_TFD_ERR_MASK 0x0000ff00 /* error register */ 247 #define AHCI_P_TFD_ERR_SHIFT 8 248 #define AHCI_P_TFD_ST 0x000000ff /* status register */ 249 #define AHCI_P_TFD_ST_SHIFT 0 250 #define AHCI_TFD_ERR(tfd) \ 251 (((tfd) & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT) 252 #define AHCI_TFD_ST(tfd) \ 253 (((tfd) & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 254 255 #define AHCI_P_SIG(p) (0x124 + AHCI_P_OFFSET(p)) /* device signature */ 256 #define AHCI_P_SIG_LBAH_MASK 0xff000000 257 #define AHCI_P_SIG_LBAH_SHIFT 24 258 #define AHCI_P_SIG_LBAM_MASK 0x00ff0000 259 #define AHCI_P_SIG_LBAM_SHIFT 16 260 #define AHCI_P_SIG_LBAL_MASK 0x0000ff00 261 #define AHCI_P_SIG_LBAL_SHIFT 8 262 #define AHCI_P_SIG_SC_MASK 0x000000ff 263 #define AHCI_P_SIG_SC_SHIFT 0 264 265 #define AHCI_P_SSTS(p) (0x128 + AHCI_P_OFFSET(p)) /* Serial ATA status */ 266 267 #define AHCI_P_SCTL(p) (0x12c + AHCI_P_OFFSET(p)) /* Serial ATA control */ 268 269 #define AHCI_P_SERR(p) (0x130 + AHCI_P_OFFSET(p)) /* Serial ATA error */ 270 271 #define AHCI_P_SACT(p) (0x134 + AHCI_P_OFFSET(p)) /* Serial ATA active */ 272 /* one bit per tag/command slot */ 273 274 #define AHCI_P_CI(p) (0x138 + AHCI_P_OFFSET(p)) /* Command issued */ 275 /* one bit per tag/command slot */ 276 277 #define AHCI_P_FNTF(p) (0x13c + AHCI_P_OFFSET(p)) /* SNotification */ 278 /* one bit per port */ 279 280 #define AHCI_P_FBS(p) (0x140 + AHCI_P_OFFSET(p)) /* Port task file data */ 281 #define AHCI_P_FBS_EN 0x00000001 /* Enable */ 282 #define AHCI_P_FBS_DEC 0x00000002 /* Device Error Clear */ 283 #define AHCI_P_FBS_SDE 0x00000004 /* Single Device Error */ 284 #define AHCI_P_FBS_DEV 0x00000f00 /* Device To Issue */ 285 #define AHCI_P_FBS_DEV_SHIFT 8 286 #define AHCI_P_FBS_ADO 0x0000f000 /* Active Device Optimiz.*/ 287 #define AHCI_P_FBS_ADO_SHIFT 12 288 #define AHCI_P_FBS_DWE 0x000f0000 /* Device With Error */ 289 #define AHCI_P_FBS_DWE_SHIFT 16 290