1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #define DEBUG_TYPE "spiller"
11
12 #include "Spiller.h"
13 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
14 #include "llvm/CodeGen/LiveRangeEdit.h"
15 #include "llvm/CodeGen/LiveStackAnalysis.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineLoopInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/VirtRegMap.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28
29 using namespace llvm;
30
31 namespace {
32 enum SpillerName { trivial, inline_ };
33 }
34
35 static cl::opt<SpillerName>
36 spillerOpt("spiller",
37 cl::desc("Spiller to use: (default: standard)"),
38 cl::Prefix,
39 cl::values(clEnumVal(trivial, "trivial spiller"),
40 clEnumValN(inline_, "inline", "inline spiller"),
41 clEnumValEnd),
42 cl::init(trivial));
43
44 // Spiller virtual destructor implementation.
~Spiller()45 Spiller::~Spiller() {}
46
47 namespace {
48
49 /// Utility class for spillers.
50 class SpillerBase : public Spiller {
51 protected:
52 MachineFunctionPass *pass;
53 MachineFunction *mf;
54 VirtRegMap *vrm;
55 LiveIntervals *lis;
56 MachineFrameInfo *mfi;
57 MachineRegisterInfo *mri;
58 const TargetInstrInfo *tii;
59 const TargetRegisterInfo *tri;
60
61 /// Construct a spiller base.
SpillerBase(MachineFunctionPass & pass,MachineFunction & mf,VirtRegMap & vrm)62 SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
63 : pass(&pass), mf(&mf), vrm(&vrm)
64 {
65 lis = &pass.getAnalysis<LiveIntervals>();
66 mfi = mf.getFrameInfo();
67 mri = &mf.getRegInfo();
68 tii = mf.getTarget().getInstrInfo();
69 tri = mf.getTarget().getRegisterInfo();
70 }
71
72 /// Add spill ranges for every use/def of the live interval, inserting loads
73 /// immediately before each use, and stores after each def. No folding or
74 /// remat is attempted.
trivialSpillEverywhere(LiveRangeEdit & LRE)75 void trivialSpillEverywhere(LiveRangeEdit& LRE) {
76 LiveInterval* li = &LRE.getParent();
77
78 DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
79
80 assert(li->weight != llvm::huge_valf &&
81 "Attempting to spill already spilled value.");
82
83 assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
84 "Trying to spill a stack slot.");
85
86 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
87
88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
89 unsigned ss = vrm->assignVirt2StackSlot(li->reg);
90
91 // Iterate over reg uses/defs.
92 for (MachineRegisterInfo::reg_iterator
93 regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
94
95 // Grab the use/def instr.
96 MachineInstr *mi = &*regItr;
97
98 DEBUG(dbgs() << " Processing " << *mi);
99
100 // Step regItr to the next use/def instr.
101 do {
102 ++regItr;
103 } while (regItr != mri->reg_end() && (&*regItr == mi));
104
105 // Collect uses & defs for this instr.
106 SmallVector<unsigned, 2> indices;
107 bool hasUse = false;
108 bool hasDef = false;
109 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
110 MachineOperand &op = mi->getOperand(i);
111 if (!op.isReg() || op.getReg() != li->reg)
112 continue;
113 hasUse |= mi->getOperand(i).isUse();
114 hasDef |= mi->getOperand(i).isDef();
115 indices.push_back(i);
116 }
117
118 // Create a new virtual register for the load and/or store.
119 unsigned NewVReg = LRE.create();
120
121 // Update the reg operands & kill flags.
122 for (unsigned i = 0; i < indices.size(); ++i) {
123 unsigned mopIdx = indices[i];
124 MachineOperand &mop = mi->getOperand(mopIdx);
125 mop.setReg(NewVReg);
126 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
127 mop.setIsKill(true);
128 }
129 }
130 assert(hasUse || hasDef);
131
132 // Insert reload if necessary.
133 MachineBasicBlock::iterator miItr(mi);
134 if (hasUse) {
135 MachineInstrSpan MIS(miItr);
136
137 tii->loadRegFromStackSlot(*mi->getParent(), miItr, NewVReg, ss, trc,
138 tri);
139 lis->InsertMachineInstrRangeInMaps(MIS.begin(), miItr);
140 }
141
142 // Insert store if necessary.
143 if (hasDef) {
144 MachineInstrSpan MIS(miItr);
145
146 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), NewVReg,
147 true, ss, trc, tri);
148 lis->InsertMachineInstrRangeInMaps(llvm::next(miItr), MIS.end());
149 }
150 }
151 }
152 };
153
154 } // end anonymous namespace
155
156 namespace {
157
158 /// Spills any live range using the spill-everywhere method with no attempt at
159 /// folding.
160 class TrivialSpiller : public SpillerBase {
161 public:
162
TrivialSpiller(MachineFunctionPass & pass,MachineFunction & mf,VirtRegMap & vrm)163 TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
164 VirtRegMap &vrm)
165 : SpillerBase(pass, mf, vrm) {}
166
spill(LiveRangeEdit & LRE)167 void spill(LiveRangeEdit &LRE) {
168 // Ignore spillIs - we don't use it.
169 trivialSpillEverywhere(LRE);
170 }
171 };
172
173 } // end anonymous namespace
174
anchor()175 void Spiller::anchor() { }
176
createSpiller(MachineFunctionPass & pass,MachineFunction & mf,VirtRegMap & vrm)177 llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
178 MachineFunction &mf,
179 VirtRegMap &vrm) {
180 switch (spillerOpt) {
181 case trivial: return new TrivialSpiller(pass, mf, vrm);
182 case inline_: return createInlineSpiller(pass, mf, vrm);
183 }
184 llvm_unreachable("Invalid spiller optimization");
185 }
186