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/freebsd-13-stable/sys/contrib/device-tree/Bindings/reset/
HDuniphier-reset.txt1 UniPhier glue reset controller
4 Peripheral core reset in glue layer
5 -----------------------------------
7 Some peripheral core reset belongs to its own glue layer. Before using
12 - compatible: Should be
13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
16 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
17 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/regulator/
HDuniphier-regulator.txt7 ---------------
9 This regulator controls VBUS and belongs to USB3 glue layer. Before using
14 - compatible: Should be
15 "socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC
16 "socionext,uniphier-pro5-usb3-regulator" - for Pro5 SoC
17 "socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC
18 "socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC
19 "socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC
20 - reg: Specifies offset and length of the register set for the device.
21 - clocks: A list of phandles to the clock gate for USB3 glue layer.
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/freebsd-13-stable/sys/contrib/device-tree/Bindings/nvmem/
HDuniphier-efuse.txt3 This UniPhier eFuse must be under soc-glue.
6 - compatible: should be "socionext,uniphier-efuse"
7 - reg: should contain the register location and length
15 soc-glue@5f900000 {
16 compatible = "socionext,uniphier-ld20-soc-glue-debug",
17 "simple-mfd";
18 #address-cells = <1>;
19 #size-cells = <1>;
23 compatible = "socionext,uniphier-efuse";
28 compatible = "socionext,uniphier-efuse";
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/freebsd-13-stable/sys/contrib/device-tree/Bindings/usb/
Dmediatek,mtk-xhci.txt3 The device node for Mediatek SOC USB3.0 host controller
6 the second one supports dual-role mode, and the host is based on xHCI
11 ------------------------------------------------------------------------
14 - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
15 soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
16 "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
18 - "mediatek,mt8173-xhci"
19 - reg : specifies physical base address and size of the registers
20 - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
21 - interrupts : interrupt used by the controller
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Dmediatek,mtu3.txt4 - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3",
5 soc-model is the name of SoC, such as mt8173, mt2712 etc,
6 when using "mediatek,mtu3" compatible string, you need SoC specific
8 - "mediatek,mt8173-mtu3"
9 - reg : specifies physical base address and size of the registers
10 - reg-names: should be "mac" for device IP and "ippc" for IP port control
11 - interrupts : interrupt used by the device IP
12 - power-domains : a phandle to USB power domain node to control USB's
14 - vusb33-supply : regulator of USB avdd3.3v
15 - clocks : a list of phandle + clock-specifier pairs, one for each
[all …]
HDdwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
12 encompasses the glue registers
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
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HDomap-usb.txt1 OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
3 OMAP MUSB GLUE
4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
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Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <narmstrong@baylibre.com>
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
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/freebsd-13-stable/sys/contrib/device-tree/Bindings/sound/
Duniphier,aio.txt1 Socionext UniPhier SoC audio driver
7 - compatible : should be one of the following:
8 "socionext,uniphier-ld11-aio"
9 "socionext,uniphier-ld20-aio"
10 "socionext,uniphier-pxs2-aio"
11 - reg : offset and length of the register set for the device.
12 - interrupts : should contain I2S or S/PDIF interrupt.
13 - pinctrl-names : should be "default".
14 - pinctrl-0 : defined I2S signal pins for an external codec chip.
15 - clock-names : should include following entries:
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Damlogic,g12a-tohdmitx.txt1 * Amlogic HDMI Tx control glue
4 - compatible: "amlogic,g12a-tohdmitx" or
5 "amlogic,sm1-tohdmitx"
6 - reg: physical base address of the controller and length of memory
8 - #sound-dai-cells: should be 1.
9 - resets: phandle to the dedicated reset line of the hdmitx glue.
11 Example on the S905X2 SoC:
13 tohdmitx: audio-controller@744 {
14 compatible = "amlogic,g12a-tohdmitx";
16 #sound-dai-cells = <1>;
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/net/
HDsti-dwmac.txt1 STMicroelectronics SoC DWMAC glue layer controller
5 and what is needed on STi platforms to program the stmmac glue logic.
10 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
11 "st,stih407-dwmac", "st,stid127-dwmac".
12 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 encompases the glue register, and the offset of the control register.
14 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 register available on STiH407 SoC.
16 - pinctrl-0: pin-control for all the MII mode supported.
19 - resets : phandle pointing to the system reset controller with correct
[all …]
HDmediatek-dwmac.txt1 MediaTek DWMAC glue layer controller
3 This file documents platform glue layer for stmmac.
9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
17 "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
18 - mac-address: See ethernet.txt in the same directory
[all …]
HDmdio-mux-meson-g12a.txt1 Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
8 - compatible : amlogic,g12a-mdio-mux
9 - reg: physical address and length of the multiplexer/glue registers
10 - clocks: list of clock phandle, one for each entry clock-names.
11 - clock-names: should contain the following:
14 * "clkin1" : SoC 50MHz MPLL
18 mdio_mux: mdio-multiplexer@4c000 {
19 compatible = "amlogic,g12a-mdio-mux";
24 clock-names = "pclk", "clkin0", "clkin1";
25 mdio-parent-bus = <&mdio0>;
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/phy/
Dsocionext,uniphier-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
17 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
22 - socionext,uniphier-pro4-usb2-phy
23 - socionext,uniphier-ld11-usb2-phy
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/pinctrl/
Dsocionext,uniphier-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
18 - socionext,uniphier-ld4-pinctrl
19 - socionext,uniphier-pro4-pinctrl
20 - socionext,uniphier-sld8-pinctrl
21 - socionext,uniphier-pro5-pinctrl
22 - socionext,uniphier-pxs2-pinctrl
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm/
HDuniphier-pro4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-pro4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
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HDuniphier-sld8.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-sld8";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
[all …]
HDuniphier-ld4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-ld4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
[all …]
HDuniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
[all …]
HDuniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/socionext/
HDuniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
[all …]
HDuniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
12 compatible = "socionext,uniphier-ld11";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <0>;
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/pci/
HDuniphier-pcie.txt9 Documentation/devicetree/bindings/pci/designware-pcie.txt.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
17 "link" - SoC-specific glue layer registers
18 "config" - PCIe configuration space
19 - clocks: A phandle to the clock gate for PCIe glue layer including
21 - resets: A phandle to the reset line for PCIe glue layer including
[all …]
/freebsd-13-stable/share/man/man4/
HDath_ahb.41 .\"-
34 .Nd "Atheros AHB device glue"
38 This module provides the AHB bus glue needed for the devices supported
45 This is only relevant for embedded System-on-Chip (SoC) devices such as
46 the Atheros AR913x series, which include an Atheros wireless MAC on-die.
/freebsd-13-stable/sys/contrib/device-tree/Bindings/nds32/
HDandestech-boards2 -----------------------------------------------------------------------------
7 - compatible = "andestech,ae3xx";
10 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 interrupt-parent = <&intc>;
19 -----------------------------------------------------------------------------
20 AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)
21 processors to provide a cost-effective and high performance solution for
23 simply attach their IP on one of the system buses together with certain glue
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