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/freebsd-13-stable/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/java_api/
HDtst.Bean.ksh.out45 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
56 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
68 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
79 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
150 …-4611686018427387904, max = -2305843009213693953, frequency = 0], org.opensolaris.os.dtrace.Distri…
151 …-4611686018427387904, max = -2305843009213693953, frequency = 0], org.opensolaris.os.dtrace.Distri…
153 …-4611686018427387904, max = -2305843009213693953, frequency = 0], org.opensolaris.os.dtrace.Distri…
154 …-4611686018427387904, max = -2305843009213693953, frequency = 0], org.opensolaris.os.dtrace.Distri…
156 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
157 …max = 10, frequency = 0], org.opensolaris.os.dtrace.Distribution$Bucket[min = 11, max = 20, freque…
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm/
HDqcom-msm8960-cdp.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
8 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
15 stdout-path = "serial0:115200n8";
41 compatible = "qcom,rpm-pm8921-regulators";
42 vin_lvs1_3_6-supply = <&pm8921_s4>;
43 vin_lvs2-supply = <&pm8921_s4>;
44 vin_lvs4_5_7-supply = <&pm8921_s4>;
45 vdd_ncp-supply = <&pm8921_l6>;
[all …]
HDexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a15";
30 clock-frequency = <1800000000>;
31 cci-control-port = <&cci_control1>;
32 operating-points-v2 = <&cluster_a15_opp_table>;
[all …]
HDbcm28155-ap.dts14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
22 compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
35 clock-frequency = <400000>;
40 clock-frequency = <400000>;
45 clock-frequency = <400000>;
50 clock-frequency = <100000>;
58 non-removable;
59 max-frequency = <48000000>;
60 vmmc-supply = <&camldo1_reg>;
[all …]
HDexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-a7";
29 clock-frequency = <1000000000>;
30 cci-control-port = <&cci_control0>;
31 operating-points-v2 = <&cluster_a7_opp_table>;
[all …]
HDqcom-apq8064-sony-xperia-yuga.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 compatible = "sony,xperia-yuga", "qcom,apq8064";
17 stdout-path = "serial0:115200n8";
20 gpio-keys {
21 compatible = "gpio-keys";
[all …]
HDat91-sama5d4_ma5d4.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
18 clock-frequency = <32768>;
22 clock-frequency = <12000000>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <20000000>;
29 clock-output-names = "clk20m";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
38 vmmc-supply = <&vcc_mmc0_reg>;
[all …]
HDqcom-mdm9615.dtsi7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
50 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
51 #include <dt-bindings/mfd/qcom-rpm.h>
52 #include <dt-bindings/soc/qcom,gsbi.h>
55 #address-cells = <1>;
56 #size-cells = <1>;
59 interrupt-parent = <&intc>;
[all …]
HDqcom-apq8064-cm-qs600.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
7 model = "CompuLab CM-QS600";
8 compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064";
15 stdout-path = "serial0:115200n8";
19 #address-cells = <1>;
20 #size-cells = <1>;
22 compatible = "simple-bus";
[all …]
HDqcom-apq8064-asus-nexus7-flo.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
8 compatible = "asus,nexus7-flo", "qcom,apq8064";
16 stdout-path = "serial0:115200n8";
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
HDdra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
33 #clock-cells = <0>;
[all …]
HDtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
27 * pre-existing /chosen node to be available to insert the
36 reserved-memory {
37 #address-cells = <1>;
[all …]
HDimx28-tx28.dts3 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
5 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
45 #include <dt-bindings/gpio/gpio.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 model = "Ka-Ro electronics TX28 module";
70 reg = <0x40000000 0>; /* will be filled in by U-Boot */
74 compatible = "w1-gpio";
79 reg_usb0_vbus: regulator-usb0-vbus {
80 compatible = "regulator-fixed";
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/iio/resolver/
HDad2s90.txt1 Analog Devices AD2S90 Resolver-to-Digital Converter
6 - compatible: should be "adi,ad2s90"
7 - reg: SPI chip select number for the device
8 - spi-max-frequency: set maximum clock frequency, must be 830000
9 - spi-cpol and spi-cpha:
11 spi-cpha, spi-cpol.
14 Documentation/devicetree/bindings/spi/spi-bus.txt
16 Note about max frequency:
17 Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
21 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
[all …]
/freebsd-13-stable/contrib/ntp/kernel/sys/
HDtimex.h21 * Added defines for hybrid phase/frequency-lock loop.
25 * defines for PPS phase-lock loop.
45 * ntp_gettime - NTP user application interface
56 * ntp_adjtime - NTP daemon application interface
76 * phase-lock loop (PLL) model used in the kernel implementation. These
81 * establishes the timer interrupt frequency, 100 Hz for the SunOS
98 #define SHIFT_KF 16 /* PLL frequency factor (shift) */
99 #define SHIFT_KH 2 /* FLL frequency factor (shift) */
105 * possible without overflow of a 32-bit word.
108 * which serves as a an extension to the low-order bits of the system
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/freescale/
HDfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
29 stdout-path = "serial0:115200n8";
37 sys_mclk: clock-mclk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
43 reg_1p8v: regulator-1p8v {
[all …]
HDfsl-ls1012a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
16 sys_mclk: clock-mclk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <24576000>;
22 reg_3p3v: regulator-3p3v {
23 compatible = "regulator-fixed";
[all …]
HDfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
HDfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 mmc-hs200-1_8v;
19 #address-cells = <2>;
20 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28 compatible = "cfi-flash";
30 bank-width = <2>;
31 device-width = <1>;
35 compatible = "fsl,ifc-nand";
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/spi/
Dqcom,spi-qup.txt4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
19 - clock-names: Should be "core" for the core clock and "iface" for the
22 - #address-cells: Number of cells required to define a chip select
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/net/wireless/
Dti,wlcore,spi.txt7 - compatible : Should be one of the following:
18 - reg : Chip select address of device
19 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
20 - interrupts : Should contain parameters for 1 interrupt line.
21 - vwlan-supply : Point the node of the regulator that powers/enable the
25 - ref-clock-frequency : Reference clock frequency (should be set for wl12xx)
26 - clock-xtal : boolean, clock is generated from XTAL
28 - Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
38 spi-max-frequency = <48000000>;
39 interrupt-parent = <&gpio3>;
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/mmc/
HDcavium-mmc.txt10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/mediatek/
HDmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
19 stdout-path = "serial0:115200n8";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 clock-output-names = "clk32k";
35 compatible = "regulator-fixed";
36 regulator-name = "it6505_pp18";
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/iio/imu/
Dadi,adis16480.txt6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/rockchip/
HDrk3399-puma-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-puma.dtsi"
10 model = "Theobroma Systems RK3399-Q7 SoM";
11 compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
14 stdout-path = "serial0:115200n8";
18 pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
20 sd_card_led: led-1 {
23 linux,default-trigger = "mmc0";
27 i2s0-sound {
[all …]

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