Home
last modified time | relevance | path

Searched +full:efuse +full:- +full:size (Results 1 – 25 of 209) sorted by relevance

123456789

/freebsd-head/sys/contrib/device-tree/src/arm/aspeed/
HDaspeed-bmc-delta-ahe50dc.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g4.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
8 efuse##n { \
9 compatible = "regulator-output"; \
10 vout-supply = <&efuse##n>; \
15 #define EFUSE(hexaddr, num) \ macro
16 efuse@##hexaddr { \
19 shunt-resistor-micro-ohms = <675>; \
[all …]
/freebsd-head/sys/contrib/device-tree/Bindings/nvmem/
HDrockchip-efuse.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip eFuse
10 - Heiko Stuebner <heiko@sntech.de>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml#
19 - rockchip,rk3066a-efuse
20 - rockchip,rk3188-efuse
[all …]
HDmtk-efuse.txt1 = Mediatek MTK-EFUSE device tree bindings =
3 This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
6 - compatible: should be
7 "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
8 "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
9 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
10 "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
11 "mediatek,mt8195-efuse", "mediatek,efuse": for MT8195
12 "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516
13 - reg: Should contain registers location and length
[all …]
HDsc27xx-efuse.txt1 = Spreadtrum SC27XX PMIC eFuse device tree bindings =
4 - compatible: Should be one of the following.
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
11 - hwlocks: Reference to a phandle of a hwlock provider node.
14 Are child nodes of eFuse, bindings of which as described in
[all …]
HDuniphier-efuse.txt1 = UniPhier eFuse device tree bindings =
3 This UniPhier eFuse must be under soc-glue.
6 - compatible: should be "socionext,uniphier-efuse"
7 - reg: should contain the register location and length
10 Are child nodes of efuse, bindings of which as described in
15 soc-glue@5f900000 {
16 compatible = "socionext,uniphier-ld20-soc-glue-debug",
17 "simple-mfd";
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
Dmediatek,efuse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek efuse
10 MediaTek's efuse is used for storing calibration data, it can be accessed
14 - Andrew-CT Chen <andrew-ct.chen@mediatek.com>
15 - Lala Lin <lala.lin@mediatek.com>
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
[all …]
HDamlogic-meson-mx-efuse.txt1 Amlogic Meson6/Meson8/Meson8b efuse
4 - compatible: depending on the SoC this should be one of:
5 - "amlogic,meson6-efuse"
6 - "amlogic,meson8-efuse"
7 - "amlogic,meson8b-efuse"
8 - reg: base address and size of the efuse registers
9 - clocks: a reference to the efuse core gate clock
10 - clock-names: must be "core"
12 All properties and sub-nodes as well as the consumer bindings
17 efuse: nvmem@0 {
[all …]
Damlogic,meson6-efuse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/amlogic,meson6-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson6 eFuse
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 - $ref: nvmem.yaml#
15 - $ref: nvmem-deprecated-cells.yaml#
20 - amlogic,meson6-efuse
[all …]
Damlogic,meson-gxbb-efuse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/amlogic,meson-gxbb-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson GX eFuse
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml#
19 - const: amlogic,meson-gxbb-efuse
20 - items:
[all …]
HDamlogic-efuse.txt1 = Amlogic Meson GX eFuse device tree bindings =
4 - compatible: should be "amlogic,meson-gxbb-efuse"
5 - clocks: phandle to the efuse peripheral clock provided by the
7 - secure-monitor: phandle to the secure-monitor node
10 Are child nodes of eFuse, bindings of which as described in
15 efuse: efuse {
16 compatible = "amlogic,meson-gxbb-efuse";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 secure-monitor = <&sm>;
[all …]
Dsocionext,uniphier-efuse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier eFuse
10 - Keiji Hayashibara <hayashibara.keiji@socionext.com>
11 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
14 - $ref: nvmem.yaml#
15 - $ref: nvmem-deprecated-cells.yaml#
19 const: socionext,uniphier-efuse
[all …]
/freebsd-head/sys/contrib/device-tree/Bindings/regulator/
HDti-abb-regulator.txt4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
[all …]
/freebsd-head/sys/contrib/device-tree/Bindings/fuse/
Dnvidia,tegra20-fuse.txt4 - compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
5 must contain "nvidia,tegra30-efuse". For Tegra114, must contain
6 "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
7 For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
8 For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
9 "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
10 For Tegra234 must contain "nvidia,tegra234-efuse".
12 nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
15 nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
16 The differences between these SoCs are the size of the efuse array,
[all …]
/freebsd-head/sys/contrib/dev/rtw88/
HDmain.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
20 #include "efuse.h"
174 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
187 struct rtw_bf_info *bf_info = &rtwdev->bf_info; in rtw_dynamic_csi_rate()
191 if (rtwvif->bfee.role != RTW_BFEE_SU && in rtw_dynamic_csi_rate()
192 rtwvif->bfee.role != RTW_BFEE_MU) in rtw_dynamic_csi_rate()
195 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, in rtw_dynamic_csi_rate()
196 bf_info->cur_csi_rpt_rate, in rtw_dynamic_csi_rate()
199 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) in rtw_dynamic_csi_rate()
[all …]
HDefuse.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
8 #include "efuse.h"
31 /* efuse header format
37 * word_en: 4 bits each word. 0 -> write; 1 -> not write
43 u32 physical_size = rtwdev->efuse.physical_size; in rtw_dump_logical_efuse_map()
44 u32 protect_size = rtwdev->efuse.protect_size; in rtw_dump_logical_efuse_map()
45 u32 logical_size = rtwdev->efuse.logical_size; in rtw_dump_logical_efuse_map()
52 for (phy_idx = 0; phy_idx < physical_size - protect_size;) { in rtw_dump_logical_efuse_map()
59 /* 2-byte header format */ in rtw_dump_logical_efuse_map()
[all …]
HDphy.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
89 .size = ARRAY_SIZE(name), \
104 .size = ARRAY_SIZE(name), \
111 .size = ARRAY_SIZE(name), \
117 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_get_rfe_def()
118 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_get_rfe_def() local
121 if (chip->rfe_defs_size == 0) in rtw_get_rfe_def()
124 if (efuse->rfe_option < chip->rfe_defs_size) in rtw_get_rfe_def()
125 rfe_def = &chip->rfe_defs[efuse->rfe_option]; in rtw_get_rfe_def()
[all …]
/freebsd-head/sys/contrib/dev/rtw89/
HDefuse_be.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
6 #include "efuse.h"
25 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_enable_efuse_pwr_cut_ddv_be()
26 struct rtw89_hal *hal = &rtwdev->hal; in rtw89_enable_efuse_pwr_cut_ddv_be()
29 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) in rtw89_enable_efuse_pwr_cut_ddv_be()
46 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_disable_efuse_pwr_cut_ddv_be()
47 struct rtw89_hal *hal = &rtwdev->hal; in rtw89_disable_efuse_pwr_cut_ddv_be()
50 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) in rtw89_disable_efuse_pwr_cut_ddv_be()
73 rtw89_err(rtwdev, "Efuse addr 0x%x or size 0x%x not aligned\n", in rtw89_dump_physical_efuse_map_ddv_be()
75 return -EINVAL; in rtw89_dump_physical_efuse_map_ddv_be()
[all …]
/freebsd-head/sys/contrib/device-tree/Bindings/net/
HDkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
[all …]
Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
22 Complex (UDMA-P) controller.
36 ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
52 "#address-cells": true
53 "#size-cells": true
[all …]
/freebsd-head/sys/contrib/device-tree/Bindings/soc/socionext/
Dsocionext,uniphier-soc-glue-debug.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic debug part
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
20 - enum:
21 - socionext,uniphier-ld4-soc-glue-debug
22 - socionext,uniphier-pro4-soc-glue-debug
[all …]
/freebsd-head/sys/contrib/dev/mediatek/mt76/mt7603/
HDeeprom.c1 // SPDX-License-Identifier: ISC
21 return -ETIMEDOUT; in mt7603_efuse_read()
51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
54 return -ENOMEM; in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
67 mt7603_has_cal_free_data(struct mt7603_dev *dev, u8 *efuse) in mt7603_has_cal_free_data() argument
69 if (!efuse[MT_EE_TEMP_SENSOR_CAL]) in mt7603_has_cal_free_data()
72 if (get_unaligned_le16(efuse + MT_EE_TX_POWER_0_START_2G) == 0) in mt7603_has_cal_free_data()
[all …]
/freebsd-head/sys/contrib/device-tree/Bindings/phy/
HDphy-mtk-xsphy.txt1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
[all …]
/freebsd-head/sys/contrib/device-tree/src/arm64/xilinx/
HDzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/freebsd-head/contrib/file/magic/Magdir/
HDxilinx2 #------------------------------------------------------------------------------
5 # Xilinx-Magic@RevRagnarok.com
6 # Got the info from FPGA-FAQ 0026
10 # http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm
19 # Next is a Pascal-style string with the NCD name. We want to capture that.
20 >>>>>>&0 pstring/H x - from %s
24 >>>>>>>>&0 pstring/H x - for %s
27 # Then the build-date
28 >>>>>>>>>>&0 pstring/H x - built %s
31 # Then the build-time
[all …]
/freebsd-head/sys/contrib/device-tree/Bindings/edac/
HDapm-xgene-edac.txt1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]

123456789