| /freebsd-13-stable/sys/contrib/device-tree/Bindings/pci/ |
| HD | rcar-pci.txt | 1 * Renesas R-Car PCIe interface
4 compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
5 "renesas,pcie-r8a7744" for the R8A7744 SoC;
6 "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
7 "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
8 "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
9 "renesas,pcie-r8a7779" for the R8A7779 SoC;
10 "renesas,pcie-r8a7790" for the R8A7790 SoC;
11 "renesas,pcie-r8a7791" for the R8A7791 SoC;
12 "renesas,pcie-r8a7793" for the R8A7793 SoC;
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| D | fsl,imx6q-pcie.txt | 1 * Freescale i.MX6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
8 - "fsl,imx6q-pcie"
9 - "fsl,imx6sx-pcie",
10 - "fsl,imx6qp-pcie"
11 - "fsl,imx7d-pcie"
12 - "fsl,imx8mq-pcie"
13 - reg: base address and length of the PCIe controller
37 - vpcie-supply: Should specify the regulator in charge of PCIe port power.
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| HD | mediatek-pcie.txt | 1 MediaTek Gen2 PCIe controller
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
11 - reg: Base addresses and lengths of the PCIe subsys and root ports.
21 - free_ck :for reference clock of PCIe subsys
33 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
47 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
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| HD | layerscape-pci.txt | 1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
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| HD | mvebu-pci.txt | 1 * Marvell EBU PCIe interfaces
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
15 - ranges: ranges describing the MMIO registers to control the PCIe
17 the memory and I/O regions of each PCIe interface.
28 registers of this PCIe interface, from the base of the internal
46 * s is the PCI slot that corresponds to this PCIe interface
58 PCIe interface, having the following mandatory properties:
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| D | nvidia,tegra20-pcie.txt | 1 NVIDIA Tegra PCIe controller
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
11 contain BPMP phandle and PCIe power partition ID. This is required only
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
79 - pcie
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| HD | pci-keystone.txt | 1 TI Keystone PCIe interface
4 hardware version 3.65. It shares common functions with the PCIe DesignWare
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
24 (required if the compatible is "ti,keystone-pcie")
26 (required if the compatible is "ti,am654-pcie-rc".
28 ti,syscon-pcie-id : phandle to the device control module required to set device
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| D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
21 - axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
26 pcie@f8050000 {
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| D | brcm,iproc-pcie.txt | 1 * Broadcom iProc PCIe controller with the platform bus interface
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
15 - reg: base address and length of the PCIe controller I/O register space
18 mapping of the PCIe interface to interrupt numbers
27 - phys: phandle of the PCIe PHY device
28 - phy-names: must be "pcie-phy"
34 - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
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| D | amlogic,meson-pcie.txt | 1 Amlogic Meson AXG DWC PCIE SoC controller
3 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
13 - "amlogic,axg-pcie" for AXG SoC Family
14 - "amlogic,g12a-pcie" for G12A SoC Family
21 - "config" PCIe configuration space
22 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
25 - "pclk" PCIe GEN 100M PLL clock
27 - "general" PCIe Phy clock
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| D | qcom,pcie.txt | 7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
27 - "dbi" DesignWare PCIe registers
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| HD | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
14 where <X> is the instance number of the pcie from the HW spec.
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| D | samsung,exynos5440-pcie.txt | 1 * Samsung Exynos 5440 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "samsung,exynos5440-pcie"
8 - reg: base addresses and lengths of the PCIe controller,
19 Documentation/devicetree/bindings/pci/designware-pcie.txt
25 pcie_phy0: pcie-phy@270000 {
32 pcie@290000 {
33 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
37 clock-names = "pcie", "pcie_bus";
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| HD | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
7 It shares common functions with the PCIe DesignWare core driver and inherits
9 Documentation/devicetree/bindings/pci/designware-pcie.txt.
12 - compatible: Should be "socionext,uniphier-pcie".
18 "config" - PCIe configuration space
19 - clocks: A phandle to the clock gate for PCIe glue layer including
21 - resets: A phandle to the reset line for PCIe glue layer including
30 - phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
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| HD | rockchip-pcie-host.txt | 1 * Rockchip AXI PCIe Root Port Bridge DT description
8 - compatible: Should contain "rockchip,rk3399-pcie"
44 - phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
45 - phy-names: MUST be "pcie-phy".
50 them won't be used for your cases. Entries are of the form "pcie-phy-N":
52 (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
60 - vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
61 - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
62 - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
63 - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
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| HD | aardvark-pci.txt | 1 Aardvark PCIe controller
3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
5 The Device Tree node describing an Aardvark PCIe controller must
8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
16 - msi-controller: indicates that the PCIe controller can itself
20 define the mapping of the PCIe interface to interrupt numbers.
22 - phys: the PCIe PHY handle
26 In addition, the Device Tree describing an Aardvark PCIe controller
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| HD | hisilicon-histb-pcie.txt | 1 HiSilicon STB PCIe host bridge DT description
3 The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
4 It shares common functions with the DesignWare PCIe core driver and inherits
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
12 "hisilicon,hi3798cv200-pcie"
15 "control": control registers of PCIe controller;
16 "rc-dbi": configuration space of PCIe controller;
17 "config": configuration transaction space of PCIe controller.
36 - reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
37 - vpcie-supply: The regulator in charge of PCIe port power.
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| /freebsd-13-stable/sys/contrib/alpine-hal/ |
| HD | al_hal_pcie.h | 41 * This header file provide API for the HAL driver of the pcie port, the driver
50 * - PCIe transactions generation and reception (except interrupts as mentioned
55 * through the fabric toward the PCIe port. This API provides management
60 * - PCIe Port Management: both link and port power management features can be
61 * managed using the PCI/PCIe standard power management and PCIe capabilities
63 * - PCIe link and protocol error handling: the feature can be managed using
64 * the Advanced Error Handling PCIe capability registers.
89 * - Enable pcie core RAM parity
90 * - Enable pcie core AXI parity
104 * AL_TRUE, // enable pcie port RAM parity
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| /freebsd-13-stable/sys/contrib/device-tree/Bindings/phy/ |
| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
15 ports (e.g. PCIe) and the lanes.
49 - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
55 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
82 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
85 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
104 PCIe pad:
113 - "phy": reset for the PCIe UPHY block
147 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
148 - functions: "pcie", "usb3-ss"
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| D | brcm,cygnus-pcie-phy.txt | 1 Broadcom Cygnus PCIe PHY
4 - compatible: must be "brcm,cygnus-pcie-phy"
5 - reg: base address and length of the PCIe PHY block
9 Each PCIe PHY should be represented by a child node
13 0 - PCIe RC 0
14 1 - PCIe RC 1
19 compatible = "brcm,cygnus-pcie-phy";
33 /* users of the PCIe phy */
35 pcie0: pcie@18012000 {
39 phy-names = "pcie-phy";
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| /freebsd-13-stable/sys/contrib/octeon-sdk/ |
| HD | cvmx-pcie.h | 49 * Interface to PCIe as a host(RC) or target(EP)
82 uint64_t did : 5; /* PCIe DID = 3 */
83 uint64_t subdid : 3; /* PCIe SubDID = 1 */
86 uint64_t port : 2; /* PCIe port 0,1 */
100 uint64_t did : 5; /* PCIe DID = 3 */
101 uint64_t subdid : 3; /* PCIe SubDID = 2 */
104 uint64_t port : 2; /* PCIe port 0,1 */
105 uint64_t address : 32; /* PCIe IO address */
112 uint64_t did : 5; /* PCIe DID = 3 */
113 uint64_t subdid : 3; /* PCIe SubDID = 3-6 */
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| HD | cvmx-pcie.c | 43 * Interface to PCIe as a host(RC) or target(EP)
73 #include <asm/octeon/cvmx-pcie.h>
82 #include "cvmx-pcie.h"
99 * Return the Core virtual base address for PCIe IO access. IOs are
102 * @param pcie_port PCIe port the IO is for
124 * @param pcie_port PCIe port the IO is for
135 * Return the Core virtual base address for PCIe MEM access. Memory is
138 * @param pcie_port PCIe port the IO is for
158 * @param pcie_port PCIe port the IO is for
172 * @param pcie_port PCIe port to initialize
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| /freebsd-13-stable/sys/contrib/device-tree/Bindings/clock/ |
| HD | mvebu-gated-clock.txt | 14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
61 5 pex1 PCIe 1
62 6 pex2 PCIe 2
63 7 pex3 PCIe 3
64 8 pex0 PCIe 0
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| /freebsd-13-stable/sys/contrib/device-tree/src/arm64/nvidia/ |
| HD | tegra210-p2371-2180.dts | 11 pcie@1003000 {
22 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
23 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
24 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
25 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
26 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
31 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
32 phy-names = "pcie-0";
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| /freebsd-13-stable/sys/contrib/device-tree/src/arm/ |
| HD | armada-xp-mv78260.dtsi | 49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
53 pciec: pcie@82000000 {
54 compatible = "marvell,armada-xp-pcie";
95 pcie1: pcie@1,0 {
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <0>;
113 pcie2: pcie@2,0 {
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <1>;
131 pcie3: pcie@3,0 {
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