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/freebsd-13-stable/sys/arm/allwinner/clkng/
HDccu_a10.c107 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
108 CCU_GATE(CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 0x60, 1)
109 CCU_GATE(CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 0x60, 2)
110 CCU_GATE(CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 0x60, 3)
111 CCU_GATE(CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 0x60, 4)
112 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
113 CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6)
114 CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7)
115 CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8)
116 CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9)
[all …]
HDccu_a13.c104 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
105 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
106 CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
107 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
108 CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6)
109 CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7)
110 CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8)
111 CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9)
112 CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10)
113 CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13)
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/arm/tegra/
Dnvidia,tegra20-ahb.txt1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/freebsd-13-stable/sys/contrib/device-tree/Bindings/clock/
Dallwinner,sun5i-a13-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock Device Tree Bindings
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
Dallwinner,sun4i-a10-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock Device Tree Bindings
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
HDnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
Dallwinner,sun9i-a80-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
7 title: Allwinner A80 AHB Clock Device Tree Bindings
20 const: allwinner,sun9i-a80-ahb-clk
46 compatible = "allwinner,sun9i-a80-ahb-clk";
Dallwinner,sun4i-a10-gates-clk.yaml26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
100 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
102 clocks = <&ahb>;
Dqca,ath79-pll.txt3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
20 - clock-output-names: should be "cpu", "ddr", "ahb"
32 clock-output-names = "cpu", "ddr", "ahb";
/freebsd-13-stable/sys/contrib/device-tree/Bindings/pci/
Dqcom,pcie.txt86 - "iface" Configuration AHB clock
121 - "ahb" AHB clock
128 - "iface" AHB clock
156 - "ahb" AHB reset
181 - "ahb" AHB reset
182 - "phy_ahb" PHY AHB reset
194 - "ahb" AHB Reset
206 - "ahb" AHB reset
294 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
/freebsd-13-stable/sys/contrib/device-tree/Bindings/dma/
HDarm-pl08x.txt15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
21 which AHB master that is used.
33 - dmas: List of DMA controller phandle, request channel and AHB master id
HDsnps-dma.txt9 - dma-masters: Number of AHB masters supported by the controller
16 - data-width: Maximum data width supported by hardware per AHB master
21 - data_width: Maximum data width supported by hardware per AHB master
28 - snps,dma-protection-control: AHB HPROT[3:1] protection setting.
/freebsd-13-stable/sys/contrib/device-tree/Bindings/misc/
Dintel,ixp4xx-ahb-queue-manager.yaml5 $id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#"
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
26 - const: intel,ixp4xx-ahb-queue-manager
48 compatible = "intel,ixp4xx-ahb-queue-manager";
/freebsd-13-stable/sys/contrib/device-tree/Bindings/iommu/
Dnvidia,tegra30-smmu.txt10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
20 nvidia,ahb = <&ahb>;
/freebsd-13-stable/sys/contrib/device-tree/Bindings/soc/qcom/
Dqcom,geni-se.yaml32 - const: m-ahb
33 - const: s-ahb
37 - description: Master AHB Clock
38 - description: Slave AHB Clock
189 clock-names = "m-ahb", "s-ahb";
/freebsd-13-stable/sys/contrib/device-tree/src/arm/
HDsun6i-a31.dtsi297 clock-names = "ahb",
350 clock-names = "ahb",
398 clock-names = "ahb",
403 reset-names = "ahb";
419 clock-names = "ahb",
424 reset-names = "ahb";
440 clock-names = "ahb",
445 reset-names = "ahb";
459 clock-names = "ahb",
464 reset-names = "ahb";
[all …]
HDsun8i-v3s.dtsi147 clock-names = "ahb",
183 clock-names = "ahb",
188 reset-names = "ahb";
204 clock-names = "ahb",
209 reset-names = "ahb";
225 clock-names = "ahb",
230 reset-names = "ahb";
412 clock-names = "ahb", "mod";
HDsun5i.dtsi208 clock-names = "ahb", "mod";
221 clock-names = "ahb", "mod";
235 clock-names = "ahb", "mod";
286 clock-names = "ahb",
324 clock-names = "ahb", "mod", "ram";
334 clock-names = "ahb", "mmc";
347 clock-names = "ahb", "mmc";
358 clock-names = "ahb", "mmc";
417 clock-names = "ahb", "mod";
425 clock-names = "ahb", "mod";
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/display/
Dallwinner,sun4i-a10-tcon.yaml197 - const: ahb
216 - const: ahb
236 - const: ahb
256 - const: ahb
275 - const: ahb
397 clock-names = "ahb",
471 clock-names = "ahb",
540 clock-names = "ahb", "tcon-ch0";
590 clock-names = "ahb", "tcon-ch0";
645 clock-names = "ahb", "tcon-ch1";
/freebsd-13-stable/sys/contrib/device-tree/Bindings/usb/
HDci-hdrc-usb2.txt44 - ahb-burst-config: it is vendor dependent, the required value should be
46 property is used to change AHB burst configuration, check the chipidea
53 "ahb-burst-config" is set to 0, if this property is missing the reset
59 "ahb-burst-config" is set to 0, if this property is missing the reset
116 ahb-burst-config = <0x0>;
136 ahb-burst-config = <0x0>;
/freebsd-13-stable/sys/contrib/device-tree/Bindings/spi/
HDspi-ath79.txt6 - clocks: phandle of the AHB clock.
7 - clock-names: has to be "ahb".
20 clock-names = "ahb";
/freebsd-13-stable/sys/contrib/device-tree/Bindings/watchdog/
HDalphascale-asm9260.txt10 "ahb" - ahb gate.
29 clock-names = "mod", "ahb";
/freebsd-13-stable/sys/contrib/device-tree/Bindings/media/
HDcoda.txt17 - clocks : Should contain the ahb and per clocks, in the order
19 - clock-names : Should be "ahb", "per"
29 clock-names = "ahb", "per";
Drockchip,vdec.yaml29 - description: The Video Decoder AHB interface clock
36 - const: ahb
68 clock-names = "axi", "ahb", "cabac", "core";
/freebsd-13-stable/sys/contrib/device-tree/Bindings/crypto/
Dallwinner,sun4i-a10-crypto.yaml42 - const: ahb
49 const: ahb
78 clock-names = "ahb", "mod";

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