1 /* $NetBSD: zssp.c,v 1.15 2021/08/07 16:19:08 thorpej Exp $ */
2 /* $OpenBSD: zaurus_ssp.c,v 1.6 2005/04/08 21:58:49 uwe Exp $ */
3
4 /*
5 * Copyright (c) 2005 Uwe Stuehler <uwe@bsdx.de>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <sys/cdefs.h>
21 __KERNEL_RCSID(0, "$NetBSD: zssp.c,v 1.15 2021/08/07 16:19:08 thorpej Exp $");
22
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 #include <sys/bus.h>
27
28 #include <arm/xscale/pxa2x0reg.h>
29 #include <arm/xscale/pxa2x0var.h>
30 #include <arm/xscale/pxa2x0_gpio.h>
31
32 #include <zaurus/dev/zsspvar.h>
33 #include <zaurus/zaurus/zaurus_var.h>
34
35 #define GPIO_ADS7846_CS_C3000 14 /* SSP SFRM */
36 #define GPIO_MAX1111_CS_C3000 20
37 #define GPIO_TG_CS_C3000 53
38 #define GPIO_ADS7846_CS_C860 24 /* SSP SFRM */
39 #define GPIO_MAX1111_CS_C860 20
40 #define GPIO_TG_CS_C860 19
41
42 #define SSCR0_ADS7846_C3000 0x06ab /* 12bit/Microwire/div by 7 */
43 #define SSCR0_MAX1111 0x0387
44 #define SSCR0_LZ9JG18 0x01ab
45 #define SSCR0_ADS7846_C860 0x00ab /* 12bit/Microwire/div by 7 */
46
47 struct zssp_ads7846 {
48 u_int gpio;
49 uint32_t sscr0;
50 };
51 struct zssp_max1111 {
52 u_int gpio;
53 uint32_t sscr0;
54 };
55 struct zssp_lz9jg18 {
56 u_int gpio;
57 uint32_t sscr0;
58 int sclk_pin;
59 int sfrm_pin;
60 int txd_pin;
61 int rxd_pin;
62 };
63
64 struct zssp_softc {
65 device_t sc_dev;
66 bus_space_tag_t sc_iot;
67 bus_space_handle_t sc_ioh;
68 bus_addr_t sc_ssp;
69 struct zssp_ads7846 ads7846;
70 struct zssp_max1111 max1111;
71 struct zssp_lz9jg18 lz9jg18;
72 };
73
74 static int zssp_match(device_t, cfdata_t, void *);
75 static void zssp_attach(device_t, device_t, void *);
76 static int zssp_search(device_t, cfdata_t, const int *, void *);
77 static int zssp_print(void *, const char *);
78
79 CFATTACH_DECL_NEW(zssp, sizeof(struct zssp_softc),
80 zssp_match, zssp_attach, NULL, NULL);
81
82 static void zssp_init(void);
83 static bool zssp_resume(device_t dv, const pmf_qual_t *);
84
85 static struct zssp_softc *zssp_sc;
86
87 static int
zssp_match(device_t parent,cfdata_t cf,void * aux)88 zssp_match(device_t parent, cfdata_t cf, void *aux)
89 {
90
91 if (zssp_sc != NULL)
92 return 0;
93 return 1;
94 }
95
96 static void
zssp_attach(device_t parent,device_t self,void * aux)97 zssp_attach(device_t parent, device_t self, void *aux)
98 {
99 struct zssp_softc *sc = device_private(self);
100
101 sc->sc_dev = self;
102 zssp_sc = sc;
103
104 aprint_normal("\n");
105 aprint_naive("\n");
106
107 sc->sc_iot = &pxa2x0_bs_tag;
108 if (ZAURUS_ISC1000 || ZAURUS_ISC3000) {
109 sc->sc_ssp = PXA2X0_SSP1_BASE;
110 sc->ads7846.gpio = GPIO_ADS7846_CS_C3000;
111 sc->ads7846.sscr0 = SSCR0_ADS7846_C3000;
112 sc->max1111.gpio = GPIO_MAX1111_CS_C3000;
113 sc->max1111.sscr0 = SSCR0_MAX1111;
114 sc->lz9jg18.gpio = GPIO_TG_CS_C3000;
115 sc->lz9jg18.sscr0 = SSCR0_LZ9JG18;
116 sc->lz9jg18.sclk_pin = 19;
117 sc->lz9jg18.sfrm_pin = 14;
118 sc->lz9jg18.txd_pin = 87;
119 sc->lz9jg18.rxd_pin = 86;
120 } else {
121 sc->sc_ssp = PXA2X0_SSP_BASE;
122 sc->ads7846.gpio = GPIO_ADS7846_CS_C860;
123 sc->ads7846.sscr0 = SSCR0_ADS7846_C860;
124 sc->max1111.gpio = GPIO_MAX1111_CS_C860;
125 sc->max1111.sscr0 = SSCR0_MAX1111;
126 sc->lz9jg18.gpio = GPIO_TG_CS_C860;
127 sc->lz9jg18.sscr0 = SSCR0_LZ9JG18;
128 sc->lz9jg18.sclk_pin = 23;
129 sc->lz9jg18.sfrm_pin = 24;
130 sc->lz9jg18.txd_pin = 25;
131 sc->lz9jg18.rxd_pin = 26;
132 }
133
134 if (bus_space_map(sc->sc_iot, sc->sc_ssp, PXA2X0_SSP_SIZE,
135 0, &sc->sc_ioh)) {
136 aprint_error_dev(sc->sc_dev, "can't map bus space\n");
137 return;
138 }
139
140 if (!pmf_device_register(sc->sc_dev, NULL, zssp_resume))
141 aprint_error_dev(sc->sc_dev,
142 "couldn't establish power handler\n");
143
144 zssp_init();
145
146 /* Attach all devices */
147 config_search(self, NULL,
148 CFARGS(.search = zssp_search));
149 }
150
151 static int
zssp_search(device_t parent,cfdata_t cf,const int * ldesc,void * aux)152 zssp_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
153 {
154 struct zssp_attach_args aa;
155
156 aa.zaa_name = cf->cf_name;
157
158 if (config_probe(parent, cf, &aa))
159 config_attach(parent, cf, &aa, zssp_print, CFARGS_NONE);
160
161 return 0;
162 }
163
164 static int
zssp_print(void * aux,const char * name)165 zssp_print(void *aux, const char *name)
166 {
167
168 return UNCONF;
169 }
170
171 /*
172 * Initialize the dedicated SSP unit and disable all chip selects.
173 * This function is called with interrupts disabled.
174 */
175 static void
zssp_init(void)176 zssp_init(void)
177 {
178 struct zssp_softc *sc;
179
180 if (__predict_false(zssp_sc == NULL)) {
181 aprint_error("%s: not configured.\n", __func__);
182 return;
183 }
184 sc = zssp_sc;
185
186 pxa2x0_clkman_config(CKEN_SSP, 1);
187
188 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->lz9jg18.sscr0);
189 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0);
190
191 pxa2x0_gpio_set_function(sc->ads7846.gpio, GPIO_OUT|GPIO_SET);
192 pxa2x0_gpio_set_function(sc->max1111.gpio, GPIO_OUT|GPIO_SET);
193 pxa2x0_gpio_set_function(sc->lz9jg18.gpio, GPIO_OUT|GPIO_SET);
194 }
195
196 static bool
zssp_resume(device_t dv,const pmf_qual_t * qual)197 zssp_resume(device_t dv, const pmf_qual_t *qual)
198 {
199 int s;
200
201 s = splhigh();
202 zssp_init();
203 splx(s);
204
205 return true;
206 }
207
208 /*
209 * Transmit a single data word to one of the ICs, keep the chip selected
210 * afterwards, and don't wait for data to be returned in SSDR. Interrupts
211 * must be held off until zssp_ic_stop() gets called.
212 */
213 void
zssp_ic_start(int ic,uint32_t data)214 zssp_ic_start(int ic, uint32_t data)
215 {
216 struct zssp_softc *sc;
217
218 if (__predict_false(zssp_sc == NULL)) {
219 aprint_error("%s: not configured.\n", __func__);
220 return;
221 }
222 sc = zssp_sc;
223
224 /* disable other ICs */
225 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
226 if (ic != ZSSP_IC_ADS7846)
227 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
228 if (ic != ZSSP_IC_LZ9JG18)
229 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
230 if (ic != ZSSP_IC_MAX1111)
231 pxa2x0_gpio_set_bit(sc->max1111.gpio);
232
233 /* activate the chosen one */
234 switch (ic) {
235 case ZSSP_IC_ADS7846:
236 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
237 sc->ads7846.sscr0);
238 pxa2x0_gpio_clear_bit(sc->ads7846.gpio);
239 delay(1); /* ADS7846 Tcss = 100ns */
240 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data);
241 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
242 & SSSR_TNF) != SSSR_TNF)
243 continue; /* poll */
244 break;
245 case ZSSP_IC_LZ9JG18:
246 pxa2x0_gpio_clear_bit(sc->lz9jg18.gpio);
247 break;
248 case ZSSP_IC_MAX1111:
249 pxa2x0_gpio_clear_bit(sc->max1111.gpio);
250 break;
251 }
252 }
253
254 /*
255 * Read the last value from SSDR and deactivate all chip-selects.
256 */
257 uint32_t
zssp_ic_stop(int ic)258 zssp_ic_stop(int ic)
259 {
260 struct zssp_softc *sc;
261 uint32_t rv;
262
263 if (__predict_false(zssp_sc == NULL)) {
264 aprint_error("%s: not configured.\n", __func__);
265 return 0;
266 }
267 sc = zssp_sc;
268
269 switch (ic) {
270 case ZSSP_IC_ADS7846:
271 /* read result of last command */
272 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
273 & SSSR_RNE) != SSSR_RNE)
274 continue; /* poll */
275 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
276 break;
277 case ZSSP_IC_LZ9JG18:
278 case ZSSP_IC_MAX1111:
279 /* last value received is irrelevant or undefined */
280 default:
281 rv = 0;
282 break;
283 }
284
285 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
286 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
287 pxa2x0_gpio_set_bit(sc->max1111.gpio);
288
289 return rv;
290 }
291
292 /*
293 * Activate one of the chip-select lines, transmit one word value in
294 * each direction, and deactivate the chip-select again.
295 */
296 uint32_t
zssp_ic_send(int ic,uint32_t data)297 zssp_ic_send(int ic, uint32_t data)
298 {
299
300 switch (ic) {
301 case ZSSP_IC_MAX1111:
302 return (zssp_read_max1111(data));
303 case ZSSP_IC_ADS7846:
304 return (zssp_read_ads7846(data));
305 case ZSSP_IC_LZ9JG18:
306 zssp_write_lz9jg18(data);
307 return 0;
308 default:
309 aprint_error("zssp: zssp_ic_send: invalid IC %d\n", ic);
310 return 0;
311 }
312 }
313
314 int
zssp_read_max1111(uint32_t cmd)315 zssp_read_max1111(uint32_t cmd)
316 {
317 struct zssp_softc *sc;
318 int data[3];
319 int voltage[3]; /* voltage[0]: dummy */
320 int i;
321 int s;
322
323 if (__predict_false(zssp_sc == NULL)) {
324 aprint_error("%s: not configured.\n", __func__);
325 return 0;
326 }
327 sc = zssp_sc;
328
329 s = splhigh();
330
331 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
332 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->max1111.sscr0);
333
334 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
335 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
336 pxa2x0_gpio_clear_bit(sc->max1111.gpio);
337
338 delay(1);
339
340 memset(data, 0, sizeof(data));
341 data[0] = cmd;
342 for (i = 0; i < __arraycount(data); i++) {
343 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data[i]);
344 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
345 & SSSR_TNF) != SSSR_TNF)
346 continue; /* poll */
347 /* XXX is this delay necessary? */
348 delay(1);
349 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
350 & SSSR_RNE) != SSSR_RNE)
351 continue; /* poll */
352 voltage[i] = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
353 SSP_SSDR);
354 }
355
356 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
357 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
358 pxa2x0_gpio_set_bit(sc->max1111.gpio);
359
360 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
361
362 splx(s);
363
364 /* XXX no idea what this means, but it's what Linux would do. */
365 if ((voltage[1] & 0xc0) != 0 || (voltage[2] & 0x3f) != 0)
366 return -1;
367 return ((voltage[1] << 2) & 0xfc) | ((voltage[2] >> 6) & 0x03);
368 }
369
370 /* XXX - only does CS_ADS7846 */
371 uint32_t
zssp_read_ads7846(uint32_t cmd)372 zssp_read_ads7846(uint32_t cmd)
373 {
374 struct zssp_softc *sc;
375 uint32_t val;
376 int s;
377
378 if (__predict_false(zssp_sc == NULL)) {
379 aprint_error("%s: not configured\n", __func__);
380 return 0;
381 }
382 sc = zssp_sc;
383
384 s = splhigh();
385
386 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
387 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->ads7846.sscr0);
388
389 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
390 pxa2x0_gpio_set_bit(sc->max1111.gpio);
391 pxa2x0_gpio_clear_bit(sc->ads7846.gpio);
392 delay(1); /* ADS7846 Tcss = 100ns */
393
394 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd);
395
396 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
397 & SSSR_TNF) != SSSR_TNF)
398 continue; /* poll */
399
400 delay(1);
401
402 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
403 & SSSR_RNE) != SSSR_RNE)
404 continue; /* poll */
405
406 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
407
408 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
409
410 splx(s);
411
412 return val;
413 }
414
415 void
zssp_write_lz9jg18(uint32_t data)416 zssp_write_lz9jg18(uint32_t data)
417 {
418 struct zssp_softc *sc;
419 int sclk_fn;
420 int sfrm_fn;
421 int txd_fn;
422 int rxd_fn;
423 int i;
424 int s;
425
426 KASSERT(zssp_sc != NULL);
427 sc = zssp_sc;
428
429 /* XXX this creates a DAC command from a backlight duty value. */
430 data = 0x40 | (data & 0x1f);
431
432 s = splhigh();
433
434 sclk_fn = pxa2x0_gpio_get_function(sc->lz9jg18.sclk_pin);
435 sfrm_fn = pxa2x0_gpio_get_function(sc->lz9jg18.sfrm_pin);
436 txd_fn = pxa2x0_gpio_get_function(sc->lz9jg18.txd_pin);
437 rxd_fn = pxa2x0_gpio_get_function(sc->lz9jg18.rxd_pin);
438
439 pxa2x0_gpio_set_function(sc->lz9jg18.sfrm_pin, GPIO_OUT | GPIO_SET);
440 pxa2x0_gpio_set_function(sc->lz9jg18.sclk_pin, GPIO_OUT | GPIO_CLR);
441 pxa2x0_gpio_set_function(sc->lz9jg18.txd_pin, GPIO_OUT | GPIO_CLR);
442 pxa2x0_gpio_set_function(sc->lz9jg18.rxd_pin, GPIO_IN);
443
444 pxa2x0_gpio_set_bit(sc->max1111.gpio);
445 pxa2x0_gpio_set_bit(sc->ads7846.gpio);
446 pxa2x0_gpio_clear_bit(sc->lz9jg18.gpio);
447
448 delay(10);
449
450 for (i = 0; i < 8; i++) {
451 if (data & 0x80)
452 pxa2x0_gpio_set_bit(sc->lz9jg18.txd_pin);
453 else
454 pxa2x0_gpio_clear_bit(sc->lz9jg18.txd_pin);
455 delay(10);
456 pxa2x0_gpio_set_bit(sc->lz9jg18.sclk_pin);
457 delay(10);
458 pxa2x0_gpio_clear_bit(sc->lz9jg18.sclk_pin);
459 delay(10);
460 data <<= 1;
461 }
462
463 pxa2x0_gpio_clear_bit(sc->lz9jg18.txd_pin);
464 pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
465
466 pxa2x0_gpio_set_function(sc->lz9jg18.sclk_pin, sclk_fn);
467 pxa2x0_gpio_set_function(sc->lz9jg18.sfrm_pin, sfrm_fn);
468 pxa2x0_gpio_set_function(sc->lz9jg18.txd_pin, txd_fn);
469 pxa2x0_gpio_set_function(sc->lz9jg18.rxd_pin, rxd_fn);
470
471 splx(s);
472 }
473