1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include <string.h>
22 #include <limits.h>
23 #include "as.h"
24 #include "sb.h"
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
27 #include "frags.h"
28 #include "subsegs.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
34
35 #ifndef uint32
36 #define uint32 unsigned int
37 #endif
38 #ifndef int32
39 #define int32 signed int
40 #endif
41
42 /* Notes:
43
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
47
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
58
59
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars[] = "#";
62 const char line_comment_chars[] = "#";
63 const char line_separator_chars[] = ";";
64 const char EXP_CHARS[] = "eE";
65 const char FLT_CHARS[] = "rRsSfFdDxXpP";
66
67
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
70
71 bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
72 bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
73
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
76
77 static vliw_insn cur_vinsn;
78
79 unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
80
81 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
82
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
85 back end. */
86 static bfd_boolean past_xtensa_end = FALSE;
87
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
91
92
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
97
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
104
105
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
108
109 typedef struct lit_state_struct
110 {
111 const char *lit_seg_name;
112 const char *lit4_seg_name;
113 const char *init_lit_seg_name;
114 const char *fini_lit_seg_name;
115 segT lit_seg;
116 segT lit4_seg;
117 segT init_lit_seg;
118 segT fini_lit_seg;
119 } lit_state;
120
121 static lit_state default_lit_sections;
122
123
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
127
128 typedef struct seg_list_struct
129 {
130 struct seg_list_struct *next;
131 segT seg;
132 } seg_list;
133
134 static seg_list literal_head_h;
135 static seg_list *literal_head = &literal_head_h;
136 static seg_list init_literal_head_h;
137 static seg_list *init_literal_head = &init_literal_head_h;
138 static seg_list fini_literal_head_h;
139 static seg_list *fini_literal_head = &fini_literal_head_h;
140
141
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
147
148 typedef struct sym_list_struct
149 {
150 struct sym_list_struct *next;
151 symbolS *sym;
152 } sym_list;
153
154 static sym_list *insn_labels = NULL;
155 static sym_list *free_insn_labels = NULL;
156 static sym_list *saved_insn_labels = NULL;
157
158 static sym_list *literal_syms;
159
160
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16 = 0;
164 int prefer_l32r = 0;
165
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals = 0;
168
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
171
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
181
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
193
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 Common usage is
200
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206 */
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223
224
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
235
236 #define XTENSA_PROP_ALIGN 0x00000800
237
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
239
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
245
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247
248
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
254
255 typedef struct frag_flags_struct frag_flags;
256
257 struct frag_flags_struct
258 {
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
262
263 unsigned is_literal : 1;
264 unsigned is_insn : 1;
265 unsigned is_data : 1;
266 unsigned is_unreachable : 1;
267
268 struct
269 {
270 unsigned is_loop_target : 1;
271 unsigned is_branch_target : 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority : 2;
273
274 unsigned is_no_density : 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform : 1;
278
279 unsigned is_no_reorder : 1;
280
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit : 1;
283 } insn;
284 unsigned is_align : 1;
285 unsigned alignment : 5;
286 };
287
288
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
292 {
293 segT sec;
294 bfd_vma offset;
295 size_t size;
296 frag_flags flags;
297 struct xtensa_block_info_struct *next;
298 };
299
300
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
303 {
304 const char *name;
305 segT now_seg;
306 subsegT now_subseg;
307 int generating_literals;
308 } emit_state;
309
310
311 /* Opcode placement information */
312
313 typedef unsigned long long bitfield;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317
318 #define MAX_FORMATS 32
319
320 typedef struct op_placement_info_struct
321 {
322 int num_formats;
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
328 format. */
329 int issuef;
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
332 and their sizes: */
333 xtensa_format single;
334 xtensa_format narrowest;
335 xtensa_format widest;
336 char narrowest_size;
337 char widest_size;
338 char single_size;
339
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
342 bitfield formats;
343
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots[MAX_FORMATS];
347
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format[MAX_FORMATS];
351
352 } op_placement_info, *op_placement_info_table;
353
354 op_placement_info_table op_placement_table;
355
356
357 /* Extra expression types. */
358
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
362
363
364 /* Directives. */
365
366 typedef enum
367 {
368 directive_none = 0,
369 directive_literal,
370 directive_density,
371 directive_transform,
372 directive_freeregs,
373 directive_longcalls,
374 directive_literal_prefix,
375 directive_schedule,
376 directive_absolute_literals,
377 directive_last_directive
378 } directiveE;
379
380 typedef struct
381 {
382 const char *name;
383 bfd_boolean can_be_negated;
384 } directive_infoS;
385
386 const directive_infoS directive_info[] =
387 {
388 { "none", FALSE },
389 { "literal", FALSE },
390 { "density", TRUE },
391 { "transform", TRUE },
392 { "freeregs", FALSE },
393 { "longcalls", TRUE },
394 { "literal_prefix", FALSE },
395 { "schedule", TRUE },
396 { "absolute-literals", TRUE }
397 };
398
399 bfd_boolean directive_state[] =
400 {
401 FALSE, /* none */
402 FALSE, /* literal */
403 #if !XCHAL_HAVE_DENSITY
404 FALSE, /* density */
405 #else
406 TRUE, /* density */
407 #endif
408 TRUE, /* transform */
409 FALSE, /* freeregs */
410 FALSE, /* longcalls */
411 FALSE, /* literal_prefix */
412 TRUE, /* schedule */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE /* absolute_literals */
415 #else
416 FALSE /* absolute_literals */
417 #endif
418 };
419
420
421 /* Directive functions. */
422
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
431
432 /* Parsing and Idiom Translation. */
433
434 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
435
436 /* Various Other Internal Functions. */
437
438 extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
439 static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
440 static void xtensa_mark_literal_pool_location (void);
441 static addressT get_expanded_loop_offset (xtensa_opcode);
442 static fragS *get_literal_pool_location (segT);
443 static void set_literal_pool_location (segT, fragS *);
444 static void xtensa_set_frag_assembly_state (fragS *);
445 static void finish_vinsn (vliw_insn *);
446 static bfd_boolean emit_single_op (TInsn *);
447 static int total_frag_text_expansion (fragS *);
448
449 /* Alignment Functions. */
450
451 static int get_text_align_power (unsigned);
452 static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
453 static int branch_align_power (segT);
454
455 /* Helpers for xtensa_relax_frag(). */
456
457 static long relax_frag_add_nop (fragS *);
458
459 /* Accessors for additional per-subsegment information. */
460
461 static unsigned get_last_insn_flags (segT, subsegT);
462 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
463 static float get_subseg_total_freq (segT, subsegT);
464 static float get_subseg_target_freq (segT, subsegT);
465 static void set_subseg_freq (segT, subsegT, float, float);
466
467 /* Segment list functions. */
468
469 static void xtensa_move_literals (void);
470 static void xtensa_reorder_segments (void);
471 static void xtensa_switch_to_literal_fragment (emit_state *);
472 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
473 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
474 static void xtensa_restore_emit_state (emit_state *);
475 static void cache_literal_section
476 (seg_list *, const char *, segT *, bfd_boolean);
477
478 /* Import from elf32-xtensa.c in BFD library. */
479
480 extern char *xtensa_get_property_section_name (asection *, const char *);
481
482 /* op_placement_info functions. */
483
484 static void init_op_placement_info_table (void);
485 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
486 static int xg_get_single_size (xtensa_opcode);
487 static xtensa_format xg_get_single_format (xtensa_opcode);
488
489 /* TInsn and IStack functions. */
490
491 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
492 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
493 static bfd_boolean tinsn_has_complex_operands (const TInsn *);
494 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
495 static bfd_boolean tinsn_check_arguments (const TInsn *);
496 static void tinsn_from_chars (TInsn *, char *, int);
497 static void tinsn_immed_from_frag (TInsn *, fragS *, int);
498 static int get_num_stack_text_bytes (IStack *);
499 static int get_num_stack_literal_bytes (IStack *);
500
501 /* vliw_insn functions. */
502
503 static void xg_init_vinsn (vliw_insn *);
504 static void xg_clear_vinsn (vliw_insn *);
505 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
506 static void xg_free_vinsn (vliw_insn *);
507 static bfd_boolean vinsn_to_insnbuf
508 (vliw_insn *, char *, fragS *, bfd_boolean);
509 static void vinsn_from_chars (vliw_insn *, char *);
510
511 /* Expression Utilities. */
512
513 bfd_boolean expr_is_const (const expressionS *);
514 offsetT get_expr_const (const expressionS *);
515 void set_expr_const (expressionS *, offsetT);
516 bfd_boolean expr_is_register (const expressionS *);
517 offsetT get_expr_register (const expressionS *);
518 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
519 static void set_expr_symbol_offset_diff
520 (expressionS *, symbolS *, symbolS *, offsetT);
521 bfd_boolean expr_is_equal (expressionS *, expressionS *);
522 static void copy_expr (expressionS *, const expressionS *);
523
524 /* Section renaming. */
525
526 static void build_section_rename (const char *);
527
528
529 /* ISA imported from bfd. */
530 extern xtensa_isa xtensa_default_isa;
531
532 extern int target_big_endian;
533
534 static xtensa_opcode xtensa_addi_opcode;
535 static xtensa_opcode xtensa_addmi_opcode;
536 static xtensa_opcode xtensa_call0_opcode;
537 static xtensa_opcode xtensa_call4_opcode;
538 static xtensa_opcode xtensa_call8_opcode;
539 static xtensa_opcode xtensa_call12_opcode;
540 static xtensa_opcode xtensa_callx0_opcode;
541 static xtensa_opcode xtensa_callx4_opcode;
542 static xtensa_opcode xtensa_callx8_opcode;
543 static xtensa_opcode xtensa_callx12_opcode;
544 static xtensa_opcode xtensa_const16_opcode;
545 static xtensa_opcode xtensa_entry_opcode;
546 static xtensa_opcode xtensa_movi_opcode;
547 static xtensa_opcode xtensa_movi_n_opcode;
548 static xtensa_opcode xtensa_isync_opcode;
549 static xtensa_opcode xtensa_jx_opcode;
550 static xtensa_opcode xtensa_l32r_opcode;
551 static xtensa_opcode xtensa_loop_opcode;
552 static xtensa_opcode xtensa_loopnez_opcode;
553 static xtensa_opcode xtensa_loopgtz_opcode;
554 static xtensa_opcode xtensa_nop_opcode;
555 static xtensa_opcode xtensa_nop_n_opcode;
556 static xtensa_opcode xtensa_or_opcode;
557 static xtensa_opcode xtensa_ret_opcode;
558 static xtensa_opcode xtensa_ret_n_opcode;
559 static xtensa_opcode xtensa_retw_opcode;
560 static xtensa_opcode xtensa_retw_n_opcode;
561 static xtensa_opcode xtensa_rsr_lcount_opcode;
562 static xtensa_opcode xtensa_waiti_opcode;
563
564
565 /* Command-line Options. */
566
567 bfd_boolean use_literal_section = TRUE;
568 static bfd_boolean align_targets = TRUE;
569 static bfd_boolean warn_unaligned_branch_targets = FALSE;
570 static bfd_boolean has_a0_b_retw = FALSE;
571 static bfd_boolean workaround_a0_b_retw = FALSE;
572 static bfd_boolean workaround_b_j_loop_end = FALSE;
573 static bfd_boolean workaround_short_loop = FALSE;
574 static bfd_boolean maybe_has_short_loop = FALSE;
575 static bfd_boolean workaround_close_loop_end = FALSE;
576 static bfd_boolean maybe_has_close_loop_end = FALSE;
577
578 /* When workaround_short_loops is TRUE, all loops with early exits must
579 have at least 3 instructions. workaround_all_short_loops is a modifier
580 to the workaround_short_loop flag. In addition to the
581 workaround_short_loop actions, all straightline loopgtz and loopnez
582 must have at least 3 instructions. */
583
584 static bfd_boolean workaround_all_short_loops = FALSE;
585
586
587 static void
xtensa_setup_hw_workarounds(int earliest,int latest)588 xtensa_setup_hw_workarounds (int earliest, int latest)
589 {
590 if (earliest > latest)
591 as_fatal (_("illegal range of target hardware versions"));
592
593 /* Enable all workarounds for pre-T1050.0 hardware. */
594 if (earliest < 105000 || latest < 105000)
595 {
596 workaround_a0_b_retw |= TRUE;
597 workaround_b_j_loop_end |= TRUE;
598 workaround_short_loop |= TRUE;
599 workaround_close_loop_end |= TRUE;
600 workaround_all_short_loops |= TRUE;
601 }
602 }
603
604
605 enum
606 {
607 option_density = OPTION_MD_BASE,
608 option_no_density,
609
610 option_relax,
611 option_no_relax,
612
613 option_link_relax,
614 option_no_link_relax,
615
616 option_generics,
617 option_no_generics,
618
619 option_transform,
620 option_no_transform,
621
622 option_text_section_literals,
623 option_no_text_section_literals,
624
625 option_absolute_literals,
626 option_no_absolute_literals,
627
628 option_align_targets,
629 option_no_align_targets,
630
631 option_warn_unaligned_targets,
632
633 option_longcalls,
634 option_no_longcalls,
635
636 option_workaround_a0_b_retw,
637 option_no_workaround_a0_b_retw,
638
639 option_workaround_b_j_loop_end,
640 option_no_workaround_b_j_loop_end,
641
642 option_workaround_short_loop,
643 option_no_workaround_short_loop,
644
645 option_workaround_all_short_loops,
646 option_no_workaround_all_short_loops,
647
648 option_workaround_close_loop_end,
649 option_no_workaround_close_loop_end,
650
651 option_no_workarounds,
652
653 option_rename_section_name,
654
655 option_prefer_l32r,
656 option_prefer_const16,
657
658 option_target_hardware
659 };
660
661 const char *md_shortopts = "";
662
663 struct option md_longopts[] =
664 {
665 { "density", no_argument, NULL, option_density },
666 { "no-density", no_argument, NULL, option_no_density },
667
668 /* Both "relax" and "generics" are deprecated and treated as equivalent
669 to the "transform" option. */
670 { "relax", no_argument, NULL, option_relax },
671 { "no-relax", no_argument, NULL, option_no_relax },
672 { "generics", no_argument, NULL, option_generics },
673 { "no-generics", no_argument, NULL, option_no_generics },
674
675 { "transform", no_argument, NULL, option_transform },
676 { "no-transform", no_argument, NULL, option_no_transform },
677 { "text-section-literals", no_argument, NULL, option_text_section_literals },
678 { "no-text-section-literals", no_argument, NULL,
679 option_no_text_section_literals },
680 { "absolute-literals", no_argument, NULL, option_absolute_literals },
681 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
682 /* This option was changed from -align-target to -target-align
683 because it conflicted with the "-al" option. */
684 { "target-align", no_argument, NULL, option_align_targets },
685 { "no-target-align", no_argument, NULL, option_no_align_targets },
686 { "warn-unaligned-targets", no_argument, NULL,
687 option_warn_unaligned_targets },
688 { "longcalls", no_argument, NULL, option_longcalls },
689 { "no-longcalls", no_argument, NULL, option_no_longcalls },
690
691 { "no-workaround-a0-b-retw", no_argument, NULL,
692 option_no_workaround_a0_b_retw },
693 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
694
695 { "no-workaround-b-j-loop-end", no_argument, NULL,
696 option_no_workaround_b_j_loop_end },
697 { "workaround-b-j-loop-end", no_argument, NULL,
698 option_workaround_b_j_loop_end },
699
700 { "no-workaround-short-loops", no_argument, NULL,
701 option_no_workaround_short_loop },
702 { "workaround-short-loops", no_argument, NULL,
703 option_workaround_short_loop },
704
705 { "no-workaround-all-short-loops", no_argument, NULL,
706 option_no_workaround_all_short_loops },
707 { "workaround-all-short-loop", no_argument, NULL,
708 option_workaround_all_short_loops },
709
710 { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
711 { "prefer-const16", no_argument, NULL, option_prefer_const16 },
712
713 { "no-workarounds", no_argument, NULL, option_no_workarounds },
714
715 { "no-workaround-close-loop-end", no_argument, NULL,
716 option_no_workaround_close_loop_end },
717 { "workaround-close-loop-end", no_argument, NULL,
718 option_workaround_close_loop_end },
719
720 { "rename-section", required_argument, NULL, option_rename_section_name },
721
722 { "link-relax", no_argument, NULL, option_link_relax },
723 { "no-link-relax", no_argument, NULL, option_no_link_relax },
724
725 { "target-hardware", required_argument, NULL, option_target_hardware },
726
727 { NULL, no_argument, NULL, 0 }
728 };
729
730 size_t md_longopts_size = sizeof md_longopts;
731
732
733 int
md_parse_option(int c,char * arg)734 md_parse_option (int c, char *arg)
735 {
736 switch (c)
737 {
738 case option_density:
739 as_warn (_("--density option is ignored"));
740 return 1;
741 case option_no_density:
742 as_warn (_("--no-density option is ignored"));
743 return 1;
744 case option_link_relax:
745 linkrelax = 1;
746 return 1;
747 case option_no_link_relax:
748 linkrelax = 0;
749 return 1;
750 case option_generics:
751 as_warn (_("--generics is deprecated; use --transform instead"));
752 return md_parse_option (option_transform, arg);
753 case option_no_generics:
754 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
755 return md_parse_option (option_no_transform, arg);
756 case option_relax:
757 as_warn (_("--relax is deprecated; use --transform instead"));
758 return md_parse_option (option_transform, arg);
759 case option_no_relax:
760 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
761 return md_parse_option (option_no_transform, arg);
762 case option_longcalls:
763 directive_state[directive_longcalls] = TRUE;
764 return 1;
765 case option_no_longcalls:
766 directive_state[directive_longcalls] = FALSE;
767 return 1;
768 case option_text_section_literals:
769 use_literal_section = FALSE;
770 return 1;
771 case option_no_text_section_literals:
772 use_literal_section = TRUE;
773 return 1;
774 case option_absolute_literals:
775 if (!absolute_literals_supported)
776 {
777 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
778 return 0;
779 }
780 directive_state[directive_absolute_literals] = TRUE;
781 return 1;
782 case option_no_absolute_literals:
783 directive_state[directive_absolute_literals] = FALSE;
784 return 1;
785
786 case option_workaround_a0_b_retw:
787 workaround_a0_b_retw = TRUE;
788 return 1;
789 case option_no_workaround_a0_b_retw:
790 workaround_a0_b_retw = FALSE;
791 return 1;
792 case option_workaround_b_j_loop_end:
793 workaround_b_j_loop_end = TRUE;
794 return 1;
795 case option_no_workaround_b_j_loop_end:
796 workaround_b_j_loop_end = FALSE;
797 return 1;
798
799 case option_workaround_short_loop:
800 workaround_short_loop = TRUE;
801 return 1;
802 case option_no_workaround_short_loop:
803 workaround_short_loop = FALSE;
804 return 1;
805
806 case option_workaround_all_short_loops:
807 workaround_all_short_loops = TRUE;
808 return 1;
809 case option_no_workaround_all_short_loops:
810 workaround_all_short_loops = FALSE;
811 return 1;
812
813 case option_workaround_close_loop_end:
814 workaround_close_loop_end = TRUE;
815 return 1;
816 case option_no_workaround_close_loop_end:
817 workaround_close_loop_end = FALSE;
818 return 1;
819
820 case option_no_workarounds:
821 workaround_a0_b_retw = FALSE;
822 workaround_b_j_loop_end = FALSE;
823 workaround_short_loop = FALSE;
824 workaround_all_short_loops = FALSE;
825 workaround_close_loop_end = FALSE;
826 return 1;
827
828 case option_align_targets:
829 align_targets = TRUE;
830 return 1;
831 case option_no_align_targets:
832 align_targets = FALSE;
833 return 1;
834
835 case option_warn_unaligned_targets:
836 warn_unaligned_branch_targets = TRUE;
837 return 1;
838
839 case option_rename_section_name:
840 build_section_rename (arg);
841 return 1;
842
843 case 'Q':
844 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
845 should be emitted or not. FIXME: Not implemented. */
846 return 1;
847
848 case option_prefer_l32r:
849 if (prefer_const16)
850 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
851 prefer_l32r = 1;
852 return 1;
853
854 case option_prefer_const16:
855 if (prefer_l32r)
856 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
857 prefer_const16 = 1;
858 return 1;
859
860 case option_target_hardware:
861 {
862 int earliest, latest = 0;
863 if (*arg == 0 || *arg == '-')
864 as_fatal (_("invalid target hardware version"));
865
866 earliest = strtol (arg, &arg, 0);
867
868 if (*arg == 0)
869 latest = earliest;
870 else if (*arg == '-')
871 {
872 if (*++arg == 0)
873 as_fatal (_("invalid target hardware version"));
874 latest = strtol (arg, &arg, 0);
875 }
876 if (*arg != 0)
877 as_fatal (_("invalid target hardware version"));
878
879 xtensa_setup_hw_workarounds (earliest, latest);
880 return 1;
881 }
882
883 case option_transform:
884 /* This option has no affect other than to use the defaults,
885 which are already set. */
886 return 1;
887
888 case option_no_transform:
889 /* This option turns off all transformations of any kind.
890 However, because we want to preserve the state of other
891 directives, we only change its own field. Thus, before
892 you perform any transformation, always check if transform
893 is available. If you use the functions we provide for this
894 purpose, you will be ok. */
895 directive_state[directive_transform] = FALSE;
896 return 1;
897
898 default:
899 return 0;
900 }
901 }
902
903
904 void
md_show_usage(FILE * stream)905 md_show_usage (FILE *stream)
906 {
907 fputs ("\n\
908 Xtensa options:\n\
909 --[no-]text-section-literals\n\
910 [Do not] put literals in the text section\n\
911 --[no-]absolute-literals\n\
912 [Do not] default to use non-PC-relative literals\n\
913 --[no-]target-align [Do not] try to align branch targets\n\
914 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
915 --[no-]transform [Do not] transform instructions\n\
916 --rename-section old=new Rename section 'old' to 'new'\n", stream);
917 }
918
919
920 /* Functions related to the list of current label symbols. */
921
922 static void
xtensa_add_insn_label(symbolS * sym)923 xtensa_add_insn_label (symbolS *sym)
924 {
925 sym_list *l;
926
927 if (!free_insn_labels)
928 l = (sym_list *) xmalloc (sizeof (sym_list));
929 else
930 {
931 l = free_insn_labels;
932 free_insn_labels = l->next;
933 }
934
935 l->sym = sym;
936 l->next = insn_labels;
937 insn_labels = l;
938 }
939
940
941 static void
xtensa_clear_insn_labels(void)942 xtensa_clear_insn_labels (void)
943 {
944 sym_list **pl;
945
946 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
947 ;
948 *pl = insn_labels;
949 insn_labels = NULL;
950 }
951
952
953 /* The "loops_ok" argument is provided to allow ignoring labels that
954 define loop ends. This fixes a bug where the NOPs to align a
955 loop opcode were included in a previous zero-cost loop:
956
957 loop a0, loopend
958 <loop1 body>
959 loopend:
960
961 loop a2, loopend2
962 <loop2 body>
963
964 would become:
965
966 loop a0, loopend
967 <loop1 body>
968 nop.n <===== bad!
969 loopend:
970
971 loop a2, loopend2
972 <loop2 body>
973
974 This argument is used to prevent moving the NOP to before the
975 loop-end label, which is what you want in this special case. */
976
977 static void
xtensa_move_labels(fragS * new_frag,valueT new_offset,bfd_boolean loops_ok)978 xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok)
979 {
980 sym_list *lit;
981
982 for (lit = insn_labels; lit; lit = lit->next)
983 {
984 symbolS *lit_sym = lit->sym;
985 if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target)
986 {
987 S_SET_VALUE (lit_sym, new_offset);
988 symbol_set_frag (lit_sym, new_frag);
989 }
990 }
991 }
992
993
994 /* Directive data and functions. */
995
996 typedef struct state_stackS_struct
997 {
998 directiveE directive;
999 bfd_boolean negated;
1000 bfd_boolean old_state;
1001 const char *file;
1002 unsigned int line;
1003 const void *datum;
1004 struct state_stackS_struct *prev;
1005 } state_stackS;
1006
1007 state_stackS *directive_state_stack;
1008
1009 const pseudo_typeS md_pseudo_table[] =
1010 {
1011 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
1012 { "literal_position", xtensa_literal_position, 0 },
1013 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */
1014 { "long", xtensa_elf_cons, 4 },
1015 { "word", xtensa_elf_cons, 4 },
1016 { "short", xtensa_elf_cons, 2 },
1017 { "begin", xtensa_begin_directive, 0 },
1018 { "end", xtensa_end_directive, 0 },
1019 { "loc", xtensa_dwarf2_directive_loc, 0 },
1020 { "literal", xtensa_literal_pseudo, 0 },
1021 { "frequency", xtensa_frequency_pseudo, 0 },
1022 { NULL, 0, 0 },
1023 };
1024
1025
1026 static bfd_boolean
use_transform(void)1027 use_transform (void)
1028 {
1029 /* After md_end, you should be checking frag by frag, rather
1030 than state directives. */
1031 assert (!past_xtensa_end);
1032 return directive_state[directive_transform];
1033 }
1034
1035
1036 static bfd_boolean
do_align_targets(void)1037 do_align_targets (void)
1038 {
1039 /* Do not use this function after md_end; just look at align_targets
1040 instead. There is no target-align directive, so alignment is either
1041 enabled for all frags or not done at all. */
1042 assert (!past_xtensa_end);
1043 return align_targets && use_transform ();
1044 }
1045
1046
1047 static void
directive_push(directiveE directive,bfd_boolean negated,const void * datum)1048 directive_push (directiveE directive, bfd_boolean negated, const void *datum)
1049 {
1050 char *file;
1051 unsigned int line;
1052 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS));
1053
1054 as_where (&file, &line);
1055
1056 stack->directive = directive;
1057 stack->negated = negated;
1058 stack->old_state = directive_state[directive];
1059 stack->file = file;
1060 stack->line = line;
1061 stack->datum = datum;
1062 stack->prev = directive_state_stack;
1063 directive_state_stack = stack;
1064
1065 directive_state[directive] = !negated;
1066 }
1067
1068
1069 static void
directive_pop(directiveE * directive,bfd_boolean * negated,const char ** file,unsigned int * line,const void ** datum)1070 directive_pop (directiveE *directive,
1071 bfd_boolean *negated,
1072 const char **file,
1073 unsigned int *line,
1074 const void **datum)
1075 {
1076 state_stackS *top = directive_state_stack;
1077
1078 if (!directive_state_stack)
1079 {
1080 as_bad (_("unmatched end directive"));
1081 *directive = directive_none;
1082 return;
1083 }
1084
1085 directive_state[directive_state_stack->directive] = top->old_state;
1086 *directive = top->directive;
1087 *negated = top->negated;
1088 *file = top->file;
1089 *line = top->line;
1090 *datum = top->datum;
1091 directive_state_stack = top->prev;
1092 free (top);
1093 }
1094
1095
1096 static void
directive_balance(void)1097 directive_balance (void)
1098 {
1099 while (directive_state_stack)
1100 {
1101 directiveE directive;
1102 bfd_boolean negated;
1103 const char *file;
1104 unsigned int line;
1105 const void *datum;
1106
1107 directive_pop (&directive, &negated, &file, &line, &datum);
1108 as_warn_where ((char *) file, line,
1109 _(".begin directive with no matching .end directive"));
1110 }
1111 }
1112
1113
1114 static bfd_boolean
inside_directive(directiveE dir)1115 inside_directive (directiveE dir)
1116 {
1117 state_stackS *top = directive_state_stack;
1118
1119 while (top && top->directive != dir)
1120 top = top->prev;
1121
1122 return (top != NULL);
1123 }
1124
1125
1126 static void
get_directive(directiveE * directive,bfd_boolean * negated)1127 get_directive (directiveE *directive, bfd_boolean *negated)
1128 {
1129 int len;
1130 unsigned i;
1131 char *directive_string;
1132
1133 if (strncmp (input_line_pointer, "no-", 3) != 0)
1134 *negated = FALSE;
1135 else
1136 {
1137 *negated = TRUE;
1138 input_line_pointer += 3;
1139 }
1140
1141 len = strspn (input_line_pointer,
1142 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1143
1144 /* This code is a hack to make .begin [no-][generics|relax] exactly
1145 equivalent to .begin [no-]transform. We should remove it when
1146 we stop accepting those options. */
1147
1148 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1149 {
1150 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1151 directive_string = "transform";
1152 }
1153 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1154 {
1155 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1156 directive_string = "transform";
1157 }
1158 else
1159 directive_string = input_line_pointer;
1160
1161 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1162 {
1163 if (strncmp (directive_string, directive_info[i].name, len) == 0)
1164 {
1165 input_line_pointer += len;
1166 *directive = (directiveE) i;
1167 if (*negated && !directive_info[i].can_be_negated)
1168 as_bad (_("directive %s cannot be negated"),
1169 directive_info[i].name);
1170 return;
1171 }
1172 }
1173
1174 as_bad (_("unknown directive"));
1175 *directive = (directiveE) XTENSA_UNDEFINED;
1176 }
1177
1178
1179 static void
xtensa_begin_directive(int ignore ATTRIBUTE_UNUSED)1180 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
1181 {
1182 directiveE directive;
1183 bfd_boolean negated;
1184 emit_state *state;
1185 int len;
1186 lit_state *ls;
1187
1188 get_directive (&directive, &negated);
1189 if (directive == (directiveE) XTENSA_UNDEFINED)
1190 {
1191 discard_rest_of_line ();
1192 return;
1193 }
1194
1195 if (cur_vinsn.inside_bundle)
1196 as_bad (_("directives are not valid inside bundles"));
1197
1198 switch (directive)
1199 {
1200 case directive_literal:
1201 if (!inside_directive (directive_literal))
1202 {
1203 /* Previous labels go with whatever follows this directive, not with
1204 the literal, so save them now. */
1205 saved_insn_labels = insn_labels;
1206 insn_labels = NULL;
1207 }
1208 as_warn (_(".begin literal is deprecated; use .literal instead"));
1209 state = (emit_state *) xmalloc (sizeof (emit_state));
1210 xtensa_switch_to_literal_fragment (state);
1211 directive_push (directive_literal, negated, state);
1212 break;
1213
1214 case directive_literal_prefix:
1215 /* Have to flush pending output because a movi relaxed to an l32r
1216 might produce a literal. */
1217 md_flush_pending_output ();
1218 /* Check to see if the current fragment is a literal
1219 fragment. If it is, then this operation is not allowed. */
1220 if (generating_literals)
1221 {
1222 as_bad (_("cannot set literal_prefix inside literal fragment"));
1223 return;
1224 }
1225
1226 /* Allocate the literal state for this section and push
1227 onto the directive stack. */
1228 ls = xmalloc (sizeof (lit_state));
1229 assert (ls);
1230
1231 *ls = default_lit_sections;
1232
1233 directive_push (directive_literal_prefix, negated, ls);
1234
1235 /* Parse the new prefix from the input_line_pointer. */
1236 SKIP_WHITESPACE ();
1237 len = strspn (input_line_pointer,
1238 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1239 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1240
1241 /* Process the new prefix. */
1242 xtensa_literal_prefix (input_line_pointer, len);
1243
1244 /* Skip the name in the input line. */
1245 input_line_pointer += len;
1246 break;
1247
1248 case directive_freeregs:
1249 /* This information is currently unused, but we'll accept the statement
1250 and just discard the rest of the line. This won't check the syntax,
1251 but it will accept every correct freeregs directive. */
1252 input_line_pointer += strcspn (input_line_pointer, "\n");
1253 directive_push (directive_freeregs, negated, 0);
1254 break;
1255
1256 case directive_schedule:
1257 md_flush_pending_output ();
1258 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1259 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1260 directive_push (directive_schedule, negated, 0);
1261 xtensa_set_frag_assembly_state (frag_now);
1262 break;
1263
1264 case directive_density:
1265 as_warn (_(".begin [no-]density is ignored"));
1266 break;
1267
1268 case directive_absolute_literals:
1269 md_flush_pending_output ();
1270 if (!absolute_literals_supported && !negated)
1271 {
1272 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1273 break;
1274 }
1275 xtensa_set_frag_assembly_state (frag_now);
1276 directive_push (directive, negated, 0);
1277 break;
1278
1279 default:
1280 md_flush_pending_output ();
1281 xtensa_set_frag_assembly_state (frag_now);
1282 directive_push (directive, negated, 0);
1283 break;
1284 }
1285
1286 demand_empty_rest_of_line ();
1287 }
1288
1289
1290 static void
xtensa_end_directive(int ignore ATTRIBUTE_UNUSED)1291 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
1292 {
1293 directiveE begin_directive, end_directive;
1294 bfd_boolean begin_negated, end_negated;
1295 const char *file;
1296 unsigned int line;
1297 emit_state *state;
1298 emit_state **state_ptr;
1299 lit_state *s;
1300
1301 if (cur_vinsn.inside_bundle)
1302 as_bad (_("directives are not valid inside bundles"));
1303
1304 get_directive (&end_directive, &end_negated);
1305
1306 md_flush_pending_output ();
1307
1308 switch (end_directive)
1309 {
1310 case (directiveE) XTENSA_UNDEFINED:
1311 discard_rest_of_line ();
1312 return;
1313
1314 case directive_density:
1315 as_warn (_(".end [no-]density is ignored"));
1316 demand_empty_rest_of_line ();
1317 break;
1318
1319 case directive_absolute_literals:
1320 if (!absolute_literals_supported && !end_negated)
1321 {
1322 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1323 demand_empty_rest_of_line ();
1324 return;
1325 }
1326 break;
1327
1328 default:
1329 break;
1330 }
1331
1332 state_ptr = &state; /* use state_ptr to avoid type-punning warning */
1333 directive_pop (&begin_directive, &begin_negated, &file, &line,
1334 (const void **) state_ptr);
1335
1336 if (begin_directive != directive_none)
1337 {
1338 if (begin_directive != end_directive || begin_negated != end_negated)
1339 {
1340 as_bad (_("does not match begin %s%s at %s:%d"),
1341 begin_negated ? "no-" : "",
1342 directive_info[begin_directive].name, file, line);
1343 }
1344 else
1345 {
1346 switch (end_directive)
1347 {
1348 case directive_literal:
1349 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1350 xtensa_restore_emit_state (state);
1351 xtensa_set_frag_assembly_state (frag_now);
1352 free (state);
1353 if (!inside_directive (directive_literal))
1354 {
1355 /* Restore the list of current labels. */
1356 xtensa_clear_insn_labels ();
1357 insn_labels = saved_insn_labels;
1358 }
1359 break;
1360
1361 case directive_literal_prefix:
1362 /* Restore the default collection sections from saved state. */
1363 s = (lit_state *) state;
1364 assert (s);
1365
1366 if (use_literal_section)
1367 default_lit_sections = *s;
1368
1369 /* free the state storage */
1370 free (s);
1371 break;
1372
1373 case directive_schedule:
1374 case directive_freeregs:
1375 break;
1376
1377 default:
1378 xtensa_set_frag_assembly_state (frag_now);
1379 break;
1380 }
1381 }
1382 }
1383
1384 demand_empty_rest_of_line ();
1385 }
1386
1387
1388 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1389
1390 static bfd_boolean xtensa_loc_directive_seen = FALSE;
1391
1392 static void
xtensa_dwarf2_directive_loc(int x)1393 xtensa_dwarf2_directive_loc (int x)
1394 {
1395 xtensa_loc_directive_seen = TRUE;
1396 dwarf2_directive_loc (x);
1397 }
1398
1399
1400 static void
xtensa_dwarf2_emit_insn(int size,struct dwarf2_line_info * loc)1401 xtensa_dwarf2_emit_insn (int size, struct dwarf2_line_info *loc)
1402 {
1403 if (debug_type != DEBUG_DWARF2 && ! xtensa_loc_directive_seen)
1404 return;
1405 xtensa_loc_directive_seen = FALSE;
1406 dwarf2_gen_line_info (frag_now_fix () - size, loc);
1407 }
1408
1409
1410 /* Place an aligned literal fragment at the current location. */
1411
1412 static void
xtensa_literal_position(int ignore ATTRIBUTE_UNUSED)1413 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
1414 {
1415 md_flush_pending_output ();
1416
1417 if (inside_directive (directive_literal))
1418 as_warn (_(".literal_position inside literal directive; ignoring"));
1419 xtensa_mark_literal_pool_location ();
1420
1421 demand_empty_rest_of_line ();
1422 xtensa_clear_insn_labels ();
1423 }
1424
1425
1426 /* Support .literal label, expr, ... */
1427
1428 static void
xtensa_literal_pseudo(int ignored ATTRIBUTE_UNUSED)1429 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
1430 {
1431 emit_state state;
1432 char *p, *base_name;
1433 char c;
1434 segT dest_seg;
1435
1436 if (inside_directive (directive_literal))
1437 {
1438 as_bad (_(".literal not allowed inside .begin literal region"));
1439 ignore_rest_of_line ();
1440 return;
1441 }
1442
1443 md_flush_pending_output ();
1444
1445 /* Previous labels go with whatever follows this directive, not with
1446 the literal, so save them now. */
1447 saved_insn_labels = insn_labels;
1448 insn_labels = NULL;
1449
1450 /* If we are using text-section literals, then this is the right value... */
1451 dest_seg = now_seg;
1452
1453 base_name = input_line_pointer;
1454
1455 xtensa_switch_to_literal_fragment (&state);
1456
1457 /* ...but if we aren't using text-section-literals, then we
1458 need to put them in the section we just switched to. */
1459 if (use_literal_section || directive_state[directive_absolute_literals])
1460 dest_seg = now_seg;
1461
1462 /* All literals are aligned to four-byte boundaries. */
1463 frag_align (2, 0, 0);
1464 record_alignment (now_seg, 2);
1465
1466 c = get_symbol_end ();
1467 /* Just after name is now '\0'. */
1468 p = input_line_pointer;
1469 *p = c;
1470 SKIP_WHITESPACE ();
1471
1472 if (*input_line_pointer != ',' && *input_line_pointer != ':')
1473 {
1474 as_bad (_("expected comma or colon after symbol name; "
1475 "rest of line ignored"));
1476 ignore_rest_of_line ();
1477 xtensa_restore_emit_state (&state);
1478 return;
1479 }
1480 *p = 0;
1481
1482 colon (base_name);
1483
1484 *p = c;
1485 input_line_pointer++; /* skip ',' or ':' */
1486
1487 xtensa_elf_cons (4);
1488
1489 xtensa_restore_emit_state (&state);
1490
1491 /* Restore the list of current labels. */
1492 xtensa_clear_insn_labels ();
1493 insn_labels = saved_insn_labels;
1494 }
1495
1496
1497 static void
xtensa_literal_prefix(char const * start,int len)1498 xtensa_literal_prefix (char const *start, int len)
1499 {
1500 char *name, *linkonce_suffix;
1501 char *newname, *newname4;
1502 size_t linkonce_len;
1503
1504 /* Get a null-terminated copy of the name. */
1505 name = xmalloc (len + 1);
1506 assert (name);
1507
1508 strncpy (name, start, len);
1509 name[len] = 0;
1510
1511 /* Allocate the sections (interesting note: the memory pointing to
1512 the name is actually used for the name by the new section). */
1513
1514 newname = xmalloc (len + strlen (".literal") + 1);
1515 newname4 = xmalloc (len + strlen (".lit4") + 1);
1516
1517 linkonce_len = sizeof (".gnu.linkonce.") - 1;
1518 if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0
1519 && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0)
1520 {
1521 strcpy (newname, ".gnu.linkonce.literal");
1522 strcpy (newname4, ".gnu.linkonce.lit4");
1523
1524 strcat (newname, linkonce_suffix);
1525 strcat (newname4, linkonce_suffix);
1526 }
1527 else
1528 {
1529 int suffix_pos = len;
1530
1531 /* If the section name ends with ".text", then replace that suffix
1532 instead of appending an additional suffix. */
1533 if (len >= 5 && strcmp (name + len - 5, ".text") == 0)
1534 suffix_pos -= 5;
1535
1536 strcpy (newname, name);
1537 strcpy (newname4, name);
1538
1539 strcpy (newname + suffix_pos, ".literal");
1540 strcpy (newname4 + suffix_pos, ".lit4");
1541 }
1542
1543 /* Note that cache_literal_section does not create a segment if
1544 it already exists. */
1545 default_lit_sections.lit_seg = NULL;
1546 default_lit_sections.lit4_seg = NULL;
1547
1548 /* Canonicalizing section names allows renaming literal
1549 sections to occur correctly. */
1550 default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname);
1551 default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4);
1552
1553 free (name);
1554 }
1555
1556
1557 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1558
1559 static void
xtensa_frequency_pseudo(int ignored ATTRIBUTE_UNUSED)1560 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
1561 {
1562 float fall_through_f, target_f;
1563
1564 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1565 if (fall_through_f < 0)
1566 {
1567 as_bad (_("fall through frequency must be greater than 0"));
1568 ignore_rest_of_line ();
1569 return;
1570 }
1571
1572 target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1573 if (target_f < 0)
1574 {
1575 as_bad (_("branch target frequency must be greater than 0"));
1576 ignore_rest_of_line ();
1577 return;
1578 }
1579
1580 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
1581
1582 demand_empty_rest_of_line ();
1583 }
1584
1585
1586 /* Like normal .long/.short/.word, except support @plt, etc.
1587 Clobbers input_line_pointer, checks end-of-line. */
1588
1589 static void
xtensa_elf_cons(int nbytes)1590 xtensa_elf_cons (int nbytes)
1591 {
1592 expressionS exp;
1593 bfd_reloc_code_real_type reloc;
1594
1595 md_flush_pending_output ();
1596
1597 if (cur_vinsn.inside_bundle)
1598 as_bad (_("directives are not valid inside bundles"));
1599
1600 if (is_it_end_of_statement ())
1601 {
1602 demand_empty_rest_of_line ();
1603 return;
1604 }
1605
1606 do
1607 {
1608 expression (&exp);
1609 if (exp.X_op == O_symbol
1610 && *input_line_pointer == '@'
1611 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1612 != BFD_RELOC_NONE))
1613 {
1614 reloc_howto_type *reloc_howto =
1615 bfd_reloc_type_lookup (stdoutput, reloc);
1616
1617 if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1618 as_bad (_("unsupported relocation"));
1619 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1620 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1621 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1622 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1623 as_bad (_("opcode-specific %s relocation used outside "
1624 "an instruction"), reloc_howto->name);
1625 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1626 as_bad (_("%s relocations do not fit in %d bytes"),
1627 reloc_howto->name, nbytes);
1628 else
1629 {
1630 char *p = frag_more ((int) nbytes);
1631 xtensa_set_frag_assembly_state (frag_now);
1632 fix_new_exp (frag_now, p - frag_now->fr_literal,
1633 nbytes, &exp, 0, reloc);
1634 }
1635 }
1636 else
1637 emit_expr (&exp, (unsigned int) nbytes);
1638 }
1639 while (*input_line_pointer++ == ',');
1640
1641 input_line_pointer--; /* Put terminator back into stream. */
1642 demand_empty_rest_of_line ();
1643 }
1644
1645
1646 /* Parsing and Idiom Translation. */
1647
1648 /* Parse @plt, etc. and return the desired relocation. */
1649 static bfd_reloc_code_real_type
xtensa_elf_suffix(char ** str_p,expressionS * exp_p)1650 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
1651 {
1652 struct map_bfd
1653 {
1654 char *string;
1655 int length;
1656 bfd_reloc_code_real_type reloc;
1657 };
1658
1659 char ident[20];
1660 char *str = *str_p;
1661 char *str2;
1662 int ch;
1663 int len;
1664 struct map_bfd *ptr;
1665
1666 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1667
1668 static struct map_bfd mapping[] =
1669 {
1670 MAP ("l", BFD_RELOC_LO16),
1671 MAP ("h", BFD_RELOC_HI16),
1672 MAP ("plt", BFD_RELOC_XTENSA_PLT),
1673 { (char *) 0, 0, BFD_RELOC_UNUSED }
1674 };
1675
1676 if (*str++ != '@')
1677 return BFD_RELOC_NONE;
1678
1679 for (ch = *str, str2 = ident;
1680 (str2 < ident + sizeof (ident) - 1
1681 && (ISALNUM (ch) || ch == '@'));
1682 ch = *++str)
1683 {
1684 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1685 }
1686
1687 *str2 = '\0';
1688 len = str2 - ident;
1689
1690 ch = ident[0];
1691 for (ptr = &mapping[0]; ptr->length > 0; ptr++)
1692 if (ch == ptr->string[0]
1693 && len == ptr->length
1694 && memcmp (ident, ptr->string, ptr->length) == 0)
1695 {
1696 /* Now check for "identifier@suffix+constant". */
1697 if (*str == '-' || *str == '+')
1698 {
1699 char *orig_line = input_line_pointer;
1700 expressionS new_exp;
1701
1702 input_line_pointer = str;
1703 expression (&new_exp);
1704 if (new_exp.X_op == O_constant)
1705 {
1706 exp_p->X_add_number += new_exp.X_add_number;
1707 str = input_line_pointer;
1708 }
1709
1710 if (&input_line_pointer != str_p)
1711 input_line_pointer = orig_line;
1712 }
1713
1714 *str_p = str;
1715 return ptr->reloc;
1716 }
1717
1718 return BFD_RELOC_UNUSED;
1719 }
1720
1721
1722 static const char *
expression_end(const char * name)1723 expression_end (const char *name)
1724 {
1725 while (1)
1726 {
1727 switch (*name)
1728 {
1729 case '}':
1730 case ';':
1731 case '\0':
1732 case ',':
1733 case ':':
1734 return name;
1735 case ' ':
1736 case '\t':
1737 ++name;
1738 continue;
1739 default:
1740 return 0;
1741 }
1742 }
1743 }
1744
1745
1746 #define ERROR_REG_NUM ((unsigned) -1)
1747
1748 static unsigned
tc_get_register(const char * prefix)1749 tc_get_register (const char *prefix)
1750 {
1751 unsigned reg;
1752 const char *next_expr;
1753 const char *old_line_pointer;
1754
1755 SKIP_WHITESPACE ();
1756 old_line_pointer = input_line_pointer;
1757
1758 if (*input_line_pointer == '$')
1759 ++input_line_pointer;
1760
1761 /* Accept "sp" as a synonym for "a1". */
1762 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1763 && expression_end (input_line_pointer + 2))
1764 {
1765 input_line_pointer += 2;
1766 return 1; /* AR[1] */
1767 }
1768
1769 while (*input_line_pointer++ == *prefix++)
1770 ;
1771 --input_line_pointer;
1772 --prefix;
1773
1774 if (*prefix)
1775 {
1776 as_bad (_("bad register name: %s"), old_line_pointer);
1777 return ERROR_REG_NUM;
1778 }
1779
1780 if (!ISDIGIT ((unsigned char) *input_line_pointer))
1781 {
1782 as_bad (_("bad register number: %s"), input_line_pointer);
1783 return ERROR_REG_NUM;
1784 }
1785
1786 reg = 0;
1787
1788 while (ISDIGIT ((int) *input_line_pointer))
1789 reg = reg * 10 + *input_line_pointer++ - '0';
1790
1791 if (!(next_expr = expression_end (input_line_pointer)))
1792 {
1793 as_bad (_("bad register name: %s"), old_line_pointer);
1794 return ERROR_REG_NUM;
1795 }
1796
1797 input_line_pointer = (char *) next_expr;
1798
1799 return reg;
1800 }
1801
1802
1803 static void
expression_maybe_register(xtensa_opcode opc,int opnd,expressionS * tok)1804 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
1805 {
1806 xtensa_isa isa = xtensa_default_isa;
1807
1808 /* Check if this is an immediate operand. */
1809 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
1810 {
1811 bfd_reloc_code_real_type reloc;
1812 segT t = expression (tok);
1813 if (t == absolute_section
1814 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
1815 {
1816 assert (tok->X_op == O_constant);
1817 tok->X_op = O_symbol;
1818 tok->X_add_symbol = &abs_symbol;
1819 }
1820
1821 if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1822 && (reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1823 && (reloc != BFD_RELOC_NONE))
1824 {
1825 switch (reloc)
1826 {
1827 default:
1828 case BFD_RELOC_UNUSED:
1829 as_bad (_("unsupported relocation"));
1830 break;
1831
1832 case BFD_RELOC_XTENSA_PLT:
1833 tok->X_op = O_pltrel;
1834 break;
1835
1836 case BFD_RELOC_LO16:
1837 if (tok->X_op == O_constant)
1838 tok->X_add_number &= 0xffff;
1839 else
1840 tok->X_op = O_lo16;
1841 break;
1842
1843 case BFD_RELOC_HI16:
1844 if (tok->X_op == O_constant)
1845 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1846 else
1847 tok->X_op = O_hi16;
1848 break;
1849 }
1850 }
1851 }
1852 else
1853 {
1854 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1855 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
1856
1857 if (reg != ERROR_REG_NUM) /* Already errored */
1858 {
1859 uint32 buf = reg;
1860 if (xtensa_operand_encode (isa, opc, opnd, &buf))
1861 as_bad (_("register number out of range"));
1862 }
1863
1864 tok->X_op = O_register;
1865 tok->X_add_symbol = 0;
1866 tok->X_add_number = reg;
1867 }
1868 }
1869
1870
1871 /* Split up the arguments for an opcode or pseudo-op. */
1872
1873 static int
tokenize_arguments(char ** args,char * str)1874 tokenize_arguments (char **args, char *str)
1875 {
1876 char *old_input_line_pointer;
1877 bfd_boolean saw_comma = FALSE;
1878 bfd_boolean saw_arg = FALSE;
1879 bfd_boolean saw_colon = FALSE;
1880 int num_args = 0;
1881 char *arg_end, *arg;
1882 int arg_len;
1883
1884 /* Save and restore input_line_pointer around this function. */
1885 old_input_line_pointer = input_line_pointer;
1886 input_line_pointer = str;
1887
1888 while (*input_line_pointer)
1889 {
1890 SKIP_WHITESPACE ();
1891 switch (*input_line_pointer)
1892 {
1893 case '\0':
1894 case '}':
1895 goto fini;
1896
1897 case ':':
1898 input_line_pointer++;
1899 if (saw_comma || saw_colon || !saw_arg)
1900 goto err;
1901 saw_colon = TRUE;
1902 break;
1903
1904 case ',':
1905 input_line_pointer++;
1906 if (saw_comma || saw_colon || !saw_arg)
1907 goto err;
1908 saw_comma = TRUE;
1909 break;
1910
1911 default:
1912 if (!saw_comma && !saw_colon && saw_arg)
1913 goto err;
1914
1915 arg_end = input_line_pointer + 1;
1916 while (!expression_end (arg_end))
1917 arg_end += 1;
1918
1919 arg_len = arg_end - input_line_pointer;
1920 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
1921 args[num_args] = arg;
1922
1923 if (saw_colon)
1924 *arg++ = ':';
1925 strncpy (arg, input_line_pointer, arg_len);
1926 arg[arg_len] = '\0';
1927
1928 input_line_pointer = arg_end;
1929 num_args += 1;
1930 saw_comma = FALSE;
1931 saw_colon = FALSE;
1932 saw_arg = TRUE;
1933 break;
1934 }
1935 }
1936
1937 fini:
1938 if (saw_comma || saw_colon)
1939 goto err;
1940 input_line_pointer = old_input_line_pointer;
1941 return num_args;
1942
1943 err:
1944 if (saw_comma)
1945 as_bad (_("extra comma"));
1946 else if (saw_colon)
1947 as_bad (_("extra colon"));
1948 else if (!saw_arg)
1949 as_bad (_("missing argument"));
1950 else
1951 as_bad (_("missing comma or colon"));
1952 input_line_pointer = old_input_line_pointer;
1953 return -1;
1954 }
1955
1956
1957 /* Parse the arguments to an opcode. Return TRUE on error. */
1958
1959 static bfd_boolean
parse_arguments(TInsn * insn,int num_args,char ** arg_strings)1960 parse_arguments (TInsn *insn, int num_args, char **arg_strings)
1961 {
1962 expressionS *tok, *last_tok;
1963 xtensa_opcode opcode = insn->opcode;
1964 bfd_boolean had_error = TRUE;
1965 xtensa_isa isa = xtensa_default_isa;
1966 int n, num_regs = 0;
1967 int opcode_operand_count;
1968 int opnd_cnt, last_opnd_cnt;
1969 unsigned int next_reg = 0;
1970 char *old_input_line_pointer;
1971
1972 if (insn->insn_type == ITYPE_LITERAL)
1973 opcode_operand_count = 1;
1974 else
1975 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
1976
1977 tok = insn->tok;
1978 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
1979
1980 /* Save and restore input_line_pointer around this function. */
1981 old_input_line_pointer = input_line_pointer;
1982
1983 last_tok = 0;
1984 last_opnd_cnt = -1;
1985 opnd_cnt = 0;
1986
1987 /* Skip invisible operands. */
1988 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
1989 {
1990 opnd_cnt += 1;
1991 tok++;
1992 }
1993
1994 for (n = 0; n < num_args; n++)
1995 {
1996 input_line_pointer = arg_strings[n];
1997 if (*input_line_pointer == ':')
1998 {
1999 xtensa_regfile opnd_rf;
2000 input_line_pointer++;
2001 if (num_regs == 0)
2002 goto err;
2003 assert (opnd_cnt > 0);
2004 num_regs--;
2005 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2006 if (next_reg
2007 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2008 as_warn (_("incorrect register number, ignoring"));
2009 next_reg++;
2010 }
2011 else
2012 {
2013 if (opnd_cnt >= opcode_operand_count)
2014 {
2015 as_warn (_("too many arguments"));
2016 goto err;
2017 }
2018 assert (opnd_cnt < MAX_INSN_ARGS);
2019
2020 expression_maybe_register (opcode, opnd_cnt, tok);
2021 next_reg = tok->X_add_number + 1;
2022
2023 if (tok->X_op == O_illegal || tok->X_op == O_absent)
2024 goto err;
2025 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2026 {
2027 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2028 /* minus 1 because we are seeing one right now */
2029 }
2030 else
2031 num_regs = 0;
2032
2033 last_tok = tok;
2034 last_opnd_cnt = opnd_cnt;
2035
2036 do
2037 {
2038 opnd_cnt += 1;
2039 tok++;
2040 }
2041 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2042 }
2043 }
2044
2045 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2046 goto err;
2047
2048 insn->ntok = tok - insn->tok;
2049 had_error = FALSE;
2050
2051 err:
2052 input_line_pointer = old_input_line_pointer;
2053 return had_error;
2054 }
2055
2056
2057 static int
get_invisible_operands(TInsn * insn)2058 get_invisible_operands (TInsn *insn)
2059 {
2060 xtensa_isa isa = xtensa_default_isa;
2061 static xtensa_insnbuf slotbuf = NULL;
2062 xtensa_format fmt;
2063 xtensa_opcode opc = insn->opcode;
2064 int slot, opnd, fmt_found;
2065 unsigned val;
2066
2067 if (!slotbuf)
2068 slotbuf = xtensa_insnbuf_alloc (isa);
2069
2070 /* Find format/slot where this can be encoded. */
2071 fmt_found = 0;
2072 slot = 0;
2073 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2074 {
2075 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2076 {
2077 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2078 {
2079 fmt_found = 1;
2080 break;
2081 }
2082 }
2083 if (fmt_found) break;
2084 }
2085
2086 if (!fmt_found)
2087 {
2088 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2089 return -1;
2090 }
2091
2092 /* First encode all the visible operands
2093 (to deal with shared field operands). */
2094 for (opnd = 0; opnd < insn->ntok; opnd++)
2095 {
2096 if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2097 && (insn->tok[opnd].X_op == O_register
2098 || insn->tok[opnd].X_op == O_constant))
2099 {
2100 val = insn->tok[opnd].X_add_number;
2101 xtensa_operand_encode (isa, opc, opnd, &val);
2102 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2103 }
2104 }
2105
2106 /* Then pull out the values for the invisible ones. */
2107 for (opnd = 0; opnd < insn->ntok; opnd++)
2108 {
2109 if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2110 {
2111 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2112 xtensa_operand_decode (isa, opc, opnd, &val);
2113 insn->tok[opnd].X_add_number = val;
2114 if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2115 insn->tok[opnd].X_op = O_register;
2116 else
2117 insn->tok[opnd].X_op = O_constant;
2118 }
2119 }
2120
2121 return 0;
2122 }
2123
2124
2125 static void
xg_reverse_shift_count(char ** cnt_argp)2126 xg_reverse_shift_count (char **cnt_argp)
2127 {
2128 char *cnt_arg, *new_arg;
2129 cnt_arg = *cnt_argp;
2130
2131 /* replace the argument with "31-(argument)" */
2132 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6);
2133 sprintf (new_arg, "31-(%s)", cnt_arg);
2134
2135 free (cnt_arg);
2136 *cnt_argp = new_arg;
2137 }
2138
2139
2140 /* If "arg" is a constant expression, return non-zero with the value
2141 in *valp. */
2142
2143 static int
xg_arg_is_constant(char * arg,offsetT * valp)2144 xg_arg_is_constant (char *arg, offsetT *valp)
2145 {
2146 expressionS exp;
2147 char *save_ptr = input_line_pointer;
2148
2149 input_line_pointer = arg;
2150 expression (&exp);
2151 input_line_pointer = save_ptr;
2152
2153 if (exp.X_op == O_constant)
2154 {
2155 *valp = exp.X_add_number;
2156 return 1;
2157 }
2158
2159 return 0;
2160 }
2161
2162
2163 static void
xg_replace_opname(char ** popname,char * newop)2164 xg_replace_opname (char **popname, char *newop)
2165 {
2166 free (*popname);
2167 *popname = (char *) xmalloc (strlen (newop) + 1);
2168 strcpy (*popname, newop);
2169 }
2170
2171
2172 static int
xg_check_num_args(int * pnum_args,int expected_num,char * opname,char ** arg_strings)2173 xg_check_num_args (int *pnum_args,
2174 int expected_num,
2175 char *opname,
2176 char **arg_strings)
2177 {
2178 int num_args = *pnum_args;
2179
2180 if (num_args < expected_num)
2181 {
2182 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2183 num_args, opname, expected_num);
2184 return -1;
2185 }
2186
2187 if (num_args > expected_num)
2188 {
2189 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2190 num_args, opname, expected_num);
2191 while (num_args-- > expected_num)
2192 {
2193 free (arg_strings[num_args]);
2194 arg_strings[num_args] = 0;
2195 }
2196 *pnum_args = expected_num;
2197 return -1;
2198 }
2199
2200 return 0;
2201 }
2202
2203
2204 /* If the register is not specified as part of the opcode,
2205 then get it from the operand and move it to the opcode. */
2206
2207 static int
xg_translate_sysreg_op(char ** popname,int * pnum_args,char ** arg_strings)2208 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
2209 {
2210 xtensa_isa isa = xtensa_default_isa;
2211 xtensa_sysreg sr;
2212 char *opname, *new_opname;
2213 const char *sr_name;
2214 int is_user, is_write;
2215 bfd_boolean has_underbar = FALSE;
2216
2217 opname = *popname;
2218 if (*opname == '_')
2219 {
2220 has_underbar = TRUE;
2221 opname += 1;
2222 }
2223 is_user = (opname[1] == 'u');
2224 is_write = (opname[0] == 'w');
2225
2226 /* Opname == [rw]ur or [rwx]sr... */
2227
2228 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2229 return -1;
2230
2231 /* Check if the argument is a symbolic register name. */
2232 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2233 /* Handle WSR to "INTSET" as a special case. */
2234 if (sr == XTENSA_UNDEFINED && is_write && !is_user
2235 && !strcasecmp (arg_strings[1], "intset"))
2236 sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2237 if (sr == XTENSA_UNDEFINED
2238 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2239 {
2240 /* Maybe it's a register number.... */
2241 offsetT val;
2242 if (!xg_arg_is_constant (arg_strings[1], &val))
2243 {
2244 as_bad (_("invalid register '%s' for '%s' instruction"),
2245 arg_strings[1], opname);
2246 return -1;
2247 }
2248 sr = xtensa_sysreg_lookup (isa, val, is_user);
2249 if (sr == XTENSA_UNDEFINED)
2250 {
2251 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2252 (long) val, opname);
2253 return -1;
2254 }
2255 }
2256
2257 /* Remove the last argument, which is now part of the opcode. */
2258 free (arg_strings[1]);
2259 arg_strings[1] = 0;
2260 *pnum_args = 1;
2261
2262 /* Translate the opcode. */
2263 sr_name = xtensa_sysreg_name (isa, sr);
2264 /* Another special case for "WSR.INTSET".... */
2265 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2266 sr_name = "intset";
2267 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2268 sprintf (new_opname, "%s%s.%s", (has_underbar ? "_" : ""),
2269 *popname, sr_name);
2270 free (*popname);
2271 *popname = new_opname;
2272
2273 return 0;
2274 }
2275
2276
2277 static int
xtensa_translate_old_userreg_ops(char ** popname)2278 xtensa_translate_old_userreg_ops (char **popname)
2279 {
2280 xtensa_isa isa = xtensa_default_isa;
2281 xtensa_sysreg sr;
2282 char *opname, *new_opname;
2283 const char *sr_name;
2284 bfd_boolean has_underbar = FALSE;
2285
2286 opname = *popname;
2287 if (opname[0] == '_')
2288 {
2289 has_underbar = TRUE;
2290 opname += 1;
2291 }
2292
2293 sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2294 if (sr != XTENSA_UNDEFINED)
2295 {
2296 /* The new default name ("nnn") is different from the old default
2297 name ("URnnn"). The old default is handled below, and we don't
2298 want to recognize [RW]nnn, so do nothing if the name is the (new)
2299 default. */
2300 static char namebuf[10];
2301 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2302 if (strcmp (namebuf, opname + 1) == 0)
2303 return 0;
2304 }
2305 else
2306 {
2307 offsetT val;
2308 char *end;
2309
2310 /* Only continue if the reg name is "URnnn". */
2311 if (opname[1] != 'u' || opname[2] != 'r')
2312 return 0;
2313 val = strtoul (opname + 3, &end, 10);
2314 if (*end != '\0')
2315 return 0;
2316
2317 sr = xtensa_sysreg_lookup (isa, val, 1);
2318 if (sr == XTENSA_UNDEFINED)
2319 {
2320 as_bad (_("invalid register number (%ld) for '%s'"),
2321 (long) val, opname);
2322 return -1;
2323 }
2324 }
2325
2326 /* Translate the opcode. */
2327 sr_name = xtensa_sysreg_name (isa, sr);
2328 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2329 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2330 opname[0], sr_name);
2331 free (*popname);
2332 *popname = new_opname;
2333
2334 return 0;
2335 }
2336
2337
2338 static int
xtensa_translate_zero_immed(char * old_op,char * new_op,char ** popname,int * pnum_args,char ** arg_strings)2339 xtensa_translate_zero_immed (char *old_op,
2340 char *new_op,
2341 char **popname,
2342 int *pnum_args,
2343 char **arg_strings)
2344 {
2345 char *opname;
2346 offsetT val;
2347
2348 opname = *popname;
2349 assert (opname[0] != '_');
2350
2351 if (strcmp (opname, old_op) != 0)
2352 return 0;
2353
2354 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2355 return -1;
2356 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2357 {
2358 xg_replace_opname (popname, new_op);
2359 free (arg_strings[1]);
2360 arg_strings[1] = arg_strings[2];
2361 arg_strings[2] = 0;
2362 *pnum_args = 2;
2363 }
2364
2365 return 0;
2366 }
2367
2368
2369 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2370 Returns non-zero if an error was found. */
2371
2372 static int
xg_translate_idioms(char ** popname,int * pnum_args,char ** arg_strings)2373 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
2374 {
2375 char *opname = *popname;
2376 bfd_boolean has_underbar = FALSE;
2377
2378 if (cur_vinsn.inside_bundle)
2379 return 0;
2380
2381 if (*opname == '_')
2382 {
2383 has_underbar = TRUE;
2384 opname += 1;
2385 }
2386
2387 if (strcmp (opname, "mov") == 0)
2388 {
2389 if (use_transform () && !has_underbar && density_supported)
2390 xg_replace_opname (popname, "mov.n");
2391 else
2392 {
2393 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2394 return -1;
2395 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2396 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
2397 strcpy (arg_strings[2], arg_strings[1]);
2398 *pnum_args = 3;
2399 }
2400 return 0;
2401 }
2402
2403 if (strcmp (opname, "bbsi.l") == 0)
2404 {
2405 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2406 return -1;
2407 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2408 if (target_big_endian)
2409 xg_reverse_shift_count (&arg_strings[1]);
2410 return 0;
2411 }
2412
2413 if (strcmp (opname, "bbci.l") == 0)
2414 {
2415 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2416 return -1;
2417 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2418 if (target_big_endian)
2419 xg_reverse_shift_count (&arg_strings[1]);
2420 return 0;
2421 }
2422
2423 if (xtensa_nop_opcode == XTENSA_UNDEFINED
2424 && strcmp (opname, "nop") == 0)
2425 {
2426 if (use_transform () && !has_underbar && density_supported)
2427 xg_replace_opname (popname, "nop.n");
2428 else
2429 {
2430 if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2431 return -1;
2432 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2433 arg_strings[0] = (char *) xmalloc (3);
2434 arg_strings[1] = (char *) xmalloc (3);
2435 arg_strings[2] = (char *) xmalloc (3);
2436 strcpy (arg_strings[0], "a1");
2437 strcpy (arg_strings[1], "a1");
2438 strcpy (arg_strings[2], "a1");
2439 *pnum_args = 3;
2440 }
2441 return 0;
2442 }
2443
2444 /* Recognize [RW]UR and [RWX]SR. */
2445 if ((((opname[0] == 'r' || opname[0] == 'w')
2446 && (opname[1] == 'u' || opname[1] == 's'))
2447 || (opname[0] == 'x' && opname[1] == 's'))
2448 && opname[2] == 'r'
2449 && opname[3] == '\0')
2450 return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2451
2452 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2453 [RW]<name> if <name> is the non-default name of a user register. */
2454 if ((opname[0] == 'r' || opname[0] == 'w')
2455 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2456 return xtensa_translate_old_userreg_ops (popname);
2457
2458 /* Relax branches that don't allow comparisons against an immediate value
2459 of zero to the corresponding branches with implicit zero immediates. */
2460 if (!has_underbar && use_transform ())
2461 {
2462 if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2463 pnum_args, arg_strings))
2464 return -1;
2465
2466 if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2467 pnum_args, arg_strings))
2468 return -1;
2469
2470 if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2471 pnum_args, arg_strings))
2472 return -1;
2473
2474 if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2475 pnum_args, arg_strings))
2476 return -1;
2477 }
2478
2479 return 0;
2480 }
2481
2482
2483 /* Functions for dealing with the Xtensa ISA. */
2484
2485 /* Currently the assembler only allows us to use a single target per
2486 fragment. Because of this, only one operand for a given
2487 instruction may be symbolic. If there is a PC-relative operand,
2488 the last one is chosen. Otherwise, the result is the number of the
2489 last immediate operand, and if there are none of those, we fail and
2490 return -1. */
2491
2492 static int
get_relaxable_immed(xtensa_opcode opcode)2493 get_relaxable_immed (xtensa_opcode opcode)
2494 {
2495 int last_immed = -1;
2496 int noperands, opi;
2497
2498 if (opcode == XTENSA_UNDEFINED)
2499 return -1;
2500
2501 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2502 for (opi = noperands - 1; opi >= 0; opi--)
2503 {
2504 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2505 continue;
2506 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2507 return opi;
2508 if (last_immed == -1
2509 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2510 last_immed = opi;
2511 }
2512 return last_immed;
2513 }
2514
2515
2516 static xtensa_opcode
get_opcode_from_buf(const char * buf,int slot)2517 get_opcode_from_buf (const char *buf, int slot)
2518 {
2519 static xtensa_insnbuf insnbuf = NULL;
2520 static xtensa_insnbuf slotbuf = NULL;
2521 xtensa_isa isa = xtensa_default_isa;
2522 xtensa_format fmt;
2523
2524 if (!insnbuf)
2525 {
2526 insnbuf = xtensa_insnbuf_alloc (isa);
2527 slotbuf = xtensa_insnbuf_alloc (isa);
2528 }
2529
2530 xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0);
2531 fmt = xtensa_format_decode (isa, insnbuf);
2532 if (fmt == XTENSA_UNDEFINED)
2533 return XTENSA_UNDEFINED;
2534
2535 if (slot >= xtensa_format_num_slots (isa, fmt))
2536 return XTENSA_UNDEFINED;
2537
2538 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2539 return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
2540 }
2541
2542
2543 #ifdef TENSILICA_DEBUG
2544
2545 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2546
2547 static void
xtensa_print_insn_table(void)2548 xtensa_print_insn_table (void)
2549 {
2550 int num_opcodes, num_operands;
2551 xtensa_opcode opcode;
2552 xtensa_isa isa = xtensa_default_isa;
2553
2554 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2555 for (opcode = 0; opcode < num_opcodes; opcode++)
2556 {
2557 int opn;
2558 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2559 num_operands = xtensa_opcode_num_operands (isa, opcode);
2560 for (opn = 0; opn < num_operands; opn++)
2561 {
2562 if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2563 continue;
2564 if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2565 {
2566 xtensa_regfile opnd_rf =
2567 xtensa_operand_regfile (isa, opcode, opn);
2568 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2569 }
2570 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2571 fputs ("[lLr] ", stderr);
2572 else
2573 fputs ("i ", stderr);
2574 }
2575 fprintf (stderr, "\n");
2576 }
2577 }
2578
2579
2580 static void
print_vliw_insn(xtensa_insnbuf vbuf)2581 print_vliw_insn (xtensa_insnbuf vbuf)
2582 {
2583 xtensa_isa isa = xtensa_default_isa;
2584 xtensa_format f = xtensa_format_decode (isa, vbuf);
2585 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2586 int op;
2587
2588 fprintf (stderr, "format = %d\n", f);
2589
2590 for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2591 {
2592 xtensa_opcode opcode;
2593 const char *opname;
2594 int operands;
2595
2596 xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2597 opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2598 opname = xtensa_opcode_name (isa, opcode);
2599
2600 fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2601 fprintf (stderr, " operands = ");
2602 for (operands = 0;
2603 operands < xtensa_opcode_num_operands (isa, opcode);
2604 operands++)
2605 {
2606 unsigned int val;
2607 if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2608 continue;
2609 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2610 xtensa_operand_decode (isa, opcode, operands, &val);
2611 fprintf (stderr, "%d ", val);
2612 }
2613 fprintf (stderr, "\n");
2614 }
2615 xtensa_insnbuf_free (isa, sbuf);
2616 }
2617
2618 #endif /* TENSILICA_DEBUG */
2619
2620
2621 static bfd_boolean
is_direct_call_opcode(xtensa_opcode opcode)2622 is_direct_call_opcode (xtensa_opcode opcode)
2623 {
2624 xtensa_isa isa = xtensa_default_isa;
2625 int n, num_operands;
2626
2627 if (xtensa_opcode_is_call (isa, opcode) == 0)
2628 return FALSE;
2629
2630 num_operands = xtensa_opcode_num_operands (isa, opcode);
2631 for (n = 0; n < num_operands; n++)
2632 {
2633 if (xtensa_operand_is_register (isa, opcode, n) == 0
2634 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2635 return TRUE;
2636 }
2637 return FALSE;
2638 }
2639
2640
2641 /* Convert from BFD relocation type code to slot and operand number.
2642 Returns non-zero on failure. */
2643
2644 static int
decode_reloc(bfd_reloc_code_real_type reloc,int * slot,bfd_boolean * is_alt)2645 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
2646 {
2647 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2648 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2649 {
2650 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2651 *is_alt = FALSE;
2652 }
2653 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2654 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
2655 {
2656 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2657 *is_alt = TRUE;
2658 }
2659 else
2660 return -1;
2661
2662 return 0;
2663 }
2664
2665
2666 /* Convert from slot number to BFD relocation type code for the
2667 standard PC-relative relocations. Return BFD_RELOC_NONE on
2668 failure. */
2669
2670 static bfd_reloc_code_real_type
encode_reloc(int slot)2671 encode_reloc (int slot)
2672 {
2673 if (slot < 0 || slot > 14)
2674 return BFD_RELOC_NONE;
2675
2676 return BFD_RELOC_XTENSA_SLOT0_OP + slot;
2677 }
2678
2679
2680 /* Convert from slot numbers to BFD relocation type code for the
2681 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2682
2683 static bfd_reloc_code_real_type
encode_alt_reloc(int slot)2684 encode_alt_reloc (int slot)
2685 {
2686 if (slot < 0 || slot > 14)
2687 return BFD_RELOC_NONE;
2688
2689 return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
2690 }
2691
2692
2693 static void
xtensa_insnbuf_set_operand(xtensa_insnbuf slotbuf,xtensa_format fmt,int slot,xtensa_opcode opcode,int operand,uint32 value,const char * file,unsigned int line)2694 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2695 xtensa_format fmt,
2696 int slot,
2697 xtensa_opcode opcode,
2698 int operand,
2699 uint32 value,
2700 const char *file,
2701 unsigned int line)
2702 {
2703 uint32 valbuf = value;
2704
2705 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
2706 {
2707 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2708 == 1)
2709 as_bad_where ((char *) file, line,
2710 _("operand %d of '%s' has out of range value '%u'"),
2711 operand + 1,
2712 xtensa_opcode_name (xtensa_default_isa, opcode),
2713 value);
2714 else
2715 as_bad_where ((char *) file, line,
2716 _("operand %d of '%s' has invalid value '%u'"),
2717 operand + 1,
2718 xtensa_opcode_name (xtensa_default_isa, opcode),
2719 value);
2720 return;
2721 }
2722
2723 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2724 slotbuf, valbuf);
2725 }
2726
2727
2728 static uint32
xtensa_insnbuf_get_operand(xtensa_insnbuf slotbuf,xtensa_format fmt,int slot,xtensa_opcode opcode,int opnum)2729 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2730 xtensa_format fmt,
2731 int slot,
2732 xtensa_opcode opcode,
2733 int opnum)
2734 {
2735 uint32 val = 0;
2736 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2737 fmt, slot, slotbuf, &val);
2738 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2739 return val;
2740 }
2741
2742
2743 /* Checks for rules from xtensa-relax tables. */
2744
2745 /* The routine xg_instruction_matches_option_term must return TRUE
2746 when a given option term is true. The meaning of all of the option
2747 terms is given interpretation by this function. This is needed when
2748 an option depends on the state of a directive, but there are no such
2749 options in use right now. */
2750
2751 static bfd_boolean
xg_instruction_matches_option_term(TInsn * insn ATTRIBUTE_UNUSED,const ReqOrOption * option)2752 xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
2753 const ReqOrOption *option)
2754 {
2755 if (strcmp (option->option_name, "realnop") == 0
2756 || strncmp (option->option_name, "IsaUse", 6) == 0)
2757 {
2758 /* These conditions were evaluated statically when building the
2759 relaxation table. There's no need to reevaluate them now. */
2760 return TRUE;
2761 }
2762 else
2763 {
2764 as_fatal (_("internal error: unknown option name '%s'"),
2765 option->option_name);
2766 }
2767 }
2768
2769
2770 static bfd_boolean
xg_instruction_matches_or_options(TInsn * insn,const ReqOrOptionList * or_option)2771 xg_instruction_matches_or_options (TInsn *insn,
2772 const ReqOrOptionList *or_option)
2773 {
2774 const ReqOrOption *option;
2775 /* Must match each of the AND terms. */
2776 for (option = or_option; option != NULL; option = option->next)
2777 {
2778 if (xg_instruction_matches_option_term (insn, option))
2779 return TRUE;
2780 }
2781 return FALSE;
2782 }
2783
2784
2785 static bfd_boolean
xg_instruction_matches_options(TInsn * insn,const ReqOptionList * options)2786 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
2787 {
2788 const ReqOption *req_options;
2789 /* Must match each of the AND terms. */
2790 for (req_options = options;
2791 req_options != NULL;
2792 req_options = req_options->next)
2793 {
2794 /* Must match one of the OR clauses. */
2795 if (!xg_instruction_matches_or_options (insn,
2796 req_options->or_option_terms))
2797 return FALSE;
2798 }
2799 return TRUE;
2800 }
2801
2802
2803 /* Return the transition rule that matches or NULL if none matches. */
2804
2805 static bfd_boolean
xg_instruction_matches_rule(TInsn * insn,TransitionRule * rule)2806 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
2807 {
2808 PreconditionList *condition_l;
2809
2810 if (rule->opcode != insn->opcode)
2811 return FALSE;
2812
2813 for (condition_l = rule->conditions;
2814 condition_l != NULL;
2815 condition_l = condition_l->next)
2816 {
2817 expressionS *exp1;
2818 expressionS *exp2;
2819 Precondition *cond = condition_l->precond;
2820
2821 switch (cond->typ)
2822 {
2823 case OP_CONSTANT:
2824 /* The expression must be the constant. */
2825 assert (cond->op_num < insn->ntok);
2826 exp1 = &insn->tok[cond->op_num];
2827 if (expr_is_const (exp1))
2828 {
2829 switch (cond->cmp)
2830 {
2831 case OP_EQUAL:
2832 if (get_expr_const (exp1) != cond->op_data)
2833 return FALSE;
2834 break;
2835 case OP_NOTEQUAL:
2836 if (get_expr_const (exp1) == cond->op_data)
2837 return FALSE;
2838 break;
2839 default:
2840 return FALSE;
2841 }
2842 }
2843 else if (expr_is_register (exp1))
2844 {
2845 switch (cond->cmp)
2846 {
2847 case OP_EQUAL:
2848 if (get_expr_register (exp1) != cond->op_data)
2849 return FALSE;
2850 break;
2851 case OP_NOTEQUAL:
2852 if (get_expr_register (exp1) == cond->op_data)
2853 return FALSE;
2854 break;
2855 default:
2856 return FALSE;
2857 }
2858 }
2859 else
2860 return FALSE;
2861 break;
2862
2863 case OP_OPERAND:
2864 assert (cond->op_num < insn->ntok);
2865 assert (cond->op_data < insn->ntok);
2866 exp1 = &insn->tok[cond->op_num];
2867 exp2 = &insn->tok[cond->op_data];
2868
2869 switch (cond->cmp)
2870 {
2871 case OP_EQUAL:
2872 if (!expr_is_equal (exp1, exp2))
2873 return FALSE;
2874 break;
2875 case OP_NOTEQUAL:
2876 if (expr_is_equal (exp1, exp2))
2877 return FALSE;
2878 break;
2879 }
2880 break;
2881
2882 case OP_LITERAL:
2883 case OP_LABEL:
2884 default:
2885 return FALSE;
2886 }
2887 }
2888 if (!xg_instruction_matches_options (insn, rule->options))
2889 return FALSE;
2890
2891 return TRUE;
2892 }
2893
2894
2895 static int
transition_rule_cmp(const TransitionRule * a,const TransitionRule * b)2896 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
2897 {
2898 bfd_boolean a_greater = FALSE;
2899 bfd_boolean b_greater = FALSE;
2900
2901 ReqOptionList *l_a = a->options;
2902 ReqOptionList *l_b = b->options;
2903
2904 /* We only care if they both are the same except for
2905 a const16 vs. an l32r. */
2906
2907 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2908 {
2909 ReqOrOptionList *l_or_a = l_a->or_option_terms;
2910 ReqOrOptionList *l_or_b = l_b->or_option_terms;
2911 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2912 {
2913 if (l_or_a->is_true != l_or_b->is_true)
2914 return 0;
2915 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
2916 {
2917 /* This is the case we care about. */
2918 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
2919 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
2920 {
2921 if (prefer_const16)
2922 a_greater = TRUE;
2923 else
2924 b_greater = TRUE;
2925 }
2926 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
2927 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
2928 {
2929 if (prefer_const16)
2930 b_greater = TRUE;
2931 else
2932 a_greater = TRUE;
2933 }
2934 else
2935 return 0;
2936 }
2937 l_or_a = l_or_a->next;
2938 l_or_b = l_or_b->next;
2939 }
2940 if (l_or_a || l_or_b)
2941 return 0;
2942
2943 l_a = l_a->next;
2944 l_b = l_b->next;
2945 }
2946 if (l_a || l_b)
2947 return 0;
2948
2949 /* Incomparable if the substitution was used differently in two cases. */
2950 if (a_greater && b_greater)
2951 return 0;
2952
2953 if (b_greater)
2954 return 1;
2955 if (a_greater)
2956 return -1;
2957
2958 return 0;
2959 }
2960
2961
2962 static TransitionRule *
xg_instruction_match(TInsn * insn)2963 xg_instruction_match (TInsn *insn)
2964 {
2965 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
2966 TransitionList *l;
2967 assert (insn->opcode < table->num_opcodes);
2968
2969 /* Walk through all of the possible transitions. */
2970 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
2971 {
2972 TransitionRule *rule = l->rule;
2973 if (xg_instruction_matches_rule (insn, rule))
2974 return rule;
2975 }
2976 return NULL;
2977 }
2978
2979
2980 /* Various Other Internal Functions. */
2981
2982 static bfd_boolean
is_unique_insn_expansion(TransitionRule * r)2983 is_unique_insn_expansion (TransitionRule *r)
2984 {
2985 if (!r->to_instr || r->to_instr->next != NULL)
2986 return FALSE;
2987 if (r->to_instr->typ != INSTR_INSTR)
2988 return FALSE;
2989 return TRUE;
2990 }
2991
2992
2993 /* Check if there is exactly one relaxation for INSN that converts it to
2994 another instruction of equal or larger size. If so, and if TARG is
2995 non-null, go ahead and generate the relaxed instruction into TARG. If
2996 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2997 instruction, i.e., ignore relaxations that convert to an instruction of
2998 equal size. In some contexts where this function is used, only
2999 a single widening is allowed and the NARROW_ONLY argument is used to
3000 exclude cases like ADDI being "widened" to an ADDMI, which may
3001 later be relaxed to an ADDMI/ADDI pair. */
3002
3003 bfd_boolean
xg_is_single_relaxable_insn(TInsn * insn,TInsn * targ,bfd_boolean narrow_only)3004 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
3005 {
3006 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3007 TransitionList *l;
3008 TransitionRule *match = 0;
3009
3010 assert (insn->insn_type == ITYPE_INSN);
3011 assert (insn->opcode < table->num_opcodes);
3012
3013 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3014 {
3015 TransitionRule *rule = l->rule;
3016
3017 if (xg_instruction_matches_rule (insn, rule)
3018 && is_unique_insn_expansion (rule)
3019 && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
3020 <= xg_get_single_size (rule->to_instr->opcode)))
3021 {
3022 if (match)
3023 return FALSE;
3024 match = rule;
3025 }
3026 }
3027 if (!match)
3028 return FALSE;
3029
3030 if (targ)
3031 xg_build_to_insn (targ, insn, match->to_instr);
3032 return TRUE;
3033 }
3034
3035
3036 /* Return the maximum number of bytes this opcode can expand to. */
3037
3038 static int
xg_get_max_insn_widen_size(xtensa_opcode opcode)3039 xg_get_max_insn_widen_size (xtensa_opcode opcode)
3040 {
3041 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3042 TransitionList *l;
3043 int max_size = xg_get_single_size (opcode);
3044
3045 assert (opcode < table->num_opcodes);
3046
3047 for (l = table->table[opcode]; l != NULL; l = l->next)
3048 {
3049 TransitionRule *rule = l->rule;
3050 BuildInstr *build_list;
3051 int this_size = 0;
3052
3053 if (!rule)
3054 continue;
3055 build_list = rule->to_instr;
3056 if (is_unique_insn_expansion (rule))
3057 {
3058 assert (build_list->typ == INSTR_INSTR);
3059 this_size = xg_get_max_insn_widen_size (build_list->opcode);
3060 }
3061 else
3062 for (; build_list != NULL; build_list = build_list->next)
3063 {
3064 switch (build_list->typ)
3065 {
3066 case INSTR_INSTR:
3067 this_size += xg_get_single_size (build_list->opcode);
3068 break;
3069 case INSTR_LITERAL_DEF:
3070 case INSTR_LABEL_DEF:
3071 default:
3072 break;
3073 }
3074 }
3075 if (this_size > max_size)
3076 max_size = this_size;
3077 }
3078 return max_size;
3079 }
3080
3081
3082 /* Return the maximum number of literal bytes this opcode can generate. */
3083
3084 static int
xg_get_max_insn_widen_literal_size(xtensa_opcode opcode)3085 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
3086 {
3087 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3088 TransitionList *l;
3089 int max_size = 0;
3090
3091 assert (opcode < table->num_opcodes);
3092
3093 for (l = table->table[opcode]; l != NULL; l = l->next)
3094 {
3095 TransitionRule *rule = l->rule;
3096 BuildInstr *build_list;
3097 int this_size = 0;
3098
3099 if (!rule)
3100 continue;
3101 build_list = rule->to_instr;
3102 if (is_unique_insn_expansion (rule))
3103 {
3104 assert (build_list->typ == INSTR_INSTR);
3105 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3106 }
3107 else
3108 for (; build_list != NULL; build_list = build_list->next)
3109 {
3110 switch (build_list->typ)
3111 {
3112 case INSTR_LITERAL_DEF:
3113 /* Hard-coded 4-byte literal. */
3114 this_size += 4;
3115 break;
3116 case INSTR_INSTR:
3117 case INSTR_LABEL_DEF:
3118 default:
3119 break;
3120 }
3121 }
3122 if (this_size > max_size)
3123 max_size = this_size;
3124 }
3125 return max_size;
3126 }
3127
3128
3129 static bfd_boolean
xg_is_relaxable_insn(TInsn * insn,int lateral_steps)3130 xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3131 {
3132 int steps_taken = 0;
3133 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3134 TransitionList *l;
3135
3136 assert (insn->insn_type == ITYPE_INSN);
3137 assert (insn->opcode < table->num_opcodes);
3138
3139 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3140 {
3141 TransitionRule *rule = l->rule;
3142
3143 if (xg_instruction_matches_rule (insn, rule))
3144 {
3145 if (steps_taken == lateral_steps)
3146 return TRUE;
3147 steps_taken++;
3148 }
3149 }
3150 return FALSE;
3151 }
3152
3153
3154 static symbolS *
get_special_literal_symbol(void)3155 get_special_literal_symbol (void)
3156 {
3157 static symbolS *sym = NULL;
3158
3159 if (sym == NULL)
3160 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3161 return sym;
3162 }
3163
3164
3165 static symbolS *
get_special_label_symbol(void)3166 get_special_label_symbol (void)
3167 {
3168 static symbolS *sym = NULL;
3169
3170 if (sym == NULL)
3171 sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3172 return sym;
3173 }
3174
3175
3176 static bfd_boolean
xg_valid_literal_expression(const expressionS * exp)3177 xg_valid_literal_expression (const expressionS *exp)
3178 {
3179 switch (exp->X_op)
3180 {
3181 case O_constant:
3182 case O_symbol:
3183 case O_big:
3184 case O_uminus:
3185 case O_subtract:
3186 case O_pltrel:
3187 return TRUE;
3188 default:
3189 return FALSE;
3190 }
3191 }
3192
3193
3194 /* This will check to see if the value can be converted into the
3195 operand type. It will return TRUE if it does not fit. */
3196
3197 static bfd_boolean
xg_check_operand(int32 value,xtensa_opcode opcode,int operand)3198 xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3199 {
3200 uint32 valbuf = value;
3201 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3202 return TRUE;
3203 return FALSE;
3204 }
3205
3206
3207 /* Assumes: All immeds are constants. Check that all constants fit
3208 into their immeds; return FALSE if not. */
3209
3210 static bfd_boolean
xg_immeds_fit(const TInsn * insn)3211 xg_immeds_fit (const TInsn *insn)
3212 {
3213 xtensa_isa isa = xtensa_default_isa;
3214 int i;
3215
3216 int n = insn->ntok;
3217 assert (insn->insn_type == ITYPE_INSN);
3218 for (i = 0; i < n; ++i)
3219 {
3220 const expressionS *expr = &insn->tok[i];
3221 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3222 continue;
3223
3224 switch (expr->X_op)
3225 {
3226 case O_register:
3227 case O_constant:
3228 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3229 return FALSE;
3230 break;
3231
3232 default:
3233 /* The symbol should have a fixup associated with it. */
3234 assert (FALSE);
3235 break;
3236 }
3237 }
3238 return TRUE;
3239 }
3240
3241
3242 /* This should only be called after we have an initial
3243 estimate of the addresses. */
3244
3245 static bfd_boolean
xg_symbolic_immeds_fit(const TInsn * insn,segT pc_seg,fragS * pc_frag,offsetT pc_offset,long stretch)3246 xg_symbolic_immeds_fit (const TInsn *insn,
3247 segT pc_seg,
3248 fragS *pc_frag,
3249 offsetT pc_offset,
3250 long stretch)
3251 {
3252 xtensa_isa isa = xtensa_default_isa;
3253 symbolS *symbolP;
3254 fragS *sym_frag;
3255 offsetT target, pc;
3256 uint32 new_offset;
3257 int i;
3258 int n = insn->ntok;
3259
3260 assert (insn->insn_type == ITYPE_INSN);
3261
3262 for (i = 0; i < n; ++i)
3263 {
3264 const expressionS *expr = &insn->tok[i];
3265 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3266 continue;
3267
3268 switch (expr->X_op)
3269 {
3270 case O_register:
3271 case O_constant:
3272 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3273 return FALSE;
3274 break;
3275
3276 case O_lo16:
3277 case O_hi16:
3278 /* Check for the worst case. */
3279 if (xg_check_operand (0xffff, insn->opcode, i))
3280 return FALSE;
3281 break;
3282
3283 case O_symbol:
3284 /* We only allow symbols for PC-relative references.
3285 If pc_frag == 0, then we don't have frag locations yet. */
3286 if (pc_frag == 0
3287 || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
3288 return FALSE;
3289
3290 /* If it is a weak symbol, then assume it won't reach. */
3291 if (S_IS_WEAK (expr->X_add_symbol))
3292 return FALSE;
3293
3294 if (is_direct_call_opcode (insn->opcode)
3295 && ! pc_frag->tc_frag_data.use_longcalls)
3296 {
3297 /* If callee is undefined or in a different segment, be
3298 optimistic and assume it will be in range. */
3299 if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3300 return TRUE;
3301 }
3302
3303 /* Only references within a segment can be known to fit in the
3304 operands at assembly time. */
3305 if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3306 return FALSE;
3307
3308 symbolP = expr->X_add_symbol;
3309 sym_frag = symbol_get_frag (symbolP);
3310 target = S_GET_VALUE (symbolP) + expr->X_add_number;
3311 pc = pc_frag->fr_address + pc_offset;
3312
3313 /* If frag has yet to be reached on this pass, assume it
3314 will move by STRETCH just as we did. If this is not so,
3315 it will be because some frag between grows, and that will
3316 force another pass. Beware zero-length frags. There
3317 should be a faster way to do this. */
3318
3319 if (stretch != 0
3320 && sym_frag->relax_marker != pc_frag->relax_marker
3321 && S_GET_SEGMENT (symbolP) == pc_seg)
3322 {
3323 target += stretch;
3324 }
3325
3326 new_offset = target;
3327 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3328 if (xg_check_operand (new_offset, insn->opcode, i))
3329 return FALSE;
3330 break;
3331
3332 default:
3333 /* The symbol should have a fixup associated with it. */
3334 return FALSE;
3335 }
3336 }
3337
3338 return TRUE;
3339 }
3340
3341
3342 /* Return TRUE on success. */
3343
3344 static bfd_boolean
xg_build_to_insn(TInsn * targ,TInsn * insn,BuildInstr * bi)3345 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
3346 {
3347 BuildOp *op;
3348 symbolS *sym;
3349
3350 memset (targ, 0, sizeof (TInsn));
3351 targ->loc = insn->loc;
3352 switch (bi->typ)
3353 {
3354 case INSTR_INSTR:
3355 op = bi->ops;
3356 targ->opcode = bi->opcode;
3357 targ->insn_type = ITYPE_INSN;
3358 targ->is_specific_opcode = FALSE;
3359
3360 for (; op != NULL; op = op->next)
3361 {
3362 int op_num = op->op_num;
3363 int op_data = op->op_data;
3364
3365 assert (op->op_num < MAX_INSN_ARGS);
3366
3367 if (targ->ntok <= op_num)
3368 targ->ntok = op_num + 1;
3369
3370 switch (op->typ)
3371 {
3372 case OP_CONSTANT:
3373 set_expr_const (&targ->tok[op_num], op_data);
3374 break;
3375 case OP_OPERAND:
3376 assert (op_data < insn->ntok);
3377 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3378 break;
3379 case OP_LITERAL:
3380 sym = get_special_literal_symbol ();
3381 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3382 break;
3383 case OP_LABEL:
3384 sym = get_special_label_symbol ();
3385 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3386 break;
3387 case OP_OPERAND_HI16U:
3388 case OP_OPERAND_LOW16U:
3389 assert (op_data < insn->ntok);
3390 if (expr_is_const (&insn->tok[op_data]))
3391 {
3392 long val;
3393 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3394 val = xg_apply_userdef_op_fn (op->typ,
3395 targ->tok[op_num].
3396 X_add_number);
3397 targ->tok[op_num].X_add_number = val;
3398 }
3399 else
3400 {
3401 /* For const16 we can create relocations for these. */
3402 if (targ->opcode == XTENSA_UNDEFINED
3403 || (targ->opcode != xtensa_const16_opcode))
3404 return FALSE;
3405 assert (op_data < insn->ntok);
3406 /* Need to build a O_lo16 or O_hi16. */
3407 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3408 if (targ->tok[op_num].X_op == O_symbol)
3409 {
3410 if (op->typ == OP_OPERAND_HI16U)
3411 targ->tok[op_num].X_op = O_hi16;
3412 else if (op->typ == OP_OPERAND_LOW16U)
3413 targ->tok[op_num].X_op = O_lo16;
3414 else
3415 return FALSE;
3416 }
3417 }
3418 break;
3419 default:
3420 /* currently handles:
3421 OP_OPERAND_LOW8
3422 OP_OPERAND_HI24S
3423 OP_OPERAND_F32MINUS */
3424 if (xg_has_userdef_op_fn (op->typ))
3425 {
3426 assert (op_data < insn->ntok);
3427 if (expr_is_const (&insn->tok[op_data]))
3428 {
3429 long val;
3430 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3431 val = xg_apply_userdef_op_fn (op->typ,
3432 targ->tok[op_num].
3433 X_add_number);
3434 targ->tok[op_num].X_add_number = val;
3435 }
3436 else
3437 return FALSE; /* We cannot use a relocation for this. */
3438 break;
3439 }
3440 assert (0);
3441 break;
3442 }
3443 }
3444 break;
3445
3446 case INSTR_LITERAL_DEF:
3447 op = bi->ops;
3448 targ->opcode = XTENSA_UNDEFINED;
3449 targ->insn_type = ITYPE_LITERAL;
3450 targ->is_specific_opcode = FALSE;
3451 for (; op != NULL; op = op->next)
3452 {
3453 int op_num = op->op_num;
3454 int op_data = op->op_data;
3455 assert (op->op_num < MAX_INSN_ARGS);
3456
3457 if (targ->ntok <= op_num)
3458 targ->ntok = op_num + 1;
3459
3460 switch (op->typ)
3461 {
3462 case OP_OPERAND:
3463 assert (op_data < insn->ntok);
3464 /* We can only pass resolvable literals through. */
3465 if (!xg_valid_literal_expression (&insn->tok[op_data]))
3466 return FALSE;
3467 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3468 break;
3469 case OP_LITERAL:
3470 case OP_CONSTANT:
3471 case OP_LABEL:
3472 default:
3473 assert (0);
3474 break;
3475 }
3476 }
3477 break;
3478
3479 case INSTR_LABEL_DEF:
3480 op = bi->ops;
3481 targ->opcode = XTENSA_UNDEFINED;
3482 targ->insn_type = ITYPE_LABEL;
3483 targ->is_specific_opcode = FALSE;
3484 /* Literal with no ops is a label? */
3485 assert (op == NULL);
3486 break;
3487
3488 default:
3489 assert (0);
3490 }
3491
3492 return TRUE;
3493 }
3494
3495
3496 /* Return TRUE on success. */
3497
3498 static bfd_boolean
xg_build_to_stack(IStack * istack,TInsn * insn,BuildInstr * bi)3499 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
3500 {
3501 for (; bi != NULL; bi = bi->next)
3502 {
3503 TInsn *next_insn = istack_push_space (istack);
3504
3505 if (!xg_build_to_insn (next_insn, insn, bi))
3506 return FALSE;
3507 }
3508 return TRUE;
3509 }
3510
3511
3512 /* Return TRUE on valid expansion. */
3513
3514 static bfd_boolean
xg_expand_to_stack(IStack * istack,TInsn * insn,int lateral_steps)3515 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
3516 {
3517 int stack_size = istack->ninsn;
3518 int steps_taken = 0;
3519 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3520 TransitionList *l;
3521
3522 assert (insn->insn_type == ITYPE_INSN);
3523 assert (insn->opcode < table->num_opcodes);
3524
3525 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3526 {
3527 TransitionRule *rule = l->rule;
3528
3529 if (xg_instruction_matches_rule (insn, rule))
3530 {
3531 if (lateral_steps == steps_taken)
3532 {
3533 int i;
3534
3535 /* This is it. Expand the rule to the stack. */
3536 if (!xg_build_to_stack (istack, insn, rule->to_instr))
3537 return FALSE;
3538
3539 /* Check to see if it fits. */
3540 for (i = stack_size; i < istack->ninsn; i++)
3541 {
3542 TInsn *insn = &istack->insn[i];
3543
3544 if (insn->insn_type == ITYPE_INSN
3545 && !tinsn_has_symbolic_operands (insn)
3546 && !xg_immeds_fit (insn))
3547 {
3548 istack->ninsn = stack_size;
3549 return FALSE;
3550 }
3551 }
3552 return TRUE;
3553 }
3554 steps_taken++;
3555 }
3556 }
3557 return FALSE;
3558 }
3559
3560
3561 /* Relax the assembly instruction at least "min_steps".
3562 Return the number of steps taken. */
3563
3564 static int
xg_assembly_relax(IStack * istack,TInsn * insn,segT pc_seg,fragS * pc_frag,offsetT pc_offset,int min_steps,long stretch)3565 xg_assembly_relax (IStack *istack,
3566 TInsn *insn,
3567 segT pc_seg,
3568 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */
3569 offsetT pc_offset, /* offset in fragment */
3570 int min_steps, /* minimum conversion steps */
3571 long stretch) /* number of bytes stretched so far */
3572 {
3573 int steps_taken = 0;
3574
3575 /* assert (has no symbolic operands)
3576 Some of its immeds don't fit.
3577 Try to build a relaxed version.
3578 This may go through a couple of stages
3579 of single instruction transformations before
3580 we get there. */
3581
3582 TInsn single_target;
3583 TInsn current_insn;
3584 int lateral_steps = 0;
3585 int istack_size = istack->ninsn;
3586
3587 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3588 && steps_taken >= min_steps)
3589 {
3590 istack_push (istack, insn);
3591 return steps_taken;
3592 }
3593 current_insn = *insn;
3594
3595 /* Walk through all of the single instruction expansions. */
3596 while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE))
3597 {
3598 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3599 stretch))
3600 {
3601 steps_taken++;
3602 if (steps_taken >= min_steps)
3603 {
3604 istack_push (istack, &single_target);
3605 return steps_taken;
3606 }
3607 }
3608 current_insn = single_target;
3609 }
3610
3611 /* Now check for a multi-instruction expansion. */
3612 while (xg_is_relaxable_insn (¤t_insn, lateral_steps))
3613 {
3614 if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset,
3615 stretch))
3616 {
3617 if (steps_taken >= min_steps)
3618 {
3619 istack_push (istack, ¤t_insn);
3620 return steps_taken;
3621 }
3622 }
3623 steps_taken++;
3624 if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps))
3625 {
3626 if (steps_taken >= min_steps)
3627 return steps_taken;
3628 }
3629 lateral_steps++;
3630 istack->ninsn = istack_size;
3631 }
3632
3633 /* It's not going to work -- use the original. */
3634 istack_push (istack, insn);
3635 return steps_taken;
3636 }
3637
3638
3639 static void
xg_force_frag_space(int size)3640 xg_force_frag_space (int size)
3641 {
3642 /* This may have the side effect of creating a new fragment for the
3643 space to go into. I just do not like the name of the "frag"
3644 functions. */
3645 frag_grow (size);
3646 }
3647
3648
3649 static void
xg_finish_frag(char * last_insn,enum xtensa_relax_statesE frag_state,enum xtensa_relax_statesE slot0_state,int max_growth,bfd_boolean is_insn)3650 xg_finish_frag (char *last_insn,
3651 enum xtensa_relax_statesE frag_state,
3652 enum xtensa_relax_statesE slot0_state,
3653 int max_growth,
3654 bfd_boolean is_insn)
3655 {
3656 /* Finish off this fragment so that it has at LEAST the desired
3657 max_growth. If it doesn't fit in this fragment, close this one
3658 and start a new one. In either case, return a pointer to the
3659 beginning of the growth area. */
3660
3661 fragS *old_frag;
3662
3663 xg_force_frag_space (max_growth);
3664
3665 old_frag = frag_now;
3666
3667 frag_now->fr_opcode = last_insn;
3668 if (is_insn)
3669 frag_now->tc_frag_data.is_insn = TRUE;
3670
3671 frag_var (rs_machine_dependent, max_growth, max_growth,
3672 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3673
3674 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3675 xtensa_set_frag_assembly_state (frag_now);
3676
3677 /* Just to make sure that we did not split it up. */
3678 assert (old_frag->fr_next == frag_now);
3679 }
3680
3681
3682 /* Return TRUE if the target frag is one of the next non-empty frags. */
3683
3684 static bfd_boolean
is_next_frag_target(const fragS * fragP,const fragS * target)3685 is_next_frag_target (const fragS *fragP, const fragS *target)
3686 {
3687 if (fragP == NULL)
3688 return FALSE;
3689
3690 for (; fragP; fragP = fragP->fr_next)
3691 {
3692 if (fragP == target)
3693 return TRUE;
3694 if (fragP->fr_fix != 0)
3695 return FALSE;
3696 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3697 return FALSE;
3698 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3699 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3700 return FALSE;
3701 if (fragP->fr_type == rs_space)
3702 return FALSE;
3703 }
3704 return FALSE;
3705 }
3706
3707
3708 static bfd_boolean
is_branch_jmp_to_next(TInsn * insn,fragS * fragP)3709 is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
3710 {
3711 xtensa_isa isa = xtensa_default_isa;
3712 int i;
3713 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3714 int target_op = -1;
3715 symbolS *sym;
3716 fragS *target_frag;
3717
3718 if (xtensa_opcode_is_branch (isa, insn->opcode) == 0
3719 && xtensa_opcode_is_jump (isa, insn->opcode) == 0)
3720 return FALSE;
3721
3722 for (i = 0; i < num_ops; i++)
3723 {
3724 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
3725 {
3726 target_op = i;
3727 break;
3728 }
3729 }
3730 if (target_op == -1)
3731 return FALSE;
3732
3733 if (insn->ntok <= target_op)
3734 return FALSE;
3735
3736 if (insn->tok[target_op].X_op != O_symbol)
3737 return FALSE;
3738
3739 sym = insn->tok[target_op].X_add_symbol;
3740 if (sym == NULL)
3741 return FALSE;
3742
3743 if (insn->tok[target_op].X_add_number != 0)
3744 return FALSE;
3745
3746 target_frag = symbol_get_frag (sym);
3747 if (target_frag == NULL)
3748 return FALSE;
3749
3750 if (is_next_frag_target (fragP->fr_next, target_frag)
3751 && S_GET_VALUE (sym) == target_frag->fr_address)
3752 return TRUE;
3753
3754 return FALSE;
3755 }
3756
3757
3758 static void
xg_add_branch_and_loop_targets(TInsn * insn)3759 xg_add_branch_and_loop_targets (TInsn *insn)
3760 {
3761 xtensa_isa isa = xtensa_default_isa;
3762 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3763
3764 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3765 {
3766 int i = 1;
3767 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3768 && insn->tok[i].X_op == O_symbol)
3769 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3770 return;
3771 }
3772
3773 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3774 || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3775 {
3776 int i;
3777
3778 for (i = 0; i < insn->ntok && i < num_ops; i++)
3779 {
3780 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3781 && insn->tok[i].X_op == O_symbol)
3782 {
3783 symbolS *sym = insn->tok[i].X_add_symbol;
3784 symbol_get_tc (sym)->is_branch_target = TRUE;
3785 if (S_IS_DEFINED (sym))
3786 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3787 }
3788 }
3789 }
3790 }
3791
3792
3793 /* Return FALSE if no error. */
3794
3795 static bfd_boolean
xg_build_token_insn(BuildInstr * instr_spec,TInsn * old_insn,TInsn * new_insn)3796 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
3797 {
3798 int num_ops = 0;
3799 BuildOp *b_op;
3800
3801 switch (instr_spec->typ)
3802 {
3803 case INSTR_INSTR:
3804 new_insn->insn_type = ITYPE_INSN;
3805 new_insn->opcode = instr_spec->opcode;
3806 new_insn->is_specific_opcode = FALSE;
3807 new_insn->loc = old_insn->loc;
3808 break;
3809 case INSTR_LITERAL_DEF:
3810 new_insn->insn_type = ITYPE_LITERAL;
3811 new_insn->opcode = XTENSA_UNDEFINED;
3812 new_insn->is_specific_opcode = FALSE;
3813 new_insn->loc = old_insn->loc;
3814 break;
3815 case INSTR_LABEL_DEF:
3816 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3817 break;
3818 }
3819
3820 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3821 {
3822 expressionS *exp;
3823 const expressionS *src_exp;
3824
3825 num_ops++;
3826 switch (b_op->typ)
3827 {
3828 case OP_CONSTANT:
3829 /* The expression must be the constant. */
3830 assert (b_op->op_num < MAX_INSN_ARGS);
3831 exp = &new_insn->tok[b_op->op_num];
3832 set_expr_const (exp, b_op->op_data);
3833 break;
3834
3835 case OP_OPERAND:
3836 assert (b_op->op_num < MAX_INSN_ARGS);
3837 assert (b_op->op_data < (unsigned) old_insn->ntok);
3838 src_exp = &old_insn->tok[b_op->op_data];
3839 exp = &new_insn->tok[b_op->op_num];
3840 copy_expr (exp, src_exp);
3841 break;
3842
3843 case OP_LITERAL:
3844 case OP_LABEL:
3845 as_bad (_("can't handle generation of literal/labels yet"));
3846 assert (0);
3847
3848 default:
3849 as_bad (_("can't handle undefined OP TYPE"));
3850 assert (0);
3851 }
3852 }
3853
3854 new_insn->ntok = num_ops;
3855 return FALSE;
3856 }
3857
3858
3859 /* Return TRUE if it was simplified. */
3860
3861 static bfd_boolean
xg_simplify_insn(TInsn * old_insn,TInsn * new_insn)3862 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
3863 {
3864 TransitionRule *rule;
3865 BuildInstr *insn_spec;
3866
3867 if (old_insn->is_specific_opcode || !density_supported)
3868 return FALSE;
3869
3870 rule = xg_instruction_match (old_insn);
3871 if (rule == NULL)
3872 return FALSE;
3873
3874 insn_spec = rule->to_instr;
3875 /* There should only be one. */
3876 assert (insn_spec != NULL);
3877 assert (insn_spec->next == NULL);
3878 if (insn_spec->next != NULL)
3879 return FALSE;
3880
3881 xg_build_token_insn (insn_spec, old_insn, new_insn);
3882
3883 return TRUE;
3884 }
3885
3886
3887 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3888 l32i.n. (2) Check the number of operands. (3) Place the instruction
3889 tokens into the stack or relax it and place multiple
3890 instructions/literals onto the stack. Return FALSE if no error. */
3891
3892 static bfd_boolean
xg_expand_assembly_insn(IStack * istack,TInsn * orig_insn)3893 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
3894 {
3895 int noperands;
3896 TInsn new_insn;
3897 bfd_boolean do_expand;
3898
3899 memset (&new_insn, 0, sizeof (TInsn));
3900
3901 /* Narrow it if we can. xg_simplify_insn now does all the
3902 appropriate checking (e.g., for the density option). */
3903 if (xg_simplify_insn (orig_insn, &new_insn))
3904 orig_insn = &new_insn;
3905
3906 noperands = xtensa_opcode_num_operands (xtensa_default_isa,
3907 orig_insn->opcode);
3908 if (orig_insn->ntok < noperands)
3909 {
3910 as_bad (_("found %d operands for '%s': Expected %d"),
3911 orig_insn->ntok,
3912 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3913 noperands);
3914 return TRUE;
3915 }
3916 if (orig_insn->ntok > noperands)
3917 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3918 orig_insn->ntok,
3919 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3920 noperands);
3921
3922 /* If there are not enough operands, we will assert above. If there
3923 are too many, just cut out the extras here. */
3924 orig_insn->ntok = noperands;
3925
3926 if (tinsn_has_invalid_symbolic_operands (orig_insn))
3927 return TRUE;
3928
3929 /* If the instruction will definitely need to be relaxed, it is better
3930 to expand it now for better scheduling. Decide whether to expand
3931 now.... */
3932 do_expand = (!orig_insn->is_specific_opcode && use_transform ());
3933
3934 /* Calls should be expanded to longcalls only in the backend relaxation
3935 so that the assembly scheduler will keep the L32R/CALLX instructions
3936 adjacent. */
3937 if (is_direct_call_opcode (orig_insn->opcode))
3938 do_expand = FALSE;
3939
3940 if (tinsn_has_symbolic_operands (orig_insn))
3941 {
3942 /* The values of symbolic operands are not known yet, so only expand
3943 now if an operand is "complex" (e.g., difference of symbols) and
3944 will have to be stored as a literal regardless of the value. */
3945 if (!tinsn_has_complex_operands (orig_insn))
3946 do_expand = FALSE;
3947 }
3948 else if (xg_immeds_fit (orig_insn))
3949 do_expand = FALSE;
3950
3951 if (do_expand)
3952 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
3953 else
3954 istack_push (istack, orig_insn);
3955
3956 return FALSE;
3957 }
3958
3959
3960 /* Return TRUE if the section flags are marked linkonce
3961 or the name is .gnu.linkonce*. */
3962
3963 static bfd_boolean
get_is_linkonce_section(bfd * abfd ATTRIBUTE_UNUSED,segT sec)3964 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
3965 {
3966 flagword flags, link_once_flags;
3967
3968 flags = bfd_get_section_flags (abfd, sec);
3969 link_once_flags = (flags & SEC_LINK_ONCE);
3970
3971 /* Flags might not be set yet. */
3972 if (!link_once_flags)
3973 {
3974 static size_t len = sizeof ".gnu.linkonce.t.";
3975
3976 if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
3977 link_once_flags = SEC_LINK_ONCE;
3978 }
3979 return (link_once_flags != 0);
3980 }
3981
3982
3983 static void
xtensa_add_literal_sym(symbolS * sym)3984 xtensa_add_literal_sym (symbolS *sym)
3985 {
3986 sym_list *l;
3987
3988 l = (sym_list *) xmalloc (sizeof (sym_list));
3989 l->sym = sym;
3990 l->next = literal_syms;
3991 literal_syms = l;
3992 }
3993
3994
3995 static symbolS *
xtensa_create_literal_symbol(segT sec,fragS * frag)3996 xtensa_create_literal_symbol (segT sec, fragS *frag)
3997 {
3998 static int lit_num = 0;
3999 static char name[256];
4000 symbolS *symbolP;
4001
4002 sprintf (name, ".L_lit_sym%d", lit_num);
4003
4004 /* Create a local symbol. If it is in a linkonce section, we have to
4005 be careful to make sure that if it is used in a relocation that the
4006 symbol will be in the output file. */
4007 if (get_is_linkonce_section (stdoutput, sec))
4008 {
4009 symbolP = symbol_new (name, sec, 0, frag);
4010 S_CLEAR_EXTERNAL (symbolP);
4011 /* symbolP->local = 1; */
4012 }
4013 else
4014 symbolP = symbol_new (name, sec, 0, frag);
4015
4016 xtensa_add_literal_sym (symbolP);
4017
4018 frag->tc_frag_data.is_literal = TRUE;
4019 lit_num++;
4020 return symbolP;
4021 }
4022
4023
4024 /* Currently all literals that are generated here are 32-bit L32R targets. */
4025
4026 static symbolS *
xg_assemble_literal(TInsn * insn)4027 xg_assemble_literal (/* const */ TInsn *insn)
4028 {
4029 emit_state state;
4030 symbolS *lit_sym = NULL;
4031
4032 /* size = 4 for L32R. It could easily be larger when we move to
4033 larger constants. Add a parameter later. */
4034 offsetT litsize = 4;
4035 offsetT litalign = 2; /* 2^2 = 4 */
4036 expressionS saved_loc;
4037 expressionS * emit_val;
4038
4039 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4040
4041 assert (insn->insn_type == ITYPE_LITERAL);
4042 assert (insn->ntok == 1); /* must be only one token here */
4043
4044 xtensa_switch_to_literal_fragment (&state);
4045
4046 emit_val = &insn->tok[0];
4047 if (emit_val->X_op == O_big)
4048 {
4049 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4050 if (size > litsize)
4051 {
4052 /* This happens when someone writes a "movi a2, big_number". */
4053 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4054 _("invalid immediate"));
4055 xtensa_restore_emit_state (&state);
4056 return NULL;
4057 }
4058 }
4059
4060 /* Force a 4-byte align here. Note that this opens a new frag, so all
4061 literals done with this function have a frag to themselves. That's
4062 important for the way text section literals work. */
4063 frag_align (litalign, 0, 0);
4064 record_alignment (now_seg, litalign);
4065
4066 if (emit_val->X_op == O_pltrel)
4067 {
4068 char *p = frag_more (litsize);
4069 xtensa_set_frag_assembly_state (frag_now);
4070 if (emit_val->X_add_symbol)
4071 emit_val->X_op = O_symbol;
4072 else
4073 emit_val->X_op = O_constant;
4074 fix_new_exp (frag_now, p - frag_now->fr_literal,
4075 litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT);
4076 }
4077 else
4078 emit_expr (emit_val, litsize);
4079
4080 assert (frag_now->tc_frag_data.literal_frag == NULL);
4081 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4082 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4083 lit_sym = frag_now->fr_symbol;
4084 frag_now->tc_frag_data.is_literal = TRUE;
4085
4086 /* Go back. */
4087 xtensa_restore_emit_state (&state);
4088 return lit_sym;
4089 }
4090
4091
4092 static void
xg_assemble_literal_space(int size,int slot)4093 xg_assemble_literal_space (/* const */ int size, int slot)
4094 {
4095 emit_state state;
4096 /* We might have to do something about this alignment. It only
4097 takes effect if something is placed here. */
4098 offsetT litalign = 2; /* 2^2 = 4 */
4099 fragS *lit_saved_frag;
4100
4101 assert (size % 4 == 0);
4102
4103 xtensa_switch_to_literal_fragment (&state);
4104
4105 /* Force a 4-byte align here. */
4106 frag_align (litalign, 0, 0);
4107 record_alignment (now_seg, litalign);
4108
4109 xg_force_frag_space (size);
4110
4111 lit_saved_frag = frag_now;
4112 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4113 frag_now->tc_frag_data.is_literal = TRUE;
4114 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4115 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
4116
4117 /* Go back. */
4118 xtensa_restore_emit_state (&state);
4119 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
4120 }
4121
4122
4123 /* Put in a fixup record based on the opcode.
4124 Return TRUE on success. */
4125
4126 static bfd_boolean
xg_add_opcode_fix(TInsn * tinsn,int opnum,xtensa_format fmt,int slot,expressionS * expr,fragS * fragP,offsetT offset)4127 xg_add_opcode_fix (TInsn *tinsn,
4128 int opnum,
4129 xtensa_format fmt,
4130 int slot,
4131 expressionS *expr,
4132 fragS *fragP,
4133 offsetT offset)
4134 {
4135 xtensa_opcode opcode = tinsn->opcode;
4136 bfd_reloc_code_real_type reloc;
4137 reloc_howto_type *howto;
4138 int fmt_length;
4139 fixS *the_fix;
4140
4141 reloc = BFD_RELOC_NONE;
4142
4143 /* First try the special cases for "alternate" relocs. */
4144 if (opcode == xtensa_l32r_opcode)
4145 {
4146 if (fragP->tc_frag_data.use_absolute_literals)
4147 reloc = encode_alt_reloc (slot);
4148 }
4149 else if (opcode == xtensa_const16_opcode)
4150 {
4151 if (expr->X_op == O_lo16)
4152 {
4153 reloc = encode_reloc (slot);
4154 expr->X_op = O_symbol;
4155 }
4156 else if (expr->X_op == O_hi16)
4157 {
4158 reloc = encode_alt_reloc (slot);
4159 expr->X_op = O_symbol;
4160 }
4161 }
4162
4163 if (opnum != get_relaxable_immed (opcode))
4164 {
4165 as_bad (_("invalid relocation for operand %i of '%s'"),
4166 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4167 return FALSE;
4168 }
4169
4170 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4171 into the symbol table where the generic portions of the assembler
4172 won't know what to do with them. */
4173 if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
4174 {
4175 as_bad (_("invalid expression for operand %i of '%s'"),
4176 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4177 return FALSE;
4178 }
4179
4180 /* Next try the generic relocs. */
4181 if (reloc == BFD_RELOC_NONE)
4182 reloc = encode_reloc (slot);
4183 if (reloc == BFD_RELOC_NONE)
4184 {
4185 as_bad (_("invalid relocation in instruction slot %i"), slot);
4186 return FALSE;
4187 }
4188
4189 howto = bfd_reloc_type_lookup (stdoutput, reloc);
4190 if (!howto)
4191 {
4192 as_bad (_("undefined symbol for opcode \"%s\""),
4193 xtensa_opcode_name (xtensa_default_isa, opcode));
4194 return FALSE;
4195 }
4196
4197 fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4198 the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
4199 howto->pc_relative, reloc);
4200 the_fix->fx_no_overflow = 1;
4201
4202 if (expr->X_add_symbol
4203 && (S_IS_EXTERNAL (expr->X_add_symbol)
4204 || S_IS_WEAK (expr->X_add_symbol)))
4205 the_fix->fx_plt = TRUE;
4206
4207 the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
4208 the_fix->tc_fix_data.X_add_number = expr->X_add_number;
4209 the_fix->tc_fix_data.slot = slot;
4210
4211 return TRUE;
4212 }
4213
4214
4215 static bfd_boolean
xg_emit_insn_to_buf(TInsn * tinsn,xtensa_format fmt,char * buf,fragS * fragP,offsetT offset,bfd_boolean build_fix)4216 xg_emit_insn_to_buf (TInsn *tinsn,
4217 xtensa_format fmt,
4218 char *buf,
4219 fragS *fragP,
4220 offsetT offset,
4221 bfd_boolean build_fix)
4222 {
4223 static xtensa_insnbuf insnbuf = NULL;
4224 bfd_boolean has_symbolic_immed = FALSE;
4225 bfd_boolean ok = TRUE;
4226 if (!insnbuf)
4227 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4228
4229 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4230 if (has_symbolic_immed && build_fix)
4231 {
4232 /* Add a fixup. */
4233 int opnum = get_relaxable_immed (tinsn->opcode);
4234 expressionS *exp = &tinsn->tok[opnum];
4235
4236 if (!xg_add_opcode_fix (tinsn, opnum, fmt, 0, exp, fragP, offset))
4237 ok = FALSE;
4238 }
4239 fragP->tc_frag_data.is_insn = TRUE;
4240 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4241 (unsigned char *) buf, 0);
4242 return ok;
4243 }
4244
4245
4246 static void
xg_resolve_literals(TInsn * insn,symbolS * lit_sym)4247 xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
4248 {
4249 symbolS *sym = get_special_literal_symbol ();
4250 int i;
4251 if (lit_sym == 0)
4252 return;
4253 assert (insn->insn_type == ITYPE_INSN);
4254 for (i = 0; i < insn->ntok; i++)
4255 if (insn->tok[i].X_add_symbol == sym)
4256 insn->tok[i].X_add_symbol = lit_sym;
4257
4258 }
4259
4260
4261 static void
xg_resolve_labels(TInsn * insn,symbolS * label_sym)4262 xg_resolve_labels (TInsn *insn, symbolS *label_sym)
4263 {
4264 symbolS *sym = get_special_label_symbol ();
4265 int i;
4266 /* assert (!insn->is_literal); */
4267 for (i = 0; i < insn->ntok; i++)
4268 if (insn->tok[i].X_add_symbol == sym)
4269 insn->tok[i].X_add_symbol = label_sym;
4270
4271 }
4272
4273
4274 /* Return TRUE if the instruction can write to the specified
4275 integer register. */
4276
4277 static bfd_boolean
is_register_writer(const TInsn * insn,const char * regset,int regnum)4278 is_register_writer (const TInsn *insn, const char *regset, int regnum)
4279 {
4280 int i;
4281 int num_ops;
4282 xtensa_isa isa = xtensa_default_isa;
4283
4284 num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
4285
4286 for (i = 0; i < num_ops; i++)
4287 {
4288 char inout;
4289 inout = xtensa_operand_inout (isa, insn->opcode, i);
4290 if ((inout == 'o' || inout == 'm')
4291 && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
4292 {
4293 xtensa_regfile opnd_rf =
4294 xtensa_operand_regfile (isa, insn->opcode, i);
4295 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
4296 {
4297 if ((insn->tok[i].X_op == O_register)
4298 && (insn->tok[i].X_add_number == regnum))
4299 return TRUE;
4300 }
4301 }
4302 }
4303 return FALSE;
4304 }
4305
4306
4307 static bfd_boolean
is_bad_loopend_opcode(const TInsn * tinsn)4308 is_bad_loopend_opcode (const TInsn *tinsn)
4309 {
4310 xtensa_opcode opcode = tinsn->opcode;
4311
4312 if (opcode == XTENSA_UNDEFINED)
4313 return FALSE;
4314
4315 if (opcode == xtensa_call0_opcode
4316 || opcode == xtensa_callx0_opcode
4317 || opcode == xtensa_call4_opcode
4318 || opcode == xtensa_callx4_opcode
4319 || opcode == xtensa_call8_opcode
4320 || opcode == xtensa_callx8_opcode
4321 || opcode == xtensa_call12_opcode
4322 || opcode == xtensa_callx12_opcode
4323 || opcode == xtensa_isync_opcode
4324 || opcode == xtensa_ret_opcode
4325 || opcode == xtensa_ret_n_opcode
4326 || opcode == xtensa_retw_opcode
4327 || opcode == xtensa_retw_n_opcode
4328 || opcode == xtensa_waiti_opcode
4329 || opcode == xtensa_rsr_lcount_opcode)
4330 return TRUE;
4331
4332 return FALSE;
4333 }
4334
4335
4336 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4337 This allows the debugger to add unaligned labels.
4338 Also, the assembler generates stabs labels that need
4339 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4340
4341 static bfd_boolean
is_unaligned_label(symbolS * sym)4342 is_unaligned_label (symbolS *sym)
4343 {
4344 const char *name = S_GET_NAME (sym);
4345 static size_t fake_size = 0;
4346
4347 if (name
4348 && name[0] == '.'
4349 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4350 return TRUE;
4351
4352 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4353 if (fake_size == 0)
4354 fake_size = strlen (FAKE_LABEL_NAME);
4355
4356 if (name
4357 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4358 && (name[fake_size] == 'F'
4359 || name[fake_size] == 'L'
4360 || (name[fake_size] == 'e'
4361 && strncmp ("endfunc", name+fake_size, 7) == 0)))
4362 return TRUE;
4363
4364 return FALSE;
4365 }
4366
4367
4368 static fragS *
next_non_empty_frag(const fragS * fragP)4369 next_non_empty_frag (const fragS *fragP)
4370 {
4371 fragS *next_fragP = fragP->fr_next;
4372
4373 /* Sometimes an empty will end up here due storage allocation issues.
4374 So we have to skip until we find something legit. */
4375 while (next_fragP && next_fragP->fr_fix == 0)
4376 next_fragP = next_fragP->fr_next;
4377
4378 if (next_fragP == NULL || next_fragP->fr_fix == 0)
4379 return NULL;
4380
4381 return next_fragP;
4382 }
4383
4384
4385 static bfd_boolean
next_frag_opcode_is_loop(const fragS * fragP,xtensa_opcode * opcode)4386 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
4387 {
4388 xtensa_opcode out_opcode;
4389 const fragS *next_fragP = next_non_empty_frag (fragP);
4390
4391 if (next_fragP == NULL)
4392 return FALSE;
4393
4394 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4395 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4396 {
4397 *opcode = out_opcode;
4398 return TRUE;
4399 }
4400 return FALSE;
4401 }
4402
4403
4404 static int
frag_format_size(const fragS * fragP)4405 frag_format_size (const fragS *fragP)
4406 {
4407 static xtensa_insnbuf insnbuf = NULL;
4408 xtensa_isa isa = xtensa_default_isa;
4409 xtensa_format fmt;
4410 int fmt_size;
4411
4412 if (!insnbuf)
4413 insnbuf = xtensa_insnbuf_alloc (isa);
4414
4415 if (fragP == NULL)
4416 return XTENSA_UNDEFINED;
4417
4418 xtensa_insnbuf_from_chars (isa, insnbuf,
4419 (unsigned char *) fragP->fr_literal, 0);
4420
4421 fmt = xtensa_format_decode (isa, insnbuf);
4422 if (fmt == XTENSA_UNDEFINED)
4423 return XTENSA_UNDEFINED;
4424 fmt_size = xtensa_format_length (isa, fmt);
4425
4426 /* If the next format won't be changing due to relaxation, just
4427 return the length of the first format. */
4428 if (fragP->fr_opcode != fragP->fr_literal)
4429 return fmt_size;
4430
4431 /* If during relaxation we have to pull an instruction out of a
4432 multi-slot instruction, we will return the more conservative
4433 number. This works because alignment on bigger instructions
4434 is more restrictive than alignment on smaller instructions.
4435 This is more conservative than we would like, but it happens
4436 infrequently. */
4437
4438 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4439 return fmt_size;
4440
4441 /* If we aren't doing one of our own relaxations or it isn't
4442 slot-based, then the insn size won't change. */
4443 if (fragP->fr_type != rs_machine_dependent)
4444 return fmt_size;
4445 if (fragP->fr_subtype != RELAX_SLOTS)
4446 return fmt_size;
4447
4448 /* If an instruction is about to grow, return the longer size. */
4449 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4450 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
4451 return 3;
4452
4453 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4454 return 2 + fragP->tc_frag_data.text_expansion[0];
4455
4456 return fmt_size;
4457 }
4458
4459
4460 static int
next_frag_format_size(const fragS * fragP)4461 next_frag_format_size (const fragS *fragP)
4462 {
4463 const fragS *next_fragP = next_non_empty_frag (fragP);
4464 return frag_format_size (next_fragP);
4465 }
4466
4467
4468 /* If the next legit fragment is an end-of-loop marker,
4469 switch its state so it will instantiate a NOP. */
4470
4471 static void
update_next_frag_state(fragS * fragP)4472 update_next_frag_state (fragS *fragP)
4473 {
4474 fragS *next_fragP = fragP->fr_next;
4475 fragS *new_target = NULL;
4476
4477 if (align_targets)
4478 {
4479 /* We are guaranteed there will be one of these... */
4480 while (!(next_fragP->fr_type == rs_machine_dependent
4481 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4482 || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4483 next_fragP = next_fragP->fr_next;
4484
4485 assert (next_fragP->fr_type == rs_machine_dependent
4486 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4487 || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4488
4489 /* ...and one of these. */
4490 new_target = next_fragP->fr_next;
4491 while (!(new_target->fr_type == rs_machine_dependent
4492 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4493 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4494 new_target = new_target->fr_next;
4495
4496 assert (new_target->fr_type == rs_machine_dependent
4497 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4498 || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4499 }
4500
4501 while (next_fragP && next_fragP->fr_fix == 0)
4502 {
4503 if (next_fragP->fr_type == rs_machine_dependent
4504 && next_fragP->fr_subtype == RELAX_LOOP_END)
4505 {
4506 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4507 return;
4508 }
4509
4510 next_fragP = next_fragP->fr_next;
4511 }
4512 }
4513
4514
4515 static bfd_boolean
next_frag_is_branch_target(const fragS * fragP)4516 next_frag_is_branch_target (const fragS *fragP)
4517 {
4518 /* Sometimes an empty will end up here due to storage allocation issues,
4519 so we have to skip until we find something legit. */
4520 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4521 {
4522 if (fragP->tc_frag_data.is_branch_target)
4523 return TRUE;
4524 if (fragP->fr_fix != 0)
4525 break;
4526 }
4527 return FALSE;
4528 }
4529
4530
4531 static bfd_boolean
next_frag_is_loop_target(const fragS * fragP)4532 next_frag_is_loop_target (const fragS *fragP)
4533 {
4534 /* Sometimes an empty will end up here due storage allocation issues.
4535 So we have to skip until we find something legit. */
4536 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4537 {
4538 if (fragP->tc_frag_data.is_loop_target)
4539 return TRUE;
4540 if (fragP->fr_fix != 0)
4541 break;
4542 }
4543 return FALSE;
4544 }
4545
4546
4547 static addressT
next_frag_pre_opcode_bytes(const fragS * fragp)4548 next_frag_pre_opcode_bytes (const fragS *fragp)
4549 {
4550 const fragS *next_fragp = fragp->fr_next;
4551 xtensa_opcode next_opcode;
4552
4553 if (!next_frag_opcode_is_loop (fragp, &next_opcode))
4554 return 0;
4555
4556 /* Sometimes an empty will end up here due to storage allocation issues,
4557 so we have to skip until we find something legit. */
4558 while (next_fragp->fr_fix == 0)
4559 next_fragp = next_fragp->fr_next;
4560
4561 if (next_fragp->fr_type != rs_machine_dependent)
4562 return 0;
4563
4564 /* There is some implicit knowledge encoded in here.
4565 The LOOP instructions that are NOT RELAX_IMMED have
4566 been relaxed. Note that we can assume that the LOOP
4567 instruction is in slot 0 because loops aren't bundleable. */
4568 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
4569 return get_expanded_loop_offset (next_opcode);
4570
4571 return 0;
4572 }
4573
4574
4575 /* Mark a location where we can later insert literal frags. Update
4576 the section's literal_pool_loc, so subsequent literals can be
4577 placed nearest to their use. */
4578
4579 static void
xtensa_mark_literal_pool_location(void)4580 xtensa_mark_literal_pool_location (void)
4581 {
4582 /* Any labels pointing to the current location need
4583 to be adjusted to after the literal pool. */
4584 emit_state s;
4585 fragS *pool_location;
4586
4587 if (use_literal_section && !directive_state[directive_absolute_literals])
4588 return;
4589
4590 frag_align (2, 0, 0);
4591 record_alignment (now_seg, 2);
4592
4593 /* We stash info in these frags so we can later move the literal's
4594 fixes into this frchain's fix list. */
4595 pool_location = frag_now;
4596 frag_now->tc_frag_data.lit_frchain = frchain_now;
4597 frag_variant (rs_machine_dependent, 0, 0,
4598 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
4599 xtensa_set_frag_assembly_state (frag_now);
4600 frag_now->tc_frag_data.lit_seg = now_seg;
4601 frag_variant (rs_machine_dependent, 0, 0,
4602 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
4603 xtensa_set_frag_assembly_state (frag_now);
4604
4605 /* Now put a frag into the literal pool that points to this location. */
4606 set_literal_pool_location (now_seg, pool_location);
4607 xtensa_switch_to_non_abs_literal_fragment (&s);
4608 frag_align (2, 0, 0);
4609 record_alignment (now_seg, 2);
4610
4611 /* Close whatever frag is there. */
4612 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4613 xtensa_set_frag_assembly_state (frag_now);
4614 frag_now->tc_frag_data.literal_frag = pool_location;
4615 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4616 xtensa_restore_emit_state (&s);
4617 xtensa_set_frag_assembly_state (frag_now);
4618 }
4619
4620
4621 /* Build a nop of the correct size into tinsn. */
4622
4623 static void
build_nop(TInsn * tinsn,int size)4624 build_nop (TInsn *tinsn, int size)
4625 {
4626 tinsn_init (tinsn);
4627 switch (size)
4628 {
4629 case 2:
4630 tinsn->opcode = xtensa_nop_n_opcode;
4631 tinsn->ntok = 0;
4632 if (tinsn->opcode == XTENSA_UNDEFINED)
4633 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4634 break;
4635
4636 case 3:
4637 if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4638 {
4639 tinsn->opcode = xtensa_or_opcode;
4640 set_expr_const (&tinsn->tok[0], 1);
4641 set_expr_const (&tinsn->tok[1], 1);
4642 set_expr_const (&tinsn->tok[2], 1);
4643 tinsn->ntok = 3;
4644 }
4645 else
4646 tinsn->opcode = xtensa_nop_opcode;
4647
4648 assert (tinsn->opcode != XTENSA_UNDEFINED);
4649 }
4650 }
4651
4652
4653 /* Assemble a NOP of the requested size in the buffer. User must have
4654 allocated "buf" with at least "size" bytes. */
4655
4656 static void
assemble_nop(int size,char * buf)4657 assemble_nop (int size, char *buf)
4658 {
4659 static xtensa_insnbuf insnbuf = NULL;
4660 TInsn tinsn;
4661
4662 build_nop (&tinsn, size);
4663
4664 if (!insnbuf)
4665 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4666
4667 tinsn_to_insnbuf (&tinsn, insnbuf);
4668 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4669 (unsigned char *) buf, 0);
4670 }
4671
4672
4673 /* Return the number of bytes for the offset of the expanded loop
4674 instruction. This should be incorporated into the relaxation
4675 specification but is hard-coded here. This is used to auto-align
4676 the loop instruction. It is invalid to call this function if the
4677 configuration does not have loops or if the opcode is not a loop
4678 opcode. */
4679
4680 static addressT
get_expanded_loop_offset(xtensa_opcode opcode)4681 get_expanded_loop_offset (xtensa_opcode opcode)
4682 {
4683 /* This is the OFFSET of the loop instruction in the expanded loop.
4684 This MUST correspond directly to the specification of the loop
4685 expansion. It will be validated on fragment conversion. */
4686 assert (opcode != XTENSA_UNDEFINED);
4687 if (opcode == xtensa_loop_opcode)
4688 return 0;
4689 if (opcode == xtensa_loopnez_opcode)
4690 return 3;
4691 if (opcode == xtensa_loopgtz_opcode)
4692 return 6;
4693 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4694 return 0;
4695 }
4696
4697
4698 static fragS *
get_literal_pool_location(segT seg)4699 get_literal_pool_location (segT seg)
4700 {
4701 return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4702 }
4703
4704
4705 static void
set_literal_pool_location(segT seg,fragS * literal_pool_loc)4706 set_literal_pool_location (segT seg, fragS *literal_pool_loc)
4707 {
4708 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4709 }
4710
4711
4712 /* Set frag assembly state should be called when a new frag is
4713 opened and after a frag has been closed. */
4714
4715 static void
xtensa_set_frag_assembly_state(fragS * fragP)4716 xtensa_set_frag_assembly_state (fragS *fragP)
4717 {
4718 if (!density_supported)
4719 fragP->tc_frag_data.is_no_density = TRUE;
4720
4721 /* This function is called from subsegs_finish, which is called
4722 after xtensa_end, so we can't use "use_transform" or
4723 "use_schedule" here. */
4724 if (!directive_state[directive_transform])
4725 fragP->tc_frag_data.is_no_transform = TRUE;
4726 if (directive_state[directive_longcalls])
4727 fragP->tc_frag_data.use_longcalls = TRUE;
4728 fragP->tc_frag_data.use_absolute_literals =
4729 directive_state[directive_absolute_literals];
4730 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4731 }
4732
4733
4734 static bfd_boolean
relaxable_section(asection * sec)4735 relaxable_section (asection *sec)
4736 {
4737 return (sec->flags & SEC_DEBUGGING) == 0;
4738 }
4739
4740
4741 static void
xtensa_find_unmarked_state_frags(void)4742 xtensa_find_unmarked_state_frags (void)
4743 {
4744 segT *seclist;
4745
4746 /* Walk over each fragment of all of the current segments. For each
4747 unmarked fragment, mark it with the same info as the previous
4748 fragment. */
4749 for (seclist = &stdoutput->sections;
4750 seclist && *seclist;
4751 seclist = &(*seclist)->next)
4752 {
4753 segT sec = *seclist;
4754 segment_info_type *seginfo;
4755 fragS *fragP;
4756 flagword flags;
4757 flags = bfd_get_section_flags (stdoutput, sec);
4758 if (flags & SEC_DEBUGGING)
4759 continue;
4760 if (!(flags & SEC_ALLOC))
4761 continue;
4762
4763 seginfo = seg_info (sec);
4764 if (seginfo && seginfo->frchainP)
4765 {
4766 fragS *last_fragP = 0;
4767 for (fragP = seginfo->frchainP->frch_root; fragP;
4768 fragP = fragP->fr_next)
4769 {
4770 if (fragP->fr_fix != 0
4771 && !fragP->tc_frag_data.is_assembly_state_set)
4772 {
4773 if (last_fragP == 0)
4774 {
4775 as_warn_where (fragP->fr_file, fragP->fr_line,
4776 _("assembly state not set for first frag in section %s"),
4777 sec->name);
4778 }
4779 else
4780 {
4781 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4782 fragP->tc_frag_data.is_no_density =
4783 last_fragP->tc_frag_data.is_no_density;
4784 fragP->tc_frag_data.is_no_transform =
4785 last_fragP->tc_frag_data.is_no_transform;
4786 fragP->tc_frag_data.use_longcalls =
4787 last_fragP->tc_frag_data.use_longcalls;
4788 fragP->tc_frag_data.use_absolute_literals =
4789 last_fragP->tc_frag_data.use_absolute_literals;
4790 }
4791 }
4792 if (fragP->tc_frag_data.is_assembly_state_set)
4793 last_fragP = fragP;
4794 }
4795 }
4796 }
4797 }
4798
4799
4800 static void
xtensa_find_unaligned_branch_targets(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,void * unused ATTRIBUTE_UNUSED)4801 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
4802 asection *sec,
4803 void *unused ATTRIBUTE_UNUSED)
4804 {
4805 flagword flags = bfd_get_section_flags (abfd, sec);
4806 segment_info_type *seginfo = seg_info (sec);
4807 fragS *frag = seginfo->frchainP->frch_root;
4808
4809 if (flags & SEC_CODE)
4810 {
4811 xtensa_isa isa = xtensa_default_isa;
4812 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4813 while (frag != NULL)
4814 {
4815 if (frag->tc_frag_data.is_branch_target)
4816 {
4817 int op_size;
4818 addressT branch_align, frag_addr;
4819 xtensa_format fmt;
4820
4821 xtensa_insnbuf_from_chars
4822 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
4823 fmt = xtensa_format_decode (isa, insnbuf);
4824 op_size = xtensa_format_length (isa, fmt);
4825 branch_align = 1 << branch_align_power (sec);
4826 frag_addr = frag->fr_address % branch_align;
4827 if (frag_addr + op_size > branch_align)
4828 as_warn_where (frag->fr_file, frag->fr_line,
4829 _("unaligned branch target: %d bytes at 0x%lx"),
4830 op_size, (long) frag->fr_address);
4831 }
4832 frag = frag->fr_next;
4833 }
4834 xtensa_insnbuf_free (isa, insnbuf);
4835 }
4836 }
4837
4838
4839 static void
xtensa_find_unaligned_loops(bfd * abfd ATTRIBUTE_UNUSED,asection * sec,void * unused ATTRIBUTE_UNUSED)4840 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
4841 asection *sec,
4842 void *unused ATTRIBUTE_UNUSED)
4843 {
4844 flagword flags = bfd_get_section_flags (abfd, sec);
4845 segment_info_type *seginfo = seg_info (sec);
4846 fragS *frag = seginfo->frchainP->frch_root;
4847 xtensa_isa isa = xtensa_default_isa;
4848
4849 if (flags & SEC_CODE)
4850 {
4851 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4852 while (frag != NULL)
4853 {
4854 if (frag->tc_frag_data.is_first_loop_insn)
4855 {
4856 int op_size;
4857 addressT frag_addr;
4858 xtensa_format fmt;
4859
4860 xtensa_insnbuf_from_chars
4861 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
4862 fmt = xtensa_format_decode (isa, insnbuf);
4863 op_size = xtensa_format_length (isa, fmt);
4864 frag_addr = frag->fr_address % xtensa_fetch_width;
4865
4866 if (frag_addr + op_size > xtensa_fetch_width)
4867 as_warn_where (frag->fr_file, frag->fr_line,
4868 _("unaligned loop: %d bytes at 0x%lx"),
4869 op_size, (long) frag->fr_address);
4870 }
4871 frag = frag->fr_next;
4872 }
4873 xtensa_insnbuf_free (isa, insnbuf);
4874 }
4875 }
4876
4877
4878 static int
xg_apply_fix_value(fixS * fixP,valueT val)4879 xg_apply_fix_value (fixS *fixP, valueT val)
4880 {
4881 xtensa_isa isa = xtensa_default_isa;
4882 static xtensa_insnbuf insnbuf = NULL;
4883 static xtensa_insnbuf slotbuf = NULL;
4884 xtensa_format fmt;
4885 int slot;
4886 bfd_boolean alt_reloc;
4887 xtensa_opcode opcode;
4888 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
4889
4890 (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc);
4891 if (alt_reloc)
4892 as_fatal (_("unexpected fix"));
4893
4894 if (!insnbuf)
4895 {
4896 insnbuf = xtensa_insnbuf_alloc (isa);
4897 slotbuf = xtensa_insnbuf_alloc (isa);
4898 }
4899
4900 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
4901 fmt = xtensa_format_decode (isa, insnbuf);
4902 if (fmt == XTENSA_UNDEFINED)
4903 as_fatal (_("undecodable fix"));
4904 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
4905 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
4906 if (opcode == XTENSA_UNDEFINED)
4907 as_fatal (_("undecodable fix"));
4908
4909 /* CONST16 immediates are not PC-relative, despite the fact that we
4910 reuse the normal PC-relative operand relocations for the low part
4911 of a CONST16 operand. */
4912 if (opcode == xtensa_const16_opcode)
4913 return 0;
4914
4915 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
4916 get_relaxable_immed (opcode), val,
4917 fixP->fx_file, fixP->fx_line);
4918
4919 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
4920 xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
4921
4922 return 1;
4923 }
4924
4925
4926 /* External Functions and Other GAS Hooks. */
4927
4928 const char *
xtensa_target_format(void)4929 xtensa_target_format (void)
4930 {
4931 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
4932 }
4933
4934
4935 void
xtensa_file_arch_init(bfd * abfd)4936 xtensa_file_arch_init (bfd *abfd)
4937 {
4938 bfd_set_private_flags (abfd, 0x100 | 0x200);
4939 }
4940
4941
4942 void
md_number_to_chars(char * buf,valueT val,int n)4943 md_number_to_chars (char *buf, valueT val, int n)
4944 {
4945 if (target_big_endian)
4946 number_to_chars_bigendian (buf, val, n);
4947 else
4948 number_to_chars_littleendian (buf, val, n);
4949 }
4950
4951
4952 /* This function is called once, at assembler startup time. It should
4953 set up all the tables, etc. that the MD part of the assembler will
4954 need. */
4955
4956 void
md_begin(void)4957 md_begin (void)
4958 {
4959 segT current_section = now_seg;
4960 int current_subsec = now_subseg;
4961 xtensa_isa isa;
4962
4963 xtensa_default_isa = xtensa_isa_init (0, 0);
4964 isa = xtensa_default_isa;
4965
4966 linkrelax = 1;
4967
4968 /* Set up the .literal, .fini.literal and .init.literal sections. */
4969 memset (&default_lit_sections, 0, sizeof (default_lit_sections));
4970 default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME;
4971 default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME;
4972 default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME;
4973 default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME;
4974
4975 subseg_set (current_section, current_subsec);
4976
4977 xg_init_vinsn (&cur_vinsn);
4978
4979 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
4980 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
4981 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
4982 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
4983 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
4984 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
4985 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
4986 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
4987 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
4988 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
4989 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
4990 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
4991 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
4992 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
4993 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
4994 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
4995 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
4996 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
4997 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
4998 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
4999 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
5000 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5001 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5002 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5003 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5004 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5005 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
5006 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
5007 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
5008
5009 init_op_placement_info_table ();
5010
5011 /* Set up the assembly state. */
5012 if (!frag_now->tc_frag_data.is_assembly_state_set)
5013 xtensa_set_frag_assembly_state (frag_now);
5014 }
5015
5016
5017 /* TC_INIT_FIX_DATA hook */
5018
5019 void
xtensa_init_fix_data(fixS * x)5020 xtensa_init_fix_data (fixS *x)
5021 {
5022 x->tc_fix_data.slot = 0;
5023 x->tc_fix_data.X_add_symbol = NULL;
5024 x->tc_fix_data.X_add_number = 0;
5025 }
5026
5027
5028 /* tc_frob_label hook */
5029
5030 void
xtensa_frob_label(symbolS * sym)5031 xtensa_frob_label (symbolS *sym)
5032 {
5033 float freq = get_subseg_target_freq (now_seg, now_subseg);
5034
5035 /* Since the label was already attached to a frag associated with the
5036 previous basic block, it now needs to be reset to the current frag. */
5037 symbol_set_frag (sym, frag_now);
5038 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5039
5040 if (generating_literals)
5041 xtensa_add_literal_sym (sym);
5042 else
5043 xtensa_add_insn_label (sym);
5044
5045 if (symbol_get_tc (sym)->is_loop_target)
5046 {
5047 if ((get_last_insn_flags (now_seg, now_subseg)
5048 & FLAG_IS_BAD_LOOPEND) != 0)
5049 as_bad (_("invalid last instruction for a zero-overhead loop"));
5050
5051 xtensa_set_frag_assembly_state (frag_now);
5052 frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END,
5053 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5054
5055 xtensa_set_frag_assembly_state (frag_now);
5056 xtensa_move_labels (frag_now, 0, TRUE);
5057 }
5058
5059 /* No target aligning in the absolute section. */
5060 if (now_seg != absolute_section
5061 && do_align_targets ()
5062 && !is_unaligned_label (sym)
5063 && !generating_literals)
5064 {
5065 xtensa_set_frag_assembly_state (frag_now);
5066
5067 frag_var (rs_machine_dependent,
5068 0, (int) freq,
5069 RELAX_DESIRE_ALIGN_IF_TARGET,
5070 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5071 xtensa_set_frag_assembly_state (frag_now);
5072 xtensa_move_labels (frag_now, 0, TRUE);
5073 }
5074
5075 /* We need to mark the following properties even if we aren't aligning. */
5076
5077 /* If the label is already known to be a branch target, i.e., a
5078 forward branch, mark the frag accordingly. Backward branches
5079 are handled by xg_add_branch_and_loop_targets. */
5080 if (symbol_get_tc (sym)->is_branch_target)
5081 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5082
5083 /* Loops only go forward, so they can be identified here. */
5084 if (symbol_get_tc (sym)->is_loop_target)
5085 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5086 }
5087
5088
5089 /* tc_unrecognized_line hook */
5090
5091 int
xtensa_unrecognized_line(int ch)5092 xtensa_unrecognized_line (int ch)
5093 {
5094 switch (ch)
5095 {
5096 case '{' :
5097 if (cur_vinsn.inside_bundle == 0)
5098 {
5099 /* PR8110: Cannot emit line number info inside a FLIX bundle
5100 when using --gstabs. Temporarily disable debug info. */
5101 generate_lineno_debug ();
5102 if (debug_type == DEBUG_STABS)
5103 {
5104 xt_saved_debug_type = debug_type;
5105 debug_type = DEBUG_NONE;
5106 }
5107
5108 cur_vinsn.inside_bundle = 1;
5109 }
5110 else
5111 {
5112 as_bad (_("extra opening brace"));
5113 return 0;
5114 }
5115 break;
5116
5117 case '}' :
5118 if (cur_vinsn.inside_bundle)
5119 finish_vinsn (&cur_vinsn);
5120 else
5121 {
5122 as_bad (_("extra closing brace"));
5123 return 0;
5124 }
5125 break;
5126 default:
5127 as_bad (_("syntax error"));
5128 return 0;
5129 }
5130 return 1;
5131 }
5132
5133
5134 /* md_flush_pending_output hook */
5135
5136 void
xtensa_flush_pending_output(void)5137 xtensa_flush_pending_output (void)
5138 {
5139 if (cur_vinsn.inside_bundle)
5140 as_bad (_("missing closing brace"));
5141
5142 /* If there is a non-zero instruction fragment, close it. */
5143 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5144 {
5145 frag_wane (frag_now);
5146 frag_new (0);
5147 xtensa_set_frag_assembly_state (frag_now);
5148 }
5149 frag_now->tc_frag_data.is_insn = FALSE;
5150
5151 xtensa_clear_insn_labels ();
5152 }
5153
5154
5155 /* We had an error while parsing an instruction. The string might look
5156 like this: "insn arg1, arg2 }". If so, we need to see the closing
5157 brace and reset some fields. Otherwise, the vinsn never gets closed
5158 and the num_slots field will grow past the end of the array of slots,
5159 and bad things happen. */
5160
5161 static void
error_reset_cur_vinsn(void)5162 error_reset_cur_vinsn (void)
5163 {
5164 if (cur_vinsn.inside_bundle)
5165 {
5166 if (*input_line_pointer == '}'
5167 || *(input_line_pointer - 1) == '}'
5168 || *(input_line_pointer - 2) == '}')
5169 xg_clear_vinsn (&cur_vinsn);
5170 }
5171 }
5172
5173
5174 void
md_assemble(char * str)5175 md_assemble (char *str)
5176 {
5177 xtensa_isa isa = xtensa_default_isa;
5178 char *opname;
5179 unsigned opnamelen;
5180 bfd_boolean has_underbar = FALSE;
5181 char *arg_strings[MAX_INSN_ARGS];
5182 int num_args;
5183 TInsn orig_insn; /* Original instruction from the input. */
5184
5185 tinsn_init (&orig_insn);
5186
5187 /* Split off the opcode. */
5188 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5189 opname = xmalloc (opnamelen + 1);
5190 memcpy (opname, str, opnamelen);
5191 opname[opnamelen] = '\0';
5192
5193 num_args = tokenize_arguments (arg_strings, str + opnamelen);
5194 if (num_args == -1)
5195 {
5196 as_bad (_("syntax error"));
5197 return;
5198 }
5199
5200 if (xg_translate_idioms (&opname, &num_args, arg_strings))
5201 return;
5202
5203 /* Check for an underbar prefix. */
5204 if (*opname == '_')
5205 {
5206 has_underbar = TRUE;
5207 opname += 1;
5208 }
5209
5210 orig_insn.insn_type = ITYPE_INSN;
5211 orig_insn.ntok = 0;
5212 orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
5213
5214 orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5215 if (orig_insn.opcode == XTENSA_UNDEFINED)
5216 {
5217 xtensa_format fmt = xtensa_format_lookup (isa, opname);
5218 if (fmt == XTENSA_UNDEFINED)
5219 {
5220 as_bad (_("unknown opcode or format name '%s'"), opname);
5221 error_reset_cur_vinsn ();
5222 return;
5223 }
5224 if (!cur_vinsn.inside_bundle)
5225 {
5226 as_bad (_("format names only valid inside bundles"));
5227 error_reset_cur_vinsn ();
5228 return;
5229 }
5230 if (cur_vinsn.format != XTENSA_UNDEFINED)
5231 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5232 opname);
5233 cur_vinsn.format = fmt;
5234 free (has_underbar ? opname - 1 : opname);
5235 error_reset_cur_vinsn ();
5236 return;
5237 }
5238
5239 /* Parse the arguments. */
5240 if (parse_arguments (&orig_insn, num_args, arg_strings))
5241 {
5242 as_bad (_("syntax error"));
5243 error_reset_cur_vinsn ();
5244 return;
5245 }
5246
5247 /* Free the opcode and argument strings, now that they've been parsed. */
5248 free (has_underbar ? opname - 1 : opname);
5249 opname = 0;
5250 while (num_args-- > 0)
5251 free (arg_strings[num_args]);
5252
5253 /* Get expressions for invisible operands. */
5254 if (get_invisible_operands (&orig_insn))
5255 {
5256 error_reset_cur_vinsn ();
5257 return;
5258 }
5259
5260 /* Check for the right number and type of arguments. */
5261 if (tinsn_check_arguments (&orig_insn))
5262 {
5263 error_reset_cur_vinsn ();
5264 return;
5265 }
5266
5267 dwarf2_where (&orig_insn.loc);
5268
5269 xg_add_branch_and_loop_targets (&orig_insn);
5270
5271 /* Special-case for "entry" instruction. */
5272 if (orig_insn.opcode == xtensa_entry_opcode)
5273 {
5274 /* Check that the third opcode (#2) is >= 16. */
5275 if (orig_insn.ntok >= 3)
5276 {
5277 expressionS *exp = &orig_insn.tok[2];
5278 switch (exp->X_op)
5279 {
5280 case O_constant:
5281 if (exp->X_add_number < 16)
5282 as_warn (_("entry instruction with stack decrement < 16"));
5283 break;
5284
5285 default:
5286 as_warn (_("entry instruction with non-constant decrement"));
5287 }
5288 }
5289 }
5290
5291 /* Finish it off:
5292 assemble_tokens (opcode, tok, ntok);
5293 expand the tokens from the orig_insn into the
5294 stack of instructions that will not expand
5295 unless required at relaxation time. */
5296
5297 if (!cur_vinsn.inside_bundle)
5298 emit_single_op (&orig_insn);
5299 else /* We are inside a bundle. */
5300 {
5301 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5302 cur_vinsn.num_slots++;
5303 if (*input_line_pointer == '}'
5304 || *(input_line_pointer - 1) == '}'
5305 || *(input_line_pointer - 2) == '}')
5306 finish_vinsn (&cur_vinsn);
5307 }
5308
5309 /* We've just emitted a new instruction so clear the list of labels. */
5310 xtensa_clear_insn_labels ();
5311 }
5312
5313
5314 /* HANDLE_ALIGN hook */
5315
5316 /* For a .align directive, we mark the previous block with the alignment
5317 information. This will be placed in the object file in the
5318 property section corresponding to this section. */
5319
5320 void
xtensa_handle_align(fragS * fragP)5321 xtensa_handle_align (fragS *fragP)
5322 {
5323 if (linkrelax
5324 && ! fragP->tc_frag_data.is_literal
5325 && (fragP->fr_type == rs_align
5326 || fragP->fr_type == rs_align_code)
5327 && fragP->fr_address + fragP->fr_fix > 0
5328 && fragP->fr_offset > 0
5329 && now_seg != bss_section)
5330 {
5331 fragP->tc_frag_data.is_align = TRUE;
5332 fragP->tc_frag_data.alignment = fragP->fr_offset;
5333 }
5334
5335 if (fragP->fr_type == rs_align_test)
5336 {
5337 int count;
5338 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5339 if (count != 0)
5340 as_bad_where (fragP->fr_file, fragP->fr_line,
5341 _("unaligned entry instruction"));
5342 }
5343 }
5344
5345
5346 /* TC_FRAG_INIT hook */
5347
5348 void
xtensa_frag_init(fragS * frag)5349 xtensa_frag_init (fragS *frag)
5350 {
5351 xtensa_set_frag_assembly_state (frag);
5352 }
5353
5354
5355 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)5356 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5357 {
5358 return NULL;
5359 }
5360
5361
5362 /* Round up a section size to the appropriate boundary. */
5363
5364 valueT
md_section_align(segT segment ATTRIBUTE_UNUSED,valueT size)5365 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5366 {
5367 return size; /* Byte alignment is fine. */
5368 }
5369
5370
5371 long
md_pcrel_from(fixS * fixP)5372 md_pcrel_from (fixS *fixP)
5373 {
5374 char *insn_p;
5375 static xtensa_insnbuf insnbuf = NULL;
5376 static xtensa_insnbuf slotbuf = NULL;
5377 int opnum;
5378 uint32 opnd_value;
5379 xtensa_opcode opcode;
5380 xtensa_format fmt;
5381 int slot;
5382 xtensa_isa isa = xtensa_default_isa;
5383 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
5384 bfd_boolean alt_reloc;
5385
5386 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5387 return 0;
5388
5389 if (!insnbuf)
5390 {
5391 insnbuf = xtensa_insnbuf_alloc (isa);
5392 slotbuf = xtensa_insnbuf_alloc (isa);
5393 }
5394
5395 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
5396 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0);
5397 fmt = xtensa_format_decode (isa, insnbuf);
5398
5399 if (fmt == XTENSA_UNDEFINED)
5400 as_fatal (_("bad instruction format"));
5401
5402 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5403 as_fatal (_("invalid relocation"));
5404
5405 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5406 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5407
5408 /* Check for "alternate" relocations (operand not specified). None
5409 of the current uses for these are really PC-relative. */
5410 if (alt_reloc || opcode == xtensa_const16_opcode)
5411 {
5412 if (opcode != xtensa_l32r_opcode
5413 && opcode != xtensa_const16_opcode)
5414 as_fatal (_("invalid relocation for '%s' instruction"),
5415 xtensa_opcode_name (isa, opcode));
5416 return 0;
5417 }
5418
5419 opnum = get_relaxable_immed (opcode);
5420 opnd_value = 0;
5421 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5422 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
5423 {
5424 as_bad_where (fixP->fx_file,
5425 fixP->fx_line,
5426 _("invalid relocation for operand %d of '%s'"),
5427 opnum, xtensa_opcode_name (isa, opcode));
5428 return 0;
5429 }
5430 return 0 - opnd_value;
5431 }
5432
5433
5434 /* TC_FORCE_RELOCATION hook */
5435
5436 int
xtensa_force_relocation(fixS * fix)5437 xtensa_force_relocation (fixS *fix)
5438 {
5439 switch (fix->fx_r_type)
5440 {
5441 case BFD_RELOC_XTENSA_ASM_EXPAND:
5442 case BFD_RELOC_XTENSA_SLOT0_ALT:
5443 case BFD_RELOC_XTENSA_SLOT1_ALT:
5444 case BFD_RELOC_XTENSA_SLOT2_ALT:
5445 case BFD_RELOC_XTENSA_SLOT3_ALT:
5446 case BFD_RELOC_XTENSA_SLOT4_ALT:
5447 case BFD_RELOC_XTENSA_SLOT5_ALT:
5448 case BFD_RELOC_XTENSA_SLOT6_ALT:
5449 case BFD_RELOC_XTENSA_SLOT7_ALT:
5450 case BFD_RELOC_XTENSA_SLOT8_ALT:
5451 case BFD_RELOC_XTENSA_SLOT9_ALT:
5452 case BFD_RELOC_XTENSA_SLOT10_ALT:
5453 case BFD_RELOC_XTENSA_SLOT11_ALT:
5454 case BFD_RELOC_XTENSA_SLOT12_ALT:
5455 case BFD_RELOC_XTENSA_SLOT13_ALT:
5456 case BFD_RELOC_XTENSA_SLOT14_ALT:
5457 return 1;
5458 default:
5459 break;
5460 }
5461
5462 if (linkrelax && fix->fx_addsy
5463 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5464 return 1;
5465
5466 return generic_force_reloc (fix);
5467 }
5468
5469
5470 /* TC_VALIDATE_FIX_SUB hook */
5471
5472 int
xtensa_validate_fix_sub(fixS * fix)5473 xtensa_validate_fix_sub (fixS *fix)
5474 {
5475 segT add_symbol_segment, sub_symbol_segment;
5476
5477 /* The difference of two symbols should be resolved by the assembler when
5478 linkrelax is not set. If the linker may relax the section containing
5479 the symbols, then an Xtensa DIFF relocation must be generated so that
5480 the linker knows to adjust the difference value. */
5481 if (!linkrelax || fix->fx_addsy == NULL)
5482 return 0;
5483
5484 /* Make sure both symbols are in the same segment, and that segment is
5485 "normal" and relaxable. If the segment is not "normal", then the
5486 fix is not valid. If the segment is not "relaxable", then the fix
5487 should have been handled earlier. */
5488 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
5489 if (! SEG_NORMAL (add_symbol_segment) ||
5490 ! relaxable_section (add_symbol_segment))
5491 return 0;
5492 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5493 return (sub_symbol_segment == add_symbol_segment);
5494 }
5495
5496
5497 /* NO_PSEUDO_DOT hook */
5498
5499 /* This function has nothing to do with pseudo dots, but this is the
5500 nearest macro to where the check needs to take place. FIXME: This
5501 seems wrong. */
5502
5503 bfd_boolean
xtensa_check_inside_bundle(void)5504 xtensa_check_inside_bundle (void)
5505 {
5506 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5507 as_bad (_("directives are not valid inside bundles"));
5508
5509 /* This function must always return FALSE because it is called via a
5510 macro that has nothing to do with bundling. */
5511 return FALSE;
5512 }
5513
5514
5515 /* md_elf_section_change_hook */
5516
5517 void
xtensa_elf_section_change_hook(void)5518 xtensa_elf_section_change_hook (void)
5519 {
5520 /* Set up the assembly state. */
5521 if (!frag_now->tc_frag_data.is_assembly_state_set)
5522 xtensa_set_frag_assembly_state (frag_now);
5523 }
5524
5525
5526 /* tc_fix_adjustable hook */
5527
5528 bfd_boolean
xtensa_fix_adjustable(fixS * fixP)5529 xtensa_fix_adjustable (fixS *fixP)
5530 {
5531 /* An offset is not allowed in combination with the difference of two
5532 symbols, but that cannot be easily detected after a local symbol
5533 has been adjusted to a (section+offset) form. Return 0 so that such
5534 an fix will not be adjusted. */
5535 if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset
5536 && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy)))
5537 return 0;
5538
5539 /* We need the symbol name for the VTABLE entries. */
5540 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5541 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5542 return 0;
5543
5544 return 1;
5545 }
5546
5547
5548 void
md_apply_fix(fixS * fixP,valueT * valP,segT seg)5549 md_apply_fix (fixS *fixP, valueT *valP, segT seg)
5550 {
5551 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5552 valueT val;
5553
5554 switch (fixP->fx_r_type)
5555 {
5556 case BFD_RELOC_32:
5557 case BFD_RELOC_16:
5558 case BFD_RELOC_8:
5559 if (linkrelax && fixP->fx_subsy)
5560 {
5561 switch (fixP->fx_r_type)
5562 {
5563 case BFD_RELOC_8:
5564 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5565 break;
5566 case BFD_RELOC_16:
5567 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5568 break;
5569 case BFD_RELOC_32:
5570 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5571 break;
5572 default:
5573 break;
5574 }
5575
5576 /* An offset is only allowed when it results from adjusting a
5577 local symbol into a section-relative offset. If the offset
5578 came from the original expression, tc_fix_adjustable will have
5579 prevented the fix from being converted to a section-relative
5580 form so that we can flag the error here. */
5581 if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy))
5582 as_bad_where (fixP->fx_file, fixP->fx_line,
5583 _("cannot represent subtraction with an offset"));
5584
5585 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5586 - S_GET_VALUE (fixP->fx_subsy));
5587
5588 /* The difference value gets written out, and the DIFF reloc
5589 identifies the address of the subtracted symbol (i.e., the one
5590 with the lowest address). */
5591 *valP = val;
5592 fixP->fx_offset -= val;
5593 fixP->fx_subsy = NULL;
5594 }
5595 else if (! fixP->fx_addsy)
5596 {
5597 val = *valP;
5598 fixP->fx_done = 1;
5599 }
5600 else
5601 break;
5602 md_number_to_chars (fixpos, val, fixP->fx_size);
5603 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */
5604 break;
5605
5606 case BFD_RELOC_XTENSA_SLOT0_OP:
5607 case BFD_RELOC_XTENSA_SLOT1_OP:
5608 case BFD_RELOC_XTENSA_SLOT2_OP:
5609 case BFD_RELOC_XTENSA_SLOT3_OP:
5610 case BFD_RELOC_XTENSA_SLOT4_OP:
5611 case BFD_RELOC_XTENSA_SLOT5_OP:
5612 case BFD_RELOC_XTENSA_SLOT6_OP:
5613 case BFD_RELOC_XTENSA_SLOT7_OP:
5614 case BFD_RELOC_XTENSA_SLOT8_OP:
5615 case BFD_RELOC_XTENSA_SLOT9_OP:
5616 case BFD_RELOC_XTENSA_SLOT10_OP:
5617 case BFD_RELOC_XTENSA_SLOT11_OP:
5618 case BFD_RELOC_XTENSA_SLOT12_OP:
5619 case BFD_RELOC_XTENSA_SLOT13_OP:
5620 case BFD_RELOC_XTENSA_SLOT14_OP:
5621 if (linkrelax)
5622 {
5623 /* Write the tentative value of a PC-relative relocation to a
5624 local symbol into the instruction. The value will be ignored
5625 by the linker, and it makes the object file disassembly
5626 readable when all branch targets are encoded in relocations. */
5627
5628 assert (fixP->fx_addsy);
5629 if (S_GET_SEGMENT (fixP->fx_addsy) == seg && !fixP->fx_plt
5630 && !S_FORCE_RELOC (fixP->fx_addsy, 1))
5631 {
5632 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5633 - md_pcrel_from (fixP));
5634 (void) xg_apply_fix_value (fixP, val);
5635 }
5636 }
5637 else if (! fixP->fx_addsy)
5638 {
5639 val = *valP;
5640 if (xg_apply_fix_value (fixP, val))
5641 fixP->fx_done = 1;
5642 }
5643 break;
5644
5645 case BFD_RELOC_XTENSA_PLT:
5646 case BFD_RELOC_XTENSA_ASM_EXPAND:
5647 case BFD_RELOC_XTENSA_SLOT0_ALT:
5648 case BFD_RELOC_XTENSA_SLOT1_ALT:
5649 case BFD_RELOC_XTENSA_SLOT2_ALT:
5650 case BFD_RELOC_XTENSA_SLOT3_ALT:
5651 case BFD_RELOC_XTENSA_SLOT4_ALT:
5652 case BFD_RELOC_XTENSA_SLOT5_ALT:
5653 case BFD_RELOC_XTENSA_SLOT6_ALT:
5654 case BFD_RELOC_XTENSA_SLOT7_ALT:
5655 case BFD_RELOC_XTENSA_SLOT8_ALT:
5656 case BFD_RELOC_XTENSA_SLOT9_ALT:
5657 case BFD_RELOC_XTENSA_SLOT10_ALT:
5658 case BFD_RELOC_XTENSA_SLOT11_ALT:
5659 case BFD_RELOC_XTENSA_SLOT12_ALT:
5660 case BFD_RELOC_XTENSA_SLOT13_ALT:
5661 case BFD_RELOC_XTENSA_SLOT14_ALT:
5662 /* These all need to be resolved at link-time. Do nothing now. */
5663 break;
5664
5665 case BFD_RELOC_VTABLE_INHERIT:
5666 case BFD_RELOC_VTABLE_ENTRY:
5667 fixP->fx_done = 0;
5668 break;
5669
5670 default:
5671 as_bad (_("unhandled local relocation fix %s"),
5672 bfd_get_reloc_code_name (fixP->fx_r_type));
5673 }
5674 }
5675
5676
5677 char *
md_atof(int type,char * litP,int * sizeP)5678 md_atof (int type, char *litP, int *sizeP)
5679 {
5680 int prec;
5681 LITTLENUM_TYPE words[4];
5682 char *t;
5683 int i;
5684
5685 switch (type)
5686 {
5687 case 'f':
5688 prec = 2;
5689 break;
5690
5691 case 'd':
5692 prec = 4;
5693 break;
5694
5695 default:
5696 *sizeP = 0;
5697 return "bad call to md_atof";
5698 }
5699
5700 t = atof_ieee (input_line_pointer, type, words);
5701 if (t)
5702 input_line_pointer = t;
5703
5704 *sizeP = prec * 2;
5705
5706 for (i = prec - 1; i >= 0; i--)
5707 {
5708 int idx = i;
5709 if (target_big_endian)
5710 idx = (prec - 1 - i);
5711
5712 md_number_to_chars (litP, (valueT) words[idx], 2);
5713 litP += 2;
5714 }
5715
5716 return NULL;
5717 }
5718
5719
5720 int
md_estimate_size_before_relax(fragS * fragP,segT seg ATTRIBUTE_UNUSED)5721 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
5722 {
5723 return total_frag_text_expansion (fragP);
5724 }
5725
5726
5727 /* Translate internal representation of relocation info to BFD target
5728 format. */
5729
5730 arelent *
tc_gen_reloc(asection * section ATTRIBUTE_UNUSED,fixS * fixp)5731 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
5732 {
5733 arelent *reloc;
5734
5735 reloc = (arelent *) xmalloc (sizeof (arelent));
5736 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5737 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5738 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5739
5740 /* Make sure none of our internal relocations make it this far.
5741 They'd better have been fully resolved by this point. */
5742 assert ((int) fixp->fx_r_type > 0);
5743
5744 reloc->addend = fixp->fx_offset;
5745
5746 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
5747 if (reloc->howto == NULL)
5748 {
5749 as_bad_where (fixp->fx_file, fixp->fx_line,
5750 _("cannot represent `%s' relocation in object file"),
5751 bfd_get_reloc_code_name (fixp->fx_r_type));
5752 free (reloc->sym_ptr_ptr);
5753 free (reloc);
5754 return NULL;
5755 }
5756
5757 if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
5758 as_fatal (_("internal error? cannot generate `%s' relocation"),
5759 bfd_get_reloc_code_name (fixp->fx_r_type));
5760
5761 return reloc;
5762 }
5763
5764
5765 /* Checks for resource conflicts between instructions. */
5766
5767 /* The func unit stuff could be implemented as bit-vectors rather
5768 than the iterative approach here. If it ends up being too
5769 slow, we will switch it. */
5770
5771 resource_table *
new_resource_table(void * data,int cycles,int nu,unit_num_copies_func uncf,opcode_num_units_func onuf,opcode_funcUnit_use_unit_func ouuf,opcode_funcUnit_use_stage_func ousf)5772 new_resource_table (void *data,
5773 int cycles,
5774 int nu,
5775 unit_num_copies_func uncf,
5776 opcode_num_units_func onuf,
5777 opcode_funcUnit_use_unit_func ouuf,
5778 opcode_funcUnit_use_stage_func ousf)
5779 {
5780 int i;
5781 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
5782 rt->data = data;
5783 rt->cycles = cycles;
5784 rt->allocated_cycles = cycles;
5785 rt->num_units = nu;
5786 rt->unit_num_copies = uncf;
5787 rt->opcode_num_units = onuf;
5788 rt->opcode_unit_use = ouuf;
5789 rt->opcode_unit_stage = ousf;
5790
5791 rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *));
5792 for (i = 0; i < cycles; i++)
5793 rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char));
5794
5795 return rt;
5796 }
5797
5798
5799 void
clear_resource_table(resource_table * rt)5800 clear_resource_table (resource_table *rt)
5801 {
5802 int i, j;
5803 for (i = 0; i < rt->allocated_cycles; i++)
5804 for (j = 0; j < rt->num_units; j++)
5805 rt->units[i][j] = 0;
5806 }
5807
5808
5809 /* We never shrink it, just fake it into thinking so. */
5810
5811 void
resize_resource_table(resource_table * rt,int cycles)5812 resize_resource_table (resource_table *rt, int cycles)
5813 {
5814 int i, old_cycles;
5815
5816 rt->cycles = cycles;
5817 if (cycles <= rt->allocated_cycles)
5818 return;
5819
5820 old_cycles = rt->allocated_cycles;
5821 rt->allocated_cycles = cycles;
5822
5823 rt->units = xrealloc (rt->units,
5824 rt->allocated_cycles * sizeof (unsigned char *));
5825 for (i = 0; i < old_cycles; i++)
5826 rt->units[i] = xrealloc (rt->units[i],
5827 rt->num_units * sizeof (unsigned char));
5828 for (i = old_cycles; i < cycles; i++)
5829 rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char));
5830 }
5831
5832
5833 bfd_boolean
resources_available(resource_table * rt,xtensa_opcode opcode,int cycle)5834 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
5835 {
5836 int i;
5837 int uses = (rt->opcode_num_units) (rt->data, opcode);
5838
5839 for (i = 0; i < uses; i++)
5840 {
5841 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5842 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5843 int copies_in_use = rt->units[stage + cycle][unit];
5844 int copies = (rt->unit_num_copies) (rt->data, unit);
5845 if (copies_in_use >= copies)
5846 return FALSE;
5847 }
5848 return TRUE;
5849 }
5850
5851
5852 void
reserve_resources(resource_table * rt,xtensa_opcode opcode,int cycle)5853 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5854 {
5855 int i;
5856 int uses = (rt->opcode_num_units) (rt->data, opcode);
5857
5858 for (i = 0; i < uses; i++)
5859 {
5860 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5861 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5862 /* Note that this allows resources to be oversubscribed. That's
5863 essential to the way the optional scheduler works.
5864 resources_available reports when a resource is over-subscribed,
5865 so it's easy to tell. */
5866 rt->units[stage + cycle][unit]++;
5867 }
5868 }
5869
5870
5871 void
release_resources(resource_table * rt,xtensa_opcode opcode,int cycle)5872 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5873 {
5874 int i;
5875 int uses = (rt->opcode_num_units) (rt->data, opcode);
5876
5877 for (i = 0; i < uses; i++)
5878 {
5879 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5880 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5881 assert (rt->units[stage + cycle][unit] > 0);
5882 rt->units[stage + cycle][unit]--;
5883 }
5884 }
5885
5886
5887 /* Wrapper functions make parameterized resource reservation
5888 more convenient. */
5889
5890 int
opcode_funcUnit_use_unit(void * data,xtensa_opcode opcode,int idx)5891 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
5892 {
5893 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
5894 return use->unit;
5895 }
5896
5897
5898 int
opcode_funcUnit_use_stage(void * data,xtensa_opcode opcode,int idx)5899 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
5900 {
5901 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
5902 return use->stage;
5903 }
5904
5905
5906 /* Note that this function does not check issue constraints, but
5907 solely whether the hardware is available to execute the given
5908 instructions together. It also doesn't check if the tinsns
5909 write the same state, or access the same tieports. That is
5910 checked by check_t1_t2_reads_and_writes. */
5911
5912 static bfd_boolean
resources_conflict(vliw_insn * vinsn)5913 resources_conflict (vliw_insn *vinsn)
5914 {
5915 int i;
5916 static resource_table *rt = NULL;
5917
5918 /* This is the most common case by far. Optimize it. */
5919 if (vinsn->num_slots == 1)
5920 return FALSE;
5921
5922 if (rt == NULL)
5923 {
5924 xtensa_isa isa = xtensa_default_isa;
5925 rt = new_resource_table
5926 (isa, xtensa_isa_num_pipe_stages (isa),
5927 xtensa_isa_num_funcUnits (isa),
5928 (unit_num_copies_func) xtensa_funcUnit_num_copies,
5929 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
5930 opcode_funcUnit_use_unit,
5931 opcode_funcUnit_use_stage);
5932 }
5933
5934 clear_resource_table (rt);
5935
5936 for (i = 0; i < vinsn->num_slots; i++)
5937 {
5938 if (!resources_available (rt, vinsn->slots[i].opcode, 0))
5939 return TRUE;
5940 reserve_resources (rt, vinsn->slots[i].opcode, 0);
5941 }
5942
5943 return FALSE;
5944 }
5945
5946
5947 /* finish_vinsn, emit_single_op and helper functions. */
5948
5949 static bfd_boolean find_vinsn_conflicts (vliw_insn *);
5950 static xtensa_format xg_find_narrowest_format (vliw_insn *);
5951 static void bundle_single_op (TInsn *);
5952 static void xg_assemble_vliw_tokens (vliw_insn *);
5953
5954
5955 /* We have reached the end of a bundle; emit into the frag. */
5956
5957 static void
finish_vinsn(vliw_insn * vinsn)5958 finish_vinsn (vliw_insn *vinsn)
5959 {
5960 IStack slotstack;
5961 int i;
5962 char *file_name;
5963 unsigned line;
5964
5965 if (find_vinsn_conflicts (vinsn))
5966 {
5967 xg_clear_vinsn (vinsn);
5968 return;
5969 }
5970
5971 /* First, find a format that works. */
5972 if (vinsn->format == XTENSA_UNDEFINED)
5973 vinsn->format = xg_find_narrowest_format (vinsn);
5974
5975 if (vinsn->format == XTENSA_UNDEFINED)
5976 {
5977 as_where (&file_name, &line);
5978 as_bad_where (file_name, line,
5979 _("couldn't find a valid instruction format"));
5980 fprintf (stderr, _(" ops were: "));
5981 for (i = 0; i < vinsn->num_slots; i++)
5982 fprintf (stderr, _(" %s;"),
5983 xtensa_opcode_name (xtensa_default_isa,
5984 vinsn->slots[i].opcode));
5985 fprintf (stderr, _("\n"));
5986 xg_clear_vinsn (vinsn);
5987 return;
5988 }
5989
5990 if (vinsn->num_slots
5991 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
5992 {
5993 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5994 xtensa_format_name (xtensa_default_isa, vinsn->format),
5995 xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
5996 vinsn->num_slots);
5997 xg_clear_vinsn (vinsn);
5998 return;
5999 }
6000
6001 if (resources_conflict (vinsn))
6002 {
6003 as_where (&file_name, &line);
6004 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6005 fprintf (stderr, " ops were: ");
6006 for (i = 0; i < vinsn->num_slots; i++)
6007 fprintf (stderr, " %s;",
6008 xtensa_opcode_name (xtensa_default_isa,
6009 vinsn->slots[i].opcode));
6010 fprintf (stderr, "\n");
6011 xg_clear_vinsn (vinsn);
6012 return;
6013 }
6014
6015 for (i = 0; i < vinsn->num_slots; i++)
6016 {
6017 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
6018 {
6019 symbolS *lit_sym = NULL;
6020 int j;
6021 bfd_boolean e = FALSE;
6022 bfd_boolean saved_density = density_supported;
6023
6024 /* We don't want to narrow ops inside multi-slot bundles. */
6025 if (vinsn->num_slots > 1)
6026 density_supported = FALSE;
6027
6028 istack_init (&slotstack);
6029 if (vinsn->slots[i].opcode == xtensa_nop_opcode)
6030 {
6031 vinsn->slots[i].opcode =
6032 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6033 vinsn->format, i);
6034 vinsn->slots[i].ntok = 0;
6035 }
6036
6037 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6038 {
6039 e = TRUE;
6040 continue;
6041 }
6042
6043 density_supported = saved_density;
6044
6045 if (e)
6046 {
6047 xg_clear_vinsn (vinsn);
6048 return;
6049 }
6050
6051 for (j = 0; j < slotstack.ninsn; j++)
6052 {
6053 TInsn *insn = &slotstack.insn[j];
6054 if (insn->insn_type == ITYPE_LITERAL)
6055 {
6056 assert (lit_sym == NULL);
6057 lit_sym = xg_assemble_literal (insn);
6058 }
6059 else
6060 {
6061 assert (insn->insn_type == ITYPE_INSN);
6062 if (lit_sym)
6063 xg_resolve_literals (insn, lit_sym);
6064 if (j != slotstack.ninsn - 1)
6065 emit_single_op (insn);
6066 }
6067 }
6068
6069 if (vinsn->num_slots > 1)
6070 {
6071 if (opcode_fits_format_slot
6072 (slotstack.insn[slotstack.ninsn - 1].opcode,
6073 vinsn->format, i))
6074 {
6075 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6076 }
6077 else
6078 {
6079 bundle_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6080 if (vinsn->format == XTENSA_UNDEFINED)
6081 vinsn->slots[i].opcode = xtensa_nop_opcode;
6082 else
6083 vinsn->slots[i].opcode
6084 = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6085 vinsn->format, i);
6086
6087 vinsn->slots[i].ntok = 0;
6088 }
6089 }
6090 else
6091 {
6092 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6093 vinsn->format = XTENSA_UNDEFINED;
6094 }
6095 }
6096 }
6097
6098 /* Now check resource conflicts on the modified bundle. */
6099 if (resources_conflict (vinsn))
6100 {
6101 as_where (&file_name, &line);
6102 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6103 fprintf (stderr, " ops were: ");
6104 for (i = 0; i < vinsn->num_slots; i++)
6105 fprintf (stderr, " %s;",
6106 xtensa_opcode_name (xtensa_default_isa,
6107 vinsn->slots[i].opcode));
6108 fprintf (stderr, "\n");
6109 xg_clear_vinsn (vinsn);
6110 return;
6111 }
6112
6113 /* First, find a format that works. */
6114 if (vinsn->format == XTENSA_UNDEFINED)
6115 vinsn->format = xg_find_narrowest_format (vinsn);
6116
6117 xg_assemble_vliw_tokens (vinsn);
6118
6119 xg_clear_vinsn (vinsn);
6120 }
6121
6122
6123 /* Given an vliw instruction, what conflicts are there in register
6124 usage and in writes to states and queues?
6125
6126 This function does two things:
6127 1. Reports an error when a vinsn contains illegal combinations
6128 of writes to registers states or queues.
6129 2. Marks individual tinsns as not relaxable if the combination
6130 contains antidependencies.
6131
6132 Job 2 handles things like swap semantics in instructions that need
6133 to be relaxed. For example,
6134
6135 addi a0, a1, 100000
6136
6137 normally would be relaxed to
6138
6139 l32r a0, some_label
6140 add a0, a1, a0
6141
6142 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6143
6144 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6145
6146 then we can't relax it into
6147
6148 l32r a0, some_label
6149 { add a0, a1, a0 ; add a2, a0, a4 ; }
6150
6151 because the value of a0 is trashed before the second add can read it. */
6152
6153 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6154
6155 static bfd_boolean
find_vinsn_conflicts(vliw_insn * vinsn)6156 find_vinsn_conflicts (vliw_insn *vinsn)
6157 {
6158 int i, j;
6159 int branches = 0;
6160 xtensa_isa isa = xtensa_default_isa;
6161
6162 assert (!past_xtensa_end);
6163
6164 for (i = 0 ; i < vinsn->num_slots; i++)
6165 {
6166 TInsn *op1 = &vinsn->slots[i];
6167 if (op1->is_specific_opcode)
6168 op1->keep_wide = TRUE;
6169 else
6170 op1->keep_wide = FALSE;
6171 }
6172
6173 for (i = 0 ; i < vinsn->num_slots; i++)
6174 {
6175 TInsn *op1 = &vinsn->slots[i];
6176
6177 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6178 branches++;
6179
6180 for (j = 0; j < vinsn->num_slots; j++)
6181 {
6182 if (i != j)
6183 {
6184 TInsn *op2 = &vinsn->slots[j];
6185 char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6186 switch (conflict_type)
6187 {
6188 case 'c':
6189 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6190 xtensa_opcode_name (isa, op1->opcode), i,
6191 xtensa_opcode_name (isa, op2->opcode), j);
6192 return TRUE;
6193 case 'd':
6194 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6195 xtensa_opcode_name (isa, op1->opcode), i,
6196 xtensa_opcode_name (isa, op2->opcode), j);
6197 return TRUE;
6198 case 'e':
6199 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6200 xtensa_opcode_name (isa, op1->opcode), i,
6201 xtensa_opcode_name (isa, op2->opcode), j);
6202 return TRUE;
6203 case 'f':
6204 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6205 xtensa_opcode_name (isa, op1->opcode), i,
6206 xtensa_opcode_name (isa, op2->opcode), j);
6207 return TRUE;
6208 default:
6209 /* Everything is OK. */
6210 break;
6211 }
6212 op2->is_specific_opcode = (op2->is_specific_opcode
6213 || conflict_type == 'a');
6214 }
6215 }
6216 }
6217
6218 if (branches > 1)
6219 {
6220 as_bad (_("multiple branches or jumps in the same bundle"));
6221 return TRUE;
6222 }
6223
6224 return FALSE;
6225 }
6226
6227
6228 /* Check how the state used by t1 and t2 relate.
6229 Cases found are:
6230
6231 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6232 case B: no relationship between what is read and written (both could
6233 read the same reg though)
6234 case C: t1 writes a register t2 writes (a register conflict within a
6235 bundle)
6236 case D: t1 writes a state that t2 also writes
6237 case E: t1 writes a tie queue that t2 also writes
6238 case F: two volatile queue accesses
6239 */
6240
6241 static char
check_t1_t2_reads_and_writes(TInsn * t1,TInsn * t2)6242 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
6243 {
6244 xtensa_isa isa = xtensa_default_isa;
6245 xtensa_regfile t1_regfile, t2_regfile;
6246 int t1_reg, t2_reg;
6247 int t1_base_reg, t1_last_reg;
6248 int t2_base_reg, t2_last_reg;
6249 char t1_inout, t2_inout;
6250 int i, j;
6251 char conflict = 'b';
6252 int t1_states;
6253 int t2_states;
6254 int t1_interfaces;
6255 int t2_interfaces;
6256 bfd_boolean t1_volatile = FALSE;
6257 bfd_boolean t2_volatile = FALSE;
6258
6259 /* Check registers. */
6260 for (j = 0; j < t2->ntok; j++)
6261 {
6262 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6263 continue;
6264
6265 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6266 t2_base_reg = t2->tok[j].X_add_number;
6267 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6268
6269 for (i = 0; i < t1->ntok; i++)
6270 {
6271 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6272 continue;
6273
6274 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6275
6276 if (t1_regfile != t2_regfile)
6277 continue;
6278
6279 t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6280 t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6281
6282 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6283 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6284 {
6285 if (t1_inout == 'm' || t1_inout == 'o'
6286 || t2_inout == 'm' || t2_inout == 'o')
6287 {
6288 conflict = 'a';
6289 continue;
6290 }
6291 }
6292
6293 t1_base_reg = t1->tok[i].X_add_number;
6294 t1_last_reg = (t1_base_reg
6295 + xtensa_operand_num_regs (isa, t1->opcode, i));
6296
6297 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6298 {
6299 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6300 {
6301 if (t1_reg != t2_reg)
6302 continue;
6303
6304 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6305 {
6306 conflict = 'a';
6307 continue;
6308 }
6309
6310 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6311 {
6312 conflict = 'a';
6313 continue;
6314 }
6315
6316 if (t1_inout != 'i' && t2_inout != 'i')
6317 return 'c';
6318 }
6319 }
6320 }
6321 }
6322
6323 /* Check states. */
6324 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6325 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6326 for (j = 0; j < t2_states; j++)
6327 {
6328 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6329 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6330 for (i = 0; i < t1_states; i++)
6331 {
6332 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6333 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6334 if (t1_so != t2_so)
6335 continue;
6336
6337 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6338 {
6339 conflict = 'a';
6340 continue;
6341 }
6342
6343 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6344 {
6345 conflict = 'a';
6346 continue;
6347 }
6348
6349 if (t1_inout != 'i' && t2_inout != 'i')
6350 return 'd';
6351 }
6352 }
6353
6354 /* Check tieports. */
6355 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6356 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6357 for (j = 0; j < t2_interfaces; j++)
6358 {
6359 xtensa_interface t2_int
6360 = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6361 int t2_class = xtensa_interface_class_id (isa, t2_int);
6362
6363 t2_inout = xtensa_interface_inout (isa, j);
6364 if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
6365 t2_volatile = TRUE;
6366
6367 for (i = 0; i < t1_interfaces; i++)
6368 {
6369 xtensa_interface t1_int
6370 = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6371 int t1_class = xtensa_interface_class_id (isa, t1_int);
6372
6373 t1_inout = xtensa_interface_inout (isa, i);
6374 if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
6375 t1_volatile = TRUE;
6376
6377 if (t1_volatile && t2_volatile && (t1_class == t2_class))
6378 return 'f';
6379
6380 if (t1_int != t2_int)
6381 continue;
6382
6383 if (t2_inout == 'i' && t1_inout == 'o')
6384 {
6385 conflict = 'a';
6386 continue;
6387 }
6388
6389 if (t1_inout == 'i' && t2_inout == 'o')
6390 {
6391 conflict = 'a';
6392 continue;
6393 }
6394
6395 if (t1_inout != 'i' && t2_inout != 'i')
6396 return 'e';
6397 }
6398 }
6399
6400 return conflict;
6401 }
6402
6403
6404 static xtensa_format
xg_find_narrowest_format(vliw_insn * vinsn)6405 xg_find_narrowest_format (vliw_insn *vinsn)
6406 {
6407 /* Right now we assume that the ops within the vinsn are properly
6408 ordered for the slots that the programmer wanted them in. In
6409 other words, we don't rearrange the ops in hopes of finding a
6410 better format. The scheduler handles that. */
6411
6412 xtensa_isa isa = xtensa_default_isa;
6413 xtensa_format format;
6414 vliw_insn v_copy = *vinsn;
6415 xtensa_opcode nop_opcode = xtensa_nop_opcode;
6416
6417 for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6418 {
6419 v_copy = *vinsn;
6420 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6421 {
6422 int slot;
6423 int fit = 0;
6424 for (slot = 0; slot < v_copy.num_slots; slot++)
6425 {
6426 if (v_copy.slots[slot].opcode == nop_opcode)
6427 {
6428 v_copy.slots[slot].opcode =
6429 xtensa_format_slot_nop_opcode (isa, format, slot);
6430 v_copy.slots[slot].ntok = 0;
6431 }
6432
6433 if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6434 format, slot))
6435 fit++;
6436 else if (v_copy.num_slots > 1)
6437 {
6438 TInsn widened;
6439 /* Try the widened version. */
6440 if (!v_copy.slots[slot].keep_wide
6441 && !v_copy.slots[slot].is_specific_opcode
6442 && xg_is_single_relaxable_insn (&v_copy.slots[slot],
6443 &widened, TRUE)
6444 && opcode_fits_format_slot (widened.opcode,
6445 format, slot))
6446 {
6447 v_copy.slots[slot] = widened;
6448 fit++;
6449 }
6450 }
6451 }
6452 if (fit == v_copy.num_slots)
6453 {
6454 *vinsn = v_copy;
6455 xtensa_format_encode (isa, format, vinsn->insnbuf);
6456 vinsn->format = format;
6457 break;
6458 }
6459 }
6460 }
6461
6462 if (format == xtensa_isa_num_formats (isa))
6463 return XTENSA_UNDEFINED;
6464
6465 return format;
6466 }
6467
6468
6469 /* Return the additional space needed in a frag
6470 for possible relaxations of any ops in a VLIW insn.
6471 Also fill out the relaxations that might be required of
6472 each tinsn in the vinsn. */
6473
6474 static int
relaxation_requirements(vliw_insn * vinsn)6475 relaxation_requirements (vliw_insn *vinsn)
6476 {
6477 int extra_space = 0;
6478 int slot;
6479
6480 for (slot = 0; slot < vinsn->num_slots; slot++)
6481 {
6482 TInsn *tinsn = &vinsn->slots[slot];
6483 if (!tinsn_has_symbolic_operands (tinsn))
6484 {
6485 /* A narrow instruction could be widened later to help
6486 alignment issues. */
6487 if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
6488 && !tinsn->is_specific_opcode
6489 && vinsn->num_slots == 1)
6490 {
6491 /* Difference in bytes between narrow and wide insns... */
6492 extra_space += 1;
6493 tinsn->subtype = RELAX_NARROW;
6494 tinsn->record_fix = TRUE;
6495 break;
6496 }
6497 else
6498 {
6499 tinsn->record_fix = FALSE;
6500 /* No extra_space needed. */
6501 }
6502 }
6503 else
6504 {
6505 if (workaround_b_j_loop_end
6506 && tinsn->opcode == xtensa_jx_opcode
6507 && use_transform ())
6508 {
6509 /* Add 2 of these. */
6510 extra_space += 3; /* for the nop size */
6511 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6512 }
6513
6514 /* Need to assemble it with space for the relocation. */
6515 if (xg_is_relaxable_insn (tinsn, 0)
6516 && !tinsn->is_specific_opcode)
6517 {
6518 int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6519 int max_literal_size =
6520 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6521
6522 tinsn->literal_space = max_literal_size;
6523
6524 tinsn->subtype = RELAX_IMMED;
6525 tinsn->record_fix = FALSE;
6526 extra_space += max_size;
6527 }
6528 else
6529 {
6530 tinsn->record_fix = TRUE;
6531 /* No extra space needed. */
6532 }
6533 }
6534 }
6535 return extra_space;
6536 }
6537
6538
6539 static void
bundle_single_op(TInsn * orig_insn)6540 bundle_single_op (TInsn *orig_insn)
6541 {
6542 xtensa_isa isa = xtensa_default_isa;
6543 vliw_insn v;
6544 int slot;
6545
6546 xg_init_vinsn (&v);
6547 v.format = op_placement_table[orig_insn->opcode].narrowest;
6548 assert (v.format != XTENSA_UNDEFINED);
6549 v.num_slots = xtensa_format_num_slots (isa, v.format);
6550
6551 for (slot = 0;
6552 !opcode_fits_format_slot (orig_insn->opcode, v.format, slot);
6553 slot++)
6554 {
6555 v.slots[slot].opcode =
6556 xtensa_format_slot_nop_opcode (isa, v.format, slot);
6557 v.slots[slot].ntok = 0;
6558 v.slots[slot].insn_type = ITYPE_INSN;
6559 }
6560
6561 v.slots[slot] = *orig_insn;
6562 slot++;
6563
6564 for ( ; slot < v.num_slots; slot++)
6565 {
6566 v.slots[slot].opcode =
6567 xtensa_format_slot_nop_opcode (isa, v.format, slot);
6568 v.slots[slot].ntok = 0;
6569 v.slots[slot].insn_type = ITYPE_INSN;
6570 }
6571
6572 finish_vinsn (&v);
6573 xg_free_vinsn (&v);
6574 }
6575
6576
6577 static bfd_boolean
emit_single_op(TInsn * orig_insn)6578 emit_single_op (TInsn *orig_insn)
6579 {
6580 int i;
6581 IStack istack; /* put instructions into here */
6582 symbolS *lit_sym = NULL;
6583 symbolS *label_sym = NULL;
6584
6585 istack_init (&istack);
6586
6587 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6588 Because the scheduling and bundling characteristics of movi and
6589 l32r or const16 are so different, we can do much better if we relax
6590 it prior to scheduling and bundling, rather than after. */
6591 if ((orig_insn->opcode == xtensa_movi_opcode
6592 || orig_insn->opcode == xtensa_movi_n_opcode)
6593 && !cur_vinsn.inside_bundle
6594 && (orig_insn->tok[1].X_op == O_symbol
6595 || orig_insn->tok[1].X_op == O_pltrel))
6596 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6597 else
6598 if (xg_expand_assembly_insn (&istack, orig_insn))
6599 return TRUE;
6600
6601 for (i = 0; i < istack.ninsn; i++)
6602 {
6603 TInsn *insn = &istack.insn[i];
6604 switch (insn->insn_type)
6605 {
6606 case ITYPE_LITERAL:
6607 assert (lit_sym == NULL);
6608 lit_sym = xg_assemble_literal (insn);
6609 break;
6610 case ITYPE_LABEL:
6611 {
6612 static int relaxed_sym_idx = 0;
6613 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
6614 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6615 colon (label);
6616 assert (label_sym == NULL);
6617 label_sym = symbol_find_or_make (label);
6618 assert (label_sym);
6619 free (label);
6620 }
6621 break;
6622 case ITYPE_INSN:
6623 if (lit_sym)
6624 xg_resolve_literals (insn, lit_sym);
6625 if (label_sym)
6626 xg_resolve_labels (insn, label_sym);
6627 bundle_single_op (insn);
6628 break;
6629 default:
6630 assert (0);
6631 break;
6632 }
6633 }
6634 return FALSE;
6635 }
6636
6637
6638 static int
total_frag_text_expansion(fragS * fragP)6639 total_frag_text_expansion (fragS *fragP)
6640 {
6641 int slot;
6642 int total_expansion = 0;
6643
6644 for (slot = 0; slot < MAX_SLOTS; slot++)
6645 total_expansion += fragP->tc_frag_data.text_expansion[slot];
6646
6647 return total_expansion;
6648 }
6649
6650
6651 /* Emit a vliw instruction to the current fragment. */
6652
6653 static void
xg_assemble_vliw_tokens(vliw_insn * vinsn)6654 xg_assemble_vliw_tokens (vliw_insn *vinsn)
6655 {
6656 bfd_boolean finish_frag = FALSE;
6657 bfd_boolean is_jump = FALSE;
6658 bfd_boolean is_branch = FALSE;
6659 xtensa_isa isa = xtensa_default_isa;
6660 int i;
6661 int insn_size;
6662 int extra_space;
6663 char *f = NULL;
6664 int slot;
6665 struct dwarf2_line_info best_loc;
6666
6667 best_loc.line = INT_MAX;
6668
6669 if (generating_literals)
6670 {
6671 static int reported = 0;
6672 if (reported < 4)
6673 as_bad_where (frag_now->fr_file, frag_now->fr_line,
6674 _("cannot assemble into a literal fragment"));
6675 if (reported == 3)
6676 as_bad (_("..."));
6677 reported++;
6678 return;
6679 }
6680
6681 if (frag_now_fix () != 0
6682 && (! frag_now->tc_frag_data.is_insn
6683 || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6684 || !use_transform () != frag_now->tc_frag_data.is_no_transform
6685 || (directive_state[directive_longcalls]
6686 != frag_now->tc_frag_data.use_longcalls)
6687 || (directive_state[directive_absolute_literals]
6688 != frag_now->tc_frag_data.use_absolute_literals)))
6689 {
6690 frag_wane (frag_now);
6691 frag_new (0);
6692 xtensa_set_frag_assembly_state (frag_now);
6693 }
6694
6695 if (workaround_a0_b_retw
6696 && vinsn->num_slots == 1
6697 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
6698 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
6699 && use_transform ())
6700 {
6701 has_a0_b_retw = TRUE;
6702
6703 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6704 After the first assembly pass we will check all of them and
6705 add a nop if needed. */
6706 frag_now->tc_frag_data.is_insn = TRUE;
6707 frag_var (rs_machine_dependent, 4, 4,
6708 RELAX_ADD_NOP_IF_A0_B_RETW,
6709 frag_now->fr_symbol,
6710 frag_now->fr_offset,
6711 NULL);
6712 xtensa_set_frag_assembly_state (frag_now);
6713 frag_now->tc_frag_data.is_insn = TRUE;
6714 frag_var (rs_machine_dependent, 4, 4,
6715 RELAX_ADD_NOP_IF_A0_B_RETW,
6716 frag_now->fr_symbol,
6717 frag_now->fr_offset,
6718 NULL);
6719 xtensa_set_frag_assembly_state (frag_now);
6720 }
6721
6722 for (i = 0; i < vinsn->num_slots; i++)
6723 {
6724 /* See if the instruction implies an aligned section. */
6725 if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
6726 record_alignment (now_seg, 2);
6727
6728 /* Also determine the best line number for debug info. */
6729 best_loc = vinsn->slots[i].loc.line < best_loc.line
6730 ? vinsn->slots[i].loc : best_loc;
6731 }
6732
6733 /* Special cases for instructions that force an alignment... */
6734 /* None of these opcodes are bundle-able. */
6735 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
6736 {
6737 int max_fill;
6738
6739 xtensa_set_frag_assembly_state (frag_now);
6740 frag_now->tc_frag_data.is_insn = TRUE;
6741
6742 max_fill = get_text_align_max_fill_size
6743 (get_text_align_power (xtensa_fetch_width),
6744 TRUE, frag_now->tc_frag_data.is_no_density);
6745
6746 if (use_transform ())
6747 frag_var (rs_machine_dependent, max_fill, max_fill,
6748 RELAX_ALIGN_NEXT_OPCODE,
6749 frag_now->fr_symbol,
6750 frag_now->fr_offset,
6751 NULL);
6752 else
6753 frag_var (rs_machine_dependent, 0, 0,
6754 RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL);
6755 xtensa_set_frag_assembly_state (frag_now);
6756
6757 xtensa_move_labels (frag_now, 0, FALSE);
6758 }
6759
6760 if (vinsn->slots[0].opcode == xtensa_entry_opcode
6761 && !vinsn->slots[0].is_specific_opcode)
6762 {
6763 xtensa_mark_literal_pool_location ();
6764 xtensa_move_labels (frag_now, 0, TRUE);
6765 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
6766 }
6767
6768 if (vinsn->num_slots == 1)
6769 {
6770 if (workaround_a0_b_retw && use_transform ())
6771 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
6772 is_register_writer (&vinsn->slots[0], "a", 0));
6773
6774 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
6775 is_bad_loopend_opcode (&vinsn->slots[0]));
6776 }
6777 else
6778 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
6779
6780 insn_size = xtensa_format_length (isa, vinsn->format);
6781
6782 extra_space = relaxation_requirements (vinsn);
6783
6784 /* vinsn_to_insnbuf will produce the error. */
6785 if (vinsn->format != XTENSA_UNDEFINED)
6786 {
6787 f = frag_more (insn_size + extra_space);
6788 xtensa_set_frag_assembly_state (frag_now);
6789 frag_now->tc_frag_data.is_insn = TRUE;
6790 }
6791
6792 vinsn_to_insnbuf (vinsn, f, frag_now, TRUE);
6793 if (vinsn->format == XTENSA_UNDEFINED)
6794 return;
6795
6796 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
6797
6798 xtensa_dwarf2_emit_insn (insn_size + extra_space, &best_loc);
6799
6800 for (slot = 0; slot < vinsn->num_slots; slot++)
6801 {
6802 TInsn *tinsn = &vinsn->slots[slot];
6803 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
6804 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
6805 frag_now->tc_frag_data.slot_sub_symbols[slot] = tinsn->sub_symbol;
6806 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
6807 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
6808 if (tinsn->literal_space != 0)
6809 xg_assemble_literal_space (tinsn->literal_space, slot);
6810
6811 if (tinsn->subtype == RELAX_NARROW)
6812 assert (vinsn->num_slots == 1);
6813 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
6814 is_jump = TRUE;
6815 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
6816 is_branch = TRUE;
6817
6818 if (tinsn->subtype || tinsn->symbol || tinsn->record_fix
6819 || tinsn->offset || tinsn->literal_frag || is_jump || is_branch)
6820 finish_frag = TRUE;
6821 }
6822
6823 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6824 frag_now->tc_frag_data.is_specific_opcode = TRUE;
6825
6826 if (finish_frag)
6827 {
6828 frag_variant (rs_machine_dependent,
6829 extra_space, extra_space, RELAX_SLOTS,
6830 frag_now->fr_symbol, frag_now->fr_offset, f);
6831 xtensa_set_frag_assembly_state (frag_now);
6832 }
6833
6834 /* Special cases for loops:
6835 close_loop_end should be inserted AFTER short_loop.
6836 Make sure that CLOSE loops are processed BEFORE short_loops
6837 when converting them. */
6838
6839 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6840 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
6841 && !vinsn->slots[0].is_specific_opcode)
6842 {
6843 if (workaround_short_loop && use_transform ())
6844 {
6845 maybe_has_short_loop = TRUE;
6846 frag_now->tc_frag_data.is_insn = TRUE;
6847 frag_var (rs_machine_dependent, 4, 4,
6848 RELAX_ADD_NOP_IF_SHORT_LOOP,
6849 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6850 frag_now->tc_frag_data.is_insn = TRUE;
6851 frag_var (rs_machine_dependent, 4, 4,
6852 RELAX_ADD_NOP_IF_SHORT_LOOP,
6853 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6854 }
6855
6856 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6857 loop at least 12 bytes away from another loop's end. */
6858 if (workaround_close_loop_end && use_transform ())
6859 {
6860 maybe_has_close_loop_end = TRUE;
6861 frag_now->tc_frag_data.is_insn = TRUE;
6862 frag_var (rs_machine_dependent, 12, 12,
6863 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
6864 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6865 }
6866 }
6867
6868 if (use_transform ())
6869 {
6870 if (is_jump)
6871 {
6872 assert (finish_frag);
6873 frag_var (rs_machine_dependent,
6874 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6875 RELAX_UNREACHABLE,
6876 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6877 xtensa_set_frag_assembly_state (frag_now);
6878 }
6879 else if (is_branch && do_align_targets ())
6880 {
6881 assert (finish_frag);
6882 frag_var (rs_machine_dependent,
6883 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6884 RELAX_MAYBE_UNREACHABLE,
6885 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6886 xtensa_set_frag_assembly_state (frag_now);
6887 frag_var (rs_machine_dependent,
6888 0, 0,
6889 RELAX_MAYBE_DESIRE_ALIGN,
6890 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6891 xtensa_set_frag_assembly_state (frag_now);
6892 }
6893 }
6894
6895 /* Now, if the original opcode was a call... */
6896 if (do_align_targets ()
6897 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
6898 {
6899 float freq = get_subseg_total_freq (now_seg, now_subseg);
6900 frag_now->tc_frag_data.is_insn = TRUE;
6901 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
6902 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6903 xtensa_set_frag_assembly_state (frag_now);
6904 }
6905
6906 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6907 {
6908 frag_wane (frag_now);
6909 frag_new (0);
6910 xtensa_set_frag_assembly_state (frag_now);
6911 }
6912 }
6913
6914
6915 /* xtensa_end and helper functions. */
6916
6917 static void xtensa_cleanup_align_frags (void);
6918 static void xtensa_fix_target_frags (void);
6919 static void xtensa_mark_narrow_branches (void);
6920 static void xtensa_mark_zcl_first_insns (void);
6921 static void xtensa_fix_a0_b_retw_frags (void);
6922 static void xtensa_fix_b_j_loop_end_frags (void);
6923 static void xtensa_fix_close_loop_end_frags (void);
6924 static void xtensa_fix_short_loop_frags (void);
6925 static void xtensa_sanity_check (void);
6926
6927 void
xtensa_end(void)6928 xtensa_end (void)
6929 {
6930 directive_balance ();
6931 xtensa_flush_pending_output ();
6932
6933 past_xtensa_end = TRUE;
6934
6935 xtensa_move_literals ();
6936
6937 xtensa_reorder_segments ();
6938 xtensa_cleanup_align_frags ();
6939 xtensa_fix_target_frags ();
6940 if (workaround_a0_b_retw && has_a0_b_retw)
6941 xtensa_fix_a0_b_retw_frags ();
6942 if (workaround_b_j_loop_end)
6943 xtensa_fix_b_j_loop_end_frags ();
6944
6945 /* "close_loop_end" should be processed BEFORE "short_loop". */
6946 if (workaround_close_loop_end && maybe_has_close_loop_end)
6947 xtensa_fix_close_loop_end_frags ();
6948
6949 if (workaround_short_loop && maybe_has_short_loop)
6950 xtensa_fix_short_loop_frags ();
6951 xtensa_mark_narrow_branches ();
6952 xtensa_mark_zcl_first_insns ();
6953
6954 xtensa_sanity_check ();
6955 }
6956
6957
6958 static void
xtensa_cleanup_align_frags(void)6959 xtensa_cleanup_align_frags (void)
6960 {
6961 frchainS *frchP;
6962
6963 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
6964 {
6965 fragS *fragP;
6966 /* Walk over all of the fragments in a subsection. */
6967 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
6968 {
6969 if ((fragP->fr_type == rs_align
6970 || fragP->fr_type == rs_align_code
6971 || (fragP->fr_type == rs_machine_dependent
6972 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
6973 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
6974 && fragP->fr_fix == 0)
6975 {
6976 fragS *next = fragP->fr_next;
6977
6978 while (next
6979 && next->fr_fix == 0
6980 && next->fr_type == rs_machine_dependent
6981 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
6982 {
6983 frag_wane (next);
6984 next = next->fr_next;
6985 }
6986 }
6987 /* If we don't widen branch targets, then they
6988 will be easier to align. */
6989 if (fragP->tc_frag_data.is_branch_target
6990 && fragP->fr_opcode == fragP->fr_literal
6991 && fragP->fr_type == rs_machine_dependent
6992 && fragP->fr_subtype == RELAX_SLOTS
6993 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
6994 frag_wane (fragP);
6995 if (fragP->fr_type == rs_machine_dependent
6996 && fragP->fr_subtype == RELAX_UNREACHABLE)
6997 fragP->tc_frag_data.is_unreachable = TRUE;
6998 }
6999 }
7000 }
7001
7002
7003 /* Re-process all of the fragments looking to convert all of the
7004 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7005 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7006 Otherwise, convert to a .fill 0. */
7007
7008 static void
xtensa_fix_target_frags(void)7009 xtensa_fix_target_frags (void)
7010 {
7011 frchainS *frchP;
7012
7013 /* When this routine is called, all of the subsections are still intact
7014 so we walk over subsections instead of sections. */
7015 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7016 {
7017 fragS *fragP;
7018
7019 /* Walk over all of the fragments in a subsection. */
7020 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7021 {
7022 if (fragP->fr_type == rs_machine_dependent
7023 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7024 {
7025 if (next_frag_is_branch_target (fragP))
7026 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7027 else
7028 frag_wane (fragP);
7029 }
7030 }
7031 }
7032 }
7033
7034
7035 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
7036
7037 static void
xtensa_mark_narrow_branches(void)7038 xtensa_mark_narrow_branches (void)
7039 {
7040 frchainS *frchP;
7041
7042 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7043 {
7044 fragS *fragP;
7045 /* Walk over all of the fragments in a subsection. */
7046 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7047 {
7048 if (fragP->fr_type == rs_machine_dependent
7049 && fragP->fr_subtype == RELAX_SLOTS
7050 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7051 {
7052 vliw_insn vinsn;
7053 const expressionS *expr;
7054 symbolS *symbolP;
7055
7056 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7057 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7058
7059 expr = &vinsn.slots[0].tok[1];
7060 symbolP = expr->X_add_symbol;
7061
7062 if (vinsn.num_slots == 1
7063 && xtensa_opcode_is_branch (xtensa_default_isa,
7064 vinsn.slots[0].opcode)
7065 && xg_get_single_size (vinsn.slots[0].opcode) == 2
7066 && is_narrow_branch_guaranteed_in_range (fragP,
7067 &vinsn.slots[0]))
7068 {
7069 fragP->fr_subtype = RELAX_SLOTS;
7070 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7071 }
7072 }
7073 }
7074 }
7075 }
7076
7077
7078 /* A branch is typically widened only when its target is out of
7079 range. However, we would like to widen them to align a subsequent
7080 branch target when possible.
7081
7082 Because the branch relaxation code is so convoluted, the optimal solution
7083 (combining the two cases) is difficult to get right in all circumstances.
7084 We therefore go with an "almost as good" solution, where we only
7085 use for alignment narrow branches that definitely will not expand to a
7086 jump and a branch. These functions find and mark these cases. */
7087
7088 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7089 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7090 We start counting beginning with the frag after the 2-byte branch, so the
7091 maximum offset is (4 - 2) + 63 = 65. */
7092 #define MAX_IMMED6 65
7093
7094 static offsetT unrelaxed_frag_max_size (fragS *);
7095
7096 static bfd_boolean
is_narrow_branch_guaranteed_in_range(fragS * fragP,TInsn * tinsn)7097 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
7098 {
7099 const expressionS *expr = &tinsn->tok[1];
7100 symbolS *symbolP = expr->X_add_symbol;
7101 fragS *target_frag = symbol_get_frag (symbolP);
7102 offsetT max_distance = expr->X_add_number;
7103 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
7104 if (is_branch_jmp_to_next (tinsn, fragP))
7105 return FALSE;
7106
7107 /* The branch doesn't branch over it's own frag,
7108 but over the subsequent ones. */
7109 fragP = fragP->fr_next;
7110 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
7111 {
7112 max_distance += unrelaxed_frag_max_size (fragP);
7113 fragP = fragP->fr_next;
7114 }
7115 if (max_distance <= MAX_IMMED6 && fragP == target_frag)
7116 return TRUE;
7117 return FALSE;
7118 }
7119
7120
7121 static void
xtensa_mark_zcl_first_insns(void)7122 xtensa_mark_zcl_first_insns (void)
7123 {
7124 frchainS *frchP;
7125
7126 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7127 {
7128 fragS *fragP;
7129 /* Walk over all of the fragments in a subsection. */
7130 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7131 {
7132 if (fragP->fr_type == rs_machine_dependent
7133 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7134 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7135 {
7136 /* Find the loop frag. */
7137 fragS *targ_frag = next_non_empty_frag (fragP);
7138 /* Find the first insn frag. */
7139 targ_frag = next_non_empty_frag (targ_frag);
7140
7141 /* Of course, sometimes (mostly for toy test cases) a
7142 zero-cost loop instruction is the last in a section. */
7143 if (targ_frag)
7144 targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
7145 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
7146 frag_wane (fragP);
7147 }
7148 }
7149 }
7150 }
7151
7152
7153 /* Re-process all of the fragments looking to convert all of the
7154 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7155 conditional branch or a retw/retw.n, convert this frag to one that
7156 will generate a NOP. In any case close it off with a .fill 0. */
7157
7158 static bfd_boolean next_instrs_are_b_retw (fragS *);
7159
7160 static void
xtensa_fix_a0_b_retw_frags(void)7161 xtensa_fix_a0_b_retw_frags (void)
7162 {
7163 frchainS *frchP;
7164
7165 /* When this routine is called, all of the subsections are still intact
7166 so we walk over subsections instead of sections. */
7167 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7168 {
7169 fragS *fragP;
7170
7171 /* Walk over all of the fragments in a subsection. */
7172 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7173 {
7174 if (fragP->fr_type == rs_machine_dependent
7175 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
7176 {
7177 if (next_instrs_are_b_retw (fragP))
7178 {
7179 if (fragP->tc_frag_data.is_no_transform)
7180 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7181 else
7182 relax_frag_add_nop (fragP);
7183 }
7184 frag_wane (fragP);
7185 }
7186 }
7187 }
7188 }
7189
7190
7191 static bfd_boolean
next_instrs_are_b_retw(fragS * fragP)7192 next_instrs_are_b_retw (fragS *fragP)
7193 {
7194 xtensa_opcode opcode;
7195 xtensa_format fmt;
7196 const fragS *next_fragP = next_non_empty_frag (fragP);
7197 static xtensa_insnbuf insnbuf = NULL;
7198 static xtensa_insnbuf slotbuf = NULL;
7199 xtensa_isa isa = xtensa_default_isa;
7200 int offset = 0;
7201 int slot;
7202 bfd_boolean branch_seen = FALSE;
7203
7204 if (!insnbuf)
7205 {
7206 insnbuf = xtensa_insnbuf_alloc (isa);
7207 slotbuf = xtensa_insnbuf_alloc (isa);
7208 }
7209
7210 if (next_fragP == NULL)
7211 return FALSE;
7212
7213 /* Check for the conditional branch. */
7214 xtensa_insnbuf_from_chars
7215 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
7216 fmt = xtensa_format_decode (isa, insnbuf);
7217 if (fmt == XTENSA_UNDEFINED)
7218 return FALSE;
7219
7220 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7221 {
7222 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
7223 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
7224
7225 branch_seen = (branch_seen
7226 || xtensa_opcode_is_branch (isa, opcode) == 1);
7227 }
7228
7229 if (!branch_seen)
7230 return FALSE;
7231
7232 offset += xtensa_format_length (isa, fmt);
7233 if (offset == next_fragP->fr_fix)
7234 {
7235 next_fragP = next_non_empty_frag (next_fragP);
7236 offset = 0;
7237 }
7238
7239 if (next_fragP == NULL)
7240 return FALSE;
7241
7242 /* Check for the retw/retw.n. */
7243 xtensa_insnbuf_from_chars
7244 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
7245 fmt = xtensa_format_decode (isa, insnbuf);
7246
7247 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7248 have no problems. */
7249 if (fmt == XTENSA_UNDEFINED
7250 || xtensa_format_num_slots (isa, fmt) != 1)
7251 return FALSE;
7252
7253 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
7254 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
7255
7256 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
7257 return TRUE;
7258
7259 return FALSE;
7260 }
7261
7262
7263 /* Re-process all of the fragments looking to convert all of the
7264 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7265 loop end label, convert this frag to one that will generate a NOP.
7266 In any case close it off with a .fill 0. */
7267
7268 static bfd_boolean next_instr_is_loop_end (fragS *);
7269
7270 static void
xtensa_fix_b_j_loop_end_frags(void)7271 xtensa_fix_b_j_loop_end_frags (void)
7272 {
7273 frchainS *frchP;
7274
7275 /* When this routine is called, all of the subsections are still intact
7276 so we walk over subsections instead of sections. */
7277 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7278 {
7279 fragS *fragP;
7280
7281 /* Walk over all of the fragments in a subsection. */
7282 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7283 {
7284 if (fragP->fr_type == rs_machine_dependent
7285 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
7286 {
7287 if (next_instr_is_loop_end (fragP))
7288 {
7289 if (fragP->tc_frag_data.is_no_transform)
7290 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7291 else
7292 relax_frag_add_nop (fragP);
7293 }
7294 frag_wane (fragP);
7295 }
7296 }
7297 }
7298 }
7299
7300
7301 static bfd_boolean
next_instr_is_loop_end(fragS * fragP)7302 next_instr_is_loop_end (fragS *fragP)
7303 {
7304 const fragS *next_fragP;
7305
7306 if (next_frag_is_loop_target (fragP))
7307 return FALSE;
7308
7309 next_fragP = next_non_empty_frag (fragP);
7310 if (next_fragP == NULL)
7311 return FALSE;
7312
7313 if (!next_frag_is_loop_target (next_fragP))
7314 return FALSE;
7315
7316 /* If the size is >= 3 then there is more than one instruction here.
7317 The hardware bug will not fire. */
7318 if (next_fragP->fr_fix > 3)
7319 return FALSE;
7320
7321 return TRUE;
7322 }
7323
7324
7325 /* Re-process all of the fragments looking to convert all of the
7326 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7327 not MY loop's loop end within 12 bytes, add enough nops here to
7328 make it at least 12 bytes away. In any case close it off with a
7329 .fill 0. */
7330
7331 static offsetT min_bytes_to_other_loop_end
7332 (fragS *, fragS *, offsetT, offsetT);
7333
7334 static void
xtensa_fix_close_loop_end_frags(void)7335 xtensa_fix_close_loop_end_frags (void)
7336 {
7337 frchainS *frchP;
7338
7339 /* When this routine is called, all of the subsections are still intact
7340 so we walk over subsections instead of sections. */
7341 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7342 {
7343 fragS *fragP;
7344
7345 fragS *current_target = NULL;
7346 offsetT current_offset = 0;
7347
7348 /* Walk over all of the fragments in a subsection. */
7349 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7350 {
7351 if (fragP->fr_type == rs_machine_dependent
7352 && ((fragP->fr_subtype == RELAX_IMMED)
7353 || ((fragP->fr_subtype == RELAX_SLOTS)
7354 && (fragP->tc_frag_data.slot_subtypes[0]
7355 == RELAX_IMMED))))
7356 {
7357 /* Read it. If the instruction is a loop, get the target. */
7358 TInsn t_insn;
7359 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7360 if (xtensa_opcode_is_loop (xtensa_default_isa,
7361 t_insn.opcode) == 1)
7362 {
7363 /* Get the current fragment target. */
7364 if (fragP->tc_frag_data.slot_symbols[0])
7365 {
7366 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7367 current_target = symbol_get_frag (sym);
7368 current_offset = fragP->fr_offset;
7369 }
7370 }
7371 }
7372
7373 if (current_target
7374 && fragP->fr_type == rs_machine_dependent
7375 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
7376 {
7377 offsetT min_bytes;
7378 int bytes_added = 0;
7379
7380 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7381 /* Max out at 12. */
7382 min_bytes = min_bytes_to_other_loop_end
7383 (fragP->fr_next, current_target, current_offset,
7384 REQUIRED_LOOP_DIVIDING_BYTES);
7385
7386 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
7387 {
7388 if (fragP->tc_frag_data.is_no_transform)
7389 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7390 else
7391 {
7392 while (min_bytes + bytes_added
7393 < REQUIRED_LOOP_DIVIDING_BYTES)
7394 {
7395 int length = 3;
7396
7397 if (fragP->fr_var < length)
7398 as_fatal (_("fr_var %lu < length %d"),
7399 (long) fragP->fr_var, length);
7400 else
7401 {
7402 assemble_nop (length,
7403 fragP->fr_literal + fragP->fr_fix);
7404 fragP->fr_fix += length;
7405 fragP->fr_var -= length;
7406 }
7407 bytes_added += length;
7408 }
7409 }
7410 }
7411 frag_wane (fragP);
7412 }
7413 assert (fragP->fr_type != rs_machine_dependent
7414 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
7415 }
7416 }
7417 }
7418
7419
7420 static offsetT unrelaxed_frag_min_size (fragS *);
7421
7422 static offsetT
min_bytes_to_other_loop_end(fragS * fragP,fragS * current_target,offsetT current_offset,offsetT max_size)7423 min_bytes_to_other_loop_end (fragS *fragP,
7424 fragS *current_target,
7425 offsetT current_offset,
7426 offsetT max_size)
7427 {
7428 offsetT offset = 0;
7429 fragS *current_fragP;
7430
7431 for (current_fragP = fragP;
7432 current_fragP;
7433 current_fragP = current_fragP->fr_next)
7434 {
7435 if (current_fragP->tc_frag_data.is_loop_target
7436 && current_fragP != current_target)
7437 return offset + current_offset;
7438
7439 offset += unrelaxed_frag_min_size (current_fragP);
7440
7441 if (offset + current_offset >= max_size)
7442 return max_size;
7443 }
7444 return max_size;
7445 }
7446
7447
7448 static offsetT
unrelaxed_frag_min_size(fragS * fragP)7449 unrelaxed_frag_min_size (fragS *fragP)
7450 {
7451 offsetT size = fragP->fr_fix;
7452
7453 /* Add fill size. */
7454 if (fragP->fr_type == rs_fill)
7455 size += fragP->fr_offset;
7456
7457 return size;
7458 }
7459
7460
7461 static offsetT
unrelaxed_frag_max_size(fragS * fragP)7462 unrelaxed_frag_max_size (fragS *fragP)
7463 {
7464 offsetT size = fragP->fr_fix;
7465 switch (fragP->fr_type)
7466 {
7467 case 0:
7468 /* Empty frags created by the obstack allocation scheme
7469 end up with type 0. */
7470 break;
7471 case rs_fill:
7472 case rs_org:
7473 case rs_space:
7474 size += fragP->fr_offset;
7475 break;
7476 case rs_align:
7477 case rs_align_code:
7478 case rs_align_test:
7479 case rs_leb128:
7480 case rs_cfa:
7481 case rs_dwarf2dbg:
7482 /* No further adjustments needed. */
7483 break;
7484 case rs_machine_dependent:
7485 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
7486 size += fragP->fr_var;
7487 break;
7488 default:
7489 /* We had darn well better know how big it is. */
7490 assert (0);
7491 break;
7492 }
7493
7494 return size;
7495 }
7496
7497
7498 /* Re-process all of the fragments looking to convert all
7499 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7500
7501 A)
7502 1) the instruction size count to the loop end label
7503 is too short (<= 2 instructions),
7504 2) loop has a jump or branch in it
7505
7506 or B)
7507 1) workaround_all_short_loops is TRUE
7508 2) The generating loop was a 'loopgtz' or 'loopnez'
7509 3) the instruction size count to the loop end label is too short
7510 (<= 2 instructions)
7511 then convert this frag (and maybe the next one) to generate a NOP.
7512 In any case close it off with a .fill 0. */
7513
7514 static int count_insns_to_loop_end (fragS *, bfd_boolean, int);
7515 static bfd_boolean branch_before_loop_end (fragS *);
7516
7517 static void
xtensa_fix_short_loop_frags(void)7518 xtensa_fix_short_loop_frags (void)
7519 {
7520 frchainS *frchP;
7521
7522 /* When this routine is called, all of the subsections are still intact
7523 so we walk over subsections instead of sections. */
7524 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7525 {
7526 fragS *fragP;
7527 fragS *current_target = NULL;
7528 offsetT current_offset = 0;
7529 xtensa_opcode current_opcode = XTENSA_UNDEFINED;
7530
7531 /* Walk over all of the fragments in a subsection. */
7532 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7533 {
7534 /* Check on the current loop. */
7535 if (fragP->fr_type == rs_machine_dependent
7536 && ((fragP->fr_subtype == RELAX_IMMED)
7537 || ((fragP->fr_subtype == RELAX_SLOTS)
7538 && (fragP->tc_frag_data.slot_subtypes[0]
7539 == RELAX_IMMED))))
7540 {
7541 TInsn t_insn;
7542
7543 /* Read it. If the instruction is a loop, get the target. */
7544 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7545 if (xtensa_opcode_is_loop (xtensa_default_isa,
7546 t_insn.opcode) == 1)
7547 {
7548 /* Get the current fragment target. */
7549 if (fragP->tc_frag_data.slot_symbols[0])
7550 {
7551 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7552 current_target = symbol_get_frag (sym);
7553 current_offset = fragP->fr_offset;
7554 current_opcode = t_insn.opcode;
7555 }
7556 }
7557 }
7558
7559 if (fragP->fr_type == rs_machine_dependent
7560 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7561 {
7562 if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
7563 && (branch_before_loop_end (fragP->fr_next)
7564 || (workaround_all_short_loops
7565 && current_opcode != XTENSA_UNDEFINED
7566 && current_opcode != xtensa_loop_opcode)))
7567 {
7568 if (fragP->tc_frag_data.is_no_transform)
7569 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7570 else
7571 relax_frag_add_nop (fragP);
7572 }
7573 frag_wane (fragP);
7574 }
7575 }
7576 }
7577 }
7578
7579
7580 static int unrelaxed_frag_min_insn_count (fragS *);
7581
7582 static int
count_insns_to_loop_end(fragS * base_fragP,bfd_boolean count_relax_add,int max_count)7583 count_insns_to_loop_end (fragS *base_fragP,
7584 bfd_boolean count_relax_add,
7585 int max_count)
7586 {
7587 fragS *fragP = NULL;
7588 int insn_count = 0;
7589
7590 fragP = base_fragP;
7591
7592 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
7593 {
7594 insn_count += unrelaxed_frag_min_insn_count (fragP);
7595 if (insn_count >= max_count)
7596 return max_count;
7597
7598 if (count_relax_add)
7599 {
7600 if (fragP->fr_type == rs_machine_dependent
7601 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7602 {
7603 /* In order to add the appropriate number of
7604 NOPs, we count an instruction for downstream
7605 occurrences. */
7606 insn_count++;
7607 if (insn_count >= max_count)
7608 return max_count;
7609 }
7610 }
7611 }
7612 return insn_count;
7613 }
7614
7615
7616 static int
unrelaxed_frag_min_insn_count(fragS * fragP)7617 unrelaxed_frag_min_insn_count (fragS *fragP)
7618 {
7619 xtensa_isa isa = xtensa_default_isa;
7620 static xtensa_insnbuf insnbuf = NULL;
7621 int insn_count = 0;
7622 int offset = 0;
7623
7624 if (!fragP->tc_frag_data.is_insn)
7625 return insn_count;
7626
7627 if (!insnbuf)
7628 insnbuf = xtensa_insnbuf_alloc (isa);
7629
7630 /* Decode the fixed instructions. */
7631 while (offset < fragP->fr_fix)
7632 {
7633 xtensa_format fmt;
7634
7635 xtensa_insnbuf_from_chars
7636 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
7637 fmt = xtensa_format_decode (isa, insnbuf);
7638
7639 if (fmt == XTENSA_UNDEFINED)
7640 {
7641 as_fatal (_("undecodable instruction in instruction frag"));
7642 return insn_count;
7643 }
7644 offset += xtensa_format_length (isa, fmt);
7645 insn_count++;
7646 }
7647
7648 return insn_count;
7649 }
7650
7651
7652 static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
7653
7654 static bfd_boolean
branch_before_loop_end(fragS * base_fragP)7655 branch_before_loop_end (fragS *base_fragP)
7656 {
7657 fragS *fragP;
7658
7659 for (fragP = base_fragP;
7660 fragP && !fragP->tc_frag_data.is_loop_target;
7661 fragP = fragP->fr_next)
7662 {
7663 if (unrelaxed_frag_has_b_j (fragP))
7664 return TRUE;
7665 }
7666 return FALSE;
7667 }
7668
7669
7670 static bfd_boolean
unrelaxed_frag_has_b_j(fragS * fragP)7671 unrelaxed_frag_has_b_j (fragS *fragP)
7672 {
7673 static xtensa_insnbuf insnbuf = NULL;
7674 xtensa_isa isa = xtensa_default_isa;
7675 int offset = 0;
7676
7677 if (!fragP->tc_frag_data.is_insn)
7678 return FALSE;
7679
7680 if (!insnbuf)
7681 insnbuf = xtensa_insnbuf_alloc (isa);
7682
7683 /* Decode the fixed instructions. */
7684 while (offset < fragP->fr_fix)
7685 {
7686 xtensa_format fmt;
7687 int slot;
7688
7689 xtensa_insnbuf_from_chars
7690 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
7691 fmt = xtensa_format_decode (isa, insnbuf);
7692 if (fmt == XTENSA_UNDEFINED)
7693 return FALSE;
7694
7695 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7696 {
7697 xtensa_opcode opcode =
7698 get_opcode_from_buf (fragP->fr_literal + offset, slot);
7699 if (xtensa_opcode_is_branch (isa, opcode) == 1
7700 || xtensa_opcode_is_jump (isa, opcode) == 1)
7701 return TRUE;
7702 }
7703 offset += xtensa_format_length (isa, fmt);
7704 }
7705 return FALSE;
7706 }
7707
7708
7709 /* Checks to be made after initial assembly but before relaxation. */
7710
7711 static bfd_boolean is_empty_loop (const TInsn *, fragS *);
7712 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
7713
7714 static void
xtensa_sanity_check(void)7715 xtensa_sanity_check (void)
7716 {
7717 char *file_name;
7718 unsigned line;
7719
7720 frchainS *frchP;
7721
7722 as_where (&file_name, &line);
7723 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7724 {
7725 fragS *fragP;
7726
7727 /* Walk over all of the fragments in a subsection. */
7728 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7729 {
7730 /* Currently we only check for empty loops here. */
7731 if (fragP->fr_type == rs_machine_dependent
7732 && fragP->fr_subtype == RELAX_IMMED)
7733 {
7734 static xtensa_insnbuf insnbuf = NULL;
7735 TInsn t_insn;
7736
7737 if (fragP->fr_opcode != NULL)
7738 {
7739 if (!insnbuf)
7740 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
7741 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7742 tinsn_immed_from_frag (&t_insn, fragP, 0);
7743
7744 if (xtensa_opcode_is_loop (xtensa_default_isa,
7745 t_insn.opcode) == 1)
7746 {
7747 if (is_empty_loop (&t_insn, fragP))
7748 {
7749 new_logical_line (fragP->fr_file, fragP->fr_line);
7750 as_bad (_("invalid empty loop"));
7751 }
7752 if (!is_local_forward_loop (&t_insn, fragP))
7753 {
7754 new_logical_line (fragP->fr_file, fragP->fr_line);
7755 as_bad (_("loop target does not follow "
7756 "loop instruction in section"));
7757 }
7758 }
7759 }
7760 }
7761 }
7762 }
7763 new_logical_line (file_name, line);
7764 }
7765
7766
7767 #define LOOP_IMMED_OPN 1
7768
7769 /* Return TRUE if the loop target is the next non-zero fragment. */
7770
7771 static bfd_boolean
is_empty_loop(const TInsn * insn,fragS * fragP)7772 is_empty_loop (const TInsn *insn, fragS *fragP)
7773 {
7774 const expressionS *expr;
7775 symbolS *symbolP;
7776 fragS *next_fragP;
7777
7778 if (insn->insn_type != ITYPE_INSN)
7779 return FALSE;
7780
7781 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
7782 return FALSE;
7783
7784 if (insn->ntok <= LOOP_IMMED_OPN)
7785 return FALSE;
7786
7787 expr = &insn->tok[LOOP_IMMED_OPN];
7788
7789 if (expr->X_op != O_symbol)
7790 return FALSE;
7791
7792 symbolP = expr->X_add_symbol;
7793 if (!symbolP)
7794 return FALSE;
7795
7796 if (symbol_get_frag (symbolP) == NULL)
7797 return FALSE;
7798
7799 if (S_GET_VALUE (symbolP) != 0)
7800 return FALSE;
7801
7802 /* Walk through the zero-size fragments from this one. If we find
7803 the target fragment, then this is a zero-size loop. */
7804
7805 for (next_fragP = fragP->fr_next;
7806 next_fragP != NULL;
7807 next_fragP = next_fragP->fr_next)
7808 {
7809 if (next_fragP == symbol_get_frag (symbolP))
7810 return TRUE;
7811 if (next_fragP->fr_fix != 0)
7812 return FALSE;
7813 }
7814 return FALSE;
7815 }
7816
7817
7818 static bfd_boolean
is_local_forward_loop(const TInsn * insn,fragS * fragP)7819 is_local_forward_loop (const TInsn *insn, fragS *fragP)
7820 {
7821 const expressionS *expr;
7822 symbolS *symbolP;
7823 fragS *next_fragP;
7824
7825 if (insn->insn_type != ITYPE_INSN)
7826 return FALSE;
7827
7828 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0)
7829 return FALSE;
7830
7831 if (insn->ntok <= LOOP_IMMED_OPN)
7832 return FALSE;
7833
7834 expr = &insn->tok[LOOP_IMMED_OPN];
7835
7836 if (expr->X_op != O_symbol)
7837 return FALSE;
7838
7839 symbolP = expr->X_add_symbol;
7840 if (!symbolP)
7841 return FALSE;
7842
7843 if (symbol_get_frag (symbolP) == NULL)
7844 return FALSE;
7845
7846 /* Walk through fragments until we find the target.
7847 If we do not find the target, then this is an invalid loop. */
7848
7849 for (next_fragP = fragP->fr_next;
7850 next_fragP != NULL;
7851 next_fragP = next_fragP->fr_next)
7852 {
7853 if (next_fragP == symbol_get_frag (symbolP))
7854 return TRUE;
7855 }
7856
7857 return FALSE;
7858 }
7859
7860
7861 /* Alignment Functions. */
7862
7863 static int
get_text_align_power(unsigned target_size)7864 get_text_align_power (unsigned target_size)
7865 {
7866 int i = 0;
7867 unsigned power = 1;
7868
7869 assert (target_size <= INT_MAX);
7870 while (target_size > power)
7871 {
7872 power <<= 1;
7873 i += 1;
7874 }
7875 return i;
7876 }
7877
7878
7879 static int
get_text_align_max_fill_size(int align_pow,bfd_boolean use_nops,bfd_boolean use_no_density)7880 get_text_align_max_fill_size (int align_pow,
7881 bfd_boolean use_nops,
7882 bfd_boolean use_no_density)
7883 {
7884 if (!use_nops)
7885 return (1 << align_pow);
7886 if (use_no_density)
7887 return 3 * (1 << align_pow);
7888
7889 return 1 + (1 << align_pow);
7890 }
7891
7892
7893 /* Calculate the minimum bytes of fill needed at "address" to align a
7894 target instruction of size "target_size" so that it does not cross a
7895 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7896 the fill can be an arbitrary number of bytes. Otherwise, the space must
7897 be filled by NOP instructions. */
7898
7899 static int
get_text_align_fill_size(addressT address,int align_pow,int target_size,bfd_boolean use_nops,bfd_boolean use_no_density)7900 get_text_align_fill_size (addressT address,
7901 int align_pow,
7902 int target_size,
7903 bfd_boolean use_nops,
7904 bfd_boolean use_no_density)
7905 {
7906 addressT alignment, fill, fill_limit, fill_step;
7907 bfd_boolean skip_one = FALSE;
7908
7909 alignment = (1 << align_pow);
7910 assert (target_size > 0 && alignment >= (addressT) target_size);
7911
7912 if (!use_nops)
7913 {
7914 fill_limit = alignment;
7915 fill_step = 1;
7916 }
7917 else if (!use_no_density)
7918 {
7919 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7920 fill_limit = alignment * 2;
7921 fill_step = 1;
7922 skip_one = TRUE;
7923 }
7924 else
7925 {
7926 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7927 fill_limit = alignment * 3;
7928 fill_step = 3;
7929 }
7930
7931 /* Try all fill sizes until finding one that works. */
7932 for (fill = 0; fill < fill_limit; fill += fill_step)
7933 {
7934 if (skip_one && fill == 1)
7935 continue;
7936 if ((address + fill) >> align_pow
7937 == (address + fill + target_size - 1) >> align_pow)
7938 return fill;
7939 }
7940 assert (0);
7941 return 0;
7942 }
7943
7944
7945 static int
branch_align_power(segT sec)7946 branch_align_power (segT sec)
7947 {
7948 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7949 is aligned to at least an 8-byte boundary, then a branch target need
7950 only fit within an 8-byte aligned block of memory to avoid a stall.
7951 Otherwise, try to fit branch targets within 4-byte aligned blocks
7952 (which may be insufficient, e.g., if the section has no alignment, but
7953 it's good enough). */
7954 if (xtensa_fetch_width == 8)
7955 {
7956 if (get_recorded_alignment (sec) >= 3)
7957 return 3;
7958 }
7959 else
7960 assert (xtensa_fetch_width == 4);
7961
7962 return 2;
7963 }
7964
7965
7966 /* This will assert if it is not possible. */
7967
7968 static int
get_text_align_nop_count(offsetT fill_size,bfd_boolean use_no_density)7969 get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density)
7970 {
7971 int count = 0;
7972
7973 if (use_no_density)
7974 {
7975 assert (fill_size % 3 == 0);
7976 return (fill_size / 3);
7977 }
7978
7979 assert (fill_size != 1); /* Bad argument. */
7980
7981 while (fill_size > 1)
7982 {
7983 int insn_size = 3;
7984 if (fill_size == 2 || fill_size == 4)
7985 insn_size = 2;
7986 fill_size -= insn_size;
7987 count++;
7988 }
7989 assert (fill_size != 1); /* Bad algorithm. */
7990 return count;
7991 }
7992
7993
7994 static int
get_text_align_nth_nop_size(offsetT fill_size,int n,bfd_boolean use_no_density)7995 get_text_align_nth_nop_size (offsetT fill_size,
7996 int n,
7997 bfd_boolean use_no_density)
7998 {
7999 int count = 0;
8000
8001 if (use_no_density)
8002 return 3;
8003
8004 assert (fill_size != 1); /* Bad argument. */
8005
8006 while (fill_size > 1)
8007 {
8008 int insn_size = 3;
8009 if (fill_size == 2 || fill_size == 4)
8010 insn_size = 2;
8011 fill_size -= insn_size;
8012 count++;
8013 if (n + 1 == count)
8014 return insn_size;
8015 }
8016 assert (0);
8017 return 0;
8018 }
8019
8020
8021 /* For the given fragment, find the appropriate address
8022 for it to begin at if we are using NOPs to align it. */
8023
8024 static addressT
get_noop_aligned_address(fragS * fragP,addressT address)8025 get_noop_aligned_address (fragS *fragP, addressT address)
8026 {
8027 /* The rule is: get next fragment's FIRST instruction. Find
8028 the smallest number of bytes that need to be added to
8029 ensure that the next fragment's FIRST instruction will fit
8030 in a single word.
8031
8032 E.G., 2 bytes : 0, 1, 2 mod 4
8033 3 bytes: 0, 1 mod 4
8034
8035 If the FIRST instruction MIGHT be relaxed,
8036 assume that it will become a 3-byte instruction.
8037
8038 Note again here that LOOP instructions are not bundleable,
8039 and this relaxation only applies to LOOP opcodes. */
8040
8041 int fill_size = 0;
8042 int first_insn_size;
8043 int loop_insn_size;
8044 addressT pre_opcode_bytes;
8045 int align_power;
8046 fragS *first_insn;
8047 xtensa_opcode opcode;
8048 bfd_boolean is_loop;
8049
8050 assert (fragP->fr_type == rs_machine_dependent);
8051 assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
8052
8053 /* Find the loop frag. */
8054 first_insn = next_non_empty_frag (fragP);
8055 /* Now find the first insn frag. */
8056 first_insn = next_non_empty_frag (first_insn);
8057
8058 is_loop = next_frag_opcode_is_loop (fragP, &opcode);
8059 assert (is_loop);
8060 loop_insn_size = xg_get_single_size (opcode);
8061
8062 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
8063 pre_opcode_bytes += loop_insn_size;
8064
8065 /* For loops, the alignment depends on the size of the
8066 instruction following the loop, not the LOOP instruction. */
8067
8068 if (first_insn == NULL)
8069 return address;
8070
8071 assert (first_insn->tc_frag_data.is_first_loop_insn);
8072
8073 first_insn_size = frag_format_size (first_insn);
8074
8075 if (first_insn_size == 2 || first_insn_size == XTENSA_UNDEFINED)
8076 first_insn_size = 3; /* ISA specifies this */
8077
8078 /* If it was 8, then we'll need a larger alignment for the section. */
8079 align_power = get_text_align_power (first_insn_size);
8080 record_alignment (now_seg, align_power);
8081
8082 fill_size = get_text_align_fill_size
8083 (address + pre_opcode_bytes, align_power, first_insn_size, TRUE,
8084 fragP->tc_frag_data.is_no_density);
8085
8086 return address + fill_size;
8087 }
8088
8089
8090 /* 3 mechanisms for relaxing an alignment:
8091
8092 Align to a power of 2.
8093 Align so the next fragment's instruction does not cross a word boundary.
8094 Align the current instruction so that if the next instruction
8095 were 3 bytes, it would not cross a word boundary.
8096
8097 We can align with:
8098
8099 zeros - This is easy; always insert zeros.
8100 nops - 3-byte and 2-byte instructions
8101 2 - 2-byte nop
8102 3 - 3-byte nop
8103 4 - 2 2-byte nops
8104 >=5 : 3-byte instruction + fn (n-3)
8105 widening - widen previous instructions. */
8106
8107 static offsetT
get_aligned_diff(fragS * fragP,addressT address,offsetT * max_diff)8108 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff)
8109 {
8110 addressT target_address, loop_insn_offset;
8111 int target_size;
8112 xtensa_opcode loop_opcode;
8113 bfd_boolean is_loop;
8114 int align_power;
8115 offsetT opt_diff;
8116 offsetT branch_align;
8117
8118 assert (fragP->fr_type == rs_machine_dependent);
8119 switch (fragP->fr_subtype)
8120 {
8121 case RELAX_DESIRE_ALIGN:
8122 target_size = next_frag_format_size (fragP);
8123 if (target_size == XTENSA_UNDEFINED)
8124 target_size = 3;
8125 align_power = branch_align_power (now_seg);
8126 branch_align = 1 << align_power;
8127 /* Don't count on the section alignment being as large as the target. */
8128 if (target_size > branch_align)
8129 target_size = branch_align;
8130 opt_diff = get_text_align_fill_size (address, align_power,
8131 target_size, FALSE, FALSE);
8132
8133 *max_diff = (opt_diff + branch_align
8134 - (target_size + ((address + opt_diff) % branch_align)));
8135 assert (*max_diff >= opt_diff);
8136 return opt_diff;
8137
8138 case RELAX_ALIGN_NEXT_OPCODE:
8139 target_size = next_frag_format_size (fragP);
8140 loop_insn_offset = 0;
8141 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
8142 assert (is_loop);
8143
8144 /* If the loop has been expanded then the LOOP instruction
8145 could be at an offset from this fragment. */
8146 if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0]
8147 != RELAX_IMMED)
8148 loop_insn_offset = get_expanded_loop_offset (loop_opcode);
8149
8150 if (target_size == 2)
8151 target_size = 3; /* ISA specifies this */
8152
8153 /* In an ideal world, which is what we are shooting for here,
8154 we wouldn't need to use any NOPs immediately prior to the
8155 LOOP instruction. If this approach fails, relax_frag_loop_align
8156 will call get_noop_aligned_address. */
8157 target_address =
8158 address + loop_insn_offset + xg_get_single_size (loop_opcode);
8159 align_power = get_text_align_power (target_size),
8160 opt_diff = get_text_align_fill_size (target_address, align_power,
8161 target_size, FALSE, FALSE);
8162
8163 *max_diff = xtensa_fetch_width
8164 - ((target_address + opt_diff) % xtensa_fetch_width)
8165 - target_size + opt_diff;
8166 assert (*max_diff >= opt_diff);
8167 return opt_diff;
8168
8169 default:
8170 break;
8171 }
8172 assert (0);
8173 return 0;
8174 }
8175
8176
8177 /* md_relax_frag Hook and Helper Functions. */
8178
8179 static long relax_frag_loop_align (fragS *, long);
8180 static long relax_frag_for_align (fragS *, long);
8181 static long relax_frag_immed
8182 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
8183
8184
8185 /* Return the number of bytes added to this fragment, given that the
8186 input has been stretched already by "stretch". */
8187
8188 long
xtensa_relax_frag(fragS * fragP,long stretch,int * stretched_p)8189 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
8190 {
8191 xtensa_isa isa = xtensa_default_isa;
8192 int unreported = fragP->tc_frag_data.unreported_expansion;
8193 long new_stretch = 0;
8194 char *file_name;
8195 unsigned line;
8196 int lit_size;
8197 static xtensa_insnbuf vbuf = NULL;
8198 int slot, num_slots;
8199 xtensa_format fmt;
8200
8201 as_where (&file_name, &line);
8202 new_logical_line (fragP->fr_file, fragP->fr_line);
8203
8204 fragP->tc_frag_data.unreported_expansion = 0;
8205
8206 switch (fragP->fr_subtype)
8207 {
8208 case RELAX_ALIGN_NEXT_OPCODE:
8209 /* Always convert. */
8210 if (fragP->tc_frag_data.relax_seen)
8211 new_stretch = relax_frag_loop_align (fragP, stretch);
8212 break;
8213
8214 case RELAX_LOOP_END:
8215 /* Do nothing. */
8216 break;
8217
8218 case RELAX_LOOP_END_ADD_NOP:
8219 /* Add a NOP and switch to .fill 0. */
8220 new_stretch = relax_frag_add_nop (fragP);
8221 frag_wane (fragP);
8222 break;
8223
8224 case RELAX_DESIRE_ALIGN:
8225 /* Do nothing. The narrowing before this frag will either align
8226 it or not. */
8227 break;
8228
8229 case RELAX_LITERAL:
8230 case RELAX_LITERAL_FINAL:
8231 return 0;
8232
8233 case RELAX_LITERAL_NR:
8234 lit_size = 4;
8235 fragP->fr_subtype = RELAX_LITERAL_FINAL;
8236 assert (unreported == lit_size);
8237 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
8238 fragP->fr_var -= lit_size;
8239 fragP->fr_fix += lit_size;
8240 new_stretch = 4;
8241 break;
8242
8243 case RELAX_SLOTS:
8244 if (vbuf == NULL)
8245 vbuf = xtensa_insnbuf_alloc (isa);
8246
8247 xtensa_insnbuf_from_chars
8248 (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0);
8249 fmt = xtensa_format_decode (isa, vbuf);
8250 num_slots = xtensa_format_num_slots (isa, fmt);
8251
8252 for (slot = 0; slot < num_slots; slot++)
8253 {
8254 switch (fragP->tc_frag_data.slot_subtypes[slot])
8255 {
8256 case RELAX_NARROW:
8257 if (fragP->tc_frag_data.relax_seen)
8258 new_stretch += relax_frag_for_align (fragP, stretch);
8259 break;
8260
8261 case RELAX_IMMED:
8262 case RELAX_IMMED_STEP1:
8263 case RELAX_IMMED_STEP2:
8264 /* Place the immediate. */
8265 new_stretch += relax_frag_immed
8266 (now_seg, fragP, stretch,
8267 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
8268 fmt, slot, stretched_p, FALSE);
8269 break;
8270
8271 default:
8272 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8273 break;
8274 }
8275 }
8276 break;
8277
8278 case RELAX_LITERAL_POOL_BEGIN:
8279 case RELAX_LITERAL_POOL_END:
8280 case RELAX_MAYBE_UNREACHABLE:
8281 case RELAX_MAYBE_DESIRE_ALIGN:
8282 /* No relaxation required. */
8283 break;
8284
8285 case RELAX_FILL_NOP:
8286 case RELAX_UNREACHABLE:
8287 if (fragP->tc_frag_data.relax_seen)
8288 new_stretch += relax_frag_for_align (fragP, stretch);
8289 break;
8290
8291 default:
8292 as_bad (_("bad relaxation state"));
8293 }
8294
8295 /* Tell gas we need another relaxation pass. */
8296 if (! fragP->tc_frag_data.relax_seen)
8297 {
8298 fragP->tc_frag_data.relax_seen = TRUE;
8299 *stretched_p = 1;
8300 }
8301
8302 new_logical_line (file_name, line);
8303 return new_stretch;
8304 }
8305
8306
8307 static long
relax_frag_loop_align(fragS * fragP,long stretch)8308 relax_frag_loop_align (fragS *fragP, long stretch)
8309 {
8310 addressT old_address, old_next_address, old_size;
8311 addressT new_address, new_next_address, new_size;
8312 addressT growth;
8313
8314 /* All the frags with relax_frag_for_alignment prior to this one in the
8315 section have been done, hopefully eliminating the need for a NOP here.
8316 But, this will put it in if necessary. */
8317
8318 /* Calculate the old address of this fragment and the next fragment. */
8319 old_address = fragP->fr_address - stretch;
8320 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
8321 fragP->tc_frag_data.text_expansion[0]);
8322 old_size = old_next_address - old_address;
8323
8324 /* Calculate the new address of this fragment and the next fragment. */
8325 new_address = fragP->fr_address;
8326 new_next_address =
8327 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
8328 new_size = new_next_address - new_address;
8329
8330 growth = new_size - old_size;
8331
8332 /* Fix up the text_expansion field and return the new growth. */
8333 fragP->tc_frag_data.text_expansion[0] += growth;
8334 return growth;
8335 }
8336
8337
8338 /* Add a NOP instruction. */
8339
8340 static long
relax_frag_add_nop(fragS * fragP)8341 relax_frag_add_nop (fragS *fragP)
8342 {
8343 char *nop_buf = fragP->fr_literal + fragP->fr_fix;
8344 int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
8345 assemble_nop (length, nop_buf);
8346 fragP->tc_frag_data.is_insn = TRUE;
8347
8348 if (fragP->fr_var < length)
8349 {
8350 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length);
8351 return 0;
8352 }
8353
8354 fragP->fr_fix += length;
8355 fragP->fr_var -= length;
8356 return length;
8357 }
8358
8359
8360 static long future_alignment_required (fragS *, long);
8361
8362 static long
relax_frag_for_align(fragS * fragP,long stretch)8363 relax_frag_for_align (fragS *fragP, long stretch)
8364 {
8365 /* Overview of the relaxation procedure for alignment:
8366 We can widen with NOPs or by widening instructions or by filling
8367 bytes after jump instructions. Find the opportune places and widen
8368 them if necessary. */
8369
8370 long stretch_me;
8371 long diff;
8372
8373 assert (fragP->fr_subtype == RELAX_FILL_NOP
8374 || fragP->fr_subtype == RELAX_UNREACHABLE
8375 || (fragP->fr_subtype == RELAX_SLOTS
8376 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
8377
8378 stretch_me = future_alignment_required (fragP, stretch);
8379 diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
8380 if (diff == 0)
8381 return 0;
8382
8383 if (diff < 0)
8384 {
8385 /* We expanded on a previous pass. Can we shrink now? */
8386 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
8387 if (shrink <= stretch && stretch > 0)
8388 {
8389 fragP->tc_frag_data.text_expansion[0] = stretch_me;
8390 return -shrink;
8391 }
8392 return 0;
8393 }
8394
8395 /* Below here, diff > 0. */
8396 fragP->tc_frag_data.text_expansion[0] = stretch_me;
8397
8398 return diff;
8399 }
8400
8401
8402 /* Return the address of the next frag that should be aligned.
8403
8404 By "address" we mean the address it _would_ be at if there
8405 is no action taken to align it between here and the target frag.
8406 In other words, if no narrows and no fill nops are used between
8407 here and the frag to align, _even_if_ some of the frags we use
8408 to align targets have already expanded on a previous relaxation
8409 pass.
8410
8411 Also, count each frag that may be used to help align the target.
8412
8413 Return 0 if there are no frags left in the chain that need to be
8414 aligned. */
8415
8416 static addressT
find_address_of_next_align_frag(fragS ** fragPP,int * wide_nops,int * narrow_nops,int * widens,bfd_boolean * paddable)8417 find_address_of_next_align_frag (fragS **fragPP,
8418 int *wide_nops,
8419 int *narrow_nops,
8420 int *widens,
8421 bfd_boolean *paddable)
8422 {
8423 fragS *fragP = *fragPP;
8424 addressT address = fragP->fr_address;
8425
8426 /* Do not reset the counts to 0. */
8427
8428 while (fragP)
8429 {
8430 /* Limit this to a small search. */
8431 if (*widens > 8)
8432 {
8433 *fragPP = fragP;
8434 return 0;
8435 }
8436 address += fragP->fr_fix;
8437
8438 if (fragP->fr_type == rs_fill)
8439 address += fragP->fr_offset * fragP->fr_var;
8440 else if (fragP->fr_type == rs_machine_dependent)
8441 {
8442 switch (fragP->fr_subtype)
8443 {
8444 case RELAX_UNREACHABLE:
8445 *paddable = TRUE;
8446 break;
8447
8448 case RELAX_FILL_NOP:
8449 (*wide_nops)++;
8450 if (!fragP->tc_frag_data.is_no_density)
8451 (*narrow_nops)++;
8452 break;
8453
8454 case RELAX_SLOTS:
8455 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8456 {
8457 (*widens)++;
8458 break;
8459 }
8460 address += total_frag_text_expansion (fragP);;
8461 break;
8462
8463 case RELAX_IMMED:
8464 address += fragP->tc_frag_data.text_expansion[0];
8465 break;
8466
8467 case RELAX_ALIGN_NEXT_OPCODE:
8468 case RELAX_DESIRE_ALIGN:
8469 *fragPP = fragP;
8470 return address;
8471
8472 case RELAX_MAYBE_UNREACHABLE:
8473 case RELAX_MAYBE_DESIRE_ALIGN:
8474 /* Do nothing. */
8475 break;
8476
8477 default:
8478 /* Just punt if we don't know the type. */
8479 *fragPP = fragP;
8480 return 0;
8481 }
8482 }
8483 else
8484 {
8485 /* Just punt if we don't know the type. */
8486 *fragPP = fragP;
8487 return 0;
8488 }
8489 fragP = fragP->fr_next;
8490 }
8491
8492 *fragPP = fragP;
8493 return 0;
8494 }
8495
8496
8497 static long bytes_to_stretch (fragS *, int, int, int, int);
8498
8499 static long
future_alignment_required(fragS * fragP,long stretch ATTRIBUTE_UNUSED)8500 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
8501 {
8502 fragS *this_frag = fragP;
8503 long address;
8504 int num_widens = 0;
8505 int wide_nops = 0;
8506 int narrow_nops = 0;
8507 bfd_boolean paddable = FALSE;
8508 offsetT local_opt_diff;
8509 offsetT opt_diff;
8510 offsetT max_diff;
8511 int stretch_amount = 0;
8512 int local_stretch_amount;
8513 int global_stretch_amount;
8514
8515 address = find_address_of_next_align_frag
8516 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
8517
8518 if (address)
8519 {
8520 local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
8521 opt_diff = local_opt_diff;
8522 assert (opt_diff >= 0);
8523 assert (max_diff >= opt_diff);
8524 if (max_diff == 0)
8525 return 0;
8526
8527 if (fragP)
8528 fragP = fragP->fr_next;
8529
8530 while (fragP && opt_diff < max_diff && address)
8531 {
8532 /* We only use these to determine if we can exit early
8533 because there will be plenty of ways to align future
8534 align frags. */
8535 int glob_widens = 0;
8536 int dnn = 0;
8537 int dw = 0;
8538 bfd_boolean glob_pad = 0;
8539 address = find_address_of_next_align_frag
8540 (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
8541 /* If there is a padable portion, then skip. */
8542 if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg)))
8543 break;
8544
8545 if (address)
8546 {
8547 offsetT next_m_diff;
8548 offsetT next_o_diff;
8549
8550 /* Downrange frags haven't had stretch added to them yet. */
8551 address += stretch;
8552
8553 /* The address also includes any text expansion from this
8554 frag in a previous pass, but we don't want that. */
8555 address -= this_frag->tc_frag_data.text_expansion[0];
8556
8557 /* Assume we are going to move at least opt_diff. In
8558 reality, we might not be able to, but assuming that
8559 we will helps catch cases where moving opt_diff pushes
8560 the next target from aligned to unaligned. */
8561 address += opt_diff;
8562
8563 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
8564
8565 /* Now cleanup for the adjustments to address. */
8566 next_o_diff += opt_diff;
8567 next_m_diff += opt_diff;
8568 if (next_o_diff <= max_diff && next_o_diff > opt_diff)
8569 opt_diff = next_o_diff;
8570 if (next_m_diff < max_diff)
8571 max_diff = next_m_diff;
8572 fragP = fragP->fr_next;
8573 }
8574 }
8575
8576 /* If there are enough wideners in between, do it. */
8577 if (paddable)
8578 {
8579 if (this_frag->fr_subtype == RELAX_UNREACHABLE)
8580 {
8581 assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
8582 return opt_diff;
8583 }
8584 return 0;
8585 }
8586 local_stretch_amount
8587 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8588 num_widens, local_opt_diff);
8589 global_stretch_amount
8590 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8591 num_widens, opt_diff);
8592 /* If the condition below is true, then the frag couldn't
8593 stretch the correct amount for the global case, so we just
8594 optimize locally. We'll rely on the subsequent frags to get
8595 the correct alignment in the global case. */
8596 if (global_stretch_amount < local_stretch_amount)
8597 stretch_amount = local_stretch_amount;
8598 else
8599 stretch_amount = global_stretch_amount;
8600
8601 if (this_frag->fr_subtype == RELAX_SLOTS
8602 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8603 assert (stretch_amount <= 1);
8604 else if (this_frag->fr_subtype == RELAX_FILL_NOP)
8605 {
8606 if (this_frag->tc_frag_data.is_no_density)
8607 assert (stretch_amount == 3 || stretch_amount == 0);
8608 else
8609 assert (stretch_amount <= 3);
8610 }
8611 }
8612 return stretch_amount;
8613 }
8614
8615
8616 /* The idea: widen everything you can to get a target or loop aligned,
8617 then start using NOPs.
8618
8619 When we must have a NOP, here is a table of how we decide
8620 (so you don't have to fight through the control flow below):
8621
8622 wide_nops = the number of wide NOPs available for aligning
8623 narrow_nops = the number of narrow NOPs available for aligning
8624 (a subset of wide_nops)
8625 widens = the number of narrow instructions that should be widened
8626
8627 Desired wide narrow
8628 Diff nop nop widens
8629 1 0 0 1
8630 2 0 1 0
8631 3a 1 0 0
8632 b 0 1 1 (case 3a makes this case unnecessary)
8633 4a 1 0 1
8634 b 0 2 0
8635 c 0 1 2 (case 4a makes this case unnecessary)
8636 5a 1 0 2
8637 b 1 1 0
8638 c 0 2 1 (case 5b makes this case unnecessary)
8639 6a 2 0 0
8640 b 1 0 3
8641 c 0 1 4 (case 6b makes this case unneccesary)
8642 d 1 1 1 (case 6a makes this case unnecessary)
8643 e 0 2 2 (case 6a makes this case unnecessary)
8644 f 0 3 0 (case 6a makes this case unnecessary)
8645 7a 1 0 4
8646 b 2 0 1
8647 c 1 1 2 (case 7b makes this case unnecessary)
8648 d 0 1 5 (case 7a makes this case unnecessary)
8649 e 0 2 3 (case 7b makes this case unnecessary)
8650 f 0 3 1 (case 7b makes this case unnecessary)
8651 g 1 2 1 (case 7b makes this case unnecessary)
8652 */
8653
8654 static long
bytes_to_stretch(fragS * this_frag,int wide_nops,int narrow_nops,int num_widens,int desired_diff)8655 bytes_to_stretch (fragS *this_frag,
8656 int wide_nops,
8657 int narrow_nops,
8658 int num_widens,
8659 int desired_diff)
8660 {
8661 int bytes_short = desired_diff - num_widens;
8662
8663 assert (desired_diff >= 0 && desired_diff < 8);
8664 if (desired_diff == 0)
8665 return 0;
8666
8667 assert (wide_nops > 0 || num_widens > 0);
8668
8669 /* Always prefer widening to NOP-filling. */
8670 if (bytes_short < 0)
8671 {
8672 /* There are enough RELAX_NARROW frags after this one
8673 to align the target without widening this frag in any way. */
8674 return 0;
8675 }
8676
8677 if (bytes_short == 0)
8678 {
8679 /* Widen every narrow between here and the align target
8680 and the align target will be properly aligned. */
8681 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8682 return 0;
8683 else
8684 return 1;
8685 }
8686
8687 /* From here we will need at least one NOP to get an alignment.
8688 However, we may not be able to align at all, in which case,
8689 don't widen. */
8690 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8691 {
8692 switch (desired_diff)
8693 {
8694 case 1:
8695 return 0;
8696 case 2:
8697 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
8698 return 2; /* case 2 */
8699 return 0;
8700 case 3:
8701 if (wide_nops > 1)
8702 return 0;
8703 else
8704 return 3; /* case 3a */
8705 case 4:
8706 if (num_widens >= 1 && wide_nops == 1)
8707 return 3; /* case 4a */
8708 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
8709 return 2; /* case 4b */
8710 return 0;
8711 case 5:
8712 if (num_widens >= 2 && wide_nops == 1)
8713 return 3; /* case 5a */
8714 /* We will need two nops. Are there enough nops
8715 between here and the align target? */
8716 if (wide_nops < 2 || narrow_nops == 0)
8717 return 0;
8718 /* Are there other nops closer that can serve instead? */
8719 if (wide_nops > 2 && narrow_nops > 1)
8720 return 0;
8721 /* Take the density one first, because there might not be
8722 another density one available. */
8723 if (!this_frag->tc_frag_data.is_no_density)
8724 return 2; /* case 5b narrow */
8725 else
8726 return 3; /* case 5b wide */
8727 return 0;
8728 case 6:
8729 if (wide_nops == 2)
8730 return 3; /* case 6a */
8731 else if (num_widens >= 3 && wide_nops == 1)
8732 return 3; /* case 6b */
8733 return 0;
8734 case 7:
8735 if (wide_nops == 1 && num_widens >= 4)
8736 return 3; /* case 7a */
8737 else if (wide_nops == 2 && num_widens >= 1)
8738 return 3; /* case 7b */
8739 return 0;
8740 default:
8741 assert (0);
8742 }
8743 }
8744 else
8745 {
8746 /* We will need a NOP no matter what, but should we widen
8747 this instruction to help?
8748
8749 This is a RELAX_FRAG_NARROW frag. */
8750 switch (desired_diff)
8751 {
8752 case 1:
8753 assert (0);
8754 return 0;
8755 case 2:
8756 case 3:
8757 return 0;
8758 case 4:
8759 if (wide_nops >= 1 && num_widens == 1)
8760 return 1; /* case 4a */
8761 return 0;
8762 case 5:
8763 if (wide_nops >= 1 && num_widens == 2)
8764 return 1; /* case 5a */
8765 return 0;
8766 case 6:
8767 if (wide_nops >= 2)
8768 return 0; /* case 6a */
8769 else if (wide_nops >= 1 && num_widens == 3)
8770 return 1; /* case 6b */
8771 return 0;
8772 case 7:
8773 if (wide_nops >= 1 && num_widens == 4)
8774 return 1; /* case 7a */
8775 else if (wide_nops >= 2 && num_widens == 1)
8776 return 1; /* case 7b */
8777 return 0;
8778 default:
8779 assert (0);
8780 return 0;
8781 }
8782 }
8783 assert (0);
8784 return 0;
8785 }
8786
8787
8788 static long
relax_frag_immed(segT segP,fragS * fragP,long stretch,int min_steps,xtensa_format fmt,int slot,int * stretched_p,bfd_boolean estimate_only)8789 relax_frag_immed (segT segP,
8790 fragS *fragP,
8791 long stretch,
8792 int min_steps,
8793 xtensa_format fmt,
8794 int slot,
8795 int *stretched_p,
8796 bfd_boolean estimate_only)
8797 {
8798 TInsn tinsn;
8799 vliw_insn orig_vinsn;
8800 int old_size;
8801 bfd_boolean negatable_branch = FALSE;
8802 bfd_boolean branch_jmp_to_next = FALSE;
8803 bfd_boolean wide_insn = FALSE;
8804 xtensa_isa isa = xtensa_default_isa;
8805 IStack istack;
8806 offsetT frag_offset;
8807 int num_steps;
8808 fragS *lit_fragP;
8809 int num_text_bytes, num_literal_bytes;
8810 int literal_diff, total_text_diff, this_text_diff, first;
8811
8812 assert (fragP->fr_opcode != NULL);
8813
8814 xg_init_vinsn (&orig_vinsn);
8815 vinsn_from_chars (&orig_vinsn, fragP->fr_opcode);
8816 if (xtensa_format_num_slots (isa, fmt) > 1)
8817 wide_insn = TRUE;
8818
8819 tinsn = orig_vinsn.slots[slot];
8820 tinsn_immed_from_frag (&tinsn, fragP, slot);
8821
8822 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode))
8823 return 0;
8824
8825 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
8826 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
8827
8828 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
8829
8830 old_size = xtensa_format_length (isa, fmt);
8831
8832 /* Special case: replace a branch to the next instruction with a NOP.
8833 This is required to work around a hardware bug in T1040.0 and also
8834 serves as an optimization. */
8835
8836 if (branch_jmp_to_next
8837 && ((old_size == 2) || (old_size == 3))
8838 && !next_frag_is_loop_target (fragP))
8839 return 0;
8840
8841 /* Here is the fun stuff: Get the immediate field from this
8842 instruction. If it fits, we are done. If not, find the next
8843 instruction sequence that fits. */
8844
8845 frag_offset = fragP->fr_opcode - fragP->fr_literal;
8846 istack_init (&istack);
8847 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
8848 min_steps, stretch);
8849 if (num_steps < min_steps)
8850 {
8851 as_fatal (_("internal error: relaxation failed"));
8852 return 0;
8853 }
8854
8855 if (num_steps > RELAX_IMMED_MAXSTEPS)
8856 {
8857 as_fatal (_("internal error: relaxation requires too many steps"));
8858 return 0;
8859 }
8860
8861 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
8862
8863 /* Figure out the number of bytes needed. */
8864 lit_fragP = 0;
8865 num_literal_bytes = get_num_stack_literal_bytes (&istack);
8866 literal_diff =
8867 num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
8868 first = 0;
8869 while (istack.insn[first].opcode == XTENSA_UNDEFINED)
8870 first++;
8871 num_text_bytes = get_num_stack_text_bytes (&istack);
8872 if (wide_insn)
8873 {
8874 num_text_bytes += old_size;
8875 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
8876 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
8877 }
8878 total_text_diff = num_text_bytes - old_size;
8879 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
8880
8881 /* It MUST get larger. If not, we could get an infinite loop. */
8882 assert (num_text_bytes >= 0);
8883 assert (literal_diff >= 0);
8884 assert (total_text_diff >= 0);
8885
8886 fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
8887 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
8888 assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
8889 assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
8890
8891 /* Find the associated expandable literal for this. */
8892 if (literal_diff != 0)
8893 {
8894 lit_fragP = fragP->tc_frag_data.literal_frags[slot];
8895 if (lit_fragP)
8896 {
8897 assert (literal_diff == 4);
8898 lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
8899
8900 /* We expect that the literal section state has NOT been
8901 modified yet. */
8902 assert (lit_fragP->fr_type == rs_machine_dependent
8903 && lit_fragP->fr_subtype == RELAX_LITERAL);
8904 lit_fragP->fr_subtype = RELAX_LITERAL_NR;
8905
8906 /* We need to mark this section for another iteration
8907 of relaxation. */
8908 (*stretched_p)++;
8909 }
8910 }
8911
8912 if (negatable_branch && istack.ninsn > 1)
8913 update_next_frag_state (fragP);
8914
8915 return this_text_diff;
8916 }
8917
8918
8919 /* md_convert_frag Hook and Helper Functions. */
8920
8921 static void convert_frag_align_next_opcode (fragS *);
8922 static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
8923 static void convert_frag_fill_nop (fragS *);
8924 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
8925
8926 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,segT sec,fragS * fragp)8927 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
8928 {
8929 static xtensa_insnbuf vbuf = NULL;
8930 xtensa_isa isa = xtensa_default_isa;
8931 int slot;
8932 int num_slots;
8933 xtensa_format fmt;
8934 char *file_name;
8935 unsigned line;
8936
8937 as_where (&file_name, &line);
8938 new_logical_line (fragp->fr_file, fragp->fr_line);
8939
8940 switch (fragp->fr_subtype)
8941 {
8942 case RELAX_ALIGN_NEXT_OPCODE:
8943 /* Always convert. */
8944 convert_frag_align_next_opcode (fragp);
8945 break;
8946
8947 case RELAX_DESIRE_ALIGN:
8948 /* Do nothing. If not aligned already, too bad. */
8949 break;
8950
8951 case RELAX_LITERAL:
8952 case RELAX_LITERAL_FINAL:
8953 break;
8954
8955 case RELAX_SLOTS:
8956 if (vbuf == NULL)
8957 vbuf = xtensa_insnbuf_alloc (isa);
8958
8959 xtensa_insnbuf_from_chars
8960 (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0);
8961 fmt = xtensa_format_decode (isa, vbuf);
8962 num_slots = xtensa_format_num_slots (isa, fmt);
8963
8964 for (slot = 0; slot < num_slots; slot++)
8965 {
8966 switch (fragp->tc_frag_data.slot_subtypes[slot])
8967 {
8968 case RELAX_NARROW:
8969 convert_frag_narrow (sec, fragp, fmt, slot);
8970 break;
8971
8972 case RELAX_IMMED:
8973 case RELAX_IMMED_STEP1:
8974 case RELAX_IMMED_STEP2:
8975 /* Place the immediate. */
8976 convert_frag_immed
8977 (sec, fragp,
8978 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
8979 fmt, slot);
8980 break;
8981
8982 default:
8983 /* This is OK because some slots could have
8984 relaxations and others have none. */
8985 break;
8986 }
8987 }
8988 break;
8989
8990 case RELAX_UNREACHABLE:
8991 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
8992 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
8993 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
8994 frag_wane (fragp);
8995 break;
8996
8997 case RELAX_MAYBE_UNREACHABLE:
8998 case RELAX_MAYBE_DESIRE_ALIGN:
8999 frag_wane (fragp);
9000 break;
9001
9002 case RELAX_FILL_NOP:
9003 convert_frag_fill_nop (fragp);
9004 break;
9005
9006 case RELAX_LITERAL_NR:
9007 if (use_literal_section)
9008 {
9009 /* This should have been handled during relaxation. When
9010 relaxing a code segment, literals sometimes need to be
9011 added to the corresponding literal segment. If that
9012 literal segment has already been relaxed, then we end up
9013 in this situation. Marking the literal segments as data
9014 would make this happen less often (since GAS always relaxes
9015 code before data), but we could still get into trouble if
9016 there are instructions in a segment that is not marked as
9017 containing code. Until we can implement a better solution,
9018 cheat and adjust the addresses of all the following frags.
9019 This could break subsequent alignments, but the linker's
9020 literal coalescing will do that anyway. */
9021
9022 fragS *f;
9023 fragp->fr_subtype = RELAX_LITERAL_FINAL;
9024 assert (fragp->tc_frag_data.unreported_expansion == 4);
9025 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
9026 fragp->fr_var -= 4;
9027 fragp->fr_fix += 4;
9028 for (f = fragp->fr_next; f; f = f->fr_next)
9029 f->fr_address += 4;
9030 }
9031 else
9032 as_bad (_("invalid relaxation fragment result"));
9033 break;
9034 }
9035
9036 fragp->fr_var = 0;
9037 new_logical_line (file_name, line);
9038 }
9039
9040
9041 static void
convert_frag_align_next_opcode(fragS * fragp)9042 convert_frag_align_next_opcode (fragS *fragp)
9043 {
9044 char *nop_buf; /* Location for Writing. */
9045 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
9046 addressT aligned_address;
9047 offsetT fill_size;
9048 int nop, nop_count;
9049
9050 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
9051 fragp->fr_fix);
9052 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
9053 nop_count = get_text_align_nop_count (fill_size, use_no_density);
9054 nop_buf = fragp->fr_literal + fragp->fr_fix;
9055
9056 for (nop = 0; nop < nop_count; nop++)
9057 {
9058 int nop_size;
9059 nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density);
9060
9061 assemble_nop (nop_size, nop_buf);
9062 nop_buf += nop_size;
9063 }
9064
9065 fragp->fr_fix += fill_size;
9066 fragp->fr_var -= fill_size;
9067 }
9068
9069
9070 static void
convert_frag_narrow(segT segP,fragS * fragP,xtensa_format fmt,int slot)9071 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
9072 {
9073 TInsn tinsn, single_target;
9074 xtensa_format single_fmt;
9075 int size, old_size, diff;
9076 offsetT frag_offset;
9077
9078 assert (slot == 0);
9079 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
9080
9081 if (xtensa_opcode_is_branch (xtensa_default_isa, tinsn.opcode) == 1)
9082 {
9083 assert (fragP->tc_frag_data.text_expansion[0] == 1
9084 || fragP->tc_frag_data.text_expansion[0] == 0);
9085 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
9086 fmt, slot);
9087 return;
9088 }
9089
9090 if (fragP->tc_frag_data.text_expansion[0] == 0)
9091 {
9092 /* No conversion. */
9093 fragP->fr_var = 0;
9094 return;
9095 }
9096
9097 assert (fragP->fr_opcode != NULL);
9098
9099 /* Frags in this relaxation state should only contain
9100 single instruction bundles. */
9101 tinsn_immed_from_frag (&tinsn, fragP, 0);
9102
9103 /* Just convert it to a wide form.... */
9104 size = 0;
9105 old_size = xg_get_single_size (tinsn.opcode);
9106
9107 tinsn_init (&single_target);
9108 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9109
9110 if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
9111 {
9112 as_bad (_("unable to widen instruction"));
9113 return;
9114 }
9115
9116 size = xg_get_single_size (single_target.opcode);
9117 single_fmt = xg_get_single_format (single_target.opcode);
9118
9119 xg_emit_insn_to_buf (&single_target, single_fmt, fragP->fr_opcode,
9120 fragP, frag_offset, TRUE);
9121
9122 diff = size - old_size;
9123 assert (diff >= 0);
9124 assert (diff <= fragP->fr_var);
9125 fragP->fr_var -= diff;
9126 fragP->fr_fix += diff;
9127
9128 /* clean it up */
9129 fragP->fr_var = 0;
9130 }
9131
9132
9133 static void
convert_frag_fill_nop(fragS * fragP)9134 convert_frag_fill_nop (fragS *fragP)
9135 {
9136 char *loc = &fragP->fr_literal[fragP->fr_fix];
9137 int size = fragP->tc_frag_data.text_expansion[0];
9138 assert ((unsigned) size == (fragP->fr_next->fr_address
9139 - fragP->fr_address - fragP->fr_fix));
9140 if (size == 0)
9141 {
9142 /* No conversion. */
9143 fragP->fr_var = 0;
9144 return;
9145 }
9146 assemble_nop (size, loc);
9147 fragP->tc_frag_data.is_insn = TRUE;
9148 fragP->fr_var -= size;
9149 fragP->fr_fix += size;
9150 frag_wane (fragP);
9151 }
9152
9153
9154 static fixS *fix_new_exp_in_seg
9155 (segT, subsegT, fragS *, int, int, expressionS *, int,
9156 bfd_reloc_code_real_type);
9157 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
9158
9159 static void
convert_frag_immed(segT segP,fragS * fragP,int min_steps,xtensa_format fmt,int slot)9160 convert_frag_immed (segT segP,
9161 fragS *fragP,
9162 int min_steps,
9163 xtensa_format fmt,
9164 int slot)
9165 {
9166 char *immed_instr = fragP->fr_opcode;
9167 TInsn orig_tinsn;
9168 bfd_boolean expanded = FALSE;
9169 bfd_boolean branch_jmp_to_next = FALSE;
9170 char *fr_opcode = fragP->fr_opcode;
9171 vliw_insn orig_vinsn;
9172 xtensa_isa isa = xtensa_default_isa;
9173 bfd_boolean wide_insn = FALSE;
9174 int bytes;
9175 bfd_boolean is_loop;
9176
9177 assert (fr_opcode != NULL);
9178
9179 xg_init_vinsn (&orig_vinsn);
9180
9181 vinsn_from_chars (&orig_vinsn, fr_opcode);
9182 if (xtensa_format_num_slots (isa, fmt) > 1)
9183 wide_insn = TRUE;
9184
9185 orig_tinsn = orig_vinsn.slots[slot];
9186 tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
9187
9188 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
9189
9190 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
9191 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
9192
9193 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
9194 {
9195 /* Conversion just inserts a NOP and marks the fix as completed. */
9196 bytes = xtensa_format_length (isa, fmt);
9197 if (bytes >= 4)
9198 {
9199 orig_vinsn.slots[slot].opcode =
9200 xtensa_format_slot_nop_opcode (isa, orig_vinsn.format, slot);
9201 orig_vinsn.slots[slot].ntok = 0;
9202 }
9203 else
9204 {
9205 bytes += fragP->tc_frag_data.text_expansion[0];
9206 assert (bytes == 2 || bytes == 3);
9207 build_nop (&orig_vinsn.slots[0], bytes);
9208 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
9209 }
9210 vinsn_to_insnbuf (&orig_vinsn, fr_opcode, frag_now, FALSE);
9211 xtensa_insnbuf_to_chars
9212 (isa, orig_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
9213 fragP->fr_var = 0;
9214 }
9215 else
9216 {
9217 /* Here is the fun stuff: Get the immediate field from this
9218 instruction. If it fits, we're done. If not, find the next
9219 instruction sequence that fits. */
9220
9221 IStack istack;
9222 int i;
9223 symbolS *lit_sym = NULL;
9224 int total_size = 0;
9225 int target_offset = 0;
9226 int old_size;
9227 int diff;
9228 symbolS *gen_label = NULL;
9229 offsetT frag_offset;
9230 bfd_boolean first = TRUE;
9231 bfd_boolean last_is_jump;
9232
9233 /* It does not fit. Find something that does and
9234 convert immediately. */
9235 frag_offset = fr_opcode - fragP->fr_literal;
9236 istack_init (&istack);
9237 xg_assembly_relax (&istack, &orig_tinsn,
9238 segP, fragP, frag_offset, min_steps, 0);
9239
9240 old_size = xtensa_format_length (isa, fmt);
9241
9242 /* Assemble this right inline. */
9243
9244 /* First, create the mapping from a label name to the REAL label. */
9245 target_offset = 0;
9246 for (i = 0; i < istack.ninsn; i++)
9247 {
9248 TInsn *tinsn = &istack.insn[i];
9249 fragS *lit_frag;
9250
9251 switch (tinsn->insn_type)
9252 {
9253 case ITYPE_LITERAL:
9254 if (lit_sym != NULL)
9255 as_bad (_("multiple literals in expansion"));
9256 /* First find the appropriate space in the literal pool. */
9257 lit_frag = fragP->tc_frag_data.literal_frags[slot];
9258 if (lit_frag == NULL)
9259 as_bad (_("no registered fragment for literal"));
9260 if (tinsn->ntok != 1)
9261 as_bad (_("number of literal tokens != 1"));
9262
9263 /* Set the literal symbol and add a fixup. */
9264 lit_sym = lit_frag->fr_symbol;
9265 break;
9266
9267 case ITYPE_LABEL:
9268 if (align_targets && !is_loop)
9269 {
9270 fragS *unreach = fragP->fr_next;
9271 while (!(unreach->fr_type == rs_machine_dependent
9272 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9273 || unreach->fr_subtype == RELAX_UNREACHABLE)))
9274 {
9275 unreach = unreach->fr_next;
9276 }
9277
9278 assert (unreach->fr_type == rs_machine_dependent
9279 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9280 || unreach->fr_subtype == RELAX_UNREACHABLE));
9281
9282 target_offset += unreach->tc_frag_data.text_expansion[0];
9283 }
9284 assert (gen_label == NULL);
9285 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
9286 fr_opcode - fragP->fr_literal
9287 + target_offset, fragP);
9288 break;
9289
9290 case ITYPE_INSN:
9291 if (first && wide_insn)
9292 {
9293 target_offset += xtensa_format_length (isa, fmt);
9294 first = FALSE;
9295 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9296 target_offset += xg_get_single_size (tinsn->opcode);
9297 }
9298 else
9299 target_offset += xg_get_single_size (tinsn->opcode);
9300 break;
9301 }
9302 }
9303
9304 total_size = 0;
9305 first = TRUE;
9306 last_is_jump = FALSE;
9307 for (i = 0; i < istack.ninsn; i++)
9308 {
9309 TInsn *tinsn = &istack.insn[i];
9310 fragS *lit_frag;
9311 int size;
9312 segT target_seg;
9313 bfd_reloc_code_real_type reloc_type;
9314
9315 switch (tinsn->insn_type)
9316 {
9317 case ITYPE_LITERAL:
9318 lit_frag = fragP->tc_frag_data.literal_frags[slot];
9319 /* Already checked. */
9320 assert (lit_frag != NULL);
9321 assert (lit_sym != NULL);
9322 assert (tinsn->ntok == 1);
9323 /* Add a fixup. */
9324 target_seg = S_GET_SEGMENT (lit_sym);
9325 assert (target_seg);
9326 if (tinsn->tok[0].X_op == O_pltrel)
9327 reloc_type = BFD_RELOC_XTENSA_PLT;
9328 else
9329 reloc_type = BFD_RELOC_32;
9330 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
9331 &tinsn->tok[0], FALSE, reloc_type);
9332 break;
9333
9334 case ITYPE_LABEL:
9335 break;
9336
9337 case ITYPE_INSN:
9338 xg_resolve_labels (tinsn, gen_label);
9339 xg_resolve_literals (tinsn, lit_sym);
9340 if (wide_insn && first)
9341 {
9342 first = FALSE;
9343 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9344 {
9345 tinsn->record_fix = TRUE;
9346 orig_vinsn.slots[slot] = *tinsn;
9347 }
9348 else
9349 {
9350 orig_vinsn.slots[slot].opcode =
9351 xtensa_format_slot_nop_opcode (isa, fmt, slot);
9352 orig_vinsn.slots[slot].ntok = 0;
9353 orig_vinsn.slots[slot].record_fix = FALSE;
9354 }
9355 vinsn_to_insnbuf (&orig_vinsn, immed_instr, fragP, TRUE);
9356 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf,
9357 (unsigned char *) immed_instr, 0);
9358 fragP->tc_frag_data.is_insn = TRUE;
9359 size = xtensa_format_length (isa, fmt);
9360 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9361 {
9362 xtensa_format single_fmt =
9363 xg_get_single_format (tinsn->opcode);
9364
9365 xg_emit_insn_to_buf
9366 (tinsn, single_fmt, immed_instr + size, fragP,
9367 immed_instr - fragP->fr_literal + size, TRUE);
9368 size += xg_get_single_size (tinsn->opcode);
9369 }
9370 }
9371 else
9372 {
9373 xtensa_format single_format;
9374 size = xg_get_single_size (tinsn->opcode);
9375 single_format = xg_get_single_format (tinsn->opcode);
9376 xg_emit_insn_to_buf (tinsn, single_format, immed_instr,
9377 fragP,
9378 immed_instr - fragP->fr_literal, TRUE);
9379 }
9380 immed_instr += size;
9381 total_size += size;
9382 break;
9383 }
9384 }
9385
9386 diff = total_size - old_size;
9387 assert (diff >= 0);
9388 if (diff != 0)
9389 expanded = TRUE;
9390 assert (diff <= fragP->fr_var);
9391 fragP->fr_var -= diff;
9392 fragP->fr_fix += diff;
9393 }
9394
9395 /* Clean it up. */
9396 xg_free_vinsn (&orig_vinsn);
9397
9398 /* Check for undefined immediates in LOOP instructions. */
9399 if (is_loop)
9400 {
9401 symbolS *sym;
9402 sym = orig_tinsn.tok[1].X_add_symbol;
9403 if (sym != NULL && !S_IS_DEFINED (sym))
9404 {
9405 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9406 return;
9407 }
9408 sym = orig_tinsn.tok[1].X_op_symbol;
9409 if (sym != NULL && !S_IS_DEFINED (sym))
9410 {
9411 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9412 return;
9413 }
9414 }
9415
9416 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
9417 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
9418
9419 if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
9420 {
9421 /* Add an expansion note on the expanded instruction. */
9422 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
9423 &orig_tinsn.tok[0], TRUE,
9424 BFD_RELOC_XTENSA_ASM_EXPAND);
9425 }
9426 }
9427
9428
9429 /* Add a new fix expression into the desired segment. We have to
9430 switch to that segment to do this. */
9431
9432 static fixS *
fix_new_exp_in_seg(segT new_seg,subsegT new_subseg,fragS * frag,int where,int size,expressionS * exp,int pcrel,bfd_reloc_code_real_type r_type)9433 fix_new_exp_in_seg (segT new_seg,
9434 subsegT new_subseg,
9435 fragS *frag,
9436 int where,
9437 int size,
9438 expressionS *exp,
9439 int pcrel,
9440 bfd_reloc_code_real_type r_type)
9441 {
9442 fixS *new_fix;
9443 segT seg = now_seg;
9444 subsegT subseg = now_subseg;
9445
9446 assert (new_seg != 0);
9447 subseg_set (new_seg, new_subseg);
9448
9449 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
9450 subseg_set (seg, subseg);
9451 return new_fix;
9452 }
9453
9454
9455 /* Relax a loop instruction so that it can span loop >256 bytes.
9456
9457 loop as, .L1
9458 .L0:
9459 rsr as, LEND
9460 wsr as, LBEG
9461 addi as, as, lo8 (label-.L1)
9462 addmi as, as, mid8 (label-.L1)
9463 wsr as, LEND
9464 isync
9465 rsr as, LCOUNT
9466 addi as, as, 1
9467 .L1:
9468 <<body>>
9469 label:
9470 */
9471
9472 static void
convert_frag_immed_finish_loop(segT segP,fragS * fragP,TInsn * tinsn)9473 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
9474 {
9475 TInsn loop_insn;
9476 TInsn addi_insn;
9477 TInsn addmi_insn;
9478 unsigned long target;
9479 static xtensa_insnbuf insnbuf = NULL;
9480 unsigned int loop_length, loop_length_hi, loop_length_lo;
9481 xtensa_isa isa = xtensa_default_isa;
9482 addressT loop_offset;
9483 addressT addi_offset = 9;
9484 addressT addmi_offset = 12;
9485 fragS *next_fragP;
9486 int target_count;
9487
9488 if (!insnbuf)
9489 insnbuf = xtensa_insnbuf_alloc (isa);
9490
9491 /* Get the loop offset. */
9492 loop_offset = get_expanded_loop_offset (tinsn->opcode);
9493
9494 /* Validate that there really is a LOOP at the loop_offset. Because
9495 loops are not bundleable, we can assume that the instruction will be
9496 in slot 0. */
9497 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
9498 tinsn_immed_from_frag (&loop_insn, fragP, 0);
9499
9500 assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
9501 addi_offset += loop_offset;
9502 addmi_offset += loop_offset;
9503
9504 assert (tinsn->ntok == 2);
9505 if (tinsn->tok[1].X_op == O_constant)
9506 target = tinsn->tok[1].X_add_number;
9507 else if (tinsn->tok[1].X_op == O_symbol)
9508 {
9509 /* Find the fragment. */
9510 symbolS *sym = tinsn->tok[1].X_add_symbol;
9511 assert (S_GET_SEGMENT (sym) == segP
9512 || S_GET_SEGMENT (sym) == absolute_section);
9513 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
9514 }
9515 else
9516 {
9517 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
9518 target = 0;
9519 }
9520
9521 know (symbolP);
9522 know (symbolP->sy_frag);
9523 know (!(S_GET_SEGMENT (symbolP) == absolute_section)
9524 || symbol_get_frag (symbolP) == &zero_address_frag);
9525
9526 loop_length = target - (fragP->fr_address + fragP->fr_fix);
9527 loop_length_hi = loop_length & ~0x0ff;
9528 loop_length_lo = loop_length & 0x0ff;
9529 if (loop_length_lo >= 128)
9530 {
9531 loop_length_lo -= 256;
9532 loop_length_hi += 256;
9533 }
9534
9535 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9536 32512. If the loop is larger than that, then we just fail. */
9537 if (loop_length_hi > 32512)
9538 as_bad_where (fragP->fr_file, fragP->fr_line,
9539 _("loop too long for LOOP instruction"));
9540
9541 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
9542 assert (addi_insn.opcode == xtensa_addi_opcode);
9543
9544 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
9545 assert (addmi_insn.opcode == xtensa_addmi_opcode);
9546
9547 set_expr_const (&addi_insn.tok[2], loop_length_lo);
9548 tinsn_to_insnbuf (&addi_insn, insnbuf);
9549
9550 fragP->tc_frag_data.is_insn = TRUE;
9551 xtensa_insnbuf_to_chars
9552 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0);
9553
9554 set_expr_const (&addmi_insn.tok[2], loop_length_hi);
9555 tinsn_to_insnbuf (&addmi_insn, insnbuf);
9556 xtensa_insnbuf_to_chars
9557 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0);
9558
9559 /* Walk through all of the frags from here to the loop end
9560 and mark them as no_transform to keep them from being modified
9561 by the linker. If we ever have a relocation for the
9562 addi/addmi of the difference of two symbols we can remove this. */
9563
9564 target_count = 0;
9565 for (next_fragP = fragP; next_fragP != NULL;
9566 next_fragP = next_fragP->fr_next)
9567 {
9568 next_fragP->tc_frag_data.is_no_transform = TRUE;
9569 if (next_fragP->tc_frag_data.is_loop_target)
9570 target_count++;
9571 if (target_count == 2)
9572 break;
9573 }
9574 }
9575
9576
9577 /* A map that keeps information on a per-subsegment basis. This is
9578 maintained during initial assembly, but is invalid once the
9579 subsegments are smashed together. I.E., it cannot be used during
9580 the relaxation. */
9581
9582 typedef struct subseg_map_struct
9583 {
9584 /* the key */
9585 segT seg;
9586 subsegT subseg;
9587
9588 /* the data */
9589 unsigned flags;
9590 float total_freq; /* fall-through + branch target frequency */
9591 float target_freq; /* branch target frequency alone */
9592
9593 struct subseg_map_struct *next;
9594 } subseg_map;
9595
9596
9597 static subseg_map *sseg_map = NULL;
9598
9599 static subseg_map *
get_subseg_info(segT seg,subsegT subseg)9600 get_subseg_info (segT seg, subsegT subseg)
9601 {
9602 subseg_map *subseg_e;
9603
9604 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
9605 {
9606 if (seg == subseg_e->seg && subseg == subseg_e->subseg)
9607 break;
9608 }
9609 return subseg_e;
9610 }
9611
9612
9613 static subseg_map *
add_subseg_info(segT seg,subsegT subseg)9614 add_subseg_info (segT seg, subsegT subseg)
9615 {
9616 subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
9617 memset (subseg_e, 0, sizeof (subseg_map));
9618 subseg_e->seg = seg;
9619 subseg_e->subseg = subseg;
9620 subseg_e->flags = 0;
9621 /* Start off considering every branch target very important. */
9622 subseg_e->target_freq = 1.0;
9623 subseg_e->total_freq = 1.0;
9624 subseg_e->next = sseg_map;
9625 sseg_map = subseg_e;
9626 return subseg_e;
9627 }
9628
9629
9630 static unsigned
get_last_insn_flags(segT seg,subsegT subseg)9631 get_last_insn_flags (segT seg, subsegT subseg)
9632 {
9633 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9634 if (subseg_e)
9635 return subseg_e->flags;
9636 return 0;
9637 }
9638
9639
9640 static void
set_last_insn_flags(segT seg,subsegT subseg,unsigned fl,bfd_boolean val)9641 set_last_insn_flags (segT seg,
9642 subsegT subseg,
9643 unsigned fl,
9644 bfd_boolean val)
9645 {
9646 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9647 if (! subseg_e)
9648 subseg_e = add_subseg_info (seg, subseg);
9649 if (val)
9650 subseg_e->flags |= fl;
9651 else
9652 subseg_e->flags &= ~fl;
9653 }
9654
9655
9656 static float
get_subseg_total_freq(segT seg,subsegT subseg)9657 get_subseg_total_freq (segT seg, subsegT subseg)
9658 {
9659 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9660 if (subseg_e)
9661 return subseg_e->total_freq;
9662 return 1.0;
9663 }
9664
9665
9666 static float
get_subseg_target_freq(segT seg,subsegT subseg)9667 get_subseg_target_freq (segT seg, subsegT subseg)
9668 {
9669 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9670 if (subseg_e)
9671 return subseg_e->target_freq;
9672 return 1.0;
9673 }
9674
9675
9676 static void
set_subseg_freq(segT seg,subsegT subseg,float total_f,float target_f)9677 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
9678 {
9679 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9680 if (! subseg_e)
9681 subseg_e = add_subseg_info (seg, subseg);
9682 subseg_e->total_freq = total_f;
9683 subseg_e->target_freq = target_f;
9684 }
9685
9686
9687 /* Segment Lists and emit_state Stuff. */
9688
9689 static void
xtensa_move_seg_list_to_beginning(seg_list * head)9690 xtensa_move_seg_list_to_beginning (seg_list *head)
9691 {
9692 head = head->next;
9693 while (head)
9694 {
9695 segT literal_section = head->seg;
9696
9697 /* Move the literal section to the front of the section list. */
9698 assert (literal_section);
9699 if (literal_section != stdoutput->sections)
9700 {
9701 bfd_section_list_remove (stdoutput, literal_section);
9702 bfd_section_list_prepend (stdoutput, literal_section);
9703 }
9704 head = head->next;
9705 }
9706 }
9707
9708
9709 static void mark_literal_frags (seg_list *);
9710
9711 static void
xtensa_move_literals(void)9712 xtensa_move_literals (void)
9713 {
9714 seg_list *segment;
9715 frchainS *frchain_from, *frchain_to;
9716 fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after;
9717 fragS **frag_splice;
9718 emit_state state;
9719 segT dest_seg;
9720 fixS *fix, *next_fix, **fix_splice;
9721 sym_list *lit;
9722
9723 mark_literal_frags (literal_head->next);
9724 mark_literal_frags (init_literal_head->next);
9725 mark_literal_frags (fini_literal_head->next);
9726
9727 if (use_literal_section)
9728 return;
9729
9730 segment = literal_head->next;
9731 while (segment)
9732 {
9733 frchain_from = seg_info (segment->seg)->frchainP;
9734 search_frag = frchain_from->frch_root;
9735 literal_pool = NULL;
9736 frchain_to = NULL;
9737 frag_splice = &(frchain_from->frch_root);
9738
9739 while (!search_frag->tc_frag_data.literal_frag)
9740 {
9741 assert (search_frag->fr_fix == 0
9742 || search_frag->fr_type == rs_align);
9743 search_frag = search_frag->fr_next;
9744 }
9745
9746 assert (search_frag->tc_frag_data.literal_frag->fr_subtype
9747 == RELAX_LITERAL_POOL_BEGIN);
9748 xtensa_switch_section_emit_state (&state, segment->seg, 0);
9749
9750 /* Make sure that all the frags in this series are closed, and
9751 that there is at least one left over of zero-size. This
9752 prevents us from making a segment with an frchain without any
9753 frags in it. */
9754 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
9755 xtensa_set_frag_assembly_state (frag_now);
9756 last_frag = frag_now;
9757 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
9758 xtensa_set_frag_assembly_state (frag_now);
9759
9760 while (search_frag != frag_now)
9761 {
9762 next_frag = search_frag->fr_next;
9763
9764 /* First, move the frag out of the literal section and
9765 to the appropriate place. */
9766 if (search_frag->tc_frag_data.literal_frag)
9767 {
9768 literal_pool = search_frag->tc_frag_data.literal_frag;
9769 assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
9770 frchain_to = literal_pool->tc_frag_data.lit_frchain;
9771 assert (frchain_to);
9772 }
9773 insert_after = literal_pool;
9774
9775 while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END)
9776 insert_after = insert_after->fr_next;
9777
9778 dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
9779
9780 *frag_splice = next_frag;
9781 search_frag->fr_next = insert_after->fr_next;
9782 insert_after->fr_next = search_frag;
9783 search_frag->tc_frag_data.lit_seg = dest_seg;
9784
9785 /* Now move any fixups associated with this frag to the
9786 right section. */
9787 fix = frchain_from->fix_root;
9788 fix_splice = &(frchain_from->fix_root);
9789 while (fix)
9790 {
9791 next_fix = fix->fx_next;
9792 if (fix->fx_frag == search_frag)
9793 {
9794 *fix_splice = next_fix;
9795 fix->fx_next = frchain_to->fix_root;
9796 frchain_to->fix_root = fix;
9797 if (frchain_to->fix_tail == NULL)
9798 frchain_to->fix_tail = fix;
9799 }
9800 else
9801 fix_splice = &(fix->fx_next);
9802 fix = next_fix;
9803 }
9804 search_frag = next_frag;
9805 }
9806
9807 if (frchain_from->fix_root != NULL)
9808 {
9809 frchain_from = seg_info (segment->seg)->frchainP;
9810 as_warn (_("fixes not all moved from %s"), segment->seg->name);
9811
9812 assert (frchain_from->fix_root == NULL);
9813 }
9814 frchain_from->fix_tail = NULL;
9815 xtensa_restore_emit_state (&state);
9816 segment = segment->next;
9817 }
9818
9819 /* Now fix up the SEGMENT value for all the literal symbols. */
9820 for (lit = literal_syms; lit; lit = lit->next)
9821 {
9822 symbolS *lit_sym = lit->sym;
9823 segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
9824 if (dest_seg)
9825 S_SET_SEGMENT (lit_sym, dest_seg);
9826 }
9827 }
9828
9829
9830 /* Walk over all the frags for segments in a list and mark them as
9831 containing literals. As clunky as this is, we can't rely on frag_var
9832 and frag_variant to get called in all situations. */
9833
9834 static void
mark_literal_frags(seg_list * segment)9835 mark_literal_frags (seg_list *segment)
9836 {
9837 frchainS *frchain_from;
9838 fragS *search_frag;
9839
9840 while (segment)
9841 {
9842 frchain_from = seg_info (segment->seg)->frchainP;
9843 search_frag = frchain_from->frch_root;
9844 while (search_frag)
9845 {
9846 search_frag->tc_frag_data.is_literal = TRUE;
9847 search_frag = search_frag->fr_next;
9848 }
9849 segment = segment->next;
9850 }
9851 }
9852
9853
9854 static void
xtensa_reorder_seg_list(seg_list * head,segT after)9855 xtensa_reorder_seg_list (seg_list *head, segT after)
9856 {
9857 /* Move all of the sections in the section list to come
9858 after "after" in the gnu segment list. */
9859
9860 head = head->next;
9861 while (head)
9862 {
9863 segT literal_section = head->seg;
9864
9865 /* Move the literal section after "after". */
9866 assert (literal_section);
9867 if (literal_section != after)
9868 {
9869 bfd_section_list_remove (stdoutput, literal_section);
9870 bfd_section_list_insert_after (stdoutput, after, literal_section);
9871 }
9872
9873 head = head->next;
9874 }
9875 }
9876
9877
9878 /* Push all the literal segments to the end of the gnu list. */
9879
9880 static void
xtensa_reorder_segments(void)9881 xtensa_reorder_segments (void)
9882 {
9883 segT sec;
9884 segT last_sec = 0;
9885 int old_count = 0;
9886 int new_count = 0;
9887
9888 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
9889 {
9890 last_sec = sec;
9891 old_count++;
9892 }
9893
9894 /* Now that we have the last section, push all the literal
9895 sections to the end. */
9896 xtensa_reorder_seg_list (literal_head, last_sec);
9897 xtensa_reorder_seg_list (init_literal_head, last_sec);
9898 xtensa_reorder_seg_list (fini_literal_head, last_sec);
9899
9900 /* Now perform the final error check. */
9901 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
9902 new_count++;
9903 assert (new_count == old_count);
9904 }
9905
9906
9907 /* Change the emit state (seg, subseg, and frag related stuff) to the
9908 correct location. Return a emit_state which can be passed to
9909 xtensa_restore_emit_state to return to current fragment. */
9910
9911 static void
xtensa_switch_to_literal_fragment(emit_state * result)9912 xtensa_switch_to_literal_fragment (emit_state *result)
9913 {
9914 if (directive_state[directive_absolute_literals])
9915 {
9916 cache_literal_section (0, default_lit_sections.lit4_seg_name,
9917 &default_lit_sections.lit4_seg, FALSE);
9918 xtensa_switch_section_emit_state (result,
9919 default_lit_sections.lit4_seg, 0);
9920 }
9921 else
9922 xtensa_switch_to_non_abs_literal_fragment (result);
9923
9924 /* Do a 4-byte align here. */
9925 frag_align (2, 0, 0);
9926 record_alignment (now_seg, 2);
9927 }
9928
9929
9930 static void
xtensa_switch_to_non_abs_literal_fragment(emit_state * result)9931 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
9932 {
9933 /* When we mark a literal pool location, we want to put a frag in
9934 the literal pool that points to it. But to do that, we want to
9935 switch_to_literal_fragment. But literal sections don't have
9936 literal pools, so their location is always null, so we would
9937 recurse forever. This is kind of hacky, but it works. */
9938
9939 static bfd_boolean recursive = FALSE;
9940 fragS *pool_location = get_literal_pool_location (now_seg);
9941 bfd_boolean is_init =
9942 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
9943
9944 bfd_boolean is_fini =
9945 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
9946
9947 if (pool_location == NULL
9948 && !use_literal_section
9949 && !recursive
9950 && !is_init && ! is_fini)
9951 {
9952 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9953 recursive = TRUE;
9954 xtensa_mark_literal_pool_location ();
9955 recursive = FALSE;
9956 }
9957
9958 /* Special case: If we are in the ".fini" or ".init" section, then
9959 we will ALWAYS be generating to the ".fini.literal" and
9960 ".init.literal" sections. */
9961
9962 if (is_init)
9963 {
9964 cache_literal_section (init_literal_head,
9965 default_lit_sections.init_lit_seg_name,
9966 &default_lit_sections.init_lit_seg, TRUE);
9967 xtensa_switch_section_emit_state (result,
9968 default_lit_sections.init_lit_seg, 0);
9969 }
9970 else if (is_fini)
9971 {
9972 cache_literal_section (fini_literal_head,
9973 default_lit_sections.fini_lit_seg_name,
9974 &default_lit_sections.fini_lit_seg, TRUE);
9975 xtensa_switch_section_emit_state (result,
9976 default_lit_sections.fini_lit_seg, 0);
9977 }
9978 else
9979 {
9980 cache_literal_section (literal_head,
9981 default_lit_sections.lit_seg_name,
9982 &default_lit_sections.lit_seg, TRUE);
9983 xtensa_switch_section_emit_state (result,
9984 default_lit_sections.lit_seg, 0);
9985 }
9986
9987 if (!use_literal_section
9988 && !is_init && !is_fini
9989 && get_literal_pool_location (now_seg) != pool_location)
9990 {
9991 /* Close whatever frag is there. */
9992 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
9993 xtensa_set_frag_assembly_state (frag_now);
9994 frag_now->tc_frag_data.literal_frag = pool_location;
9995 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
9996 xtensa_set_frag_assembly_state (frag_now);
9997 }
9998 }
9999
10000
10001 /* Call this function before emitting data into the literal section.
10002 This is a helper function for xtensa_switch_to_literal_fragment.
10003 This is similar to a .section new_now_seg subseg. */
10004
10005 static void
xtensa_switch_section_emit_state(emit_state * state,segT new_now_seg,subsegT new_now_subseg)10006 xtensa_switch_section_emit_state (emit_state *state,
10007 segT new_now_seg,
10008 subsegT new_now_subseg)
10009 {
10010 state->name = now_seg->name;
10011 state->now_seg = now_seg;
10012 state->now_subseg = now_subseg;
10013 state->generating_literals = generating_literals;
10014 generating_literals++;
10015 subseg_set (new_now_seg, new_now_subseg);
10016 }
10017
10018
10019 /* Use to restore the emitting into the normal place. */
10020
10021 static void
xtensa_restore_emit_state(emit_state * state)10022 xtensa_restore_emit_state (emit_state *state)
10023 {
10024 generating_literals = state->generating_literals;
10025 subseg_set (state->now_seg, state->now_subseg);
10026 }
10027
10028
10029 /* Get a segment of a given name. If the segment is already
10030 present, return it; otherwise, create a new one. */
10031
10032 static void
cache_literal_section(seg_list * head,const char * name,segT * pseg,bfd_boolean is_code)10033 cache_literal_section (seg_list *head,
10034 const char *name,
10035 segT *pseg,
10036 bfd_boolean is_code)
10037 {
10038 segT current_section = now_seg;
10039 int current_subsec = now_subseg;
10040 segT seg;
10041
10042 if (*pseg != 0)
10043 return;
10044
10045 /* Check if the named section exists. */
10046 for (seg = stdoutput->sections; seg; seg = seg->next)
10047 {
10048 if (!strcmp (segment_name (seg), name))
10049 break;
10050 }
10051
10052 if (!seg)
10053 {
10054 /* Create a new literal section. */
10055 seg = subseg_new (name, (subsegT) 0);
10056 if (head)
10057 {
10058 /* Add the newly created literal segment to the specified list. */
10059 seg_list *n = (seg_list *) xmalloc (sizeof (seg_list));
10060 n->seg = seg;
10061 n->next = head->next;
10062 head->next = n;
10063 }
10064 bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS |
10065 SEC_READONLY | SEC_ALLOC | SEC_LOAD
10066 | (is_code ? SEC_CODE : SEC_DATA));
10067 bfd_set_section_alignment (stdoutput, seg, 2);
10068 }
10069
10070 *pseg = seg;
10071 subseg_set (current_section, current_subsec);
10072 }
10073
10074
10075 /* Property Tables Stuff. */
10076
10077 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10078 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10079 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10080
10081 typedef bfd_boolean (*frag_predicate) (const fragS *);
10082 typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
10083
10084 static bfd_boolean get_frag_is_literal (const fragS *);
10085 static void xtensa_create_property_segments
10086 (frag_predicate, frag_predicate, const char *, xt_section_type);
10087 static void xtensa_create_xproperty_segments
10088 (frag_flags_fn, const char *, xt_section_type);
10089 static segment_info_type *retrieve_segment_info (segT);
10090 static segT retrieve_xtensa_section (char *);
10091 static bfd_boolean section_has_property (segT, frag_predicate);
10092 static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
10093 static void add_xt_block_frags
10094 (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate);
10095 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
10096 static void xtensa_frag_flags_init (frag_flags *);
10097 static void get_frag_property_flags (const fragS *, frag_flags *);
10098 static bfd_vma frag_flags_to_number (const frag_flags *);
10099 static void add_xt_prop_frags
10100 (segT, segT, xtensa_block_info **, frag_flags_fn);
10101
10102 /* Set up property tables after relaxation. */
10103
10104 void
xtensa_post_relax_hook(void)10105 xtensa_post_relax_hook (void)
10106 {
10107 xtensa_move_seg_list_to_beginning (literal_head);
10108 xtensa_move_seg_list_to_beginning (init_literal_head);
10109 xtensa_move_seg_list_to_beginning (fini_literal_head);
10110
10111 xtensa_find_unmarked_state_frags ();
10112
10113 if (use_literal_section)
10114 xtensa_create_property_segments (get_frag_is_literal,
10115 NULL,
10116 XTENSA_LIT_SEC_NAME,
10117 xt_literal_sec);
10118 xtensa_create_xproperty_segments (get_frag_property_flags,
10119 XTENSA_PROP_SEC_NAME,
10120 xt_prop_sec);
10121
10122 if (warn_unaligned_branch_targets)
10123 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
10124 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
10125 }
10126
10127
10128 /* This function is only meaningful after xtensa_move_literals. */
10129
10130 static bfd_boolean
get_frag_is_literal(const fragS * fragP)10131 get_frag_is_literal (const fragS *fragP)
10132 {
10133 assert (fragP != NULL);
10134 return fragP->tc_frag_data.is_literal;
10135 }
10136
10137
10138 static void
xtensa_create_property_segments(frag_predicate property_function,frag_predicate end_property_function,const char * section_name_base,xt_section_type sec_type)10139 xtensa_create_property_segments (frag_predicate property_function,
10140 frag_predicate end_property_function,
10141 const char *section_name_base,
10142 xt_section_type sec_type)
10143 {
10144 segT *seclist;
10145
10146 /* Walk over all of the current segments.
10147 Walk over each fragment
10148 For each non-empty fragment,
10149 Build a property record (append where possible). */
10150
10151 for (seclist = &stdoutput->sections;
10152 seclist && *seclist;
10153 seclist = &(*seclist)->next)
10154 {
10155 segT sec = *seclist;
10156 flagword flags;
10157
10158 flags = bfd_get_section_flags (stdoutput, sec);
10159 if (flags & SEC_DEBUGGING)
10160 continue;
10161 if (!(flags & SEC_ALLOC))
10162 continue;
10163
10164 if (section_has_property (sec, property_function))
10165 {
10166 char *property_section_name =
10167 xtensa_get_property_section_name (sec, section_name_base);
10168 segT insn_sec = retrieve_xtensa_section (property_section_name);
10169 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10170 xtensa_block_info **xt_blocks =
10171 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10172 /* Walk over all of the frchains here and add new sections. */
10173 add_xt_block_frags (sec, insn_sec, xt_blocks, property_function,
10174 end_property_function);
10175 }
10176 }
10177
10178 /* Now we fill them out.... */
10179
10180 for (seclist = &stdoutput->sections;
10181 seclist && *seclist;
10182 seclist = &(*seclist)->next)
10183 {
10184 segment_info_type *seginfo;
10185 xtensa_block_info *block;
10186 segT sec = *seclist;
10187
10188 seginfo = seg_info (sec);
10189 block = seginfo->tc_segment_info_data.blocks[sec_type];
10190
10191 if (block)
10192 {
10193 xtensa_block_info *cur_block;
10194 /* This is a section with some data. */
10195 int num_recs = 0;
10196 bfd_size_type rec_size;
10197
10198 for (cur_block = block; cur_block; cur_block = cur_block->next)
10199 num_recs++;
10200
10201 rec_size = num_recs * 8;
10202 bfd_set_section_size (stdoutput, sec, rec_size);
10203
10204 /* In order to make this work with the assembler, we have to
10205 build some frags and then build the "fixups" for it. It
10206 would be easier to just set the contents then set the
10207 arlents. */
10208
10209 if (num_recs)
10210 {
10211 /* Allocate a fragment and leak it. */
10212 fragS *fragP;
10213 bfd_size_type frag_size;
10214 fixS *fixes;
10215 frchainS *frchainP;
10216 int i;
10217 char *frag_data;
10218
10219 frag_size = sizeof (fragS) + rec_size;
10220 fragP = (fragS *) xmalloc (frag_size);
10221
10222 memset (fragP, 0, frag_size);
10223 fragP->fr_address = 0;
10224 fragP->fr_next = NULL;
10225 fragP->fr_fix = rec_size;
10226 fragP->fr_var = 0;
10227 fragP->fr_type = rs_fill;
10228 /* The rest are zeros. */
10229
10230 frchainP = seginfo->frchainP;
10231 frchainP->frch_root = fragP;
10232 frchainP->frch_last = fragP;
10233
10234 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10235 memset (fixes, 0, sizeof (fixS) * num_recs);
10236
10237 seginfo->fix_root = fixes;
10238 seginfo->fix_tail = &fixes[num_recs - 1];
10239 cur_block = block;
10240 frag_data = &fragP->fr_literal[0];
10241 for (i = 0; i < num_recs; i++)
10242 {
10243 fixS *fix = &fixes[i];
10244 assert (cur_block);
10245
10246 /* Write the fixup. */
10247 if (i != num_recs - 1)
10248 fix->fx_next = &fixes[i + 1];
10249 else
10250 fix->fx_next = NULL;
10251 fix->fx_size = 4;
10252 fix->fx_done = 0;
10253 fix->fx_frag = fragP;
10254 fix->fx_where = i * 8;
10255 fix->fx_addsy = section_symbol (cur_block->sec);
10256 fix->fx_offset = cur_block->offset;
10257 fix->fx_r_type = BFD_RELOC_32;
10258 fix->fx_file = "Internal Assembly";
10259 fix->fx_line = 0;
10260
10261 /* Write the length. */
10262 md_number_to_chars (&frag_data[4 + 8 * i],
10263 cur_block->size, 4);
10264 cur_block = cur_block->next;
10265 }
10266 }
10267 }
10268 }
10269 }
10270
10271
10272 static void
xtensa_create_xproperty_segments(frag_flags_fn flag_fn,const char * section_name_base,xt_section_type sec_type)10273 xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
10274 const char *section_name_base,
10275 xt_section_type sec_type)
10276 {
10277 segT *seclist;
10278
10279 /* Walk over all of the current segments.
10280 Walk over each fragment.
10281 For each fragment that has instructions,
10282 build an instruction record (append where possible). */
10283
10284 for (seclist = &stdoutput->sections;
10285 seclist && *seclist;
10286 seclist = &(*seclist)->next)
10287 {
10288 segT sec = *seclist;
10289 flagword flags;
10290
10291 flags = bfd_get_section_flags (stdoutput, sec);
10292 if ((flags & SEC_DEBUGGING)
10293 || !(flags & SEC_ALLOC)
10294 || (flags & SEC_MERGE))
10295 continue;
10296
10297 if (section_has_xproperty (sec, flag_fn))
10298 {
10299 char *property_section_name =
10300 xtensa_get_property_section_name (sec, section_name_base);
10301 segT insn_sec = retrieve_xtensa_section (property_section_name);
10302 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10303 xtensa_block_info **xt_blocks =
10304 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10305 /* Walk over all of the frchains here and add new sections. */
10306 add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn);
10307 }
10308 }
10309
10310 /* Now we fill them out.... */
10311
10312 for (seclist = &stdoutput->sections;
10313 seclist && *seclist;
10314 seclist = &(*seclist)->next)
10315 {
10316 segment_info_type *seginfo;
10317 xtensa_block_info *block;
10318 segT sec = *seclist;
10319
10320 seginfo = seg_info (sec);
10321 block = seginfo->tc_segment_info_data.blocks[sec_type];
10322
10323 if (block)
10324 {
10325 xtensa_block_info *cur_block;
10326 /* This is a section with some data. */
10327 int num_recs = 0;
10328 bfd_size_type rec_size;
10329
10330 for (cur_block = block; cur_block; cur_block = cur_block->next)
10331 num_recs++;
10332
10333 rec_size = num_recs * (8 + 4);
10334 bfd_set_section_size (stdoutput, sec, rec_size);
10335
10336 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10337
10338 /* In order to make this work with the assembler, we have to build
10339 some frags then build the "fixups" for it. It would be easier to
10340 just set the contents then set the arlents. */
10341
10342 if (num_recs)
10343 {
10344 /* Allocate a fragment and (unfortunately) leak it. */
10345 fragS *fragP;
10346 bfd_size_type frag_size;
10347 fixS *fixes;
10348 frchainS *frchainP;
10349 int i;
10350 char *frag_data;
10351
10352 frag_size = sizeof (fragS) + rec_size;
10353 fragP = (fragS *) xmalloc (frag_size);
10354
10355 memset (fragP, 0, frag_size);
10356 fragP->fr_address = 0;
10357 fragP->fr_next = NULL;
10358 fragP->fr_fix = rec_size;
10359 fragP->fr_var = 0;
10360 fragP->fr_type = rs_fill;
10361 /* The rest are zeros. */
10362
10363 frchainP = seginfo->frchainP;
10364 frchainP->frch_root = fragP;
10365 frchainP->frch_last = fragP;
10366
10367 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10368 memset (fixes, 0, sizeof (fixS) * num_recs);
10369
10370 seginfo->fix_root = fixes;
10371 seginfo->fix_tail = &fixes[num_recs - 1];
10372 cur_block = block;
10373 frag_data = &fragP->fr_literal[0];
10374 for (i = 0; i < num_recs; i++)
10375 {
10376 fixS *fix = &fixes[i];
10377 assert (cur_block);
10378
10379 /* Write the fixup. */
10380 if (i != num_recs - 1)
10381 fix->fx_next = &fixes[i + 1];
10382 else
10383 fix->fx_next = NULL;
10384 fix->fx_size = 4;
10385 fix->fx_done = 0;
10386 fix->fx_frag = fragP;
10387 fix->fx_where = i * (8 + 4);
10388 fix->fx_addsy = section_symbol (cur_block->sec);
10389 fix->fx_offset = cur_block->offset;
10390 fix->fx_r_type = BFD_RELOC_32;
10391 fix->fx_file = "Internal Assembly";
10392 fix->fx_line = 0;
10393
10394 /* Write the length. */
10395 md_number_to_chars (&frag_data[4 + (8+4) * i],
10396 cur_block->size, 4);
10397 md_number_to_chars (&frag_data[8 + (8+4) * i],
10398 frag_flags_to_number (&cur_block->flags),
10399 4);
10400 cur_block = cur_block->next;
10401 }
10402 }
10403 }
10404 }
10405 }
10406
10407
10408 static segment_info_type *
retrieve_segment_info(segT seg)10409 retrieve_segment_info (segT seg)
10410 {
10411 segment_info_type *seginfo;
10412 seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
10413 if (!seginfo)
10414 {
10415 frchainS *frchainP;
10416
10417 seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
10418 memset ((void *) seginfo, 0, sizeof (*seginfo));
10419 seginfo->fix_root = NULL;
10420 seginfo->fix_tail = NULL;
10421 seginfo->bfd_section = seg;
10422 seginfo->sym = 0;
10423 /* We will not be dealing with these, only our special ones. */
10424 bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
10425
10426 frchainP = (frchainS *) xmalloc (sizeof (frchainS));
10427 frchainP->frch_root = NULL;
10428 frchainP->frch_last = NULL;
10429 frchainP->frch_next = NULL;
10430 frchainP->frch_seg = seg;
10431 frchainP->frch_subseg = 0;
10432 frchainP->fix_root = NULL;
10433 frchainP->fix_tail = NULL;
10434 /* Do not init the objstack. */
10435 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10436 /* frchainP->frch_frag_now = fragP; */
10437 frchainP->frch_frag_now = NULL;
10438
10439 seginfo->frchainP = frchainP;
10440 }
10441
10442 return seginfo;
10443 }
10444
10445
10446 static segT
retrieve_xtensa_section(char * sec_name)10447 retrieve_xtensa_section (char *sec_name)
10448 {
10449 bfd *abfd = stdoutput;
10450 flagword flags, out_flags, link_once_flags;
10451 segT s;
10452
10453 flags = bfd_get_section_flags (abfd, now_seg);
10454 link_once_flags = (flags & SEC_LINK_ONCE);
10455 if (link_once_flags)
10456 link_once_flags |= (flags & SEC_LINK_DUPLICATES);
10457 out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags);
10458
10459 s = bfd_make_section_old_way (abfd, sec_name);
10460 if (s == NULL)
10461 as_bad (_("could not create section %s"), sec_name);
10462 if (!bfd_set_section_flags (abfd, s, out_flags))
10463 as_bad (_("invalid flag combination on section %s"), sec_name);
10464
10465 return s;
10466 }
10467
10468
10469 static bfd_boolean
section_has_property(segT sec,frag_predicate property_function)10470 section_has_property (segT sec, frag_predicate property_function)
10471 {
10472 segment_info_type *seginfo = seg_info (sec);
10473 fragS *fragP;
10474
10475 if (seginfo && seginfo->frchainP)
10476 {
10477 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10478 {
10479 if (property_function (fragP)
10480 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10481 return TRUE;
10482 }
10483 }
10484 return FALSE;
10485 }
10486
10487
10488 static bfd_boolean
section_has_xproperty(segT sec,frag_flags_fn property_function)10489 section_has_xproperty (segT sec, frag_flags_fn property_function)
10490 {
10491 segment_info_type *seginfo = seg_info (sec);
10492 fragS *fragP;
10493
10494 if (seginfo && seginfo->frchainP)
10495 {
10496 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10497 {
10498 frag_flags prop_flags;
10499 property_function (fragP, &prop_flags);
10500 if (!xtensa_frag_flags_is_empty (&prop_flags))
10501 return TRUE;
10502 }
10503 }
10504 return FALSE;
10505 }
10506
10507
10508 /* Two types of block sections exist right now: literal and insns. */
10509
10510 static void
add_xt_block_frags(segT sec,segT xt_block_sec,xtensa_block_info ** xt_block,frag_predicate property_function,frag_predicate end_property_function)10511 add_xt_block_frags (segT sec,
10512 segT xt_block_sec,
10513 xtensa_block_info **xt_block,
10514 frag_predicate property_function,
10515 frag_predicate end_property_function)
10516 {
10517 segment_info_type *seg_info;
10518 segment_info_type *xt_seg_info;
10519 bfd_vma seg_offset;
10520 fragS *fragP;
10521
10522 xt_seg_info = retrieve_segment_info (xt_block_sec);
10523 seg_info = retrieve_segment_info (sec);
10524
10525 /* Build it if needed. */
10526 while (*xt_block != NULL)
10527 xt_block = &(*xt_block)->next;
10528 /* We are either at NULL at the beginning or at the end. */
10529
10530 /* Walk through the frags. */
10531 seg_offset = 0;
10532
10533 if (seg_info->frchainP)
10534 {
10535 for (fragP = seg_info->frchainP->frch_root;
10536 fragP;
10537 fragP = fragP->fr_next)
10538 {
10539 if (property_function (fragP)
10540 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10541 {
10542 if (*xt_block != NULL)
10543 {
10544 if ((*xt_block)->offset + (*xt_block)->size
10545 == fragP->fr_address)
10546 (*xt_block)->size += fragP->fr_fix;
10547 else
10548 xt_block = &((*xt_block)->next);
10549 }
10550 if (*xt_block == NULL)
10551 {
10552 xtensa_block_info *new_block = (xtensa_block_info *)
10553 xmalloc (sizeof (xtensa_block_info));
10554 new_block->sec = sec;
10555 new_block->offset = fragP->fr_address;
10556 new_block->size = fragP->fr_fix;
10557 new_block->next = NULL;
10558 xtensa_frag_flags_init (&new_block->flags);
10559 *xt_block = new_block;
10560 }
10561 if (end_property_function
10562 && end_property_function (fragP))
10563 {
10564 xt_block = &((*xt_block)->next);
10565 }
10566 }
10567 }
10568 }
10569 }
10570
10571
10572 /* Break the encapsulation of add_xt_prop_frags here. */
10573
10574 static bfd_boolean
xtensa_frag_flags_is_empty(const frag_flags * prop_flags)10575 xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
10576 {
10577 if (prop_flags->is_literal
10578 || prop_flags->is_insn
10579 || prop_flags->is_data
10580 || prop_flags->is_unreachable)
10581 return FALSE;
10582 return TRUE;
10583 }
10584
10585
10586 static void
xtensa_frag_flags_init(frag_flags * prop_flags)10587 xtensa_frag_flags_init (frag_flags *prop_flags)
10588 {
10589 memset (prop_flags, 0, sizeof (frag_flags));
10590 }
10591
10592
10593 static void
get_frag_property_flags(const fragS * fragP,frag_flags * prop_flags)10594 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
10595 {
10596 xtensa_frag_flags_init (prop_flags);
10597 if (fragP->tc_frag_data.is_literal)
10598 prop_flags->is_literal = TRUE;
10599 if (fragP->tc_frag_data.is_unreachable)
10600 prop_flags->is_unreachable = TRUE;
10601 else if (fragP->tc_frag_data.is_insn)
10602 {
10603 prop_flags->is_insn = TRUE;
10604 if (fragP->tc_frag_data.is_loop_target)
10605 prop_flags->insn.is_loop_target = TRUE;
10606 if (fragP->tc_frag_data.is_branch_target)
10607 prop_flags->insn.is_branch_target = TRUE;
10608 if (fragP->tc_frag_data.is_specific_opcode
10609 || fragP->tc_frag_data.is_no_transform)
10610 prop_flags->insn.is_no_transform = TRUE;
10611 if (fragP->tc_frag_data.is_no_density)
10612 prop_flags->insn.is_no_density = TRUE;
10613 if (fragP->tc_frag_data.use_absolute_literals)
10614 prop_flags->insn.is_abslit = TRUE;
10615 }
10616 if (fragP->tc_frag_data.is_align)
10617 {
10618 prop_flags->is_align = TRUE;
10619 prop_flags->alignment = fragP->tc_frag_data.alignment;
10620 if (xtensa_frag_flags_is_empty (prop_flags))
10621 prop_flags->is_data = TRUE;
10622 }
10623 }
10624
10625
10626 static bfd_vma
frag_flags_to_number(const frag_flags * prop_flags)10627 frag_flags_to_number (const frag_flags *prop_flags)
10628 {
10629 bfd_vma num = 0;
10630 if (prop_flags->is_literal)
10631 num |= XTENSA_PROP_LITERAL;
10632 if (prop_flags->is_insn)
10633 num |= XTENSA_PROP_INSN;
10634 if (prop_flags->is_data)
10635 num |= XTENSA_PROP_DATA;
10636 if (prop_flags->is_unreachable)
10637 num |= XTENSA_PROP_UNREACHABLE;
10638 if (prop_flags->insn.is_loop_target)
10639 num |= XTENSA_PROP_INSN_LOOP_TARGET;
10640 if (prop_flags->insn.is_branch_target)
10641 {
10642 num |= XTENSA_PROP_INSN_BRANCH_TARGET;
10643 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
10644 }
10645
10646 if (prop_flags->insn.is_no_density)
10647 num |= XTENSA_PROP_INSN_NO_DENSITY;
10648 if (prop_flags->insn.is_no_transform)
10649 num |= XTENSA_PROP_INSN_NO_TRANSFORM;
10650 if (prop_flags->insn.is_no_reorder)
10651 num |= XTENSA_PROP_INSN_NO_REORDER;
10652 if (prop_flags->insn.is_abslit)
10653 num |= XTENSA_PROP_INSN_ABSLIT;
10654
10655 if (prop_flags->is_align)
10656 {
10657 num |= XTENSA_PROP_ALIGN;
10658 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
10659 }
10660
10661 return num;
10662 }
10663
10664
10665 static bfd_boolean
xtensa_frag_flags_combinable(const frag_flags * prop_flags_1,const frag_flags * prop_flags_2)10666 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
10667 const frag_flags *prop_flags_2)
10668 {
10669 /* Cannot combine with an end marker. */
10670
10671 if (prop_flags_1->is_literal != prop_flags_2->is_literal)
10672 return FALSE;
10673 if (prop_flags_1->is_insn != prop_flags_2->is_insn)
10674 return FALSE;
10675 if (prop_flags_1->is_data != prop_flags_2->is_data)
10676 return FALSE;
10677
10678 if (prop_flags_1->is_insn)
10679 {
10680 /* Properties of the beginning of the frag. */
10681 if (prop_flags_2->insn.is_loop_target)
10682 return FALSE;
10683 if (prop_flags_2->insn.is_branch_target)
10684 return FALSE;
10685 if (prop_flags_1->insn.is_no_density !=
10686 prop_flags_2->insn.is_no_density)
10687 return FALSE;
10688 if (prop_flags_1->insn.is_no_transform !=
10689 prop_flags_2->insn.is_no_transform)
10690 return FALSE;
10691 if (prop_flags_1->insn.is_no_reorder !=
10692 prop_flags_2->insn.is_no_reorder)
10693 return FALSE;
10694 if (prop_flags_1->insn.is_abslit !=
10695 prop_flags_2->insn.is_abslit)
10696 return FALSE;
10697 }
10698
10699 if (prop_flags_1->is_align)
10700 return FALSE;
10701
10702 return TRUE;
10703 }
10704
10705
10706 static bfd_vma
xt_block_aligned_size(const xtensa_block_info * xt_block)10707 xt_block_aligned_size (const xtensa_block_info *xt_block)
10708 {
10709 bfd_vma end_addr;
10710 unsigned align_bits;
10711
10712 if (!xt_block->flags.is_align)
10713 return xt_block->size;
10714
10715 end_addr = xt_block->offset + xt_block->size;
10716 align_bits = xt_block->flags.alignment;
10717 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
10718 return end_addr - xt_block->offset;
10719 }
10720
10721
10722 static bfd_boolean
xtensa_xt_block_combine(xtensa_block_info * xt_block,const xtensa_block_info * xt_block_2)10723 xtensa_xt_block_combine (xtensa_block_info *xt_block,
10724 const xtensa_block_info *xt_block_2)
10725 {
10726 if (xt_block->sec != xt_block_2->sec)
10727 return FALSE;
10728 if (xt_block->offset + xt_block_aligned_size (xt_block)
10729 != xt_block_2->offset)
10730 return FALSE;
10731
10732 if (xt_block_2->size == 0
10733 && (!xt_block_2->flags.is_unreachable
10734 || xt_block->flags.is_unreachable))
10735 {
10736 if (xt_block_2->flags.is_align
10737 && xt_block->flags.is_align)
10738 {
10739 /* Nothing needed. */
10740 if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
10741 return TRUE;
10742 }
10743 else
10744 {
10745 if (xt_block_2->flags.is_align)
10746 {
10747 /* Push alignment to previous entry. */
10748 xt_block->flags.is_align = xt_block_2->flags.is_align;
10749 xt_block->flags.alignment = xt_block_2->flags.alignment;
10750 }
10751 return TRUE;
10752 }
10753 }
10754 if (!xtensa_frag_flags_combinable (&xt_block->flags,
10755 &xt_block_2->flags))
10756 return FALSE;
10757
10758 xt_block->size += xt_block_2->size;
10759
10760 if (xt_block_2->flags.is_align)
10761 {
10762 xt_block->flags.is_align = TRUE;
10763 xt_block->flags.alignment = xt_block_2->flags.alignment;
10764 }
10765
10766 return TRUE;
10767 }
10768
10769
10770 static void
add_xt_prop_frags(segT sec,segT xt_block_sec,xtensa_block_info ** xt_block,frag_flags_fn property_function)10771 add_xt_prop_frags (segT sec,
10772 segT xt_block_sec,
10773 xtensa_block_info **xt_block,
10774 frag_flags_fn property_function)
10775 {
10776 segment_info_type *seg_info;
10777 segment_info_type *xt_seg_info;
10778 bfd_vma seg_offset;
10779 fragS *fragP;
10780
10781 xt_seg_info = retrieve_segment_info (xt_block_sec);
10782 seg_info = retrieve_segment_info (sec);
10783 /* Build it if needed. */
10784 while (*xt_block != NULL)
10785 {
10786 xt_block = &(*xt_block)->next;
10787 }
10788 /* We are either at NULL at the beginning or at the end. */
10789
10790 /* Walk through the frags. */
10791 seg_offset = 0;
10792
10793 if (seg_info->frchainP)
10794 {
10795 for (fragP = seg_info->frchainP->frch_root; fragP;
10796 fragP = fragP->fr_next)
10797 {
10798 xtensa_block_info tmp_block;
10799 tmp_block.sec = sec;
10800 tmp_block.offset = fragP->fr_address;
10801 tmp_block.size = fragP->fr_fix;
10802 tmp_block.next = NULL;
10803 property_function (fragP, &tmp_block.flags);
10804
10805 if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
10806 /* && fragP->fr_fix != 0) */
10807 {
10808 if ((*xt_block) == NULL
10809 || !xtensa_xt_block_combine (*xt_block, &tmp_block))
10810 {
10811 xtensa_block_info *new_block;
10812 if ((*xt_block) != NULL)
10813 xt_block = &(*xt_block)->next;
10814 new_block = (xtensa_block_info *)
10815 xmalloc (sizeof (xtensa_block_info));
10816 *new_block = tmp_block;
10817 *xt_block = new_block;
10818 }
10819 }
10820 }
10821 }
10822 }
10823
10824
10825 /* op_placement_info_table */
10826
10827 /* op_placement_info makes it easier to determine which
10828 ops can go in which slots. */
10829
10830 static void
init_op_placement_info_table(void)10831 init_op_placement_info_table (void)
10832 {
10833 xtensa_isa isa = xtensa_default_isa;
10834 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
10835 xtensa_opcode opcode;
10836 xtensa_format fmt;
10837 int slot;
10838 int num_opcodes = xtensa_isa_num_opcodes (isa);
10839
10840 op_placement_table = (op_placement_info_table)
10841 xmalloc (sizeof (op_placement_info) * num_opcodes);
10842 assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
10843
10844 for (opcode = 0; opcode < num_opcodes; opcode++)
10845 {
10846 op_placement_info *opi = &op_placement_table[opcode];
10847 /* FIXME: Make tinsn allocation dynamic. */
10848 if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS)
10849 as_fatal (_("too many operands in instruction"));
10850 opi->single = XTENSA_UNDEFINED;
10851 opi->single_size = 0;
10852 opi->widest = XTENSA_UNDEFINED;
10853 opi->widest_size = 0;
10854 opi->narrowest = XTENSA_UNDEFINED;
10855 opi->narrowest_size = 0x7F;
10856 opi->formats = 0;
10857 opi->num_formats = 0;
10858 opi->issuef = 0;
10859 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
10860 {
10861 opi->slots[fmt] = 0;
10862 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
10863 {
10864 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
10865 {
10866 int fmt_length = xtensa_format_length (isa, fmt);
10867 opi->issuef++;
10868 set_bit (fmt, opi->formats);
10869 set_bit (slot, opi->slots[fmt]);
10870 /* opi->slot_count[fmt]++; */
10871 if (fmt_length < opi->narrowest_size)
10872 {
10873 opi->narrowest = fmt;
10874 opi->narrowest_size = fmt_length;
10875 }
10876 if (fmt_length > opi->widest_size)
10877 {
10878 opi->widest = fmt;
10879 opi->widest_size = fmt_length;
10880 }
10881 if (xtensa_format_num_slots (isa, fmt) == 1)
10882 {
10883 if (opi->single_size == 0
10884 || fmt_length < opi->single_size)
10885 {
10886 opi->single = fmt;
10887 opi->single_size = fmt_length;
10888 }
10889 }
10890 }
10891 }
10892 if (opi->formats)
10893 opi->num_formats++;
10894 }
10895 }
10896 xtensa_insnbuf_free (isa, ibuf);
10897 }
10898
10899
10900 bfd_boolean
opcode_fits_format_slot(xtensa_opcode opcode,xtensa_format fmt,int slot)10901 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
10902 {
10903 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
10904 }
10905
10906
10907 /* If the opcode is available in a single slot format, return its size. */
10908
10909 static int
xg_get_single_size(xtensa_opcode opcode)10910 xg_get_single_size (xtensa_opcode opcode)
10911 {
10912 assert (op_placement_table[opcode].single != XTENSA_UNDEFINED);
10913 return op_placement_table[opcode].single_size;
10914 }
10915
10916
10917 static xtensa_format
xg_get_single_format(xtensa_opcode opcode)10918 xg_get_single_format (xtensa_opcode opcode)
10919 {
10920 return op_placement_table[opcode].single;
10921 }
10922
10923
10924 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10925
10926 void
istack_init(IStack * stack)10927 istack_init (IStack *stack)
10928 {
10929 memset (stack, 0, sizeof (IStack));
10930 stack->ninsn = 0;
10931 }
10932
10933
10934 bfd_boolean
istack_empty(IStack * stack)10935 istack_empty (IStack *stack)
10936 {
10937 return (stack->ninsn == 0);
10938 }
10939
10940
10941 bfd_boolean
istack_full(IStack * stack)10942 istack_full (IStack *stack)
10943 {
10944 return (stack->ninsn == MAX_ISTACK);
10945 }
10946
10947
10948 /* Return a pointer to the top IStack entry.
10949 It is an error to call this if istack_empty () is TRUE. */
10950
10951 TInsn *
istack_top(IStack * stack)10952 istack_top (IStack *stack)
10953 {
10954 int rec = stack->ninsn - 1;
10955 assert (!istack_empty (stack));
10956 return &stack->insn[rec];
10957 }
10958
10959
10960 /* Add a new TInsn to an IStack.
10961 It is an error to call this if istack_full () is TRUE. */
10962
10963 void
istack_push(IStack * stack,TInsn * insn)10964 istack_push (IStack *stack, TInsn *insn)
10965 {
10966 int rec = stack->ninsn;
10967 assert (!istack_full (stack));
10968 stack->insn[rec] = *insn;
10969 stack->ninsn++;
10970 }
10971
10972
10973 /* Clear space for the next TInsn on the IStack and return a pointer
10974 to it. It is an error to call this if istack_full () is TRUE. */
10975
10976 TInsn *
istack_push_space(IStack * stack)10977 istack_push_space (IStack *stack)
10978 {
10979 int rec = stack->ninsn;
10980 TInsn *insn;
10981 assert (!istack_full (stack));
10982 insn = &stack->insn[rec];
10983 memset (insn, 0, sizeof (TInsn));
10984 stack->ninsn++;
10985 return insn;
10986 }
10987
10988
10989 /* Remove the last pushed instruction. It is an error to call this if
10990 istack_empty () returns TRUE. */
10991
10992 void
istack_pop(IStack * stack)10993 istack_pop (IStack *stack)
10994 {
10995 int rec = stack->ninsn - 1;
10996 assert (!istack_empty (stack));
10997 stack->ninsn--;
10998 memset (&stack->insn[rec], 0, sizeof (TInsn));
10999 }
11000
11001
11002 /* TInsn functions. */
11003
11004 void
tinsn_init(TInsn * dst)11005 tinsn_init (TInsn *dst)
11006 {
11007 memset (dst, 0, sizeof (TInsn));
11008 }
11009
11010
11011 /* Get the ``num''th token of the TInsn.
11012 It is illegal to call this if num > insn->ntoks. */
11013
11014 expressionS *
tinsn_get_tok(TInsn * insn,int num)11015 tinsn_get_tok (TInsn *insn, int num)
11016 {
11017 assert (num < insn->ntok);
11018 return &insn->tok[num];
11019 }
11020
11021
11022 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11023
11024 static bfd_boolean
tinsn_has_symbolic_operands(const TInsn * insn)11025 tinsn_has_symbolic_operands (const TInsn *insn)
11026 {
11027 int i;
11028 int n = insn->ntok;
11029
11030 assert (insn->insn_type == ITYPE_INSN);
11031
11032 for (i = 0; i < n; ++i)
11033 {
11034 switch (insn->tok[i].X_op)
11035 {
11036 case O_register:
11037 case O_constant:
11038 break;
11039 default:
11040 return TRUE;
11041 }
11042 }
11043 return FALSE;
11044 }
11045
11046
11047 bfd_boolean
tinsn_has_invalid_symbolic_operands(const TInsn * insn)11048 tinsn_has_invalid_symbolic_operands (const TInsn *insn)
11049 {
11050 xtensa_isa isa = xtensa_default_isa;
11051 int i;
11052 int n = insn->ntok;
11053
11054 assert (insn->insn_type == ITYPE_INSN);
11055
11056 for (i = 0; i < n; ++i)
11057 {
11058 switch (insn->tok[i].X_op)
11059 {
11060 case O_register:
11061 case O_constant:
11062 break;
11063 case O_big:
11064 case O_illegal:
11065 case O_absent:
11066 /* Errors for these types are caught later. */
11067 break;
11068 case O_hi16:
11069 case O_lo16:
11070 default:
11071 /* Symbolic immediates are only allowed on the last immediate
11072 operand. At this time, CONST16 is the only opcode where we
11073 support non-PC-relative relocations. (It isn't necessary
11074 to complain about non-PC-relative relocations here, but
11075 otherwise, no error is reported until the relocations are
11076 generated, and the assembler won't get that far if there
11077 are any other errors. It's nice to see all the problems
11078 at once.) */
11079 if (i != get_relaxable_immed (insn->opcode)
11080 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
11081 && insn->opcode != xtensa_const16_opcode))
11082 {
11083 as_bad (_("invalid symbolic operand %d on '%s'"),
11084 i, xtensa_opcode_name (isa, insn->opcode));
11085 return TRUE;
11086 }
11087 }
11088 }
11089 return FALSE;
11090 }
11091
11092
11093 /* For assembly code with complex expressions (e.g. subtraction),
11094 we have to build them in the literal pool so that
11095 their results are calculated correctly after relaxation.
11096 The relaxation only handles expressions that
11097 boil down to SYMBOL + OFFSET. */
11098
11099 static bfd_boolean
tinsn_has_complex_operands(const TInsn * insn)11100 tinsn_has_complex_operands (const TInsn *insn)
11101 {
11102 int i;
11103 int n = insn->ntok;
11104 assert (insn->insn_type == ITYPE_INSN);
11105 for (i = 0; i < n; ++i)
11106 {
11107 switch (insn->tok[i].X_op)
11108 {
11109 case O_register:
11110 case O_constant:
11111 case O_symbol:
11112 case O_lo16:
11113 case O_hi16:
11114 break;
11115 default:
11116 return TRUE;
11117 }
11118 }
11119 return FALSE;
11120 }
11121
11122
11123 /* Convert the constant operands in the tinsn to insnbuf.
11124 Return TRUE if there is a symbol in the immediate field.
11125
11126 Before this is called,
11127 1) the number of operands are correct
11128 2) the tinsn is a ITYPE_INSN
11129 3) ONLY the relaxable_ is built
11130 4) All operands are O_constant, O_symbol. All constants fit
11131 The return value tells whether there are any remaining O_symbols. */
11132
11133 static bfd_boolean
tinsn_to_insnbuf(TInsn * tinsn,xtensa_insnbuf insnbuf)11134 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
11135 {
11136 static xtensa_insnbuf slotbuf = 0;
11137 xtensa_isa isa = xtensa_default_isa;
11138 xtensa_opcode opcode = tinsn->opcode;
11139 xtensa_format fmt = xg_get_single_format (opcode);
11140 bfd_boolean has_fixup = FALSE;
11141 int noperands = xtensa_opcode_num_operands (isa, opcode);
11142 int i;
11143 uint32 opnd_value;
11144 char *file_name;
11145 unsigned line;
11146
11147 if (!slotbuf)
11148 slotbuf = xtensa_insnbuf_alloc (isa);
11149
11150 assert (tinsn->insn_type == ITYPE_INSN);
11151 if (noperands != tinsn->ntok)
11152 as_fatal (_("operand number mismatch"));
11153
11154 if (xtensa_opcode_encode (isa, fmt, 0, slotbuf, opcode))
11155 as_fatal (_("cannot encode opcode"));
11156
11157 for (i = 0; i < noperands; ++i)
11158 {
11159 expressionS *expr = &tinsn->tok[i];
11160 switch (expr->X_op)
11161 {
11162 case O_register:
11163 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11164 break;
11165 /* The register number has already been checked in
11166 expression_maybe_register, so we don't need to check here. */
11167 opnd_value = expr->X_add_number;
11168 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11169 xtensa_operand_set_field (isa, opcode, i, fmt, 0,
11170 slotbuf, opnd_value);
11171 break;
11172
11173 case O_constant:
11174 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11175 break;
11176 as_where (&file_name, &line);
11177 /* It is a constant and we called this function,
11178 then we have to try to fit it. */
11179 xtensa_insnbuf_set_operand (slotbuf, fmt, 0, opcode, i,
11180 expr->X_add_number, file_name, line);
11181 break;
11182
11183 default:
11184 has_fixup = TRUE;
11185 break;
11186 }
11187 }
11188
11189 xtensa_format_encode (isa, fmt, insnbuf);
11190 xtensa_format_set_slot (isa, fmt, 0, insnbuf, slotbuf);
11191
11192 return has_fixup;
11193 }
11194
11195
11196 /* Convert the constant operands in the tinsn to slotbuf.
11197 Return TRUE if there is a symbol in the immediate field.
11198 (Eventually this should replace tinsn_to_insnbuf.) */
11199
11200 /* Before this is called,
11201 1) the number of operands are correct
11202 2) the tinsn is a ITYPE_INSN
11203 3) ONLY the relaxable_ is built
11204 4) All operands are
11205 O_constant, O_symbol
11206 All constants fit
11207
11208 The return value tells whether there are any remaining O_symbols. */
11209
11210 static bfd_boolean
tinsn_to_slotbuf(xtensa_format fmt,int slot,TInsn * tinsn,xtensa_insnbuf slotbuf)11211 tinsn_to_slotbuf (xtensa_format fmt,
11212 int slot,
11213 TInsn *tinsn,
11214 xtensa_insnbuf slotbuf)
11215 {
11216 xtensa_isa isa = xtensa_default_isa;
11217 xtensa_opcode opcode = tinsn->opcode;
11218 bfd_boolean has_fixup = FALSE;
11219 int noperands = xtensa_opcode_num_operands (isa, opcode);
11220 int i;
11221
11222 *((int *) &slotbuf[0]) = 0;
11223 *((int *) &slotbuf[1]) = 0;
11224 assert (tinsn->insn_type == ITYPE_INSN);
11225 if (noperands != tinsn->ntok)
11226 as_fatal (_("operand number mismatch"));
11227
11228 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
11229 {
11230 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11231 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
11232 return FALSE;
11233 }
11234
11235 for (i = 0; i < noperands; i++)
11236 {
11237 expressionS *expr = &tinsn->tok[i];
11238 int rc;
11239 unsigned line;
11240 char *file_name;
11241 uint32 opnd_value;
11242
11243 switch (expr->X_op)
11244 {
11245 case O_register:
11246 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11247 break;
11248 /* The register number has already been checked in
11249 expression_maybe_register, so we don't need to check here. */
11250 opnd_value = expr->X_add_number;
11251 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11252 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
11253 opnd_value);
11254 if (rc != 0)
11255 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
11256 break;
11257
11258 case O_constant:
11259 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11260 break;
11261 as_where (&file_name, &line);
11262 /* It is a constant and we called this function
11263 then we have to try to fit it. */
11264 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
11265 expr->X_add_number, file_name, line);
11266 break;
11267
11268 default:
11269 has_fixup = TRUE;
11270 break;
11271 }
11272 }
11273
11274 return has_fixup;
11275 }
11276
11277
11278 /* Check the instruction arguments. Return TRUE on failure. */
11279
11280 static bfd_boolean
tinsn_check_arguments(const TInsn * insn)11281 tinsn_check_arguments (const TInsn *insn)
11282 {
11283 xtensa_isa isa = xtensa_default_isa;
11284 xtensa_opcode opcode = insn->opcode;
11285
11286 if (opcode == XTENSA_UNDEFINED)
11287 {
11288 as_bad (_("invalid opcode"));
11289 return TRUE;
11290 }
11291
11292 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
11293 {
11294 as_bad (_("too few operands"));
11295 return TRUE;
11296 }
11297
11298 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
11299 {
11300 as_bad (_("too many operands"));
11301 return TRUE;
11302 }
11303 return FALSE;
11304 }
11305
11306
11307 /* Load an instruction from its encoded form. */
11308
11309 static void
tinsn_from_chars(TInsn * tinsn,char * f,int slot)11310 tinsn_from_chars (TInsn *tinsn, char *f, int slot)
11311 {
11312 vliw_insn vinsn;
11313
11314 xg_init_vinsn (&vinsn);
11315 vinsn_from_chars (&vinsn, f);
11316
11317 *tinsn = vinsn.slots[slot];
11318 xg_free_vinsn (&vinsn);
11319 }
11320
11321
11322 static void
tinsn_from_insnbuf(TInsn * tinsn,xtensa_insnbuf slotbuf,xtensa_format fmt,int slot)11323 tinsn_from_insnbuf (TInsn *tinsn,
11324 xtensa_insnbuf slotbuf,
11325 xtensa_format fmt,
11326 int slot)
11327 {
11328 int i;
11329 xtensa_isa isa = xtensa_default_isa;
11330
11331 /* Find the immed. */
11332 tinsn_init (tinsn);
11333 tinsn->insn_type = ITYPE_INSN;
11334 tinsn->is_specific_opcode = FALSE; /* must not be specific */
11335 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
11336 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
11337 for (i = 0; i < tinsn->ntok; i++)
11338 {
11339 set_expr_const (&tinsn->tok[i],
11340 xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
11341 tinsn->opcode, i));
11342 }
11343 }
11344
11345
11346 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11347
11348 static void
tinsn_immed_from_frag(TInsn * tinsn,fragS * fragP,int slot)11349 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
11350 {
11351 xtensa_opcode opcode = tinsn->opcode;
11352 int opnum;
11353
11354 if (fragP->tc_frag_data.slot_symbols[slot])
11355 {
11356 opnum = get_relaxable_immed (opcode);
11357 assert (opnum >= 0);
11358 if (fragP->tc_frag_data.slot_sub_symbols[slot])
11359 {
11360 set_expr_symbol_offset_diff
11361 (&tinsn->tok[opnum],
11362 fragP->tc_frag_data.slot_symbols[slot],
11363 fragP->tc_frag_data.slot_sub_symbols[slot],
11364 fragP->tc_frag_data.slot_offsets[slot]);
11365 }
11366 else
11367 {
11368 set_expr_symbol_offset
11369 (&tinsn->tok[opnum],
11370 fragP->tc_frag_data.slot_symbols[slot],
11371 fragP->tc_frag_data.slot_offsets[slot]);
11372 }
11373 }
11374 }
11375
11376
11377 static int
get_num_stack_text_bytes(IStack * istack)11378 get_num_stack_text_bytes (IStack *istack)
11379 {
11380 int i;
11381 int text_bytes = 0;
11382
11383 for (i = 0; i < istack->ninsn; i++)
11384 {
11385 TInsn *tinsn = &istack->insn[i];
11386 if (tinsn->insn_type == ITYPE_INSN)
11387 text_bytes += xg_get_single_size (tinsn->opcode);
11388 }
11389 return text_bytes;
11390 }
11391
11392
11393 static int
get_num_stack_literal_bytes(IStack * istack)11394 get_num_stack_literal_bytes (IStack *istack)
11395 {
11396 int i;
11397 int lit_bytes = 0;
11398
11399 for (i = 0; i < istack->ninsn; i++)
11400 {
11401 TInsn *tinsn = &istack->insn[i];
11402 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
11403 lit_bytes += 4;
11404 }
11405 return lit_bytes;
11406 }
11407
11408
11409 /* vliw_insn functions. */
11410
11411 static void
xg_init_vinsn(vliw_insn * v)11412 xg_init_vinsn (vliw_insn *v)
11413 {
11414 int i;
11415 xtensa_isa isa = xtensa_default_isa;
11416
11417 xg_clear_vinsn (v);
11418
11419 v->insnbuf = xtensa_insnbuf_alloc (isa);
11420 if (v->insnbuf == NULL)
11421 as_fatal (_("out of memory"));
11422
11423 for (i = 0; i < MAX_SLOTS; i++)
11424 {
11425 tinsn_init (&v->slots[i]);
11426 v->slots[i].opcode = XTENSA_UNDEFINED;
11427 v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
11428 if (v->slotbuf[i] == NULL)
11429 as_fatal (_("out of memory"));
11430 }
11431 }
11432
11433
11434 static void
xg_clear_vinsn(vliw_insn * v)11435 xg_clear_vinsn (vliw_insn *v)
11436 {
11437 int i;
11438 v->format = XTENSA_UNDEFINED;
11439 v->num_slots = 0;
11440 v->inside_bundle = FALSE;
11441
11442 if (xt_saved_debug_type != DEBUG_NONE)
11443 debug_type = xt_saved_debug_type;
11444
11445 for (i = 0; i < MAX_SLOTS; i++)
11446 {
11447 memset (&v->slots[i], 0, sizeof (TInsn));
11448 v->slots[i].opcode = XTENSA_UNDEFINED;
11449 }
11450 }
11451
11452
11453 static bfd_boolean
vinsn_has_specific_opcodes(vliw_insn * v)11454 vinsn_has_specific_opcodes (vliw_insn *v)
11455 {
11456 int i;
11457
11458 for (i = 0; i < v->num_slots; i++)
11459 {
11460 if (v->slots[i].is_specific_opcode)
11461 return TRUE;
11462 }
11463 return FALSE;
11464 }
11465
11466
11467 static void
xg_free_vinsn(vliw_insn * v)11468 xg_free_vinsn (vliw_insn *v)
11469 {
11470 int i;
11471 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
11472 for (i = 0; i < MAX_SLOTS; i++)
11473 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
11474 }
11475
11476
11477 /* Before this is called, we should have
11478 filled out the following fields:
11479
11480 1) the number of operands for each opcode are correct
11481 2) the tinsn in the slots are ITYPE_INSN
11482 3) ONLY the relaxable_ is built
11483 4) All operands are
11484 O_constant, O_symbol
11485 All constants fit
11486
11487 The return value tells whether there are any remaining O_symbols. */
11488
11489 static bfd_boolean
vinsn_to_insnbuf(vliw_insn * vinsn,char * frag_offset,fragS * fragP,bfd_boolean record_fixup)11490 vinsn_to_insnbuf (vliw_insn *vinsn,
11491 char *frag_offset,
11492 fragS *fragP,
11493 bfd_boolean record_fixup)
11494 {
11495 xtensa_isa isa = xtensa_default_isa;
11496 xtensa_format fmt = vinsn->format;
11497 xtensa_insnbuf insnbuf = vinsn->insnbuf;
11498 int slot;
11499 bfd_boolean has_fixup = FALSE;
11500
11501 xtensa_format_encode (isa, fmt, insnbuf);
11502
11503 for (slot = 0; slot < vinsn->num_slots; slot++)
11504 {
11505 TInsn *tinsn = &vinsn->slots[slot];
11506 bfd_boolean tinsn_has_fixup =
11507 tinsn_to_slotbuf (vinsn->format, slot, tinsn,
11508 vinsn->slotbuf[slot]);
11509
11510 xtensa_format_set_slot (isa, fmt, slot,
11511 insnbuf, vinsn->slotbuf[slot]);
11512 /* tinsn_has_fixup tracks if there is a fixup at all.
11513 record_fixup controls globally. I.E., we use this
11514 function from several places, some of which are after
11515 fixups have already been recorded. Finally,
11516 tinsn->record_fixup controls based on the individual ops,
11517 which may or may not need it based on the relaxation
11518 requirements. */
11519 if (tinsn_has_fixup && record_fixup)
11520 {
11521 int i;
11522 xtensa_opcode opcode = tinsn->opcode;
11523 int noperands = xtensa_opcode_num_operands (isa, opcode);
11524 has_fixup = TRUE;
11525
11526 for (i = 0; i < noperands; i++)
11527 {
11528 expressionS* expr = &tinsn->tok[i];
11529 switch (expr->X_op)
11530 {
11531 case O_symbol:
11532 case O_lo16:
11533 case O_hi16:
11534 if (get_relaxable_immed (opcode) == i)
11535 {
11536 if (tinsn->record_fix || expr->X_op != O_symbol)
11537 {
11538 if (!xg_add_opcode_fix
11539 (tinsn, i, fmt, slot, expr, fragP,
11540 frag_offset - fragP->fr_literal))
11541 as_bad (_("instruction with constant operands does not fit"));
11542 }
11543 else
11544 {
11545 tinsn->symbol = expr->X_add_symbol;
11546 tinsn->offset = expr->X_add_number;
11547 }
11548 }
11549 else
11550 as_bad (_("invalid operand %d on '%s'"),
11551 i, xtensa_opcode_name (isa, opcode));
11552 break;
11553
11554 case O_constant:
11555 case O_register:
11556 break;
11557
11558 case O_subtract:
11559 if (get_relaxable_immed (opcode) == i)
11560 {
11561 if (tinsn->record_fix)
11562 as_bad (_("invalid subtract operand"));
11563 else
11564 {
11565 tinsn->symbol = expr->X_add_symbol;
11566 tinsn->sub_symbol = expr->X_op_symbol;
11567 tinsn->offset = expr->X_add_number;
11568 }
11569 }
11570 else
11571 as_bad (_("invalid operand %d on '%s'"),
11572 i, xtensa_opcode_name (isa, opcode));
11573 break;
11574
11575 default:
11576 as_bad (_("invalid expression for operand %d on '%s'"),
11577 i, xtensa_opcode_name (isa, opcode));
11578 break;
11579 }
11580 }
11581 }
11582 }
11583
11584 return has_fixup;
11585 }
11586
11587
11588 static void
vinsn_from_chars(vliw_insn * vinsn,char * f)11589 vinsn_from_chars (vliw_insn *vinsn, char *f)
11590 {
11591 static xtensa_insnbuf insnbuf = NULL;
11592 static xtensa_insnbuf slotbuf = NULL;
11593 int i;
11594 xtensa_format fmt;
11595 xtensa_isa isa = xtensa_default_isa;
11596
11597 if (!insnbuf)
11598 {
11599 insnbuf = xtensa_insnbuf_alloc (isa);
11600 slotbuf = xtensa_insnbuf_alloc (isa);
11601 }
11602
11603 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0);
11604 fmt = xtensa_format_decode (isa, insnbuf);
11605 if (fmt == XTENSA_UNDEFINED)
11606 as_fatal (_("cannot decode instruction format"));
11607 vinsn->format = fmt;
11608 vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
11609
11610 for (i = 0; i < vinsn->num_slots; i++)
11611 {
11612 TInsn *tinsn = &vinsn->slots[i];
11613 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
11614 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
11615 }
11616 }
11617
11618
11619 /* Expression utilities. */
11620
11621 /* Return TRUE if the expression is an integer constant. */
11622
11623 bfd_boolean
expr_is_const(const expressionS * s)11624 expr_is_const (const expressionS *s)
11625 {
11626 return (s->X_op == O_constant);
11627 }
11628
11629
11630 /* Get the expression constant.
11631 Calling this is illegal if expr_is_const () returns TRUE. */
11632
11633 offsetT
get_expr_const(const expressionS * s)11634 get_expr_const (const expressionS *s)
11635 {
11636 assert (expr_is_const (s));
11637 return s->X_add_number;
11638 }
11639
11640
11641 /* Set the expression to a constant value. */
11642
11643 void
set_expr_const(expressionS * s,offsetT val)11644 set_expr_const (expressionS *s, offsetT val)
11645 {
11646 s->X_op = O_constant;
11647 s->X_add_number = val;
11648 s->X_add_symbol = NULL;
11649 s->X_op_symbol = NULL;
11650 }
11651
11652
11653 bfd_boolean
expr_is_register(const expressionS * s)11654 expr_is_register (const expressionS *s)
11655 {
11656 return (s->X_op == O_register);
11657 }
11658
11659
11660 /* Get the expression constant.
11661 Calling this is illegal if expr_is_const () returns TRUE. */
11662
11663 offsetT
get_expr_register(const expressionS * s)11664 get_expr_register (const expressionS *s)
11665 {
11666 assert (expr_is_register (s));
11667 return s->X_add_number;
11668 }
11669
11670
11671 /* Set the expression to a symbol + constant offset. */
11672
11673 void
set_expr_symbol_offset(expressionS * s,symbolS * sym,offsetT offset)11674 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
11675 {
11676 s->X_op = O_symbol;
11677 s->X_add_symbol = sym;
11678 s->X_op_symbol = NULL; /* unused */
11679 s->X_add_number = offset;
11680 }
11681
11682
11683 /* Set the expression to symbol - minus_sym + offset. */
11684
11685 static void
set_expr_symbol_offset_diff(expressionS * s,symbolS * sym,symbolS * minus_sym,offsetT offset)11686 set_expr_symbol_offset_diff (expressionS *s,
11687 symbolS *sym,
11688 symbolS *minus_sym,
11689 offsetT offset)
11690 {
11691 s->X_op = O_subtract;
11692 s->X_add_symbol = sym;
11693 s->X_op_symbol = minus_sym; /* unused */
11694 s->X_add_number = offset;
11695 }
11696
11697
11698 /* Return TRUE if the two expressions are equal. */
11699
11700 bfd_boolean
expr_is_equal(expressionS * s1,expressionS * s2)11701 expr_is_equal (expressionS *s1, expressionS *s2)
11702 {
11703 if (s1->X_op != s2->X_op)
11704 return FALSE;
11705 if (s1->X_add_symbol != s2->X_add_symbol)
11706 return FALSE;
11707 if (s1->X_op_symbol != s2->X_op_symbol)
11708 return FALSE;
11709 if (s1->X_add_number != s2->X_add_number)
11710 return FALSE;
11711 return TRUE;
11712 }
11713
11714
11715 static void
copy_expr(expressionS * dst,const expressionS * src)11716 copy_expr (expressionS *dst, const expressionS *src)
11717 {
11718 memcpy (dst, src, sizeof (expressionS));
11719 }
11720
11721
11722 /* Support for the "--rename-section" option. */
11723
11724 struct rename_section_struct
11725 {
11726 char *old_name;
11727 char *new_name;
11728 struct rename_section_struct *next;
11729 };
11730
11731 static struct rename_section_struct *section_rename;
11732
11733
11734 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11735 entries to the section_rename list. Note: Specifying multiple
11736 renamings separated by colons is not documented and is retained only
11737 for backward compatibility. */
11738
11739 static void
build_section_rename(const char * arg)11740 build_section_rename (const char *arg)
11741 {
11742 struct rename_section_struct *r;
11743 char *this_arg = NULL;
11744 char *next_arg = NULL;
11745
11746 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
11747 {
11748 char *old_name, *new_name;
11749
11750 if (this_arg)
11751 {
11752 next_arg = strchr (this_arg, ':');
11753 if (next_arg)
11754 {
11755 *next_arg = '\0';
11756 next_arg++;
11757 }
11758 }
11759
11760 old_name = this_arg;
11761 new_name = strchr (this_arg, '=');
11762
11763 if (*old_name == '\0')
11764 {
11765 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11766 continue;
11767 }
11768 if (!new_name || new_name[1] == '\0')
11769 {
11770 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11771 old_name);
11772 continue;
11773 }
11774 *new_name = '\0';
11775 new_name++;
11776
11777 /* Check for invalid section renaming. */
11778 for (r = section_rename; r != NULL; r = r->next)
11779 {
11780 if (strcmp (r->old_name, old_name) == 0)
11781 as_bad (_("section %s renamed multiple times"), old_name);
11782 if (strcmp (r->new_name, new_name) == 0)
11783 as_bad (_("multiple sections remapped to output section %s"),
11784 new_name);
11785 }
11786
11787 /* Now add it. */
11788 r = (struct rename_section_struct *)
11789 xmalloc (sizeof (struct rename_section_struct));
11790 r->old_name = xstrdup (old_name);
11791 r->new_name = xstrdup (new_name);
11792 r->next = section_rename;
11793 section_rename = r;
11794 }
11795 }
11796
11797
11798 char *
xtensa_section_rename(char * name)11799 xtensa_section_rename (char *name)
11800 {
11801 struct rename_section_struct *r = section_rename;
11802
11803 for (r = section_rename; r != NULL; r = r->next)
11804 {
11805 if (strcmp (r->old_name, name) == 0)
11806 return r->new_name;
11807 }
11808
11809 return name;
11810 }
11811