xref: /freebsd-13-stable/sys/dev/mlx5/mlx5_ifc.h (revision f8167e0404dab9ffeaca95853dd237ab7c587f82) 
1 /*-
2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  */
25 
26 #ifndef MLX5_IFC_H
27 #define MLX5_IFC_H
28 
29 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
30 
31 enum {
32 	MLX5_EVENT_TYPE_COMP                                       = 0x0,
33 	MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
34 	MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
35 	MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
36 	MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
37 	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
38 	MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
39 	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
40 	MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
41 	MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
42 	MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
43 	MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
44 	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
45 	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
46 	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
47 	MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
48 	MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
49 	MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
50 	MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
51 	MLX5_EVENT_TYPE_TEMP_WARN_EVENT                            = 0x17,
52 	MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
53 	MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
54 	MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
55 	MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
56 	MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
57 	MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
58 	MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
59 	MLX5_EVENT_TYPE_CMD                                        = 0xa,
60 	MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
61 	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
62 	MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
63 	MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
64 	MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT                   = 0x27,
65 };
66 
67 enum {
68 	MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
69 	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
70 	MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
71 	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
72 	MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
73 };
74 
75 enum {
76 	MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
77 };
78 
79 enum {
80 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
81 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
82 };
83 
84 enum {
85 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
86 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
87 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
88 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
89 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
90 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
91 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
92 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
93 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
94 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
95 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
96 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
97 	MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
98 	MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
99 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
100 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
101 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
102 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
103 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
104 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
105 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
106 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
107 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
108 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
109 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
110 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
111 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
112 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
113 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
114 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
115 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
116 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
117 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
118 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
119 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
120 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
121 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
122 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
123 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
124 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
125 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
126 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
127 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
128 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
129 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
130 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
131 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
132 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
133 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
134 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
135 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
136 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
137 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
138 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
139 	MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
140 	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
141 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
142 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
143 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
144 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
145 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
146 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
147 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
148 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
149 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
150 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
151 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
152 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
153 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
154 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
155 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
156 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
157 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
158 	MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
159 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
160 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
161 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
162 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
163 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
164 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
165 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
166 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
167 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
168 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
169 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
170 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
171 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
172 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
173 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
174 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
175 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
176 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
177 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
178 	MLX5_CMD_OP_NOP                           = 0x80d,
179 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
180 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
181 	MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
182 	MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
183 	MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
184 	MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
185 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
186 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
187 	MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS       = 0x819,
188 	MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
189 	MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
190 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
191 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
192 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
193 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
194 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
195 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
196 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
197 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
198 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
199 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
200 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
201 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
202 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
203 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
204 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
205 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
206 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
207 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
208 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
209 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
210 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
211 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
212 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
213 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
214 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
215 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
216 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
217 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
218 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
219 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
220 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
221 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
222 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
223 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
224 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
225 	MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
226 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
227 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
228 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
229 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
230 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
231 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
232 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
233 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
234 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
235 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
236 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
237 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
238 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
239 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
240 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
241 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
242 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
243 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
244 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
245 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
246 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
247 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
248 	MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
249 	MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
250 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
251 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
252 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
253 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
254 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
255 	MLX5_CMD_OP_CREATE_GENERAL_OBJ            = 0xa00,
256 	MLX5_CMD_OP_MODIFY_GENERAL_OBJ            = 0xa01,
257 	MLX5_CMD_OP_QUERY_GENERAL_OBJ             = 0xa02,
258 	MLX5_CMD_OP_DESTROY_GENERAL_OBJ           = 0xa03,
259 
260 };
261 
262 enum {
263 	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
264 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
265 	MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
266 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
267 	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
268 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
269 	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
270 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
271 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
272 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
273 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
274 	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
275 };
276 
277 enum {
278 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
279 };
280 
281 enum {
282 	MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
283 };
284 
285 enum {
286 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
287 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
288 };
289 
290 enum {
291 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
292 };
293 
294 struct mlx5_ifc_flow_table_fields_supported_bits {
295 	u8         outer_dmac[0x1];
296 	u8         outer_smac[0x1];
297 	u8         outer_ether_type[0x1];
298 	u8         outer_ip_version[0x1];
299 	u8         outer_first_prio[0x1];
300 	u8         outer_first_cfi[0x1];
301 	u8         outer_first_vid[0x1];
302 	u8         reserved_1[0x1];
303 	u8         outer_second_prio[0x1];
304 	u8         outer_second_cfi[0x1];
305 	u8         outer_second_vid[0x1];
306 	u8         outer_ipv6_flow_label[0x1];
307 	u8         outer_sip[0x1];
308 	u8         outer_dip[0x1];
309 	u8         outer_frag[0x1];
310 	u8         outer_ip_protocol[0x1];
311 	u8         outer_ip_ecn[0x1];
312 	u8         outer_ip_dscp[0x1];
313 	u8         outer_udp_sport[0x1];
314 	u8         outer_udp_dport[0x1];
315 	u8         outer_tcp_sport[0x1];
316 	u8         outer_tcp_dport[0x1];
317 	u8         outer_tcp_flags[0x1];
318 	u8         outer_gre_protocol[0x1];
319 	u8         outer_gre_key[0x1];
320 	u8         outer_vxlan_vni[0x1];
321 	u8         outer_geneve_vni[0x1];
322 	u8         outer_geneve_oam[0x1];
323 	u8         outer_geneve_protocol_type[0x1];
324 	u8         outer_geneve_opt_len[0x1];
325 	u8         reserved_2[0x1];
326 	u8         source_eswitch_port[0x1];
327 
328 	u8         inner_dmac[0x1];
329 	u8         inner_smac[0x1];
330 	u8         inner_ether_type[0x1];
331 	u8         inner_ip_version[0x1];
332 	u8         inner_first_prio[0x1];
333 	u8         inner_first_cfi[0x1];
334 	u8         inner_first_vid[0x1];
335 	u8         reserved_4[0x1];
336 	u8         inner_second_prio[0x1];
337 	u8         inner_second_cfi[0x1];
338 	u8         inner_second_vid[0x1];
339 	u8         inner_ipv6_flow_label[0x1];
340 	u8         inner_sip[0x1];
341 	u8         inner_dip[0x1];
342 	u8         inner_frag[0x1];
343 	u8         inner_ip_protocol[0x1];
344 	u8         inner_ip_ecn[0x1];
345 	u8         inner_ip_dscp[0x1];
346 	u8         inner_udp_sport[0x1];
347 	u8         inner_udp_dport[0x1];
348 	u8         inner_tcp_sport[0x1];
349 	u8         inner_tcp_dport[0x1];
350 	u8         inner_tcp_flags[0x1];
351 	u8         reserved_5[0x9];
352 
353 	u8         reserved_6[0x1a];
354 	u8         bth_dst_qp[0x1];
355 	u8         reserved_7[0x4];
356 	u8         source_sqn[0x1];
357 
358 	u8         reserved_8[0x20];
359 };
360 
361 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
362 	u8         ingress_general_high[0x20];
363 
364 	u8         ingress_general_low[0x20];
365 
366 	u8         ingress_policy_engine_high[0x20];
367 
368 	u8         ingress_policy_engine_low[0x20];
369 
370 	u8         ingress_vlan_membership_high[0x20];
371 
372 	u8         ingress_vlan_membership_low[0x20];
373 
374 	u8         ingress_tag_frame_type_high[0x20];
375 
376 	u8         ingress_tag_frame_type_low[0x20];
377 
378 	u8         egress_vlan_membership_high[0x20];
379 
380 	u8         egress_vlan_membership_low[0x20];
381 
382 	u8         loopback_filter_high[0x20];
383 
384 	u8         loopback_filter_low[0x20];
385 
386 	u8         egress_general_high[0x20];
387 
388 	u8         egress_general_low[0x20];
389 
390 	u8         reserved_at_1c0[0x40];
391 
392 	u8         egress_hoq_high[0x20];
393 
394 	u8         egress_hoq_low[0x20];
395 
396 	u8         port_isolation_high[0x20];
397 
398 	u8         port_isolation_low[0x20];
399 
400 	u8         egress_policy_engine_high[0x20];
401 
402 	u8         egress_policy_engine_low[0x20];
403 
404 	u8         ingress_tx_link_down_high[0x20];
405 
406 	u8         ingress_tx_link_down_low[0x20];
407 
408 	u8         egress_stp_filter_high[0x20];
409 
410 	u8         egress_stp_filter_low[0x20];
411 
412 	u8         egress_hoq_stall_high[0x20];
413 
414 	u8         egress_hoq_stall_low[0x20];
415 
416 	u8         reserved_at_340[0x440];
417 };
418 struct mlx5_ifc_flow_table_prop_layout_bits {
419 	u8         ft_support[0x1];
420 	u8         flow_tag[0x1];
421 	u8         flow_counter[0x1];
422 	u8         flow_modify_en[0x1];
423 	u8         modify_root[0x1];
424 	u8         identified_miss_table[0x1];
425 	u8         flow_table_modify[0x1];
426 	u8         encap[0x1];
427 	u8         decap[0x1];
428 	u8         reset_root_to_default[0x1];
429 	u8         reserved_at_a[0x16];
430 
431 	u8         reserved_at_20[0x2];
432 	u8         log_max_ft_size[0x6];
433 	u8         reserved_at_28[0x10];
434 	u8         max_ft_level[0x8];
435 
436 	u8         reserved_at_40[0x20];
437 
438 	u8         reserved_at_60[0x18];
439 	u8         log_max_ft_num[0x8];
440 
441 	u8         reserved_at_80[0x10];
442 	u8         log_max_flow_counter[0x8];
443 	u8         log_max_destination[0x8];
444 
445 	u8         reserved_at_a0[0x18];
446 	u8         log_max_flow[0x8];
447 
448 	u8         reserved_at_c0[0x40];
449 
450 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
451 
452 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
453 };
454 
455 struct mlx5_ifc_odp_per_transport_service_cap_bits {
456 	u8         send[0x1];
457 	u8         receive[0x1];
458 	u8         write[0x1];
459 	u8         read[0x1];
460 	u8         atomic[0x1];
461 	u8         srq_receive[0x1];
462 	u8         reserved_0[0x1a];
463 };
464 
465 struct mlx5_ifc_flow_counter_list_bits {
466 	u8         reserved_0[0x10];
467 	u8         flow_counter_id[0x10];
468 
469 	u8         reserved_1[0x20];
470 };
471 
472 enum {
473 	MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
474 	MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
475 	MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
476 	MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
477 };
478 
479 struct mlx5_ifc_dest_format_struct_bits {
480 	u8         destination_type[0x8];
481 	u8         destination_id[0x18];
482 
483 	u8         reserved_0[0x20];
484 };
485 
486 struct mlx5_ifc_ipv4_layout_bits {
487 	u8         reserved_at_0[0x60];
488 
489 	u8         ipv4[0x20];
490 };
491 
492 struct mlx5_ifc_ipv6_layout_bits {
493 	u8         ipv6[16][0x8];
494 };
495 
496 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
497 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
498 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
499 	u8         reserved_at_0[0x80];
500 };
501 
502 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
503 	u8         smac_47_16[0x20];
504 
505 	u8         smac_15_0[0x10];
506 	u8         ethertype[0x10];
507 
508 	u8         dmac_47_16[0x20];
509 
510 	u8         dmac_15_0[0x10];
511 	u8         first_prio[0x3];
512 	u8         first_cfi[0x1];
513 	u8         first_vid[0xc];
514 
515 	u8         ip_protocol[0x8];
516 	u8         ip_dscp[0x6];
517 	u8         ip_ecn[0x2];
518 	u8         cvlan_tag[0x1];
519 	u8         svlan_tag[0x1];
520 	u8         frag[0x1];
521 	u8         ip_version[0x4];
522 	u8         tcp_flags[0x9];
523 
524 	u8         tcp_sport[0x10];
525 	u8         tcp_dport[0x10];
526 
527 	u8         reserved_2[0x20];
528 
529 	u8         udp_sport[0x10];
530 	u8         udp_dport[0x10];
531 
532 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
533 
534 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
535 };
536 
537 struct mlx5_ifc_fte_match_set_misc_bits {
538 	u8         reserved_0[0x8];
539 	u8         source_sqn[0x18];
540 
541 	u8         reserved_1[0x10];
542 	u8         source_port[0x10];
543 
544 	u8         outer_second_prio[0x3];
545 	u8         outer_second_cfi[0x1];
546 	u8         outer_second_vid[0xc];
547 	u8         inner_second_prio[0x3];
548 	u8         inner_second_cfi[0x1];
549 	u8         inner_second_vid[0xc];
550 
551 	u8         outer_second_vlan_tag[0x1];
552 	u8         inner_second_vlan_tag[0x1];
553 	u8         reserved_2[0xe];
554 	u8         gre_protocol[0x10];
555 
556 	u8         gre_key_h[0x18];
557 	u8         gre_key_l[0x8];
558 
559 	u8         vxlan_vni[0x18];
560 	u8         reserved_3[0x8];
561 
562 	u8         geneve_vni[0x18];
563 	u8         reserved4[0x7];
564 	u8         geneve_oam[0x1];
565 
566 	u8         reserved_5[0xc];
567 	u8         outer_ipv6_flow_label[0x14];
568 
569 	u8         reserved_6[0xc];
570 	u8         inner_ipv6_flow_label[0x14];
571 
572 	u8         reserved_7[0xa];
573 	u8         geneve_opt_len[0x6];
574 	u8         geneve_protocol_type[0x10];
575 
576 	u8         reserved_8[0x8];
577 	u8         bth_dst_qp[0x18];
578 
579 	u8         reserved_9[0xa0];
580 };
581 
582 struct mlx5_ifc_cmd_pas_bits {
583 	u8         pa_h[0x20];
584 
585 	u8         pa_l[0x14];
586 	u8         reserved_0[0xc];
587 };
588 
589 struct mlx5_ifc_uint64_bits {
590 	u8         hi[0x20];
591 
592 	u8         lo[0x20];
593 };
594 
595 struct mlx5_ifc_application_prio_entry_bits {
596 	u8         reserved_0[0x8];
597 	u8         priority[0x3];
598 	u8         reserved_1[0x2];
599 	u8         sel[0x3];
600 	u8         protocol_id[0x10];
601 };
602 
603 struct mlx5_ifc_nodnic_ring_doorbell_bits {
604 	u8         reserved_0[0x8];
605 	u8         ring_pi[0x10];
606 	u8         reserved_1[0x8];
607 };
608 
609 enum {
610 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
611 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
612 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
613 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
614 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
615 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
616 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
617 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
618 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
619 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
620 };
621 
622 struct mlx5_ifc_ads_bits {
623 	u8         fl[0x1];
624 	u8         free_ar[0x1];
625 	u8         reserved_0[0xe];
626 	u8         pkey_index[0x10];
627 
628 	u8         reserved_1[0x8];
629 	u8         grh[0x1];
630 	u8         mlid[0x7];
631 	u8         rlid[0x10];
632 
633 	u8         ack_timeout[0x5];
634 	u8         reserved_2[0x3];
635 	u8         src_addr_index[0x8];
636 	u8         log_rtm[0x4];
637 	u8         stat_rate[0x4];
638 	u8         hop_limit[0x8];
639 
640 	u8         reserved_3[0x4];
641 	u8         tclass[0x8];
642 	u8         flow_label[0x14];
643 
644 	u8         rgid_rip[16][0x8];
645 
646 	u8         reserved_4[0x4];
647 	u8         f_dscp[0x1];
648 	u8         f_ecn[0x1];
649 	u8         reserved_5[0x1];
650 	u8         f_eth_prio[0x1];
651 	u8         ecn[0x2];
652 	u8         dscp[0x6];
653 	u8         udp_sport[0x10];
654 
655 	u8         dei_cfi[0x1];
656 	u8         eth_prio[0x3];
657 	u8         sl[0x4];
658 	u8         port[0x8];
659 	u8         rmac_47_32[0x10];
660 
661 	u8         rmac_31_0[0x20];
662 };
663 
664 struct mlx5_ifc_diagnostic_counter_cap_bits {
665 	u8         sync[0x1];
666 	u8         reserved_0[0xf];
667 	u8         counter_id[0x10];
668 };
669 
670 struct mlx5_ifc_debug_cap_bits {
671 	u8         reserved_0[0x18];
672 	u8         log_max_samples[0x8];
673 
674 	u8         single[0x1];
675 	u8         repetitive[0x1];
676 	u8         health_mon_rx_activity[0x1];
677 	u8         reserved_1[0x15];
678 	u8         log_min_sample_period[0x8];
679 
680 	u8         reserved_2[0x1c0];
681 
682 	struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
683 };
684 
685 struct mlx5_ifc_qos_cap_bits {
686 	u8         packet_pacing[0x1];
687 	u8         esw_scheduling[0x1];
688 	u8         esw_bw_share[0x1];
689 	u8         esw_rate_limit[0x1];
690 	u8         hll[0x1];
691 	u8         packet_pacing_burst_bound[0x1];
692 	u8         packet_pacing_typical_size[0x1];
693 	u8         reserved_at_7[0x19];
694 
695 	u8 	   reserved_at_20[0xA];
696 	u8	   qos_remap_pp[0x1];
697 	u8         reserved_at_2b[0x15];
698 
699 	u8         packet_pacing_max_rate[0x20];
700 
701 	u8         packet_pacing_min_rate[0x20];
702 
703 	u8         reserved_at_80[0x10];
704 	u8         packet_pacing_rate_table_size[0x10];
705 
706 	u8         esw_element_type[0x10];
707 	u8         esw_tsar_type[0x10];
708 
709 	u8         reserved_at_c0[0x10];
710 	u8         max_qos_para_vport[0x10];
711 
712 	u8         max_tsar_bw_share[0x20];
713 
714 	u8         reserved_at_100[0x700];
715 };
716 
717 struct mlx5_ifc_snapshot_cap_bits {
718 	u8         reserved_0[0x1d];
719 	u8         suspend_qp_uc[0x1];
720 	u8         suspend_qp_ud[0x1];
721 	u8         suspend_qp_rc[0x1];
722 
723 	u8         reserved_1[0x1c];
724 	u8         restore_pd[0x1];
725 	u8         restore_uar[0x1];
726 	u8         restore_mkey[0x1];
727 	u8         restore_qp[0x1];
728 
729 	u8         reserved_2[0x1e];
730 	u8         named_mkey[0x1];
731 	u8         named_qp[0x1];
732 
733 	u8         reserved_3[0x7a0];
734 };
735 
736 struct mlx5_ifc_e_switch_cap_bits {
737 	u8         vport_svlan_strip[0x1];
738 	u8         vport_cvlan_strip[0x1];
739 	u8         vport_svlan_insert[0x1];
740 	u8         vport_cvlan_insert_if_not_exist[0x1];
741 	u8         vport_cvlan_insert_overwrite[0x1];
742 
743 	u8         reserved_0[0x19];
744 
745 	u8         nic_vport_node_guid_modify[0x1];
746 	u8         nic_vport_port_guid_modify[0x1];
747 
748 	u8         reserved_1[0x7e0];
749 };
750 
751 struct mlx5_ifc_flow_table_eswitch_cap_bits {
752 	u8         reserved_0[0x200];
753 
754 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
755 
756 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
757 
758 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
759 
760 	u8         reserved_1[0x7800];
761 };
762 
763 struct mlx5_ifc_flow_table_nic_cap_bits {
764 	u8         nic_rx_multi_path_tirs[0x1];
765 	u8         nic_rx_multi_path_tirs_fts[0x1];
766 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
767 	u8         reserved_at_3[0x1fd];
768 
769 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
770 
771 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
772 
773 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
774 
775 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
776 
777 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
778 
779 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
780 
781 	u8         reserved_1[0x7200];
782 };
783 
784 struct mlx5_ifc_pddr_module_info_bits {
785 	u8         cable_technology[0x8];
786 	u8         cable_breakout[0x8];
787 	u8         ext_ethernet_compliance_code[0x8];
788 	u8         ethernet_compliance_code[0x8];
789 
790 	u8         cable_type[0x4];
791 	u8         cable_vendor[0x4];
792 	u8         cable_length[0x8];
793 	u8         cable_identifier[0x8];
794 	u8         cable_power_class[0x8];
795 
796 	u8         reserved_at_40[0x8];
797 	u8         cable_rx_amp[0x8];
798 	u8         cable_rx_emphasis[0x8];
799 	u8         cable_tx_equalization[0x8];
800 
801 	u8         reserved_at_60[0x8];
802 	u8         cable_attenuation_12g[0x8];
803 	u8         cable_attenuation_7g[0x8];
804 	u8         cable_attenuation_5g[0x8];
805 
806 	u8         reserved_at_80[0x8];
807 	u8         rx_cdr_cap[0x4];
808 	u8         tx_cdr_cap[0x4];
809 	u8         reserved_at_90[0x4];
810 	u8         rx_cdr_state[0x4];
811 	u8         reserved_at_98[0x4];
812 	u8         tx_cdr_state[0x4];
813 
814 	u8         vendor_name[16][0x8];
815 
816 	u8         vendor_pn[16][0x8];
817 
818 	u8         vendor_rev[0x20];
819 
820 	u8         fw_version[0x20];
821 
822 	u8         vendor_sn[16][0x8];
823 
824 	u8         temperature[0x10];
825 	u8         voltage[0x10];
826 
827 	u8         rx_power_lane0[0x10];
828 	u8         rx_power_lane1[0x10];
829 
830 	u8         rx_power_lane2[0x10];
831 	u8         rx_power_lane3[0x10];
832 
833 	u8         reserved_at_2c0[0x40];
834 
835 	u8         tx_power_lane0[0x10];
836 	u8         tx_power_lane1[0x10];
837 
838 	u8         tx_power_lane2[0x10];
839 	u8         tx_power_lane3[0x10];
840 
841 	u8         reserved_at_340[0x40];
842 
843 	u8         tx_bias_lane0[0x10];
844 	u8         tx_bias_lane1[0x10];
845 
846 	u8         tx_bias_lane2[0x10];
847 	u8         tx_bias_lane3[0x10];
848 
849 	u8         reserved_at_3c0[0x40];
850 
851 	u8         temperature_high_th[0x10];
852 	u8         temperature_low_th[0x10];
853 
854 	u8         voltage_high_th[0x10];
855 	u8         voltage_low_th[0x10];
856 
857 	u8         rx_power_high_th[0x10];
858 	u8         rx_power_low_th[0x10];
859 
860 	u8         tx_power_high_th[0x10];
861 	u8         tx_power_low_th[0x10];
862 
863 	u8         tx_bias_high_th[0x10];
864 	u8         tx_bias_low_th[0x10];
865 
866 	u8         reserved_at_4a0[0x10];
867 	u8         wavelength[0x10];
868 
869 	u8         reserved_at_4c0[0x300];
870 };
871 
872 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
873 	u8         csum_cap[0x1];
874 	u8         vlan_cap[0x1];
875 	u8         lro_cap[0x1];
876 	u8         lro_psh_flag[0x1];
877 	u8         lro_time_stamp[0x1];
878 	u8         lro_max_msg_sz_mode[0x2];
879 	u8         wqe_vlan_insert[0x1];
880 	u8         self_lb_en_modifiable[0x1];
881 	u8         self_lb_mc[0x1];
882 	u8         self_lb_uc[0x1];
883 	u8         max_lso_cap[0x5];
884 	u8         multi_pkt_send_wqe[0x2];
885 	u8         wqe_inline_mode[0x2];
886 	u8         rss_ind_tbl_cap[0x4];
887 	u8	   reg_umr_sq[0x1];
888 	u8         scatter_fcs[0x1];
889 	u8	   enhanced_multi_pkt_send_wqe[0x1];
890 	u8         tunnel_lso_const_out_ip_id[0x1];
891 	u8         tunnel_lro_gre[0x1];
892 	u8         tunnel_lro_vxlan[0x1];
893 	u8         tunnel_statless_gre[0x1];
894 	u8         tunnel_stateless_vxlan[0x1];
895 
896 	u8         swp[0x1];
897 	u8         swp_csum[0x1];
898 	u8         swp_lso[0x1];
899 	u8         reserved_2[0x1b];
900 	u8         max_geneve_opt_len[0x1];
901 	u8         tunnel_stateless_geneve_rx[0x1];
902 
903 	u8         reserved_3[0x10];
904 	u8         lro_min_mss_size[0x10];
905 
906 	u8         reserved_4[0x120];
907 
908 	u8         lro_timer_supported_periods[4][0x20];
909 
910 	u8         reserved_5[0x600];
911 };
912 
913 enum {
914 	MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
915 	MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
916 	MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
917 };
918 
919 enum {
920 	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
921 	MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
922 	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
923 };
924 
925 struct mlx5_ifc_roce_cap_bits {
926 	u8         roce_apm[0x1];
927 	u8         rts2rts_primary_eth_prio[0x1];
928 	u8         roce_rx_allow_untagged[0x1];
929 	u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
930 	u8         reserved_at_4[0x1a];
931 	u8         qp_ts_format[0x2];
932 
933 	u8         reserved_1[0x60];
934 
935 	u8         reserved_2[0xc];
936 	u8         l3_type[0x4];
937 	u8         reserved_3[0x8];
938 	u8         roce_version[0x8];
939 
940 	u8         reserved_4[0x10];
941 	u8         r_roce_dest_udp_port[0x10];
942 
943 	u8         r_roce_max_src_udp_port[0x10];
944 	u8         r_roce_min_src_udp_port[0x10];
945 
946 	u8         reserved_5[0x10];
947 	u8         roce_address_table_size[0x10];
948 
949 	u8         reserved_6[0x700];
950 };
951 
952 enum {
953 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
954 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
955 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
956 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
957 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
958 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
959 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
960 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
961 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
962 };
963 
964 enum {
965 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
966 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
967 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
968 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
969 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
970 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
971 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
972 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
973 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
974 };
975 
976 struct mlx5_ifc_atomic_caps_bits {
977 	u8         reserved_0[0x40];
978 
979 	u8         atomic_req_8B_endianess_mode[0x2];
980 	u8         reserved_1[0x4];
981 	u8         supported_atomic_req_8B_endianess_mode_1[0x1];
982 
983 	u8         reserved_2[0x19];
984 
985 	u8         reserved_3[0x20];
986 
987 	u8         reserved_4[0x10];
988 	u8         atomic_operations[0x10];
989 
990 	u8         reserved_5[0x10];
991 	u8         atomic_size_qp[0x10];
992 
993 	u8         reserved_6[0x10];
994 	u8         atomic_size_dc[0x10];
995 
996 	u8         reserved_7[0x720];
997 };
998 
999 struct mlx5_ifc_odp_cap_bits {
1000 	u8         reserved_0[0x40];
1001 
1002 	u8         sig[0x1];
1003 	u8         reserved_1[0x1f];
1004 
1005 	u8         reserved_2[0x20];
1006 
1007 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1008 
1009 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1010 
1011 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1012 
1013 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1014 
1015 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1016 
1017 	u8         reserved_3[0x6e0];
1018 };
1019 
1020 enum {
1021 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1022 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1023 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1024 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1025 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1026 };
1027 
1028 enum {
1029 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1030 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1031 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1032 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1033 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1034 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1035 };
1036 
1037 enum {
1038 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1039 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1040 };
1041 
1042 enum {
1043 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1044 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1045 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1046 };
1047 
1048 enum {
1049 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1050 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1051 	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1052 };
1053 
1054 enum {
1055 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1056 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1057 	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1058 };
1059 
1060 struct mlx5_ifc_cmd_hca_cap_bits {
1061 	u8         reserved_0[0x80];
1062 
1063 	u8         log_max_srq_sz[0x8];
1064 	u8         log_max_qp_sz[0x8];
1065 	u8         reserved_1[0xb];
1066 	u8         log_max_qp[0x5];
1067 
1068 	u8         reserved_2[0xb];
1069 	u8         log_max_srq[0x5];
1070 	u8         reserved_3[0x10];
1071 
1072 	u8         reserved_4[0x8];
1073 	u8         log_max_cq_sz[0x8];
1074 	u8         relaxed_ordering_write_umr[0x1];
1075 	u8         relaxed_ordering_read_umr[0x1];
1076 	u8         reserved_5[0x9];
1077 	u8         log_max_cq[0x5];
1078 
1079 	u8         log_max_eq_sz[0x8];
1080 	u8         relaxed_ordering_write[0x1];
1081 	u8         relaxed_ordering_read[0x1];
1082 	u8         log_max_mkey[0x6];
1083 	u8         reserved_7[0xb];
1084 	u8         fast_teardown[0x1];
1085 	u8         log_max_eq[0x4];
1086 
1087 	u8         max_indirection[0x8];
1088 	u8         reserved_8[0x1];
1089 	u8         log_max_mrw_sz[0x7];
1090 	u8	   force_teardown[0x1];
1091 	u8         reserved_9[0x1];
1092 	u8         log_max_bsf_list_size[0x6];
1093 	u8         reserved_10[0x2];
1094 	u8         log_max_klm_list_size[0x6];
1095 
1096 	u8         reserved_11[0xa];
1097 	u8         log_max_ra_req_dc[0x6];
1098 	u8         reserved_12[0xa];
1099 	u8         log_max_ra_res_dc[0x6];
1100 
1101 	u8         reserved_13[0xa];
1102 	u8         log_max_ra_req_qp[0x6];
1103 	u8         reserved_14[0xa];
1104 	u8         log_max_ra_res_qp[0x6];
1105 
1106 	u8         pad_cap[0x1];
1107 	u8         cc_query_allowed[0x1];
1108 	u8         cc_modify_allowed[0x1];
1109 	u8         start_pad[0x1];
1110 	u8         cache_line_128byte[0x1];
1111 	u8         reserved_at_165[0xa];
1112 	u8         qcam_reg[0x1];
1113 	u8         gid_table_size[0x10];
1114 
1115 	u8         out_of_seq_cnt[0x1];
1116 	u8         vport_counters[0x1];
1117 	u8         retransmission_q_counters[0x1];
1118 	u8         debug[0x1];
1119 	u8         modify_rq_counters_set_id[0x1];
1120 	u8         rq_delay_drop[0x1];
1121 	u8         max_qp_cnt[0xa];
1122 	u8         pkey_table_size[0x10];
1123 
1124 	u8         vport_group_manager[0x1];
1125 	u8         vhca_group_manager[0x1];
1126 	u8         ib_virt[0x1];
1127 	u8         eth_virt[0x1];
1128 	u8         reserved_17[0x1];
1129 	u8         ets[0x1];
1130 	u8         nic_flow_table[0x1];
1131 	u8         eswitch_flow_table[0x1];
1132 	u8         reserved_18[0x1];
1133 	u8         mcam_reg[0x1];
1134 	u8         pcam_reg[0x1];
1135 	u8         local_ca_ack_delay[0x5];
1136 	u8         port_module_event[0x1];
1137 	u8         reserved_19[0x5];
1138 	u8         port_type[0x2];
1139 	u8         num_ports[0x8];
1140 
1141 	u8         snapshot[0x1];
1142 	u8         reserved_20[0x2];
1143 	u8         log_max_msg[0x5];
1144 	u8         reserved_21[0x4];
1145 	u8         max_tc[0x4];
1146 	u8         temp_warn_event[0x1];
1147 	u8         dcbx[0x1];
1148 	u8         general_notification_event[0x1];
1149 	u8         reserved_at_1d3[0x2];
1150 	u8         fpga[0x1];
1151 	u8         rol_s[0x1];
1152 	u8         rol_g[0x1];
1153 	u8         reserved_23[0x1];
1154 	u8         wol_s[0x1];
1155 	u8         wol_g[0x1];
1156 	u8         wol_a[0x1];
1157 	u8         wol_b[0x1];
1158 	u8         wol_m[0x1];
1159 	u8         wol_u[0x1];
1160 	u8         wol_p[0x1];
1161 
1162 	u8         stat_rate_support[0x10];
1163 	u8         reserved_24[0xc];
1164 	u8         cqe_version[0x4];
1165 
1166 	u8         compact_address_vector[0x1];
1167 	u8         striding_rq[0x1];
1168 	u8         reserved_25[0x1];
1169 	u8         ipoib_enhanced_offloads[0x1];
1170 	u8         ipoib_ipoib_offloads[0x1];
1171 	u8         reserved_26[0x8];
1172 	u8         dc_connect_qp[0x1];
1173 	u8         dc_cnak_trace[0x1];
1174 	u8         drain_sigerr[0x1];
1175 	u8         cmdif_checksum[0x2];
1176 	u8         sigerr_cqe[0x1];
1177 	u8         reserved_27[0x1];
1178 	u8         wq_signature[0x1];
1179 	u8         sctr_data_cqe[0x1];
1180 	u8         reserved_28[0x1];
1181 	u8         sho[0x1];
1182 	u8         tph[0x1];
1183 	u8         rf[0x1];
1184 	u8         dct[0x1];
1185 	u8         qos[0x1];
1186 	u8         eth_net_offloads[0x1];
1187 	u8         roce[0x1];
1188 	u8         atomic[0x1];
1189 	u8         reserved_30[0x1];
1190 
1191 	u8         cq_oi[0x1];
1192 	u8         cq_resize[0x1];
1193 	u8         cq_moderation[0x1];
1194 	u8         cq_period_mode_modify[0x1];
1195 	u8         cq_invalidate[0x1];
1196 	u8         reserved_at_225[0x1];
1197 	u8         cq_eq_remap[0x1];
1198 	u8         pg[0x1];
1199 	u8         block_lb_mc[0x1];
1200 	u8         exponential_backoff[0x1];
1201 	u8         scqe_break_moderation[0x1];
1202 	u8         cq_period_start_from_cqe[0x1];
1203 	u8         cd[0x1];
1204 	u8         atm[0x1];
1205 	u8         apm[0x1];
1206 	u8	   imaicl[0x1];
1207 	u8         reserved_32[0x6];
1208 	u8         qkv[0x1];
1209 	u8         pkv[0x1];
1210 	u8	   set_deth_sqpn[0x1];
1211 	u8         reserved_33[0x3];
1212 	u8         xrc[0x1];
1213 	u8         ud[0x1];
1214 	u8         uc[0x1];
1215 	u8         rc[0x1];
1216 
1217 	u8         uar_4k[0x1];
1218 	u8         reserved_at_241[0x9];
1219 	u8         uar_sz[0x6];
1220 	u8         reserved_35[0x8];
1221 	u8         log_pg_sz[0x8];
1222 
1223 	u8         bf[0x1];
1224 	u8         driver_version[0x1];
1225 	u8         pad_tx_eth_packet[0x1];
1226 	u8         reserved_36[0x8];
1227 	u8         log_bf_reg_size[0x5];
1228 	u8         reserved_37[0x10];
1229 
1230 	u8         num_of_diagnostic_counters[0x10];
1231 	u8         max_wqe_sz_sq[0x10];
1232 
1233 	u8         reserved_38[0x10];
1234 	u8         max_wqe_sz_rq[0x10];
1235 
1236 	u8         reserved_39[0x10];
1237 	u8         max_wqe_sz_sq_dc[0x10];
1238 
1239 	u8         reserved_40[0x7];
1240 	u8         max_qp_mcg[0x19];
1241 
1242 	u8         reserved_41[0x18];
1243 	u8         log_max_mcg[0x8];
1244 
1245 	u8         reserved_42[0x3];
1246 	u8         log_max_transport_domain[0x5];
1247 	u8         reserved_43[0x3];
1248 	u8         log_max_pd[0x5];
1249 	u8         reserved_44[0xb];
1250 	u8         log_max_xrcd[0x5];
1251 
1252 	u8         nic_receive_steering_discard[0x1];
1253 	u8	   reserved_45[0x7];
1254 	u8         log_max_flow_counter_bulk[0x8];
1255 	u8         max_flow_counter[0x10];
1256 
1257 	u8         reserved_46[0x3];
1258 	u8         log_max_rq[0x5];
1259 	u8         reserved_47[0x3];
1260 	u8         log_max_sq[0x5];
1261 	u8         reserved_48[0x3];
1262 	u8         log_max_tir[0x5];
1263 	u8         reserved_49[0x3];
1264 	u8         log_max_tis[0x5];
1265 
1266 	u8         basic_cyclic_rcv_wqe[0x1];
1267 	u8         reserved_50[0x2];
1268 	u8         log_max_rmp[0x5];
1269 	u8         reserved_51[0x3];
1270 	u8         log_max_rqt[0x5];
1271 	u8         reserved_52[0x3];
1272 	u8         log_max_rqt_size[0x5];
1273 	u8         reserved_53[0x3];
1274 	u8         log_max_tis_per_sq[0x5];
1275 
1276 	u8         reserved_54[0x3];
1277 	u8         log_max_stride_sz_rq[0x5];
1278 	u8         reserved_55[0x3];
1279 	u8         log_min_stride_sz_rq[0x5];
1280 	u8         reserved_56[0x3];
1281 	u8         log_max_stride_sz_sq[0x5];
1282 	u8         reserved_57[0x3];
1283 	u8         log_min_stride_sz_sq[0x5];
1284 
1285 	u8         reserved_58[0x1b];
1286 	u8         log_max_wq_sz[0x5];
1287 
1288 	u8         nic_vport_change_event[0x1];
1289 	u8         disable_local_lb_uc[0x1];
1290 	u8         disable_local_lb_mc[0x1];
1291 	u8         reserved_59[0x8];
1292 	u8         log_max_vlan_list[0x5];
1293 	u8         reserved_60[0x3];
1294 	u8         log_max_current_mc_list[0x5];
1295 	u8         reserved_61[0x3];
1296 	u8         log_max_current_uc_list[0x5];
1297 
1298 	u8         general_obj_types[0x40];
1299 
1300 	u8         sq_ts_format[0x2];
1301 	u8         rq_ts_format[0x2];
1302 	u8         reserved_at_444[0x4];
1303 	u8         create_qp_start_hint[0x18];
1304 
1305 	u8         reserved_at_460[0x3];
1306 	u8         log_max_uctx[0x5];
1307 	u8         reserved_at_468[0x3];
1308 	u8         log_max_umem[0x5];
1309 	u8         max_num_eqs[0x10];
1310 
1311 	u8         reserved_at_480[0x1];
1312 	u8         tls_tx[0x1];
1313 	u8         reserved_at_482[0x1];
1314 	u8         log_max_l2_table[0x5];
1315 	u8         reserved_64[0x8];
1316 	u8         log_uar_page_sz[0x10];
1317 
1318 	u8         reserved_65[0x20];
1319 
1320 	u8         device_frequency_mhz[0x20];
1321 
1322 	u8         device_frequency_khz[0x20];
1323 
1324 	u8         reserved_at_500[0x20];
1325 	u8	   num_of_uars_per_page[0x20];
1326 	u8         reserved_at_540[0x40];
1327 
1328 	u8         log_max_atomic_size_qp[0x8];
1329 	u8         reserved_67[0x10];
1330 	u8         log_max_atomic_size_dc[0x8];
1331 
1332 	u8         reserved_at_5a0[0x13];
1333 	u8         log_max_dek[0x5];
1334 	u8         reserved_at_5b8[0x4];
1335 	u8         mini_cqe_resp_stride_index[0x1];
1336 	u8         cqe_128_always[0x1];
1337 	u8         cqe_compression_128b[0x1];
1338 
1339 	u8         cqe_compression[0x1];
1340 
1341 	u8         cqe_compression_timeout[0x10];
1342 	u8         cqe_compression_max_num[0x10];
1343 
1344 	u8         reserved_69[0x220];
1345 };
1346 
1347 enum mlx5_flow_destination_type {
1348 	MLX5_FLOW_DESTINATION_TYPE_VPORT	= 0x0,
1349 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE	= 0x1,
1350 	MLX5_FLOW_DESTINATION_TYPE_TIR		= 0x2,
1351 };
1352 
1353 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1354 	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1355 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1356 	u8         reserved_0[0x40];
1357 };
1358 
1359 struct mlx5_ifc_fte_match_param_bits {
1360 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1361 
1362 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1363 
1364 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1365 
1366 	u8         reserved_0[0xa00];
1367 };
1368 
1369 enum {
1370 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1371 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1372 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1373 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1374 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1375 };
1376 
1377 struct mlx5_ifc_rx_hash_field_select_bits {
1378 	u8         l3_prot_type[0x1];
1379 	u8         l4_prot_type[0x1];
1380 	u8         selected_fields[0x1e];
1381 };
1382 
1383 struct mlx5_ifc_tls_capabilities_bits {
1384 	u8         tls_1_2_aes_gcm_128[0x1];
1385 	u8         tls_1_3_aes_gcm_128[0x1];
1386 	u8         tls_1_2_aes_gcm_256[0x1];
1387 	u8         tls_1_3_aes_gcm_256[0x1];
1388 	u8         reserved_at_4[0x1c];
1389 
1390 	u8         reserved_at_20[0x7e0];
1391 };
1392 
1393 enum {
1394 	MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
1395 	MLX5_WQ_TYPE_CYCLIC                      = 0x1,
1396 	MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
1397 	MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
1398 };
1399 
1400 enum rq_type {
1401 	RQ_TYPE_NONE,
1402 	RQ_TYPE_STRIDE,
1403 };
1404 
1405 enum {
1406 	MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
1407 	MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
1408 };
1409 
1410 struct mlx5_ifc_wq_bits {
1411 	u8         wq_type[0x4];
1412 	u8         wq_signature[0x1];
1413 	u8         end_padding_mode[0x2];
1414 	u8         cd_slave[0x1];
1415 	u8         reserved_0[0x18];
1416 
1417 	u8         hds_skip_first_sge[0x1];
1418 	u8         log2_hds_buf_size[0x3];
1419 	u8         reserved_1[0x7];
1420 	u8         page_offset[0x5];
1421 	u8         lwm[0x10];
1422 
1423 	u8         reserved_2[0x8];
1424 	u8         pd[0x18];
1425 
1426 	u8         reserved_3[0x8];
1427 	u8         uar_page[0x18];
1428 
1429 	u8         dbr_addr[0x40];
1430 
1431 	u8         hw_counter[0x20];
1432 
1433 	u8         sw_counter[0x20];
1434 
1435 	u8         reserved_4[0xc];
1436 	u8         log_wq_stride[0x4];
1437 	u8         reserved_5[0x3];
1438 	u8         log_wq_pg_sz[0x5];
1439 	u8         reserved_6[0x3];
1440 	u8         log_wq_sz[0x5];
1441 
1442 	u8         reserved_7[0x15];
1443 	u8         single_wqe_log_num_of_strides[0x3];
1444 	u8         two_byte_shift_en[0x1];
1445 	u8         reserved_8[0x4];
1446 	u8         single_stride_log_num_of_bytes[0x3];
1447 
1448 	u8         reserved_9[0x4c0];
1449 
1450 	struct mlx5_ifc_cmd_pas_bits pas[0];
1451 };
1452 
1453 struct mlx5_ifc_rq_num_bits {
1454 	u8         reserved_0[0x8];
1455 	u8         rq_num[0x18];
1456 };
1457 
1458 struct mlx5_ifc_mac_address_layout_bits {
1459 	u8         reserved_0[0x10];
1460 	u8         mac_addr_47_32[0x10];
1461 
1462 	u8         mac_addr_31_0[0x20];
1463 };
1464 
1465 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1466 	u8         reserved_0[0xa0];
1467 
1468 	u8         min_time_between_cnps[0x20];
1469 
1470 	u8         reserved_1[0x12];
1471 	u8         cnp_dscp[0x6];
1472 	u8         reserved_2[0x4];
1473 	u8         cnp_prio_mode[0x1];
1474 	u8         cnp_802p_prio[0x3];
1475 
1476 	u8         reserved_3[0x720];
1477 };
1478 
1479 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1480 	u8         reserved_0[0x60];
1481 
1482 	u8         reserved_1[0x4];
1483 	u8         clamp_tgt_rate[0x1];
1484 	u8         reserved_2[0x3];
1485 	u8         clamp_tgt_rate_after_time_inc[0x1];
1486 	u8         reserved_3[0x17];
1487 
1488 	u8         reserved_4[0x20];
1489 
1490 	u8         rpg_time_reset[0x20];
1491 
1492 	u8         rpg_byte_reset[0x20];
1493 
1494 	u8         rpg_threshold[0x20];
1495 
1496 	u8         rpg_max_rate[0x20];
1497 
1498 	u8         rpg_ai_rate[0x20];
1499 
1500 	u8         rpg_hai_rate[0x20];
1501 
1502 	u8         rpg_gd[0x20];
1503 
1504 	u8         rpg_min_dec_fac[0x20];
1505 
1506 	u8         rpg_min_rate[0x20];
1507 
1508 	u8         reserved_5[0xe0];
1509 
1510 	u8         rate_to_set_on_first_cnp[0x20];
1511 
1512 	u8         dce_tcp_g[0x20];
1513 
1514 	u8         dce_tcp_rtt[0x20];
1515 
1516 	u8         rate_reduce_monitor_period[0x20];
1517 
1518 	u8         reserved_6[0x20];
1519 
1520 	u8         initial_alpha_value[0x20];
1521 
1522 	u8         reserved_7[0x4a0];
1523 };
1524 
1525 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1526 	u8         reserved_0[0x80];
1527 
1528 	u8         rppp_max_rps[0x20];
1529 
1530 	u8         rpg_time_reset[0x20];
1531 
1532 	u8         rpg_byte_reset[0x20];
1533 
1534 	u8         rpg_threshold[0x20];
1535 
1536 	u8         rpg_max_rate[0x20];
1537 
1538 	u8         rpg_ai_rate[0x20];
1539 
1540 	u8         rpg_hai_rate[0x20];
1541 
1542 	u8         rpg_gd[0x20];
1543 
1544 	u8         rpg_min_dec_fac[0x20];
1545 
1546 	u8         rpg_min_rate[0x20];
1547 
1548 	u8         reserved_1[0x640];
1549 };
1550 
1551 enum {
1552 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1553 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1554 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1555 };
1556 
1557 struct mlx5_ifc_resize_field_select_bits {
1558 	u8         resize_field_select[0x20];
1559 };
1560 
1561 enum {
1562 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1563 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1564 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1565 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1566 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
1567 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
1568 };
1569 
1570 struct mlx5_ifc_modify_field_select_bits {
1571 	u8         modify_field_select[0x20];
1572 };
1573 
1574 struct mlx5_ifc_field_select_r_roce_np_bits {
1575 	u8         field_select_r_roce_np[0x20];
1576 };
1577 
1578 enum {
1579 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1580 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1581 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1582 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1583 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1584 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1585 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1586 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1587 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1588 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1589 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1590 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1591 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1592 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1593 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1594 };
1595 
1596 struct mlx5_ifc_field_select_r_roce_rp_bits {
1597 	u8         field_select_r_roce_rp[0x20];
1598 };
1599 
1600 enum {
1601 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1602 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1603 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1604 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1605 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1606 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1607 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1608 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1609 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1610 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1611 };
1612 
1613 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1614 	u8         field_select_8021qaurp[0x20];
1615 };
1616 
1617 struct mlx5_ifc_pptb_reg_bits {
1618 	u8         reserved_at_0[0x2];
1619 	u8         mm[0x2];
1620 	u8         reserved_at_4[0x4];
1621 	u8         local_port[0x8];
1622 	u8         reserved_at_10[0x6];
1623 	u8         cm[0x1];
1624 	u8         um[0x1];
1625 	u8         pm[0x8];
1626 
1627 	u8         prio_x_buff[0x20];
1628 
1629 	u8         pm_msb[0x8];
1630 	u8         reserved_at_48[0x10];
1631 	u8         ctrl_buff[0x4];
1632 	u8         untagged_buff[0x4];
1633 };
1634 
1635 struct mlx5_ifc_dcbx_app_reg_bits {
1636 	u8         reserved_0[0x8];
1637 	u8         port_number[0x8];
1638 	u8         reserved_1[0x10];
1639 
1640 	u8         reserved_2[0x1a];
1641 	u8         num_app_prio[0x6];
1642 
1643 	u8         reserved_3[0x40];
1644 
1645 	struct mlx5_ifc_application_prio_entry_bits app_prio[0];
1646 };
1647 
1648 struct mlx5_ifc_dcbx_param_reg_bits {
1649 	u8         dcbx_cee_cap[0x1];
1650 	u8         dcbx_ieee_cap[0x1];
1651 	u8         dcbx_standby_cap[0x1];
1652 	u8         reserved_0[0x5];
1653 	u8         port_number[0x8];
1654 	u8         reserved_1[0xa];
1655 	u8         max_application_table_size[0x6];
1656 
1657 	u8         reserved_2[0x15];
1658 	u8         version_oper[0x3];
1659 	u8         reserved_3[0x5];
1660 	u8         version_admin[0x3];
1661 
1662 	u8         willing_admin[0x1];
1663 	u8         reserved_4[0x3];
1664 	u8         pfc_cap_oper[0x4];
1665 	u8         reserved_5[0x4];
1666 	u8         pfc_cap_admin[0x4];
1667 	u8         reserved_6[0x4];
1668 	u8         num_of_tc_oper[0x4];
1669 	u8         reserved_7[0x4];
1670 	u8         num_of_tc_admin[0x4];
1671 
1672 	u8         remote_willing[0x1];
1673 	u8         reserved_8[0x3];
1674 	u8         remote_pfc_cap[0x4];
1675 	u8         reserved_9[0x14];
1676 	u8         remote_num_of_tc[0x4];
1677 
1678 	u8         reserved_10[0x18];
1679 	u8         error[0x8];
1680 
1681 	u8         reserved_11[0x160];
1682 };
1683 
1684 struct mlx5_ifc_qhll_bits {
1685 	u8         reserved_at_0[0x8];
1686 	u8         local_port[0x8];
1687 	u8         reserved_at_10[0x10];
1688 
1689 	u8         reserved_at_20[0x1b];
1690 	u8         hll_time[0x5];
1691 
1692 	u8         stall_en[0x1];
1693 	u8         reserved_at_41[0x1c];
1694 	u8         stall_cnt[0x3];
1695 };
1696 
1697 struct mlx5_ifc_qetcr_reg_bits {
1698 	u8         operation_type[0x2];
1699 	u8         cap_local_admin[0x1];
1700 	u8         cap_remote_admin[0x1];
1701 	u8         reserved_0[0x4];
1702 	u8         port_number[0x8];
1703 	u8         reserved_1[0x10];
1704 
1705 	u8         reserved_2[0x20];
1706 
1707 	u8         tc[8][0x40];
1708 
1709 	u8         global_configuration[0x40];
1710 };
1711 
1712 struct mlx5_ifc_nodnic_ring_config_reg_bits {
1713 	u8         queue_address_63_32[0x20];
1714 
1715 	u8         queue_address_31_12[0x14];
1716 	u8         reserved_0[0x6];
1717 	u8         log_size[0x6];
1718 
1719 	struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1720 
1721 	u8         reserved_1[0x8];
1722 	u8         queue_number[0x18];
1723 
1724 	u8         q_key[0x20];
1725 
1726 	u8         reserved_2[0x10];
1727 	u8         pkey_index[0x10];
1728 
1729 	u8         reserved_3[0x40];
1730 };
1731 
1732 struct mlx5_ifc_nodnic_cq_arming_word_bits {
1733 	u8         reserved_0[0x8];
1734 	u8         cq_ci[0x10];
1735 	u8         reserved_1[0x8];
1736 };
1737 
1738 enum {
1739 	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1740 	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1741 };
1742 
1743 enum {
1744 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1745 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1746 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1747 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1748 };
1749 
1750 struct mlx5_ifc_nodnic_event_word_bits {
1751 	u8         driver_reset_needed[0x1];
1752 	u8         port_management_change_event[0x1];
1753 	u8         reserved_0[0x19];
1754 	u8         link_type[0x1];
1755 	u8         port_state[0x4];
1756 };
1757 
1758 struct mlx5_ifc_nic_vport_change_event_bits {
1759 	u8         reserved_0[0x10];
1760 	u8         vport_num[0x10];
1761 
1762 	u8         reserved_1[0xc0];
1763 };
1764 
1765 struct mlx5_ifc_pages_req_event_bits {
1766 	u8         reserved_0[0x10];
1767 	u8         function_id[0x10];
1768 
1769 	u8         num_pages[0x20];
1770 
1771 	u8         reserved_1[0xa0];
1772 };
1773 
1774 struct mlx5_ifc_cmd_inter_comp_event_bits {
1775 	u8         command_completion_vector[0x20];
1776 
1777 	u8         reserved_0[0xc0];
1778 };
1779 
1780 struct mlx5_ifc_stall_vl_event_bits {
1781 	u8         reserved_0[0x18];
1782 	u8         port_num[0x1];
1783 	u8         reserved_1[0x3];
1784 	u8         vl[0x4];
1785 
1786 	u8         reserved_2[0xa0];
1787 };
1788 
1789 struct mlx5_ifc_db_bf_congestion_event_bits {
1790 	u8         event_subtype[0x8];
1791 	u8         reserved_0[0x8];
1792 	u8         congestion_level[0x8];
1793 	u8         reserved_1[0x8];
1794 
1795 	u8         reserved_2[0xa0];
1796 };
1797 
1798 struct mlx5_ifc_gpio_event_bits {
1799 	u8         reserved_0[0x60];
1800 
1801 	u8         gpio_event_hi[0x20];
1802 
1803 	u8         gpio_event_lo[0x20];
1804 
1805 	u8         reserved_1[0x40];
1806 };
1807 
1808 struct mlx5_ifc_port_state_change_event_bits {
1809 	u8         reserved_0[0x40];
1810 
1811 	u8         port_num[0x4];
1812 	u8         reserved_1[0x1c];
1813 
1814 	u8         reserved_2[0x80];
1815 };
1816 
1817 struct mlx5_ifc_dropped_packet_logged_bits {
1818 	u8         reserved_0[0xe0];
1819 };
1820 
1821 enum {
1822 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1823 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1824 };
1825 
1826 struct mlx5_ifc_cq_error_bits {
1827 	u8         reserved_0[0x8];
1828 	u8         cqn[0x18];
1829 
1830 	u8         reserved_1[0x20];
1831 
1832 	u8         reserved_2[0x18];
1833 	u8         syndrome[0x8];
1834 
1835 	u8         reserved_3[0x80];
1836 };
1837 
1838 struct mlx5_ifc_rdma_page_fault_event_bits {
1839 	u8         bytes_commited[0x20];
1840 
1841 	u8         r_key[0x20];
1842 
1843 	u8         reserved_0[0x10];
1844 	u8         packet_len[0x10];
1845 
1846 	u8         rdma_op_len[0x20];
1847 
1848 	u8         rdma_va[0x40];
1849 
1850 	u8         reserved_1[0x5];
1851 	u8         rdma[0x1];
1852 	u8         write[0x1];
1853 	u8         requestor[0x1];
1854 	u8         qp_number[0x18];
1855 };
1856 
1857 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1858 	u8         bytes_committed[0x20];
1859 
1860 	u8         reserved_0[0x10];
1861 	u8         wqe_index[0x10];
1862 
1863 	u8         reserved_1[0x10];
1864 	u8         len[0x10];
1865 
1866 	u8         reserved_2[0x60];
1867 
1868 	u8         reserved_3[0x5];
1869 	u8         rdma[0x1];
1870 	u8         write_read[0x1];
1871 	u8         requestor[0x1];
1872 	u8         qpn[0x18];
1873 };
1874 
1875 enum {
1876 	MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1877 	MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1878 	MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1879 };
1880 
1881 struct mlx5_ifc_qp_events_bits {
1882 	u8         reserved_0[0xa0];
1883 
1884 	u8         type[0x8];
1885 	u8         reserved_1[0x18];
1886 
1887 	u8         reserved_2[0x8];
1888 	u8         qpn_rqn_sqn[0x18];
1889 };
1890 
1891 struct mlx5_ifc_dct_events_bits {
1892 	u8         reserved_0[0xc0];
1893 
1894 	u8         reserved_1[0x8];
1895 	u8         dct_number[0x18];
1896 };
1897 
1898 struct mlx5_ifc_comp_event_bits {
1899 	u8         reserved_0[0xc0];
1900 
1901 	u8         reserved_1[0x8];
1902 	u8         cq_number[0x18];
1903 };
1904 
1905 struct mlx5_ifc_fw_version_bits {
1906 	u8         major[0x10];
1907 	u8         reserved_0[0x10];
1908 
1909 	u8         minor[0x10];
1910 	u8         subminor[0x10];
1911 
1912 	u8         second[0x8];
1913 	u8         minute[0x8];
1914 	u8         hour[0x8];
1915 	u8         reserved_1[0x8];
1916 
1917 	u8         year[0x10];
1918 	u8         month[0x8];
1919 	u8         day[0x8];
1920 };
1921 
1922 enum {
1923 	MLX5_QPC_STATE_RST        = 0x0,
1924 	MLX5_QPC_STATE_INIT       = 0x1,
1925 	MLX5_QPC_STATE_RTR        = 0x2,
1926 	MLX5_QPC_STATE_RTS        = 0x3,
1927 	MLX5_QPC_STATE_SQER       = 0x4,
1928 	MLX5_QPC_STATE_SQD        = 0x5,
1929 	MLX5_QPC_STATE_ERR        = 0x6,
1930 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
1931 };
1932 
1933 enum {
1934 	MLX5_QPC_ST_RC            = 0x0,
1935 	MLX5_QPC_ST_UC            = 0x1,
1936 	MLX5_QPC_ST_UD            = 0x2,
1937 	MLX5_QPC_ST_XRC           = 0x3,
1938 	MLX5_QPC_ST_DCI           = 0x5,
1939 	MLX5_QPC_ST_QP0           = 0x7,
1940 	MLX5_QPC_ST_QP1           = 0x8,
1941 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1942 	MLX5_QPC_ST_REG_UMR       = 0xc,
1943 };
1944 
1945 enum {
1946 	MLX5_QP_PM_ARMED            = 0x0,
1947 	MLX5_QP_PM_REARM            = 0x1,
1948 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1949 	MLX5_QP_PM_MIGRATED         = 0x3,
1950 };
1951 
1952 enum {
1953 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1954 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1955 };
1956 
1957 enum {
1958 	MLX5_QPC_MTU_256_BYTES        = 0x1,
1959 	MLX5_QPC_MTU_512_BYTES        = 0x2,
1960 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
1961 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
1962 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
1963 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1964 };
1965 
1966 enum {
1967 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1968 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1969 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1970 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1971 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1972 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1973 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1974 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1975 };
1976 
1977 enum {
1978 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1979 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1980 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1981 };
1982 
1983 enum {
1984 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
1985 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1986 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1987 };
1988 
1989 enum {
1990 	MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1991 	MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
1992 	MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
1993 };
1994 
1995 struct mlx5_ifc_qpc_bits {
1996 	u8         state[0x4];
1997 	u8         lag_tx_port_affinity[0x4];
1998 	u8         st[0x8];
1999 	u8         reserved_1[0x3];
2000 	u8         pm_state[0x2];
2001 	u8         reserved_2[0x7];
2002 	u8         end_padding_mode[0x2];
2003 	u8         reserved_3[0x2];
2004 
2005 	u8         wq_signature[0x1];
2006 	u8         block_lb_mc[0x1];
2007 	u8         atomic_like_write_en[0x1];
2008 	u8         latency_sensitive[0x1];
2009 	u8         reserved_4[0x1];
2010 	u8         drain_sigerr[0x1];
2011 	u8         reserved_5[0x2];
2012 	u8         pd[0x18];
2013 
2014 	u8         mtu[0x3];
2015 	u8         log_msg_max[0x5];
2016 	u8         reserved_6[0x1];
2017 	u8         log_rq_size[0x4];
2018 	u8         log_rq_stride[0x3];
2019 	u8         no_sq[0x1];
2020 	u8         log_sq_size[0x4];
2021 	u8         reserved_at_55[0x3];
2022 	u8         ts_format[0x2];
2023 	u8         reserved_at_5a[0x1];
2024 	u8         rlky[0x1];
2025 	u8         ulp_stateless_offload_mode[0x4];
2026 
2027 	u8         counter_set_id[0x8];
2028 	u8         uar_page[0x18];
2029 
2030 	u8         reserved_8[0x8];
2031 	u8         user_index[0x18];
2032 
2033 	u8         reserved_9[0x3];
2034 	u8         log_page_size[0x5];
2035 	u8         remote_qpn[0x18];
2036 
2037 	struct mlx5_ifc_ads_bits primary_address_path;
2038 
2039 	struct mlx5_ifc_ads_bits secondary_address_path;
2040 
2041 	u8         log_ack_req_freq[0x4];
2042 	u8         reserved_10[0x4];
2043 	u8         log_sra_max[0x3];
2044 	u8         reserved_11[0x2];
2045 	u8         retry_count[0x3];
2046 	u8         rnr_retry[0x3];
2047 	u8         reserved_12[0x1];
2048 	u8         fre[0x1];
2049 	u8         cur_rnr_retry[0x3];
2050 	u8         cur_retry_count[0x3];
2051 	u8         reserved_13[0x5];
2052 
2053 	u8         reserved_14[0x20];
2054 
2055 	u8         reserved_15[0x8];
2056 	u8         next_send_psn[0x18];
2057 
2058 	u8         reserved_16[0x8];
2059 	u8         cqn_snd[0x18];
2060 
2061 	u8         reserved_at_400[0x8];
2062 
2063 	u8         deth_sqpn[0x18];
2064 	u8         reserved_17[0x20];
2065 
2066 	u8         reserved_18[0x8];
2067 	u8         last_acked_psn[0x18];
2068 
2069 	u8         reserved_19[0x8];
2070 	u8         ssn[0x18];
2071 
2072 	u8         reserved_20[0x8];
2073 	u8         log_rra_max[0x3];
2074 	u8         reserved_21[0x1];
2075 	u8         atomic_mode[0x4];
2076 	u8         rre[0x1];
2077 	u8         rwe[0x1];
2078 	u8         rae[0x1];
2079 	u8         reserved_22[0x1];
2080 	u8         page_offset[0x6];
2081 	u8         reserved_23[0x3];
2082 	u8         cd_slave_receive[0x1];
2083 	u8         cd_slave_send[0x1];
2084 	u8         cd_master[0x1];
2085 
2086 	u8         reserved_24[0x3];
2087 	u8         min_rnr_nak[0x5];
2088 	u8         next_rcv_psn[0x18];
2089 
2090 	u8         reserved_25[0x8];
2091 	u8         xrcd[0x18];
2092 
2093 	u8         reserved_26[0x8];
2094 	u8         cqn_rcv[0x18];
2095 
2096 	u8         dbr_addr[0x40];
2097 
2098 	u8         q_key[0x20];
2099 
2100 	u8         reserved_27[0x5];
2101 	u8         rq_type[0x3];
2102 	u8         srqn_rmpn[0x18];
2103 
2104 	u8         reserved_28[0x8];
2105 	u8         rmsn[0x18];
2106 
2107 	u8         hw_sq_wqebb_counter[0x10];
2108 	u8         sw_sq_wqebb_counter[0x10];
2109 
2110 	u8         hw_rq_counter[0x20];
2111 
2112 	u8         sw_rq_counter[0x20];
2113 
2114 	u8         reserved_29[0x20];
2115 
2116 	u8         reserved_30[0xf];
2117 	u8         cgs[0x1];
2118 	u8         cs_req[0x8];
2119 	u8         cs_res[0x8];
2120 
2121 	u8         dc_access_key[0x40];
2122 
2123 	u8         rdma_active[0x1];
2124 	u8         comm_est[0x1];
2125 	u8         suspended[0x1];
2126 	u8         reserved_31[0x5];
2127 	u8         send_msg_psn[0x18];
2128 
2129 	u8         reserved_32[0x8];
2130 	u8         rcv_msg_psn[0x18];
2131 
2132 	u8         rdma_va[0x40];
2133 
2134 	u8         rdma_key[0x20];
2135 
2136 	u8         reserved_33[0x20];
2137 };
2138 
2139 struct mlx5_ifc_roce_addr_layout_bits {
2140 	u8         source_l3_address[16][0x8];
2141 
2142 	u8         reserved_0[0x3];
2143 	u8         vlan_valid[0x1];
2144 	u8         vlan_id[0xc];
2145 	u8         source_mac_47_32[0x10];
2146 
2147 	u8         source_mac_31_0[0x20];
2148 
2149 	u8         reserved_1[0x14];
2150 	u8         roce_l3_type[0x4];
2151 	u8         roce_version[0x8];
2152 
2153 	u8         reserved_2[0x20];
2154 };
2155 
2156 struct mlx5_ifc_rdbc_bits {
2157 	u8         reserved_0[0x1c];
2158 	u8         type[0x4];
2159 
2160 	u8         reserved_1[0x20];
2161 
2162 	u8         reserved_2[0x8];
2163 	u8         psn[0x18];
2164 
2165 	u8         rkey[0x20];
2166 
2167 	u8         address[0x40];
2168 
2169 	u8         byte_count[0x20];
2170 
2171 	u8         reserved_3[0x20];
2172 
2173 	u8         atomic_resp[32][0x8];
2174 };
2175 
2176 enum {
2177 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2178 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2179 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2180 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2181 };
2182 
2183 struct mlx5_ifc_flow_context_bits {
2184 	u8         reserved_0[0x20];
2185 
2186 	u8         group_id[0x20];
2187 
2188 	u8         reserved_1[0x8];
2189 	u8         flow_tag[0x18];
2190 
2191 	u8         reserved_2[0x10];
2192 	u8         action[0x10];
2193 
2194 	u8         reserved_3[0x8];
2195 	u8         destination_list_size[0x18];
2196 
2197 	u8         reserved_4[0x8];
2198 	u8         flow_counter_list_size[0x18];
2199 
2200 	u8         reserved_5[0x140];
2201 
2202 	struct mlx5_ifc_fte_match_param_bits match_value;
2203 
2204 	u8         reserved_6[0x600];
2205 
2206 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2207 };
2208 
2209 enum {
2210 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2211 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2212 };
2213 
2214 struct mlx5_ifc_xrc_srqc_bits {
2215 	u8         state[0x4];
2216 	u8         log_xrc_srq_size[0x4];
2217 	u8         reserved_0[0x18];
2218 
2219 	u8         wq_signature[0x1];
2220 	u8         cont_srq[0x1];
2221 	u8         reserved_1[0x1];
2222 	u8         rlky[0x1];
2223 	u8         basic_cyclic_rcv_wqe[0x1];
2224 	u8         log_rq_stride[0x3];
2225 	u8         xrcd[0x18];
2226 
2227 	u8         page_offset[0x6];
2228 	u8         reserved_2[0x2];
2229 	u8         cqn[0x18];
2230 
2231 	u8         reserved_3[0x20];
2232 
2233 	u8         reserved_4[0x2];
2234 	u8         log_page_size[0x6];
2235 	u8         user_index[0x18];
2236 
2237 	u8         reserved_5[0x20];
2238 
2239 	u8         reserved_6[0x8];
2240 	u8         pd[0x18];
2241 
2242 	u8         lwm[0x10];
2243 	u8         wqe_cnt[0x10];
2244 
2245 	u8         reserved_7[0x40];
2246 
2247 	u8         db_record_addr_h[0x20];
2248 
2249 	u8         db_record_addr_l[0x1e];
2250 	u8         reserved_8[0x2];
2251 
2252 	u8         reserved_9[0x80];
2253 };
2254 
2255 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2256 	u8         counter_error_queues[0x20];
2257 
2258 	u8         total_error_queues[0x20];
2259 
2260 	u8         send_queue_priority_update_flow[0x20];
2261 
2262 	u8         reserved_at_60[0x20];
2263 
2264 	u8         nic_receive_steering_discard[0x40];
2265 
2266 	u8         receive_discard_vport_down[0x40];
2267 
2268 	u8         transmit_discard_vport_down[0x40];
2269 
2270 	u8         reserved_at_140[0xec0];
2271 };
2272 
2273 struct mlx5_ifc_traffic_counter_bits {
2274 	u8         packets[0x40];
2275 
2276 	u8         octets[0x40];
2277 };
2278 
2279 struct mlx5_ifc_tisc_bits {
2280 	u8         strict_lag_tx_port_affinity[0x1];
2281 	u8         tls_en[0x1];
2282 	u8         reserved_at_2[0x2];
2283 	u8         lag_tx_port_affinity[0x04];
2284 
2285 	u8         reserved_at_8[0x4];
2286 	u8         prio[0x4];
2287 	u8         reserved_1[0x10];
2288 
2289 	u8         reserved_2[0x100];
2290 
2291 	u8         reserved_3[0x8];
2292 	u8         transport_domain[0x18];
2293 
2294 	u8         reserved_4[0x8];
2295 	u8         underlay_qpn[0x18];
2296 
2297 	u8         reserved_5[0x8];
2298 	u8         pd[0x18];
2299 
2300 	u8         reserved_6[0x380];
2301 };
2302 
2303 enum {
2304 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2305 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2306 };
2307 
2308 enum {
2309 	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2310 	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2311 };
2312 
2313 enum {
2314 	MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
2315 	MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
2316 	MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
2317 };
2318 
2319 enum {
2320 	MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
2321 	MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
2322 };
2323 
2324 struct mlx5_ifc_tirc_bits {
2325 	u8         reserved_0[0x20];
2326 
2327 	u8         disp_type[0x4];
2328 	u8         tls_en[0x1];
2329 	u8         reserved_at_25[0x1b];
2330 
2331 	u8         reserved_2[0x40];
2332 
2333 	u8         reserved_3[0x4];
2334 	u8         lro_timeout_period_usecs[0x10];
2335 	u8         lro_enable_mask[0x4];
2336 	u8         lro_max_msg_sz[0x8];
2337 
2338 	u8         reserved_4[0x40];
2339 
2340 	u8         reserved_5[0x8];
2341 	u8         inline_rqn[0x18];
2342 
2343 	u8         rx_hash_symmetric[0x1];
2344 	u8         reserved_6[0x1];
2345 	u8         tunneled_offload_en[0x1];
2346 	u8         reserved_7[0x5];
2347 	u8         indirect_table[0x18];
2348 
2349 	u8         rx_hash_fn[0x4];
2350 	u8         reserved_8[0x2];
2351 	u8         self_lb_en[0x2];
2352 	u8         transport_domain[0x18];
2353 
2354 	u8         rx_hash_toeplitz_key[10][0x20];
2355 
2356 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2357 
2358 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2359 
2360 	u8         reserved_9[0x4c0];
2361 };
2362 
2363 enum {
2364 	MLX5_SRQC_STATE_GOOD   = 0x0,
2365 	MLX5_SRQC_STATE_ERROR  = 0x1,
2366 };
2367 
2368 struct mlx5_ifc_srqc_bits {
2369 	u8         state[0x4];
2370 	u8         log_srq_size[0x4];
2371 	u8         reserved_0[0x18];
2372 
2373 	u8         wq_signature[0x1];
2374 	u8         cont_srq[0x1];
2375 	u8         reserved_1[0x1];
2376 	u8         rlky[0x1];
2377 	u8         reserved_2[0x1];
2378 	u8         log_rq_stride[0x3];
2379 	u8         xrcd[0x18];
2380 
2381 	u8         page_offset[0x6];
2382 	u8         reserved_3[0x2];
2383 	u8         cqn[0x18];
2384 
2385 	u8         reserved_4[0x20];
2386 
2387 	u8         reserved_5[0x2];
2388 	u8         log_page_size[0x6];
2389 	u8         reserved_6[0x18];
2390 
2391 	u8         reserved_7[0x20];
2392 
2393 	u8         reserved_8[0x8];
2394 	u8         pd[0x18];
2395 
2396 	u8         lwm[0x10];
2397 	u8         wqe_cnt[0x10];
2398 
2399 	u8         reserved_9[0x40];
2400 
2401 	u8	   dbr_addr[0x40];
2402 
2403 	u8	   reserved_10[0x80];
2404 };
2405 
2406 enum {
2407 	MLX5_SQC_STATE_RST  = 0x0,
2408 	MLX5_SQC_STATE_RDY  = 0x1,
2409 	MLX5_SQC_STATE_ERR  = 0x3,
2410 };
2411 
2412 enum {
2413 	MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2414 	MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2415 	MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2416 };
2417 
2418 struct mlx5_ifc_sqc_bits {
2419 	u8         rlkey[0x1];
2420 	u8         cd_master[0x1];
2421 	u8         fre[0x1];
2422 	u8         flush_in_error_en[0x1];
2423 	u8         allow_multi_pkt_send_wqe[0x1];
2424 	u8         min_wqe_inline_mode[0x3];
2425 	u8         state[0x4];
2426 	u8         reg_umr[0x1];
2427 	u8         allow_swp[0x1];
2428 	u8         reserved_at_e[0x4];
2429 	u8	   qos_remap_en[0x1];
2430 	u8	   reserved_at_d[0x7];
2431 	u8         ts_format[0x2];
2432 	u8         reserved_at_1c[0x4];
2433 
2434 	u8         reserved_1[0x8];
2435 	u8         user_index[0x18];
2436 
2437 	u8         reserved_2[0x8];
2438 	u8         cqn[0x18];
2439 
2440 	u8         reserved_3[0x80];
2441 
2442 	u8         qos_para_vport_number[0x10];
2443 	u8         packet_pacing_rate_limit_index[0x10];
2444 
2445 	u8         tis_lst_sz[0x10];
2446 	u8         qos_queue_group_id[0x10];
2447 
2448 	u8	   reserved_4[0x8];
2449 	u8	   queue_handle[0x18];
2450 
2451 	u8         reserved_5[0x20];
2452 
2453 	u8         reserved_6[0x8];
2454 	u8         tis_num_0[0x18];
2455 
2456 	struct mlx5_ifc_wq_bits wq;
2457 };
2458 
2459 struct mlx5_ifc_query_pp_rate_limit_in_bits {
2460 	u8	   opcode[0x10];
2461 	u8	   uid[0x10];
2462 
2463 	u8	   reserved1[0x10];
2464 	u8         op_mod[0x10];
2465 
2466 	u8         reserved2[0x10];
2467         u8         rate_limit_index[0x10];
2468 
2469 	u8         reserved_3[0x20];
2470 };
2471 
2472 struct mlx5_ifc_pp_context_bits {
2473 	u8	   rate_limit[0x20];
2474 
2475 	u8	   burst_upper_bound[0x20];
2476 
2477 	u8	   reserved_1[0xc];
2478 	u8	   rate_mode[0x4];
2479 	u8	   typical_packet_size[0x10];
2480 
2481 	u8	   reserved_2[0x8];
2482 	u8	   qos_handle[0x18];
2483 
2484 	u8	   reserved_3[0x40];
2485 };
2486 
2487 struct mlx5_ifc_query_pp_rate_limit_out_bits {
2488         u8	   status[0x8];
2489 	u8         reserved_1[0x18];
2490 
2491         u8         syndrome[0x20];
2492 
2493         u8         reserved_2[0x40];
2494 
2495 	struct mlx5_ifc_pp_context_bits pp_context;
2496 };
2497 
2498 enum {
2499 	MLX5_TSAR_TYPE_DWRR = 0,
2500 	MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
2501 	MLX5_TSAR_TYPE_ETS = 2
2502 };
2503 
2504 struct mlx5_ifc_tsar_element_attributes_bits {
2505 	u8         reserved_0[0x8];
2506 	u8         tsar_type[0x8];
2507 	u8	   reserved_1[0x10];
2508 };
2509 
2510 struct mlx5_ifc_vport_element_attributes_bits {
2511 	u8         reserved_0[0x10];
2512 	u8         vport_number[0x10];
2513 };
2514 
2515 struct mlx5_ifc_vport_tc_element_attributes_bits {
2516 	u8         traffic_class[0x10];
2517 	u8         vport_number[0x10];
2518 };
2519 
2520 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
2521 	u8         reserved_0[0x0C];
2522 	u8         traffic_class[0x04];
2523 	u8         qos_para_vport_number[0x10];
2524 };
2525 
2526 enum {
2527 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
2528 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
2529 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
2530 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
2531 };
2532 
2533 struct mlx5_ifc_scheduling_context_bits {
2534 	u8         element_type[0x8];
2535 	u8         reserved_at_8[0x18];
2536 
2537 	u8         element_attributes[0x20];
2538 
2539 	u8         parent_element_id[0x20];
2540 
2541 	u8         reserved_at_60[0x40];
2542 
2543 	u8         bw_share[0x20];
2544 
2545 	u8         max_average_bw[0x20];
2546 
2547 	u8         reserved_at_e0[0x120];
2548 };
2549 
2550 struct mlx5_ifc_rqtc_bits {
2551 	u8         reserved_0[0xa0];
2552 
2553 	u8         reserved_1[0x10];
2554 	u8         rqt_max_size[0x10];
2555 
2556 	u8         reserved_2[0x10];
2557 	u8         rqt_actual_size[0x10];
2558 
2559 	u8         reserved_3[0x6a0];
2560 
2561 	struct mlx5_ifc_rq_num_bits rq_num[0];
2562 };
2563 
2564 enum {
2565 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
2566 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
2567 };
2568 
2569 enum {
2570 	MLX5_RQC_STATE_RST  = 0x0,
2571 	MLX5_RQC_STATE_RDY  = 0x1,
2572 	MLX5_RQC_STATE_ERR  = 0x3,
2573 };
2574 
2575 enum {
2576 	MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
2577 	MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
2578 };
2579 
2580 enum {
2581 	MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2582 	MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2583 	MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2584 };
2585 
2586 struct mlx5_ifc_rqc_bits {
2587 	u8         rlkey[0x1];
2588 	u8         delay_drop_en[0x1];
2589 	u8         scatter_fcs[0x1];
2590 	u8         vlan_strip_disable[0x1];
2591 	u8         mem_rq_type[0x4];
2592 	u8         state[0x4];
2593 	u8         reserved_1[0x1];
2594 	u8         flush_in_error_en[0x1];
2595 	u8         reserved_at_e[0xc];
2596 	u8         ts_format[0x2];
2597 	u8         reserved_at_1c[0x4];
2598 
2599 	u8         reserved_3[0x8];
2600 	u8         user_index[0x18];
2601 
2602 	u8         reserved_4[0x8];
2603 	u8         cqn[0x18];
2604 
2605 	u8         counter_set_id[0x8];
2606 	u8         reserved_5[0x18];
2607 
2608 	u8         reserved_6[0x8];
2609 	u8         rmpn[0x18];
2610 
2611 	u8         reserved_7[0xe0];
2612 
2613 	struct mlx5_ifc_wq_bits wq;
2614 };
2615 
2616 enum {
2617 	MLX5_RMPC_STATE_RDY  = 0x1,
2618 	MLX5_RMPC_STATE_ERR  = 0x3,
2619 };
2620 
2621 struct mlx5_ifc_rmpc_bits {
2622 	u8         reserved_0[0x8];
2623 	u8         state[0x4];
2624 	u8         reserved_1[0x14];
2625 
2626 	u8         basic_cyclic_rcv_wqe[0x1];
2627 	u8         reserved_2[0x1f];
2628 
2629 	u8         reserved_3[0x140];
2630 
2631 	struct mlx5_ifc_wq_bits wq;
2632 };
2633 
2634 enum {
2635 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2636 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
2637 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
2638 };
2639 
2640 struct mlx5_ifc_nic_vport_context_bits {
2641 	u8         reserved_0[0x5];
2642 	u8         min_wqe_inline_mode[0x3];
2643 	u8         reserved_1[0x15];
2644 	u8         disable_mc_local_lb[0x1];
2645 	u8         disable_uc_local_lb[0x1];
2646 	u8         roce_en[0x1];
2647 
2648 	u8         arm_change_event[0x1];
2649 	u8         reserved_2[0x1a];
2650 	u8         event_on_mtu[0x1];
2651 	u8         event_on_promisc_change[0x1];
2652 	u8         event_on_vlan_change[0x1];
2653 	u8         event_on_mc_address_change[0x1];
2654 	u8         event_on_uc_address_change[0x1];
2655 
2656 	u8         reserved_3[0xe0];
2657 
2658 	u8         reserved_4[0x10];
2659 	u8         mtu[0x10];
2660 
2661 	u8         system_image_guid[0x40];
2662 
2663 	u8         port_guid[0x40];
2664 
2665 	u8         node_guid[0x40];
2666 
2667 	u8         reserved_5[0x140];
2668 
2669 	u8         qkey_violation_counter[0x10];
2670 	u8         reserved_6[0x10];
2671 
2672 	u8         reserved_7[0x420];
2673 
2674 	u8         promisc_uc[0x1];
2675 	u8         promisc_mc[0x1];
2676 	u8         promisc_all[0x1];
2677 	u8         reserved_8[0x2];
2678 	u8         allowed_list_type[0x3];
2679 	u8         reserved_9[0xc];
2680 	u8         allowed_list_size[0xc];
2681 
2682 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
2683 
2684 	u8         reserved_10[0x20];
2685 
2686 	u8         current_uc_mac_address[0][0x40];
2687 };
2688 
2689 enum {
2690 	MLX5_ACCESS_MODE_PA        = 0x0,
2691 	MLX5_ACCESS_MODE_MTT       = 0x1,
2692 	MLX5_ACCESS_MODE_KLM       = 0x2,
2693 };
2694 
2695 struct mlx5_ifc_mkc_bits {
2696 	u8         reserved_at_0[0x1];
2697 	u8         free[0x1];
2698 	u8         reserved_at_2[0x1];
2699 	u8         access_mode_4_2[0x3];
2700 	u8         reserved_at_6[0x7];
2701 	u8         relaxed_ordering_write[0x1];
2702 	u8         reserved_at_e[0x1];
2703 	u8         small_fence_on_rdma_read_response[0x1];
2704 	u8         umr_en[0x1];
2705 	u8         a[0x1];
2706 	u8         rw[0x1];
2707 	u8         rr[0x1];
2708 	u8         lw[0x1];
2709 	u8         lr[0x1];
2710 	u8         access_mode[0x2];
2711 	u8         reserved_2[0x8];
2712 
2713 	u8         qpn[0x18];
2714 	u8         mkey_7_0[0x8];
2715 
2716 	u8         reserved_3[0x20];
2717 
2718 	u8         length64[0x1];
2719 	u8         bsf_en[0x1];
2720 	u8         sync_umr[0x1];
2721 	u8         reserved_4[0x2];
2722 	u8         expected_sigerr_count[0x1];
2723 	u8         reserved_5[0x1];
2724 	u8         en_rinval[0x1];
2725 	u8         pd[0x18];
2726 
2727 	u8         start_addr[0x40];
2728 
2729 	u8         len[0x40];
2730 
2731 	u8         bsf_octword_size[0x20];
2732 
2733 	u8         reserved_6[0x80];
2734 
2735 	u8         translations_octword_size[0x20];
2736 
2737 	u8         reserved_at_1c0[0x19];
2738 	u8         relaxed_ordering_read[0x1];
2739 	u8         reserved_at_1d9[0x1];
2740 	u8         log_page_size[0x5];
2741 
2742 	u8         reserved_8[0x20];
2743 };
2744 
2745 struct mlx5_ifc_pkey_bits {
2746 	u8         reserved_0[0x10];
2747 	u8         pkey[0x10];
2748 };
2749 
2750 struct mlx5_ifc_array128_auto_bits {
2751 	u8         array128_auto[16][0x8];
2752 };
2753 
2754 enum {
2755 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2756 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2757 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2758 };
2759 
2760 enum {
2761 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2762 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2763 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2764 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2765 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2766 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2767 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2768 };
2769 
2770 enum {
2771 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2772 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2773 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2774 };
2775 
2776 enum {
2777 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2778 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2779 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2780 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2781 };
2782 
2783 enum {
2784 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2785 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2786 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2787 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2788 };
2789 
2790 struct mlx5_ifc_hca_vport_context_bits {
2791 	u8         field_select[0x20];
2792 
2793 	u8         reserved_0[0xe0];
2794 
2795 	u8         sm_virt_aware[0x1];
2796 	u8         has_smi[0x1];
2797 	u8         has_raw[0x1];
2798 	u8         grh_required[0x1];
2799 	u8         reserved_1[0x1];
2800 	u8         min_wqe_inline_mode[0x3];
2801 	u8         reserved_2[0x8];
2802 	u8         port_physical_state[0x4];
2803 	u8         vport_state_policy[0x4];
2804 	u8         port_state[0x4];
2805 	u8         vport_state[0x4];
2806 
2807 	u8         reserved_3[0x20];
2808 
2809 	u8         system_image_guid[0x40];
2810 
2811 	u8         port_guid[0x40];
2812 
2813 	u8         node_guid[0x40];
2814 
2815 	u8         cap_mask1[0x20];
2816 
2817 	u8         cap_mask1_field_select[0x20];
2818 
2819 	u8         cap_mask2[0x20];
2820 
2821 	u8         cap_mask2_field_select[0x20];
2822 
2823 	u8         reserved_4[0x80];
2824 
2825 	u8         lid[0x10];
2826 	u8         reserved_5[0x4];
2827 	u8         init_type_reply[0x4];
2828 	u8         lmc[0x3];
2829 	u8         subnet_timeout[0x5];
2830 
2831 	u8         sm_lid[0x10];
2832 	u8         sm_sl[0x4];
2833 	u8         reserved_6[0xc];
2834 
2835 	u8         qkey_violation_counter[0x10];
2836 	u8         pkey_violation_counter[0x10];
2837 
2838 	u8         reserved_7[0xca0];
2839 };
2840 
2841 union mlx5_ifc_hca_cap_union_bits {
2842 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2843 	struct mlx5_ifc_odp_cap_bits odp_cap;
2844 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
2845 	struct mlx5_ifc_roce_cap_bits roce_cap;
2846 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2847 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2848 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2849 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2850 	struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
2851 	struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
2852 	struct mlx5_ifc_qos_cap_bits qos_cap;
2853 	struct mlx5_ifc_tls_capabilities_bits tls_capabilities;
2854 	u8         reserved_0[0x8000];
2855 };
2856 
2857 enum {
2858 	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
2859 	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
2860 };
2861 
2862 struct mlx5_ifc_flow_table_context_bits {
2863 	u8         encap_en[0x1];
2864 	u8         decap_en[0x1];
2865 	u8         reserved_at_2[0x2];
2866 	u8         table_miss_action[0x4];
2867 	u8         level[0x8];
2868 	u8         reserved_at_10[0x8];
2869 	u8         log_size[0x8];
2870 
2871 	u8         reserved_at_20[0x8];
2872 	u8         table_miss_id[0x18];
2873 
2874 	u8         reserved_at_40[0x8];
2875 	u8         lag_master_next_table_id[0x18];
2876 
2877 	u8         reserved_at_60[0xe0];
2878 };
2879 
2880 struct mlx5_ifc_esw_vport_context_bits {
2881 	u8         reserved_0[0x3];
2882 	u8         vport_svlan_strip[0x1];
2883 	u8         vport_cvlan_strip[0x1];
2884 	u8         vport_svlan_insert[0x1];
2885 	u8         vport_cvlan_insert[0x2];
2886 	u8         reserved_1[0x18];
2887 
2888 	u8         reserved_2[0x20];
2889 
2890 	u8         svlan_cfi[0x1];
2891 	u8         svlan_pcp[0x3];
2892 	u8         svlan_id[0xc];
2893 	u8         cvlan_cfi[0x1];
2894 	u8         cvlan_pcp[0x3];
2895 	u8         cvlan_id[0xc];
2896 
2897 	u8         reserved_3[0x7a0];
2898 };
2899 
2900 enum {
2901 	MLX5_EQC_STATUS_OK                = 0x0,
2902 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2903 };
2904 
2905 enum {
2906 	MLX5_EQ_STATE_ARMED = 0x9,
2907 	MLX5_EQ_STATE_FIRED = 0xa,
2908 };
2909 
2910 struct mlx5_ifc_eqc_bits {
2911 	u8         status[0x4];
2912 	u8         reserved_0[0x9];
2913 	u8         ec[0x1];
2914 	u8         oi[0x1];
2915 	u8         reserved_1[0x5];
2916 	u8         st[0x4];
2917 	u8         reserved_2[0x8];
2918 
2919 	u8         reserved_3[0x20];
2920 
2921 	u8         reserved_4[0x14];
2922 	u8         page_offset[0x6];
2923 	u8         reserved_5[0x6];
2924 
2925 	u8         reserved_6[0x3];
2926 	u8         log_eq_size[0x5];
2927 	u8         uar_page[0x18];
2928 
2929 	u8         reserved_7[0x20];
2930 
2931 	u8         reserved_8[0x18];
2932 	u8         intr[0x8];
2933 
2934 	u8         reserved_9[0x3];
2935 	u8         log_page_size[0x5];
2936 	u8         reserved_10[0x18];
2937 
2938 	u8         reserved_11[0x60];
2939 
2940 	u8         reserved_12[0x8];
2941 	u8         consumer_counter[0x18];
2942 
2943 	u8         reserved_13[0x8];
2944 	u8         producer_counter[0x18];
2945 
2946 	u8         reserved_14[0x80];
2947 };
2948 
2949 enum {
2950 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
2951 	MLX5_DCTC_STATE_DRAINING  = 0x1,
2952 	MLX5_DCTC_STATE_DRAINED   = 0x2,
2953 };
2954 
2955 enum {
2956 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2957 	MLX5_DCTC_CS_RES_NA         = 0x1,
2958 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2959 };
2960 
2961 enum {
2962 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
2963 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
2964 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2965 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2966 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2967 };
2968 
2969 struct mlx5_ifc_dctc_bits {
2970 	u8         reserved_0[0x4];
2971 	u8         state[0x4];
2972 	u8         reserved_1[0x18];
2973 
2974 	u8         reserved_2[0x8];
2975 	u8         user_index[0x18];
2976 
2977 	u8         reserved_3[0x8];
2978 	u8         cqn[0x18];
2979 
2980 	u8         counter_set_id[0x8];
2981 	u8         atomic_mode[0x4];
2982 	u8         rre[0x1];
2983 	u8         rwe[0x1];
2984 	u8         rae[0x1];
2985 	u8         atomic_like_write_en[0x1];
2986 	u8         latency_sensitive[0x1];
2987 	u8         rlky[0x1];
2988 	u8         reserved_4[0xe];
2989 
2990 	u8         reserved_5[0x8];
2991 	u8         cs_res[0x8];
2992 	u8         reserved_6[0x3];
2993 	u8         min_rnr_nak[0x5];
2994 	u8         reserved_7[0x8];
2995 
2996 	u8         reserved_8[0x8];
2997 	u8         srqn[0x18];
2998 
2999 	u8         reserved_9[0x8];
3000 	u8         pd[0x18];
3001 
3002 	u8         tclass[0x8];
3003 	u8         reserved_10[0x4];
3004 	u8         flow_label[0x14];
3005 
3006 	u8         dc_access_key[0x40];
3007 
3008 	u8         reserved_11[0x5];
3009 	u8         mtu[0x3];
3010 	u8         port[0x8];
3011 	u8         pkey_index[0x10];
3012 
3013 	u8         reserved_12[0x8];
3014 	u8         my_addr_index[0x8];
3015 	u8         reserved_13[0x8];
3016 	u8         hop_limit[0x8];
3017 
3018 	u8         dc_access_key_violation_count[0x20];
3019 
3020 	u8         reserved_14[0x14];
3021 	u8         dei_cfi[0x1];
3022 	u8         eth_prio[0x3];
3023 	u8         ecn[0x2];
3024 	u8         dscp[0x6];
3025 
3026 	u8         reserved_15[0x40];
3027 };
3028 
3029 enum {
3030 	MLX5_CQC_STATUS_OK             = 0x0,
3031 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3032 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3033 };
3034 
3035 enum {
3036 	CQE_SIZE_64                = 0x0,
3037 	CQE_SIZE_128               = 0x1,
3038 };
3039 
3040 enum {
3041 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
3042 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
3043 };
3044 
3045 enum {
3046 	MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
3047 	MLX5_CQ_STATE_ARMED                               = 0x9,
3048 	MLX5_CQ_STATE_FIRED                               = 0xa,
3049 };
3050 
3051 struct mlx5_ifc_cqc_bits {
3052 	u8         status[0x4];
3053 	u8         reserved_0[0x4];
3054 	u8         cqe_sz[0x3];
3055 	u8         cc[0x1];
3056 	u8         reserved_1[0x1];
3057 	u8         scqe_break_moderation_en[0x1];
3058 	u8         oi[0x1];
3059 	u8         cq_period_mode[0x2];
3060 	u8         cqe_compression_en[0x1];
3061 	u8         mini_cqe_res_format[0x2];
3062 	u8         st[0x4];
3063 	u8         reserved_2[0x8];
3064 
3065 	u8         reserved_3[0x20];
3066 
3067 	u8         reserved_4[0x14];
3068 	u8         page_offset[0x6];
3069 	u8         reserved_5[0x6];
3070 
3071 	u8         reserved_6[0x3];
3072 	u8         log_cq_size[0x5];
3073 	u8         uar_page[0x18];
3074 
3075 	u8         reserved_7[0x4];
3076 	u8         cq_period[0xc];
3077 	u8         cq_max_count[0x10];
3078 
3079 	u8         reserved_8[0x18];
3080 	u8         c_eqn[0x8];
3081 
3082 	u8         reserved_9[0x3];
3083 	u8         log_page_size[0x5];
3084 	u8         reserved_10[0x18];
3085 
3086 	u8         reserved_11[0x20];
3087 
3088 	u8         reserved_12[0x8];
3089 	u8         last_notified_index[0x18];
3090 
3091 	u8         reserved_13[0x8];
3092 	u8         last_solicit_index[0x18];
3093 
3094 	u8         reserved_14[0x8];
3095 	u8         consumer_counter[0x18];
3096 
3097 	u8         reserved_15[0x8];
3098 	u8         producer_counter[0x18];
3099 
3100 	u8         reserved_16[0x40];
3101 
3102 	u8         dbr_addr[0x40];
3103 };
3104 
3105 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3106 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3107 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3108 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3109 	u8         reserved_0[0x800];
3110 };
3111 
3112 struct mlx5_ifc_query_adapter_param_block_bits {
3113 	u8         reserved_0[0xc0];
3114 
3115 	u8         reserved_1[0x8];
3116 	u8         ieee_vendor_id[0x18];
3117 
3118 	u8         reserved_2[0x10];
3119 	u8         vsd_vendor_id[0x10];
3120 
3121 	u8         vsd[208][0x8];
3122 
3123 	u8         vsd_contd_psid[16][0x8];
3124 };
3125 
3126 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3127 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
3128 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
3129 	u8         reserved_0[0x20];
3130 };
3131 
3132 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3133 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3134 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3135 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3136 	u8         reserved_0[0x20];
3137 };
3138 
3139 struct mlx5_ifc_bufferx_reg_bits {
3140 	u8         reserved_0[0x6];
3141 	u8         lossy[0x1];
3142 	u8         epsb[0x1];
3143 	u8         reserved_1[0xc];
3144 	u8         size[0xc];
3145 
3146 	u8         xoff_threshold[0x10];
3147 	u8         xon_threshold[0x10];
3148 };
3149 
3150 struct mlx5_ifc_config_item_bits {
3151 	u8         valid[0x2];
3152 	u8         reserved_0[0x2];
3153 	u8         header_type[0x2];
3154 	u8         reserved_1[0x2];
3155 	u8         default_location[0x1];
3156 	u8         reserved_2[0x7];
3157 	u8         version[0x4];
3158 	u8         reserved_3[0x3];
3159 	u8         length[0x9];
3160 
3161 	u8         type[0x20];
3162 
3163 	u8         reserved_4[0x10];
3164 	u8         crc16[0x10];
3165 };
3166 
3167 struct mlx5_ifc_nodnic_port_config_reg_bits {
3168 	struct mlx5_ifc_nodnic_event_word_bits event;
3169 
3170 	u8         network_en[0x1];
3171 	u8         dma_en[0x1];
3172 	u8         promisc_en[0x1];
3173 	u8         promisc_multicast_en[0x1];
3174 	u8         reserved_0[0x17];
3175 	u8         receive_filter_en[0x5];
3176 
3177 	u8         reserved_1[0x10];
3178 	u8         mac_47_32[0x10];
3179 
3180 	u8         mac_31_0[0x20];
3181 
3182 	u8         receive_filters_mgid_mac[64][0x8];
3183 
3184 	u8         gid[16][0x8];
3185 
3186 	u8         reserved_2[0x10];
3187 	u8         lid[0x10];
3188 
3189 	u8         reserved_3[0xc];
3190 	u8         sm_sl[0x4];
3191 	u8         sm_lid[0x10];
3192 
3193 	u8         completion_address_63_32[0x20];
3194 
3195 	u8         completion_address_31_12[0x14];
3196 	u8         reserved_4[0x6];
3197 	u8         log_cq_size[0x6];
3198 
3199 	u8         working_buffer_address_63_32[0x20];
3200 
3201 	u8         working_buffer_address_31_12[0x14];
3202 	u8         reserved_5[0xc];
3203 
3204 	struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
3205 
3206 	u8         pkey_index[0x10];
3207 	u8         pkey[0x10];
3208 
3209 	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
3210 
3211 	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
3212 
3213 	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
3214 
3215 	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
3216 
3217 	u8         reserved_6[0x400];
3218 };
3219 
3220 union mlx5_ifc_event_auto_bits {
3221 	struct mlx5_ifc_comp_event_bits comp_event;
3222 	struct mlx5_ifc_dct_events_bits dct_events;
3223 	struct mlx5_ifc_qp_events_bits qp_events;
3224 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3225 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3226 	struct mlx5_ifc_cq_error_bits cq_error;
3227 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3228 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3229 	struct mlx5_ifc_gpio_event_bits gpio_event;
3230 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3231 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3232 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3233 	struct mlx5_ifc_pages_req_event_bits pages_req_event;
3234 	struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
3235 	u8         reserved_0[0xe0];
3236 };
3237 
3238 struct mlx5_ifc_health_buffer_bits {
3239 	u8         reserved_0[0x100];
3240 
3241 	u8         assert_existptr[0x20];
3242 
3243 	u8         assert_callra[0x20];
3244 
3245 	u8         reserved_1[0x40];
3246 
3247 	u8         fw_version[0x20];
3248 
3249 	u8         hw_id[0x20];
3250 
3251 	u8         reserved_2[0x20];
3252 
3253 	u8         irisc_index[0x8];
3254 	u8         synd[0x8];
3255 	u8         ext_synd[0x10];
3256 };
3257 
3258 struct mlx5_ifc_register_loopback_control_bits {
3259 	u8         no_lb[0x1];
3260 	u8         reserved_0[0x7];
3261 	u8         port[0x8];
3262 	u8         reserved_1[0x10];
3263 
3264 	u8         reserved_2[0x60];
3265 };
3266 
3267 struct mlx5_ifc_lrh_bits {
3268 	u8	vl[4];
3269 	u8	lver[4];
3270 	u8	sl[4];
3271 	u8	reserved2[2];
3272 	u8	lnh[2];
3273 	u8	dlid[16];
3274 	u8	reserved5[5];
3275 	u8	pkt_len[11];
3276 	u8	slid[16];
3277 };
3278 
3279 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
3280 	u8         reserved_0[0x40];
3281 
3282 	u8         reserved_1[0x10];
3283 	u8         rol_mode[0x8];
3284 	u8         wol_mode[0x8];
3285 };
3286 
3287 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
3288 	u8         reserved_0[0x40];
3289 
3290 	u8         rol_mode_valid[0x1];
3291 	u8         wol_mode_valid[0x1];
3292 	u8         reserved_1[0xe];
3293 	u8         rol_mode[0x8];
3294 	u8         wol_mode[0x8];
3295 
3296 	u8         reserved_2[0x7a0];
3297 };
3298 
3299 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
3300 	u8         virtual_mac_en[0x1];
3301 	u8         mac_aux_v[0x1];
3302 	u8         reserved_0[0x1e];
3303 
3304 	u8         reserved_1[0x40];
3305 
3306 	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3307 
3308 	u8         reserved_2[0x760];
3309 };
3310 
3311 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
3312 	u8         virtual_mac_en[0x1];
3313 	u8         mac_aux_v[0x1];
3314 	u8         reserved_0[0x1e];
3315 
3316 	struct mlx5_ifc_mac_address_layout_bits permanent_mac;
3317 
3318 	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
3319 
3320 	u8         reserved_1[0x760];
3321 };
3322 
3323 struct mlx5_ifc_icmd_query_fw_info_out_bits {
3324 	struct mlx5_ifc_fw_version_bits fw_version;
3325 
3326 	u8         reserved_0[0x10];
3327 	u8         hash_signature[0x10];
3328 
3329 	u8         psid[16][0x8];
3330 
3331 	u8         reserved_1[0x6e0];
3332 };
3333 
3334 struct mlx5_ifc_icmd_query_cap_in_bits {
3335 	u8         reserved_0[0x10];
3336 	u8         capability_group[0x10];
3337 };
3338 
3339 struct mlx5_ifc_icmd_query_cap_general_bits {
3340 	u8         nv_access[0x1];
3341 	u8         fw_info_psid[0x1];
3342 	u8         reserved_0[0x1e];
3343 
3344 	u8         reserved_1[0x16];
3345 	u8         rol_s[0x1];
3346 	u8         rol_g[0x1];
3347 	u8         reserved_2[0x1];
3348 	u8         wol_s[0x1];
3349 	u8         wol_g[0x1];
3350 	u8         wol_a[0x1];
3351 	u8         wol_b[0x1];
3352 	u8         wol_m[0x1];
3353 	u8         wol_u[0x1];
3354 	u8         wol_p[0x1];
3355 };
3356 
3357 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
3358 	u8         status[0x8];
3359 	u8         reserved_0[0x18];
3360 
3361 	u8         reserved_1[0x7e0];
3362 };
3363 
3364 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
3365 	u8         status[0x8];
3366 	u8         reserved_0[0x18];
3367 
3368 	u8         reserved_1[0x7e0];
3369 };
3370 
3371 struct mlx5_ifc_icmd_ocbb_init_in_bits {
3372 	u8         address_hi[0x20];
3373 
3374 	u8         address_lo[0x20];
3375 
3376 	u8         reserved_0[0x7c0];
3377 };
3378 
3379 struct mlx5_ifc_icmd_init_ocsd_in_bits {
3380 	u8         reserved_0[0x20];
3381 
3382 	u8         address_hi[0x20];
3383 
3384 	u8         address_lo[0x20];
3385 
3386 	u8         reserved_1[0x7a0];
3387 };
3388 
3389 struct mlx5_ifc_icmd_access_reg_out_bits {
3390 	u8         reserved_0[0x11];
3391 	u8         status[0x7];
3392 	u8         reserved_1[0x8];
3393 
3394 	u8         register_id[0x10];
3395 	u8         reserved_2[0x10];
3396 
3397 	u8         reserved_3[0x40];
3398 
3399 	u8         reserved_4[0x5];
3400 	u8         len[0xb];
3401 	u8         reserved_5[0x10];
3402 
3403 	u8         register_data[0][0x20];
3404 };
3405 
3406 enum {
3407 	MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
3408 	MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
3409 };
3410 
3411 struct mlx5_ifc_icmd_access_reg_in_bits {
3412 	u8         constant_1[0x5];
3413 	u8         constant_2[0xb];
3414 	u8         reserved_0[0x10];
3415 
3416 	u8         register_id[0x10];
3417 	u8         reserved_1[0x1];
3418 	u8         method[0x7];
3419 	u8         constant_3[0x8];
3420 
3421 	u8         reserved_2[0x40];
3422 
3423 	u8         constant_4[0x5];
3424 	u8         len[0xb];
3425 	u8         reserved_3[0x10];
3426 
3427 	u8         register_data[0][0x20];
3428 };
3429 
3430 enum {
3431 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3432 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3433 };
3434 
3435 struct mlx5_ifc_teardown_hca_out_bits {
3436 	u8         status[0x8];
3437 	u8         reserved_0[0x18];
3438 
3439 	u8         syndrome[0x20];
3440 
3441 	u8         reserved_1[0x3f];
3442 
3443 	u8	   state[0x1];
3444 };
3445 
3446 enum {
3447 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3448 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3449 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3450 };
3451 
3452 struct mlx5_ifc_teardown_hca_in_bits {
3453 	u8         opcode[0x10];
3454 	u8         reserved_0[0x10];
3455 
3456 	u8         reserved_1[0x10];
3457 	u8         op_mod[0x10];
3458 
3459 	u8         reserved_2[0x10];
3460 	u8         profile[0x10];
3461 
3462 	u8         reserved_3[0x20];
3463 };
3464 
3465 struct mlx5_ifc_set_delay_drop_params_out_bits {
3466 	u8         status[0x8];
3467 	u8         reserved_at_8[0x18];
3468 
3469 	u8         syndrome[0x20];
3470 
3471 	u8         reserved_at_40[0x40];
3472 };
3473 
3474 struct mlx5_ifc_set_delay_drop_params_in_bits {
3475 	u8         opcode[0x10];
3476 	u8         reserved_at_10[0x10];
3477 
3478 	u8         reserved_at_20[0x10];
3479 	u8         op_mod[0x10];
3480 
3481 	u8         reserved_at_40[0x20];
3482 
3483 	u8         reserved_at_60[0x10];
3484 	u8         delay_drop_timeout[0x10];
3485 };
3486 
3487 struct mlx5_ifc_query_delay_drop_params_out_bits {
3488 	u8         status[0x8];
3489 	u8         reserved_at_8[0x18];
3490 
3491 	u8         syndrome[0x20];
3492 
3493 	u8         reserved_at_40[0x20];
3494 
3495 	u8         reserved_at_60[0x10];
3496 	u8         delay_drop_timeout[0x10];
3497 };
3498 
3499 struct mlx5_ifc_query_delay_drop_params_in_bits {
3500 	u8         opcode[0x10];
3501 	u8         reserved_at_10[0x10];
3502 
3503 	u8         reserved_at_20[0x10];
3504 	u8         op_mod[0x10];
3505 
3506 	u8         reserved_at_40[0x40];
3507 };
3508 
3509 struct mlx5_ifc_suspend_qp_out_bits {
3510 	u8         status[0x8];
3511 	u8         reserved_0[0x18];
3512 
3513 	u8         syndrome[0x20];
3514 
3515 	u8         reserved_1[0x40];
3516 };
3517 
3518 struct mlx5_ifc_suspend_qp_in_bits {
3519 	u8         opcode[0x10];
3520 	u8         reserved_0[0x10];
3521 
3522 	u8         reserved_1[0x10];
3523 	u8         op_mod[0x10];
3524 
3525 	u8         reserved_2[0x8];
3526 	u8         qpn[0x18];
3527 
3528 	u8         reserved_3[0x20];
3529 };
3530 
3531 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3532 	u8         status[0x8];
3533 	u8         reserved_0[0x18];
3534 
3535 	u8         syndrome[0x20];
3536 
3537 	u8         reserved_1[0x40];
3538 };
3539 
3540 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3541 	u8         opcode[0x10];
3542 	u8         uid[0x10];
3543 
3544 	u8         reserved_1[0x10];
3545 	u8         op_mod[0x10];
3546 
3547 	u8         reserved_2[0x8];
3548 	u8         qpn[0x18];
3549 
3550 	u8         reserved_3[0x20];
3551 
3552 	u8         opt_param_mask[0x20];
3553 
3554 	u8         reserved_4[0x20];
3555 
3556 	struct mlx5_ifc_qpc_bits qpc;
3557 
3558 	u8         reserved_5[0x80];
3559 };
3560 
3561 struct mlx5_ifc_sqd2rts_qp_out_bits {
3562 	u8         status[0x8];
3563 	u8         reserved_0[0x18];
3564 
3565 	u8         syndrome[0x20];
3566 
3567 	u8         reserved_1[0x40];
3568 };
3569 
3570 struct mlx5_ifc_sqd2rts_qp_in_bits {
3571 	u8         opcode[0x10];
3572 	u8         reserved_0[0x10];
3573 
3574 	u8         reserved_1[0x10];
3575 	u8         op_mod[0x10];
3576 
3577 	u8         reserved_2[0x8];
3578 	u8         qpn[0x18];
3579 
3580 	u8         reserved_3[0x20];
3581 
3582 	u8         opt_param_mask[0x20];
3583 
3584 	u8         reserved_4[0x20];
3585 
3586 	struct mlx5_ifc_qpc_bits qpc;
3587 
3588 	u8         reserved_5[0x80];
3589 };
3590 
3591 struct mlx5_ifc_set_wol_rol_out_bits {
3592 	u8         status[0x8];
3593 	u8         reserved_0[0x18];
3594 
3595 	u8         syndrome[0x20];
3596 
3597 	u8         reserved_1[0x40];
3598 };
3599 
3600 struct mlx5_ifc_set_wol_rol_in_bits {
3601 	u8         opcode[0x10];
3602 	u8         reserved_0[0x10];
3603 
3604 	u8         reserved_1[0x10];
3605 	u8         op_mod[0x10];
3606 
3607 	u8         rol_mode_valid[0x1];
3608 	u8         wol_mode_valid[0x1];
3609 	u8         reserved_2[0xe];
3610 	u8         rol_mode[0x8];
3611 	u8         wol_mode[0x8];
3612 
3613 	u8         reserved_3[0x20];
3614 };
3615 
3616 struct mlx5_ifc_set_roce_address_out_bits {
3617 	u8         status[0x8];
3618 	u8         reserved_0[0x18];
3619 
3620 	u8         syndrome[0x20];
3621 
3622 	u8         reserved_1[0x40];
3623 };
3624 
3625 struct mlx5_ifc_set_roce_address_in_bits {
3626 	u8         opcode[0x10];
3627 	u8         reserved_0[0x10];
3628 
3629 	u8         reserved_1[0x10];
3630 	u8         op_mod[0x10];
3631 
3632 	u8         roce_address_index[0x10];
3633 	u8         reserved_2[0x10];
3634 
3635 	u8         reserved_3[0x20];
3636 
3637 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
3638 };
3639 
3640 struct mlx5_ifc_set_rdb_out_bits {
3641 	u8         status[0x8];
3642 	u8         reserved_0[0x18];
3643 
3644 	u8         syndrome[0x20];
3645 
3646 	u8         reserved_1[0x40];
3647 };
3648 
3649 struct mlx5_ifc_set_rdb_in_bits {
3650 	u8         opcode[0x10];
3651 	u8         reserved_0[0x10];
3652 
3653 	u8         reserved_1[0x10];
3654 	u8         op_mod[0x10];
3655 
3656 	u8         reserved_2[0x8];
3657 	u8         qpn[0x18];
3658 
3659 	u8         reserved_3[0x18];
3660 	u8         rdb_list_size[0x8];
3661 
3662 	struct mlx5_ifc_rdbc_bits rdb_context[0];
3663 };
3664 
3665 struct mlx5_ifc_set_mad_demux_out_bits {
3666 	u8         status[0x8];
3667 	u8         reserved_0[0x18];
3668 
3669 	u8         syndrome[0x20];
3670 
3671 	u8         reserved_1[0x40];
3672 };
3673 
3674 enum {
3675 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3676 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3677 };
3678 
3679 struct mlx5_ifc_set_mad_demux_in_bits {
3680 	u8         opcode[0x10];
3681 	u8         reserved_0[0x10];
3682 
3683 	u8         reserved_1[0x10];
3684 	u8         op_mod[0x10];
3685 
3686 	u8         reserved_2[0x20];
3687 
3688 	u8         reserved_3[0x6];
3689 	u8         demux_mode[0x2];
3690 	u8         reserved_4[0x18];
3691 };
3692 
3693 struct mlx5_ifc_set_l2_table_entry_out_bits {
3694 	u8         status[0x8];
3695 	u8         reserved_0[0x18];
3696 
3697 	u8         syndrome[0x20];
3698 
3699 	u8         reserved_1[0x40];
3700 };
3701 
3702 struct mlx5_ifc_set_l2_table_entry_in_bits {
3703 	u8         opcode[0x10];
3704 	u8         reserved_0[0x10];
3705 
3706 	u8         reserved_1[0x10];
3707 	u8         op_mod[0x10];
3708 
3709 	u8         reserved_2[0x60];
3710 
3711 	u8         reserved_3[0x8];
3712 	u8         table_index[0x18];
3713 
3714 	u8         reserved_4[0x20];
3715 
3716 	u8         reserved_5[0x13];
3717 	u8         vlan_valid[0x1];
3718 	u8         vlan[0xc];
3719 
3720 	struct mlx5_ifc_mac_address_layout_bits mac_address;
3721 
3722 	u8         reserved_6[0xc0];
3723 };
3724 
3725 struct mlx5_ifc_set_issi_out_bits {
3726 	u8         status[0x8];
3727 	u8         reserved_0[0x18];
3728 
3729 	u8         syndrome[0x20];
3730 
3731 	u8         reserved_1[0x40];
3732 };
3733 
3734 struct mlx5_ifc_set_issi_in_bits {
3735 	u8         opcode[0x10];
3736 	u8         reserved_0[0x10];
3737 
3738 	u8         reserved_1[0x10];
3739 	u8         op_mod[0x10];
3740 
3741 	u8         reserved_2[0x10];
3742 	u8         current_issi[0x10];
3743 
3744 	u8         reserved_3[0x20];
3745 };
3746 
3747 struct mlx5_ifc_set_hca_cap_out_bits {
3748 	u8         status[0x8];
3749 	u8         reserved_0[0x18];
3750 
3751 	u8         syndrome[0x20];
3752 
3753 	u8         reserved_1[0x40];
3754 };
3755 
3756 struct mlx5_ifc_set_hca_cap_in_bits {
3757 	u8         opcode[0x10];
3758 	u8         reserved_0[0x10];
3759 
3760 	u8         reserved_1[0x10];
3761 	u8         op_mod[0x10];
3762 
3763 	u8         reserved_2[0x40];
3764 
3765 	union mlx5_ifc_hca_cap_union_bits capability;
3766 };
3767 
3768 enum {
3769 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION			= 0x0,
3770 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG		= 0x1,
3771 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST	= 0x2,
3772 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS		= 0x3
3773 };
3774 
3775 struct mlx5_ifc_set_flow_table_root_out_bits {
3776 	u8         status[0x8];
3777 	u8         reserved_0[0x18];
3778 
3779 	u8         syndrome[0x20];
3780 
3781 	u8         reserved_1[0x40];
3782 };
3783 
3784 struct mlx5_ifc_set_flow_table_root_in_bits {
3785 	u8         opcode[0x10];
3786 	u8         reserved_0[0x10];
3787 
3788 	u8         reserved_1[0x10];
3789 	u8         op_mod[0x10];
3790 
3791 	u8         other_vport[0x1];
3792 	u8         reserved_2[0xf];
3793 	u8         vport_number[0x10];
3794 
3795 	u8         reserved_3[0x20];
3796 
3797 	u8         table_type[0x8];
3798 	u8         reserved_4[0x18];
3799 
3800 	u8         reserved_5[0x8];
3801 	u8         table_id[0x18];
3802 
3803 	u8         reserved_6[0x8];
3804 	u8         underlay_qpn[0x18];
3805 
3806 	u8         reserved_7[0x120];
3807 };
3808 
3809 struct mlx5_ifc_set_fte_out_bits {
3810 	u8         status[0x8];
3811 	u8         reserved_0[0x18];
3812 
3813 	u8         syndrome[0x20];
3814 
3815 	u8         reserved_1[0x40];
3816 };
3817 
3818 struct mlx5_ifc_set_fte_in_bits {
3819 	u8         opcode[0x10];
3820 	u8         reserved_0[0x10];
3821 
3822 	u8         reserved_1[0x10];
3823 	u8         op_mod[0x10];
3824 
3825 	u8         other_vport[0x1];
3826 	u8         reserved_2[0xf];
3827 	u8         vport_number[0x10];
3828 
3829 	u8         reserved_3[0x20];
3830 
3831 	u8         table_type[0x8];
3832 	u8         reserved_4[0x18];
3833 
3834 	u8         reserved_5[0x8];
3835 	u8         table_id[0x18];
3836 
3837 	u8         reserved_6[0x18];
3838 	u8         modify_enable_mask[0x8];
3839 
3840 	u8         reserved_7[0x20];
3841 
3842 	u8         flow_index[0x20];
3843 
3844 	u8         reserved_8[0xe0];
3845 
3846 	struct mlx5_ifc_flow_context_bits flow_context;
3847 };
3848 
3849 struct mlx5_ifc_set_driver_version_out_bits {
3850 	u8         status[0x8];
3851 	u8         reserved_0[0x18];
3852 
3853 	u8         syndrome[0x20];
3854 
3855 	u8         reserved_1[0x40];
3856 };
3857 
3858 struct mlx5_ifc_set_driver_version_in_bits {
3859 	u8         opcode[0x10];
3860 	u8         reserved_0[0x10];
3861 
3862 	u8         reserved_1[0x10];
3863 	u8         op_mod[0x10];
3864 
3865 	u8         reserved_2[0x40];
3866 
3867 	u8         driver_version[64][0x8];
3868 };
3869 
3870 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3871 	u8         status[0x8];
3872 	u8         reserved_0[0x18];
3873 
3874 	u8         syndrome[0x20];
3875 
3876 	u8         reserved_1[0x40];
3877 };
3878 
3879 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3880 	u8         opcode[0x10];
3881 	u8         reserved_0[0x10];
3882 
3883 	u8         reserved_1[0x10];
3884 	u8         op_mod[0x10];
3885 
3886 	u8         enable[0x1];
3887 	u8         reserved_2[0x1f];
3888 
3889 	u8         reserved_3[0x160];
3890 
3891 	struct mlx5_ifc_cmd_pas_bits pas;
3892 };
3893 
3894 struct mlx5_ifc_set_burst_size_out_bits {
3895 	u8         status[0x8];
3896 	u8         reserved_0[0x18];
3897 
3898 	u8         syndrome[0x20];
3899 
3900 	u8         reserved_1[0x40];
3901 };
3902 
3903 struct mlx5_ifc_set_burst_size_in_bits {
3904 	u8         opcode[0x10];
3905 	u8         reserved_0[0x10];
3906 
3907 	u8         reserved_1[0x10];
3908 	u8         op_mod[0x10];
3909 
3910 	u8         reserved_2[0x20];
3911 
3912 	u8         reserved_3[0x9];
3913 	u8         device_burst_size[0x17];
3914 };
3915 
3916 struct mlx5_ifc_rts2rts_qp_out_bits {
3917 	u8         status[0x8];
3918 	u8         reserved_0[0x18];
3919 
3920 	u8         syndrome[0x20];
3921 
3922 	u8         reserved_1[0x40];
3923 };
3924 
3925 struct mlx5_ifc_rts2rts_qp_in_bits {
3926 	u8         opcode[0x10];
3927 	u8         uid[0x10];
3928 
3929 	u8         reserved_1[0x10];
3930 	u8         op_mod[0x10];
3931 
3932 	u8         reserved_2[0x8];
3933 	u8         qpn[0x18];
3934 
3935 	u8         reserved_3[0x20];
3936 
3937 	u8         opt_param_mask[0x20];
3938 
3939 	u8         reserved_4[0x20];
3940 
3941 	struct mlx5_ifc_qpc_bits qpc;
3942 
3943 	u8         reserved_5[0x80];
3944 };
3945 
3946 struct mlx5_ifc_rtr2rts_qp_out_bits {
3947 	u8         status[0x8];
3948 	u8         reserved_0[0x18];
3949 
3950 	u8         syndrome[0x20];
3951 
3952 	u8         reserved_1[0x40];
3953 };
3954 
3955 struct mlx5_ifc_rtr2rts_qp_in_bits {
3956 	u8         opcode[0x10];
3957 	u8         uid[0x10];
3958 
3959 	u8         reserved_1[0x10];
3960 	u8         op_mod[0x10];
3961 
3962 	u8         reserved_2[0x8];
3963 	u8         qpn[0x18];
3964 
3965 	u8         reserved_3[0x20];
3966 
3967 	u8         opt_param_mask[0x20];
3968 
3969 	u8         reserved_4[0x20];
3970 
3971 	struct mlx5_ifc_qpc_bits qpc;
3972 
3973 	u8         reserved_5[0x80];
3974 };
3975 
3976 struct mlx5_ifc_rst2init_qp_out_bits {
3977 	u8         status[0x8];
3978 	u8         reserved_0[0x18];
3979 
3980 	u8         syndrome[0x20];
3981 
3982 	u8         reserved_1[0x40];
3983 };
3984 
3985 struct mlx5_ifc_rst2init_qp_in_bits {
3986 	u8         opcode[0x10];
3987 	u8         uid[0x10];
3988 
3989 	u8         reserved_1[0x10];
3990 	u8         op_mod[0x10];
3991 
3992 	u8         reserved_2[0x8];
3993 	u8         qpn[0x18];
3994 
3995 	u8         reserved_3[0x20];
3996 
3997 	u8         opt_param_mask[0x20];
3998 
3999 	u8         reserved_4[0x20];
4000 
4001 	struct mlx5_ifc_qpc_bits qpc;
4002 
4003 	u8         reserved_5[0x80];
4004 };
4005 
4006 struct mlx5_ifc_resume_qp_out_bits {
4007 	u8         status[0x8];
4008 	u8         reserved_0[0x18];
4009 
4010 	u8         syndrome[0x20];
4011 
4012 	u8         reserved_1[0x40];
4013 };
4014 
4015 struct mlx5_ifc_resume_qp_in_bits {
4016 	u8         opcode[0x10];
4017 	u8         reserved_0[0x10];
4018 
4019 	u8         reserved_1[0x10];
4020 	u8         op_mod[0x10];
4021 
4022 	u8         reserved_2[0x8];
4023 	u8         qpn[0x18];
4024 
4025 	u8         reserved_3[0x20];
4026 };
4027 
4028 struct mlx5_ifc_query_xrc_srq_out_bits {
4029 	u8         status[0x8];
4030 	u8         reserved_0[0x18];
4031 
4032 	u8         syndrome[0x20];
4033 
4034 	u8         reserved_1[0x40];
4035 
4036 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4037 
4038 	u8         reserved_2[0x600];
4039 
4040 	u8         pas[0][0x40];
4041 };
4042 
4043 struct mlx5_ifc_query_xrc_srq_in_bits {
4044 	u8         opcode[0x10];
4045 	u8         reserved_0[0x10];
4046 
4047 	u8         reserved_1[0x10];
4048 	u8         op_mod[0x10];
4049 
4050 	u8         reserved_2[0x8];
4051 	u8         xrc_srqn[0x18];
4052 
4053 	u8         reserved_3[0x20];
4054 };
4055 
4056 struct mlx5_ifc_query_wol_rol_out_bits {
4057 	u8         status[0x8];
4058 	u8         reserved_0[0x18];
4059 
4060 	u8         syndrome[0x20];
4061 
4062 	u8         reserved_1[0x10];
4063 	u8         rol_mode[0x8];
4064 	u8         wol_mode[0x8];
4065 
4066 	u8         reserved_2[0x20];
4067 };
4068 
4069 struct mlx5_ifc_query_wol_rol_in_bits {
4070 	u8         opcode[0x10];
4071 	u8         reserved_0[0x10];
4072 
4073 	u8         reserved_1[0x10];
4074 	u8         op_mod[0x10];
4075 
4076 	u8         reserved_2[0x40];
4077 };
4078 
4079 enum {
4080 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4081 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4082 };
4083 
4084 struct mlx5_ifc_query_vport_state_out_bits {
4085 	u8         status[0x8];
4086 	u8         reserved_0[0x18];
4087 
4088 	u8         syndrome[0x20];
4089 
4090 	u8         reserved_1[0x20];
4091 
4092 	u8         reserved_2[0x18];
4093 	u8         admin_state[0x4];
4094 	u8         state[0x4];
4095 };
4096 
4097 enum {
4098 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
4099 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
4100 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
4101 };
4102 
4103 struct mlx5_ifc_query_vport_state_in_bits {
4104 	u8         opcode[0x10];
4105 	u8         reserved_0[0x10];
4106 
4107 	u8         reserved_1[0x10];
4108 	u8         op_mod[0x10];
4109 
4110 	u8         other_vport[0x1];
4111 	u8         reserved_2[0xf];
4112 	u8         vport_number[0x10];
4113 
4114 	u8         reserved_3[0x20];
4115 };
4116 
4117 struct mlx5_ifc_query_vnic_env_out_bits {
4118 	u8         status[0x8];
4119 	u8         reserved_at_8[0x18];
4120 
4121 	u8         syndrome[0x20];
4122 
4123 	u8         reserved_at_40[0x40];
4124 
4125 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4126 };
4127 
4128 enum {
4129 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4130 };
4131 
4132 struct mlx5_ifc_query_vnic_env_in_bits {
4133 	u8         opcode[0x10];
4134 	u8         reserved_at_10[0x10];
4135 
4136 	u8         reserved_at_20[0x10];
4137 	u8         op_mod[0x10];
4138 
4139 	u8         other_vport[0x1];
4140 	u8         reserved_at_41[0xf];
4141 	u8         vport_number[0x10];
4142 
4143 	u8         reserved_at_60[0x20];
4144 };
4145 
4146 struct mlx5_ifc_query_vport_counter_out_bits {
4147 	u8         status[0x8];
4148 	u8         reserved_0[0x18];
4149 
4150 	u8         syndrome[0x20];
4151 
4152 	u8         reserved_1[0x40];
4153 
4154 	struct mlx5_ifc_traffic_counter_bits received_errors;
4155 
4156 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
4157 
4158 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4159 
4160 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4161 
4162 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4163 
4164 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4165 
4166 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4167 
4168 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4169 
4170 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4171 
4172 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4173 
4174 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4175 
4176 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4177 
4178 	u8         reserved_2[0xa00];
4179 };
4180 
4181 enum {
4182 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4183 };
4184 
4185 struct mlx5_ifc_query_vport_counter_in_bits {
4186 	u8         opcode[0x10];
4187 	u8         reserved_0[0x10];
4188 
4189 	u8         reserved_1[0x10];
4190 	u8         op_mod[0x10];
4191 
4192 	u8         other_vport[0x1];
4193 	u8         reserved_2[0xb];
4194 	u8         port_num[0x4];
4195 	u8         vport_number[0x10];
4196 
4197 	u8         reserved_3[0x60];
4198 
4199 	u8         clear[0x1];
4200 	u8         reserved_4[0x1f];
4201 
4202 	u8         reserved_5[0x20];
4203 };
4204 
4205 struct mlx5_ifc_query_tis_out_bits {
4206 	u8         status[0x8];
4207 	u8         reserved_0[0x18];
4208 
4209 	u8         syndrome[0x20];
4210 
4211 	u8         reserved_1[0x40];
4212 
4213 	struct mlx5_ifc_tisc_bits tis_context;
4214 };
4215 
4216 struct mlx5_ifc_query_tis_in_bits {
4217 	u8         opcode[0x10];
4218 	u8         reserved_0[0x10];
4219 
4220 	u8         reserved_1[0x10];
4221 	u8         op_mod[0x10];
4222 
4223 	u8         reserved_2[0x8];
4224 	u8         tisn[0x18];
4225 
4226 	u8         reserved_3[0x20];
4227 };
4228 
4229 struct mlx5_ifc_query_tir_out_bits {
4230 	u8         status[0x8];
4231 	u8         reserved_0[0x18];
4232 
4233 	u8         syndrome[0x20];
4234 
4235 	u8         reserved_1[0xc0];
4236 
4237 	struct mlx5_ifc_tirc_bits tir_context;
4238 };
4239 
4240 struct mlx5_ifc_query_tir_in_bits {
4241 	u8         opcode[0x10];
4242 	u8         reserved_0[0x10];
4243 
4244 	u8         reserved_1[0x10];
4245 	u8         op_mod[0x10];
4246 
4247 	u8         reserved_2[0x8];
4248 	u8         tirn[0x18];
4249 
4250 	u8         reserved_3[0x20];
4251 };
4252 
4253 struct mlx5_ifc_query_srq_out_bits {
4254 	u8         status[0x8];
4255 	u8         reserved_0[0x18];
4256 
4257 	u8         syndrome[0x20];
4258 
4259 	u8         reserved_1[0x40];
4260 
4261 	struct mlx5_ifc_srqc_bits srq_context_entry;
4262 
4263 	u8         reserved_2[0x600];
4264 
4265 	u8         pas[0][0x40];
4266 };
4267 
4268 struct mlx5_ifc_query_srq_in_bits {
4269 	u8         opcode[0x10];
4270 	u8         reserved_0[0x10];
4271 
4272 	u8         reserved_1[0x10];
4273 	u8         op_mod[0x10];
4274 
4275 	u8         reserved_2[0x8];
4276 	u8         srqn[0x18];
4277 
4278 	u8         reserved_3[0x20];
4279 };
4280 
4281 struct mlx5_ifc_query_sq_out_bits {
4282 	u8         status[0x8];
4283 	u8         reserved_0[0x18];
4284 
4285 	u8         syndrome[0x20];
4286 
4287 	u8         reserved_1[0xc0];
4288 
4289 	struct mlx5_ifc_sqc_bits sq_context;
4290 };
4291 
4292 struct mlx5_ifc_query_sq_in_bits {
4293 	u8         opcode[0x10];
4294 	u8         reserved_0[0x10];
4295 
4296 	u8         reserved_1[0x10];
4297 	u8         op_mod[0x10];
4298 
4299 	u8         reserved_2[0x8];
4300 	u8         sqn[0x18];
4301 
4302 	u8         reserved_3[0x20];
4303 };
4304 
4305 struct mlx5_ifc_query_special_contexts_out_bits {
4306 	u8         status[0x8];
4307 	u8         reserved_0[0x18];
4308 
4309 	u8         syndrome[0x20];
4310 
4311 	u8	   dump_fill_mkey[0x20];
4312 
4313 	u8         resd_lkey[0x20];
4314 };
4315 
4316 struct mlx5_ifc_query_special_contexts_in_bits {
4317 	u8         opcode[0x10];
4318 	u8         reserved_0[0x10];
4319 
4320 	u8         reserved_1[0x10];
4321 	u8         op_mod[0x10];
4322 
4323 	u8         reserved_2[0x40];
4324 };
4325 
4326 struct mlx5_ifc_query_scheduling_element_out_bits {
4327 	u8         status[0x8];
4328 	u8         reserved_at_8[0x18];
4329 
4330 	u8         syndrome[0x20];
4331 
4332 	u8         reserved_at_40[0xc0];
4333 
4334 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
4335 
4336 	u8         reserved_at_300[0x100];
4337 };
4338 
4339 enum {
4340 	MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4341 };
4342 
4343 struct mlx5_ifc_query_scheduling_element_in_bits {
4344 	u8         opcode[0x10];
4345 	u8         reserved_at_10[0x10];
4346 
4347 	u8         reserved_at_20[0x10];
4348 	u8         op_mod[0x10];
4349 
4350 	u8         scheduling_hierarchy[0x8];
4351 	u8         reserved_at_48[0x18];
4352 
4353 	u8         scheduling_element_id[0x20];
4354 
4355 	u8         reserved_at_80[0x180];
4356 };
4357 
4358 struct mlx5_ifc_query_rqt_out_bits {
4359 	u8         status[0x8];
4360 	u8         reserved_0[0x18];
4361 
4362 	u8         syndrome[0x20];
4363 
4364 	u8         reserved_1[0xc0];
4365 
4366 	struct mlx5_ifc_rqtc_bits rqt_context;
4367 };
4368 
4369 struct mlx5_ifc_query_rqt_in_bits {
4370 	u8         opcode[0x10];
4371 	u8         reserved_0[0x10];
4372 
4373 	u8         reserved_1[0x10];
4374 	u8         op_mod[0x10];
4375 
4376 	u8         reserved_2[0x8];
4377 	u8         rqtn[0x18];
4378 
4379 	u8         reserved_3[0x20];
4380 };
4381 
4382 struct mlx5_ifc_query_rq_out_bits {
4383 	u8         status[0x8];
4384 	u8         reserved_0[0x18];
4385 
4386 	u8         syndrome[0x20];
4387 
4388 	u8         reserved_1[0xc0];
4389 
4390 	struct mlx5_ifc_rqc_bits rq_context;
4391 };
4392 
4393 struct mlx5_ifc_query_rq_in_bits {
4394 	u8         opcode[0x10];
4395 	u8         reserved_0[0x10];
4396 
4397 	u8         reserved_1[0x10];
4398 	u8         op_mod[0x10];
4399 
4400 	u8         reserved_2[0x8];
4401 	u8         rqn[0x18];
4402 
4403 	u8         reserved_3[0x20];
4404 };
4405 
4406 struct mlx5_ifc_query_roce_address_out_bits {
4407 	u8         status[0x8];
4408 	u8         reserved_0[0x18];
4409 
4410 	u8         syndrome[0x20];
4411 
4412 	u8         reserved_1[0x40];
4413 
4414 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4415 };
4416 
4417 struct mlx5_ifc_query_roce_address_in_bits {
4418 	u8         opcode[0x10];
4419 	u8         reserved_0[0x10];
4420 
4421 	u8         reserved_1[0x10];
4422 	u8         op_mod[0x10];
4423 
4424 	u8         roce_address_index[0x10];
4425 	u8         reserved_2[0x10];
4426 
4427 	u8         reserved_3[0x20];
4428 };
4429 
4430 struct mlx5_ifc_query_rmp_out_bits {
4431 	u8         status[0x8];
4432 	u8         reserved_0[0x18];
4433 
4434 	u8         syndrome[0x20];
4435 
4436 	u8         reserved_1[0xc0];
4437 
4438 	struct mlx5_ifc_rmpc_bits rmp_context;
4439 };
4440 
4441 struct mlx5_ifc_query_rmp_in_bits {
4442 	u8         opcode[0x10];
4443 	u8         reserved_0[0x10];
4444 
4445 	u8         reserved_1[0x10];
4446 	u8         op_mod[0x10];
4447 
4448 	u8         reserved_2[0x8];
4449 	u8         rmpn[0x18];
4450 
4451 	u8         reserved_3[0x20];
4452 };
4453 
4454 struct mlx5_ifc_query_rdb_out_bits {
4455 	u8         status[0x8];
4456 	u8         reserved_0[0x18];
4457 
4458 	u8         syndrome[0x20];
4459 
4460 	u8         reserved_1[0x20];
4461 
4462 	u8         reserved_2[0x18];
4463 	u8         rdb_list_size[0x8];
4464 
4465 	struct mlx5_ifc_rdbc_bits rdb_context[0];
4466 };
4467 
4468 struct mlx5_ifc_query_rdb_in_bits {
4469 	u8         opcode[0x10];
4470 	u8         reserved_0[0x10];
4471 
4472 	u8         reserved_1[0x10];
4473 	u8         op_mod[0x10];
4474 
4475 	u8         reserved_2[0x8];
4476 	u8         qpn[0x18];
4477 
4478 	u8         reserved_3[0x20];
4479 };
4480 
4481 struct mlx5_ifc_query_qp_out_bits {
4482 	u8         status[0x8];
4483 	u8         reserved_0[0x18];
4484 
4485 	u8         syndrome[0x20];
4486 
4487 	u8         reserved_1[0x40];
4488 
4489 	u8         opt_param_mask[0x20];
4490 
4491 	u8         reserved_2[0x20];
4492 
4493 	struct mlx5_ifc_qpc_bits qpc;
4494 
4495 	u8         reserved_3[0x80];
4496 
4497 	u8         pas[0][0x40];
4498 };
4499 
4500 struct mlx5_ifc_query_qp_in_bits {
4501 	u8         opcode[0x10];
4502 	u8         reserved_0[0x10];
4503 
4504 	u8         reserved_1[0x10];
4505 	u8         op_mod[0x10];
4506 
4507 	u8         reserved_2[0x8];
4508 	u8         qpn[0x18];
4509 
4510 	u8         reserved_3[0x20];
4511 };
4512 
4513 struct mlx5_ifc_query_q_counter_out_bits {
4514 	u8         status[0x8];
4515 	u8         reserved_0[0x18];
4516 
4517 	u8         syndrome[0x20];
4518 
4519 	u8         reserved_1[0x40];
4520 
4521 	u8         rx_write_requests[0x20];
4522 
4523 	u8         reserved_2[0x20];
4524 
4525 	u8         rx_read_requests[0x20];
4526 
4527 	u8         reserved_3[0x20];
4528 
4529 	u8         rx_atomic_requests[0x20];
4530 
4531 	u8         reserved_4[0x20];
4532 
4533 	u8         rx_dct_connect[0x20];
4534 
4535 	u8         reserved_5[0x20];
4536 
4537 	u8         out_of_buffer[0x20];
4538 
4539 	u8         reserved_7[0x20];
4540 
4541 	u8         out_of_sequence[0x20];
4542 
4543 	u8         reserved_8[0x20];
4544 
4545 	u8         duplicate_request[0x20];
4546 
4547 	u8         reserved_9[0x20];
4548 
4549 	u8         rnr_nak_retry_err[0x20];
4550 
4551 	u8         reserved_10[0x20];
4552 
4553 	u8         packet_seq_err[0x20];
4554 
4555 	u8         reserved_11[0x20];
4556 
4557 	u8         implied_nak_seq_err[0x20];
4558 
4559 	u8         reserved_12[0x20];
4560 
4561 	u8         local_ack_timeout_err[0x20];
4562 
4563 	u8         reserved_13[0x20];
4564 
4565 	u8         resp_rnr_nak[0x20];
4566 
4567 	u8         reserved_14[0x20];
4568 
4569 	u8         req_rnr_retries_exceeded[0x20];
4570 
4571 	u8         reserved_15[0x460];
4572 };
4573 
4574 struct mlx5_ifc_query_q_counter_in_bits {
4575 	u8         opcode[0x10];
4576 	u8         reserved_0[0x10];
4577 
4578 	u8         reserved_1[0x10];
4579 	u8         op_mod[0x10];
4580 
4581 	u8         reserved_2[0x80];
4582 
4583 	u8         clear[0x1];
4584 	u8         reserved_3[0x1f];
4585 
4586 	u8         reserved_4[0x18];
4587 	u8         counter_set_id[0x8];
4588 };
4589 
4590 struct mlx5_ifc_query_pages_out_bits {
4591 	u8         status[0x8];
4592 	u8         reserved_0[0x18];
4593 
4594 	u8         syndrome[0x20];
4595 
4596 	u8         reserved_1[0x10];
4597 	u8         function_id[0x10];
4598 
4599 	u8         num_pages[0x20];
4600 };
4601 
4602 enum {
4603 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES	  = 0x1,
4604 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES	  = 0x2,
4605 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4606 };
4607 
4608 struct mlx5_ifc_query_pages_in_bits {
4609 	u8         opcode[0x10];
4610 	u8         reserved_0[0x10];
4611 
4612 	u8         reserved_1[0x10];
4613 	u8         op_mod[0x10];
4614 
4615 	u8         reserved_2[0x10];
4616 	u8         function_id[0x10];
4617 
4618 	u8         reserved_3[0x20];
4619 };
4620 
4621 struct mlx5_ifc_query_nic_vport_context_out_bits {
4622 	u8         status[0x8];
4623 	u8         reserved_0[0x18];
4624 
4625 	u8         syndrome[0x20];
4626 
4627 	u8         reserved_1[0x40];
4628 
4629 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4630 };
4631 
4632 struct mlx5_ifc_query_nic_vport_context_in_bits {
4633 	u8         opcode[0x10];
4634 	u8         reserved_0[0x10];
4635 
4636 	u8         reserved_1[0x10];
4637 	u8         op_mod[0x10];
4638 
4639 	u8         other_vport[0x1];
4640 	u8         reserved_2[0xf];
4641 	u8         vport_number[0x10];
4642 
4643 	u8         reserved_3[0x5];
4644 	u8         allowed_list_type[0x3];
4645 	u8         reserved_4[0x18];
4646 };
4647 
4648 struct mlx5_ifc_query_mkey_out_bits {
4649 	u8         status[0x8];
4650 	u8         reserved_0[0x18];
4651 
4652 	u8         syndrome[0x20];
4653 
4654 	u8         reserved_1[0x40];
4655 
4656 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4657 
4658 	u8         reserved_2[0x600];
4659 
4660 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4661 
4662 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4663 };
4664 
4665 struct mlx5_ifc_query_mkey_in_bits {
4666 	u8         opcode[0x10];
4667 	u8         reserved_0[0x10];
4668 
4669 	u8         reserved_1[0x10];
4670 	u8         op_mod[0x10];
4671 
4672 	u8         reserved_2[0x8];
4673 	u8         mkey_index[0x18];
4674 
4675 	u8         pg_access[0x1];
4676 	u8         reserved_3[0x1f];
4677 };
4678 
4679 struct mlx5_ifc_query_mad_demux_out_bits {
4680 	u8         status[0x8];
4681 	u8         reserved_0[0x18];
4682 
4683 	u8         syndrome[0x20];
4684 
4685 	u8         reserved_1[0x40];
4686 
4687 	u8         mad_dumux_parameters_block[0x20];
4688 };
4689 
4690 struct mlx5_ifc_query_mad_demux_in_bits {
4691 	u8         opcode[0x10];
4692 	u8         reserved_0[0x10];
4693 
4694 	u8         reserved_1[0x10];
4695 	u8         op_mod[0x10];
4696 
4697 	u8         reserved_2[0x40];
4698 };
4699 
4700 struct mlx5_ifc_query_l2_table_entry_out_bits {
4701 	u8         status[0x8];
4702 	u8         reserved_0[0x18];
4703 
4704 	u8         syndrome[0x20];
4705 
4706 	u8         reserved_1[0xa0];
4707 
4708 	u8         reserved_2[0x13];
4709 	u8         vlan_valid[0x1];
4710 	u8         vlan[0xc];
4711 
4712 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4713 
4714 	u8         reserved_3[0xc0];
4715 };
4716 
4717 struct mlx5_ifc_query_l2_table_entry_in_bits {
4718 	u8         opcode[0x10];
4719 	u8         reserved_0[0x10];
4720 
4721 	u8         reserved_1[0x10];
4722 	u8         op_mod[0x10];
4723 
4724 	u8         reserved_2[0x60];
4725 
4726 	u8         reserved_3[0x8];
4727 	u8         table_index[0x18];
4728 
4729 	u8         reserved_4[0x140];
4730 };
4731 
4732 struct mlx5_ifc_query_issi_out_bits {
4733 	u8         status[0x8];
4734 	u8         reserved_0[0x18];
4735 
4736 	u8         syndrome[0x20];
4737 
4738 	u8         reserved_1[0x10];
4739 	u8         current_issi[0x10];
4740 
4741 	u8         reserved_2[0xa0];
4742 
4743 	u8         supported_issi_reserved[76][0x8];
4744 	u8         supported_issi_dw0[0x20];
4745 };
4746 
4747 struct mlx5_ifc_query_issi_in_bits {
4748 	u8         opcode[0x10];
4749 	u8         reserved_0[0x10];
4750 
4751 	u8         reserved_1[0x10];
4752 	u8         op_mod[0x10];
4753 
4754 	u8         reserved_2[0x40];
4755 };
4756 
4757 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4758 	u8         status[0x8];
4759 	u8         reserved_0[0x18];
4760 
4761 	u8         syndrome[0x20];
4762 
4763 	u8         reserved_1[0x40];
4764 
4765 	struct mlx5_ifc_pkey_bits pkey[0];
4766 };
4767 
4768 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4769 	u8         opcode[0x10];
4770 	u8         reserved_0[0x10];
4771 
4772 	u8         reserved_1[0x10];
4773 	u8         op_mod[0x10];
4774 
4775 	u8         other_vport[0x1];
4776 	u8         reserved_2[0xb];
4777 	u8         port_num[0x4];
4778 	u8         vport_number[0x10];
4779 
4780 	u8         reserved_3[0x10];
4781 	u8         pkey_index[0x10];
4782 };
4783 
4784 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4785 	u8         status[0x8];
4786 	u8         reserved_0[0x18];
4787 
4788 	u8         syndrome[0x20];
4789 
4790 	u8         reserved_1[0x20];
4791 
4792 	u8         gids_num[0x10];
4793 	u8         reserved_2[0x10];
4794 
4795 	struct mlx5_ifc_array128_auto_bits gid[0];
4796 };
4797 
4798 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4799 	u8         opcode[0x10];
4800 	u8         reserved_0[0x10];
4801 
4802 	u8         reserved_1[0x10];
4803 	u8         op_mod[0x10];
4804 
4805 	u8         other_vport[0x1];
4806 	u8         reserved_2[0xb];
4807 	u8         port_num[0x4];
4808 	u8         vport_number[0x10];
4809 
4810 	u8         reserved_3[0x10];
4811 	u8         gid_index[0x10];
4812 };
4813 
4814 struct mlx5_ifc_query_hca_vport_context_out_bits {
4815 	u8         status[0x8];
4816 	u8         reserved_0[0x18];
4817 
4818 	u8         syndrome[0x20];
4819 
4820 	u8         reserved_1[0x40];
4821 
4822 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4823 };
4824 
4825 struct mlx5_ifc_query_hca_vport_context_in_bits {
4826 	u8         opcode[0x10];
4827 	u8         reserved_0[0x10];
4828 
4829 	u8         reserved_1[0x10];
4830 	u8         op_mod[0x10];
4831 
4832 	u8         other_vport[0x1];
4833 	u8         reserved_2[0xb];
4834 	u8         port_num[0x4];
4835 	u8         vport_number[0x10];
4836 
4837 	u8         reserved_3[0x20];
4838 };
4839 
4840 struct mlx5_ifc_query_hca_cap_out_bits {
4841 	u8         status[0x8];
4842 	u8         reserved_0[0x18];
4843 
4844 	u8         syndrome[0x20];
4845 
4846 	u8         reserved_1[0x40];
4847 
4848 	union mlx5_ifc_hca_cap_union_bits capability;
4849 };
4850 
4851 struct mlx5_ifc_query_hca_cap_in_bits {
4852 	u8         opcode[0x10];
4853 	u8         reserved_0[0x10];
4854 
4855 	u8         reserved_1[0x10];
4856 	u8         op_mod[0x10];
4857 
4858 	u8         reserved_2[0x40];
4859 };
4860 
4861 struct mlx5_ifc_query_flow_table_out_bits {
4862 	u8         status[0x8];
4863 	u8         reserved_at_8[0x18];
4864 
4865 	u8         syndrome[0x20];
4866 
4867 	u8         reserved_at_40[0x80];
4868 
4869 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
4870 };
4871 
4872 struct mlx5_ifc_query_flow_table_in_bits {
4873 	u8         opcode[0x10];
4874 	u8         reserved_0[0x10];
4875 
4876 	u8         reserved_1[0x10];
4877 	u8         op_mod[0x10];
4878 
4879 	u8         other_vport[0x1];
4880 	u8         reserved_2[0xf];
4881 	u8         vport_number[0x10];
4882 
4883 	u8         reserved_3[0x20];
4884 
4885 	u8         table_type[0x8];
4886 	u8         reserved_4[0x18];
4887 
4888 	u8         reserved_5[0x8];
4889 	u8         table_id[0x18];
4890 
4891 	u8         reserved_6[0x140];
4892 };
4893 
4894 struct mlx5_ifc_query_fte_out_bits {
4895 	u8         status[0x8];
4896 	u8         reserved_0[0x18];
4897 
4898 	u8         syndrome[0x20];
4899 
4900 	u8         reserved_1[0x1c0];
4901 
4902 	struct mlx5_ifc_flow_context_bits flow_context;
4903 };
4904 
4905 struct mlx5_ifc_query_fte_in_bits {
4906 	u8         opcode[0x10];
4907 	u8         reserved_0[0x10];
4908 
4909 	u8         reserved_1[0x10];
4910 	u8         op_mod[0x10];
4911 
4912 	u8         other_vport[0x1];
4913 	u8         reserved_2[0xf];
4914 	u8         vport_number[0x10];
4915 
4916 	u8         reserved_3[0x20];
4917 
4918 	u8         table_type[0x8];
4919 	u8         reserved_4[0x18];
4920 
4921 	u8         reserved_5[0x8];
4922 	u8         table_id[0x18];
4923 
4924 	u8         reserved_6[0x40];
4925 
4926 	u8         flow_index[0x20];
4927 
4928 	u8         reserved_7[0xe0];
4929 };
4930 
4931 enum {
4932 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4933 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4934 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4935 };
4936 
4937 struct mlx5_ifc_query_flow_group_out_bits {
4938 	u8         status[0x8];
4939 	u8         reserved_0[0x18];
4940 
4941 	u8         syndrome[0x20];
4942 
4943 	u8         reserved_1[0xa0];
4944 
4945 	u8         start_flow_index[0x20];
4946 
4947 	u8         reserved_2[0x20];
4948 
4949 	u8         end_flow_index[0x20];
4950 
4951 	u8         reserved_3[0xa0];
4952 
4953 	u8         reserved_4[0x18];
4954 	u8         match_criteria_enable[0x8];
4955 
4956 	struct mlx5_ifc_fte_match_param_bits match_criteria;
4957 
4958 	u8         reserved_5[0xe00];
4959 };
4960 
4961 struct mlx5_ifc_query_flow_group_in_bits {
4962 	u8         opcode[0x10];
4963 	u8         reserved_0[0x10];
4964 
4965 	u8         reserved_1[0x10];
4966 	u8         op_mod[0x10];
4967 
4968 	u8         other_vport[0x1];
4969 	u8         reserved_2[0xf];
4970 	u8         vport_number[0x10];
4971 
4972 	u8         reserved_3[0x20];
4973 
4974 	u8         table_type[0x8];
4975 	u8         reserved_4[0x18];
4976 
4977 	u8         reserved_5[0x8];
4978 	u8         table_id[0x18];
4979 
4980 	u8         group_id[0x20];
4981 
4982 	u8         reserved_6[0x120];
4983 };
4984 
4985 struct mlx5_ifc_query_flow_counter_out_bits {
4986 	u8         status[0x8];
4987 	u8         reserved_at_8[0x18];
4988 
4989 	u8         syndrome[0x20];
4990 
4991 	u8         reserved_at_40[0x40];
4992 
4993 	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4994 };
4995 
4996 struct mlx5_ifc_query_flow_counter_in_bits {
4997 	u8         opcode[0x10];
4998 	u8         reserved_at_10[0x10];
4999 
5000 	u8         reserved_at_20[0x10];
5001 	u8         op_mod[0x10];
5002 
5003 	u8         reserved_at_40[0x80];
5004 
5005 	u8         clear[0x1];
5006 	u8         reserved_at_c1[0xf];
5007 	u8         num_of_counters[0x10];
5008 
5009 	u8         reserved_at_e0[0x10];
5010 	u8         flow_counter_id[0x10];
5011 };
5012 
5013 struct mlx5_ifc_query_esw_vport_context_out_bits {
5014 	u8         status[0x8];
5015 	u8         reserved_0[0x18];
5016 
5017 	u8         syndrome[0x20];
5018 
5019 	u8         reserved_1[0x40];
5020 
5021 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5022 };
5023 
5024 struct mlx5_ifc_query_esw_vport_context_in_bits {
5025 	u8         opcode[0x10];
5026 	u8         reserved_0[0x10];
5027 
5028 	u8         reserved_1[0x10];
5029 	u8         op_mod[0x10];
5030 
5031 	u8         other_vport[0x1];
5032 	u8         reserved_2[0xf];
5033 	u8         vport_number[0x10];
5034 
5035 	u8         reserved_3[0x20];
5036 };
5037 
5038 struct mlx5_ifc_query_eq_out_bits {
5039 	u8         status[0x8];
5040 	u8         reserved_0[0x18];
5041 
5042 	u8         syndrome[0x20];
5043 
5044 	u8         reserved_1[0x40];
5045 
5046 	struct mlx5_ifc_eqc_bits eq_context_entry;
5047 
5048 	u8         reserved_2[0x40];
5049 
5050 	u8         event_bitmask[0x40];
5051 
5052 	u8         reserved_3[0x580];
5053 
5054 	u8         pas[0][0x40];
5055 };
5056 
5057 struct mlx5_ifc_query_eq_in_bits {
5058 	u8         opcode[0x10];
5059 	u8         reserved_0[0x10];
5060 
5061 	u8         reserved_1[0x10];
5062 	u8         op_mod[0x10];
5063 
5064 	u8         reserved_2[0x18];
5065 	u8         eq_number[0x8];
5066 
5067 	u8         reserved_3[0x20];
5068 };
5069 
5070 struct mlx5_ifc_query_dct_out_bits {
5071 	u8         status[0x8];
5072 	u8         reserved_0[0x18];
5073 
5074 	u8         syndrome[0x20];
5075 
5076 	u8         reserved_1[0x40];
5077 
5078 	struct mlx5_ifc_dctc_bits dct_context_entry;
5079 
5080 	u8         reserved_2[0x180];
5081 };
5082 
5083 struct mlx5_ifc_query_dct_in_bits {
5084 	u8         opcode[0x10];
5085 	u8         reserved_0[0x10];
5086 
5087 	u8         reserved_1[0x10];
5088 	u8         op_mod[0x10];
5089 
5090 	u8         reserved_2[0x8];
5091 	u8         dctn[0x18];
5092 
5093 	u8         reserved_3[0x20];
5094 };
5095 
5096 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
5097 	u8         status[0x8];
5098 	u8         reserved_0[0x18];
5099 
5100 	u8         syndrome[0x20];
5101 
5102 	u8         enable[0x1];
5103 	u8         reserved_1[0x1f];
5104 
5105 	u8         reserved_2[0x160];
5106 
5107 	struct mlx5_ifc_cmd_pas_bits pas;
5108 };
5109 
5110 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
5111 	u8         opcode[0x10];
5112 	u8         reserved_0[0x10];
5113 
5114 	u8         reserved_1[0x10];
5115 	u8         op_mod[0x10];
5116 
5117 	u8         reserved_2[0x40];
5118 };
5119 
5120 struct mlx5_ifc_diagnostic_cntr_struct_bits {
5121 	u8         counter_id[0x10];
5122 	u8         sample_id[0x10];
5123 
5124 	u8         time_stamp_31_0[0x20];
5125 
5126 	u8         counter_value_h[0x20];
5127 
5128 	u8         counter_value_l[0x20];
5129 };
5130 
5131 enum {
5132 	MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_ENABLE   = 0x1,
5133 	MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_DISABLE  = 0x0,
5134 };
5135 
5136 struct mlx5_ifc_query_cq_out_bits {
5137 	u8         status[0x8];
5138 	u8         reserved_0[0x18];
5139 
5140 	u8         syndrome[0x20];
5141 
5142 	u8         reserved_1[0x40];
5143 
5144 	struct mlx5_ifc_cqc_bits cq_context;
5145 
5146 	u8         reserved_2[0x600];
5147 
5148 	u8         pas[0][0x40];
5149 };
5150 
5151 struct mlx5_ifc_query_cq_in_bits {
5152 	u8         opcode[0x10];
5153 	u8         reserved_0[0x10];
5154 
5155 	u8         reserved_1[0x10];
5156 	u8         op_mod[0x10];
5157 
5158 	u8         reserved_2[0x8];
5159 	u8         cqn[0x18];
5160 
5161 	u8         reserved_3[0x20];
5162 };
5163 
5164 struct mlx5_ifc_query_cong_status_out_bits {
5165 	u8         status[0x8];
5166 	u8         reserved_0[0x18];
5167 
5168 	u8         syndrome[0x20];
5169 
5170 	u8         reserved_1[0x20];
5171 
5172 	u8         enable[0x1];
5173 	u8         tag_enable[0x1];
5174 	u8         reserved_2[0x1e];
5175 };
5176 
5177 struct mlx5_ifc_query_cong_status_in_bits {
5178 	u8         opcode[0x10];
5179 	u8         reserved_0[0x10];
5180 
5181 	u8         reserved_1[0x10];
5182 	u8         op_mod[0x10];
5183 
5184 	u8         reserved_2[0x18];
5185 	u8         priority[0x4];
5186 	u8         cong_protocol[0x4];
5187 
5188 	u8         reserved_3[0x20];
5189 };
5190 
5191 struct mlx5_ifc_query_cong_statistics_out_bits {
5192 	u8         status[0x8];
5193 	u8         reserved_0[0x18];
5194 
5195 	u8         syndrome[0x20];
5196 
5197 	u8         reserved_1[0x40];
5198 
5199 	u8         rp_cur_flows[0x20];
5200 
5201 	u8         sum_flows[0x20];
5202 
5203 	u8         rp_cnp_ignored_high[0x20];
5204 
5205 	u8         rp_cnp_ignored_low[0x20];
5206 
5207 	u8         rp_cnp_handled_high[0x20];
5208 
5209 	u8         rp_cnp_handled_low[0x20];
5210 
5211 	u8         reserved_2[0x100];
5212 
5213 	u8         time_stamp_high[0x20];
5214 
5215 	u8         time_stamp_low[0x20];
5216 
5217 	u8         accumulators_period[0x20];
5218 
5219 	u8         np_ecn_marked_roce_packets_high[0x20];
5220 
5221 	u8         np_ecn_marked_roce_packets_low[0x20];
5222 
5223 	u8         np_cnp_sent_high[0x20];
5224 
5225 	u8         np_cnp_sent_low[0x20];
5226 
5227 	u8         reserved_3[0x560];
5228 };
5229 
5230 struct mlx5_ifc_query_cong_statistics_in_bits {
5231 	u8         opcode[0x10];
5232 	u8         reserved_0[0x10];
5233 
5234 	u8         reserved_1[0x10];
5235 	u8         op_mod[0x10];
5236 
5237 	u8         clear[0x1];
5238 	u8         reserved_2[0x1f];
5239 
5240 	u8         reserved_3[0x20];
5241 };
5242 
5243 struct mlx5_ifc_query_cong_params_out_bits {
5244 	u8         status[0x8];
5245 	u8         reserved_0[0x18];
5246 
5247 	u8         syndrome[0x20];
5248 
5249 	u8         reserved_1[0x40];
5250 
5251 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5252 };
5253 
5254 struct mlx5_ifc_query_cong_params_in_bits {
5255 	u8         opcode[0x10];
5256 	u8         reserved_0[0x10];
5257 
5258 	u8         reserved_1[0x10];
5259 	u8         op_mod[0x10];
5260 
5261 	u8         reserved_2[0x1c];
5262 	u8         cong_protocol[0x4];
5263 
5264 	u8         reserved_3[0x20];
5265 };
5266 
5267 struct mlx5_ifc_query_burst_size_out_bits {
5268 	u8         status[0x8];
5269 	u8         reserved_0[0x18];
5270 
5271 	u8         syndrome[0x20];
5272 
5273 	u8         reserved_1[0x20];
5274 
5275 	u8         reserved_2[0x9];
5276 	u8         device_burst_size[0x17];
5277 };
5278 
5279 struct mlx5_ifc_query_burst_size_in_bits {
5280 	u8         opcode[0x10];
5281 	u8         reserved_0[0x10];
5282 
5283 	u8         reserved_1[0x10];
5284 	u8         op_mod[0x10];
5285 
5286 	u8         reserved_2[0x40];
5287 };
5288 
5289 struct mlx5_ifc_query_adapter_out_bits {
5290 	u8         status[0x8];
5291 	u8         reserved_0[0x18];
5292 
5293 	u8         syndrome[0x20];
5294 
5295 	u8         reserved_1[0x40];
5296 
5297 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5298 };
5299 
5300 struct mlx5_ifc_query_adapter_in_bits {
5301 	u8         opcode[0x10];
5302 	u8         reserved_0[0x10];
5303 
5304 	u8         reserved_1[0x10];
5305 	u8         op_mod[0x10];
5306 
5307 	u8         reserved_2[0x40];
5308 };
5309 
5310 struct mlx5_ifc_qp_2rst_out_bits {
5311 	u8         status[0x8];
5312 	u8         reserved_0[0x18];
5313 
5314 	u8         syndrome[0x20];
5315 
5316 	u8         reserved_1[0x40];
5317 };
5318 
5319 struct mlx5_ifc_qp_2rst_in_bits {
5320 	u8         opcode[0x10];
5321 	u8         uid[0x10];
5322 
5323 	u8         reserved_1[0x10];
5324 	u8         op_mod[0x10];
5325 
5326 	u8         reserved_2[0x8];
5327 	u8         qpn[0x18];
5328 
5329 	u8         reserved_3[0x20];
5330 };
5331 
5332 struct mlx5_ifc_qp_2err_out_bits {
5333 	u8         status[0x8];
5334 	u8         reserved_0[0x18];
5335 
5336 	u8         syndrome[0x20];
5337 
5338 	u8         reserved_1[0x40];
5339 };
5340 
5341 struct mlx5_ifc_qp_2err_in_bits {
5342 	u8         opcode[0x10];
5343 	u8         uid[0x10];
5344 
5345 	u8         reserved_1[0x10];
5346 	u8         op_mod[0x10];
5347 
5348 	u8         reserved_2[0x8];
5349 	u8         qpn[0x18];
5350 
5351 	u8         reserved_3[0x20];
5352 };
5353 
5354 struct mlx5_ifc_para_vport_element_bits {
5355 	u8         reserved_at_0[0xc];
5356 	u8         traffic_class[0x4];
5357 	u8         qos_para_vport_number[0x10];
5358 };
5359 
5360 struct mlx5_ifc_page_fault_resume_out_bits {
5361 	u8         status[0x8];
5362 	u8         reserved_0[0x18];
5363 
5364 	u8         syndrome[0x20];
5365 
5366 	u8         reserved_1[0x40];
5367 };
5368 
5369 struct mlx5_ifc_page_fault_resume_in_bits {
5370 	u8         opcode[0x10];
5371 	u8         reserved_0[0x10];
5372 
5373 	u8         reserved_1[0x10];
5374 	u8         op_mod[0x10];
5375 
5376 	u8         error[0x1];
5377 	u8         reserved_2[0x4];
5378 	u8         rdma[0x1];
5379 	u8         read_write[0x1];
5380 	u8         req_res[0x1];
5381 	u8         qpn[0x18];
5382 
5383 	u8         reserved_3[0x20];
5384 };
5385 
5386 struct mlx5_ifc_nop_out_bits {
5387 	u8         status[0x8];
5388 	u8         reserved_0[0x18];
5389 
5390 	u8         syndrome[0x20];
5391 
5392 	u8         reserved_1[0x40];
5393 };
5394 
5395 struct mlx5_ifc_nop_in_bits {
5396 	u8         opcode[0x10];
5397 	u8         reserved_0[0x10];
5398 
5399 	u8         reserved_1[0x10];
5400 	u8         op_mod[0x10];
5401 
5402 	u8         reserved_2[0x40];
5403 };
5404 
5405 struct mlx5_ifc_modify_vport_state_out_bits {
5406 	u8         status[0x8];
5407 	u8         reserved_0[0x18];
5408 
5409 	u8         syndrome[0x20];
5410 
5411 	u8         reserved_1[0x40];
5412 };
5413 
5414 enum {
5415 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
5416 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
5417 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
5418 };
5419 
5420 enum {
5421 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
5422 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
5423 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
5424 };
5425 
5426 struct mlx5_ifc_modify_vport_state_in_bits {
5427 	u8         opcode[0x10];
5428 	u8         reserved_0[0x10];
5429 
5430 	u8         reserved_1[0x10];
5431 	u8         op_mod[0x10];
5432 
5433 	u8         other_vport[0x1];
5434 	u8         reserved_2[0xf];
5435 	u8         vport_number[0x10];
5436 
5437 	u8         reserved_3[0x18];
5438 	u8         admin_state[0x4];
5439 	u8         reserved_4[0x4];
5440 };
5441 
5442 struct mlx5_ifc_modify_tis_out_bits {
5443 	u8         status[0x8];
5444 	u8         reserved_0[0x18];
5445 
5446 	u8         syndrome[0x20];
5447 
5448 	u8         reserved_1[0x40];
5449 };
5450 
5451 struct mlx5_ifc_modify_tis_bitmask_bits {
5452 	u8         reserved_at_0[0x20];
5453 
5454 	u8         reserved_at_20[0x1d];
5455 	u8         lag_tx_port_affinity[0x1];
5456 	u8         strict_lag_tx_port_affinity[0x1];
5457 	u8         prio[0x1];
5458 };
5459 
5460 struct mlx5_ifc_modify_tis_in_bits {
5461 	u8         opcode[0x10];
5462 	u8         reserved_0[0x10];
5463 
5464 	u8         reserved_1[0x10];
5465 	u8         op_mod[0x10];
5466 
5467 	u8         reserved_2[0x8];
5468 	u8         tisn[0x18];
5469 
5470 	u8         reserved_3[0x20];
5471 
5472 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5473 
5474 	u8         reserved_4[0x40];
5475 
5476 	struct mlx5_ifc_tisc_bits ctx;
5477 };
5478 
5479 struct mlx5_ifc_modify_tir_out_bits {
5480 	u8         status[0x8];
5481 	u8         reserved_0[0x18];
5482 
5483 	u8         syndrome[0x20];
5484 
5485 	u8         reserved_1[0x40];
5486 };
5487 
5488 enum
5489 {
5490 	MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
5491 	MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =		0x1 << 1
5492 };
5493 
5494 struct mlx5_ifc_modify_tir_in_bits {
5495 	u8         opcode[0x10];
5496 	u8         reserved_0[0x10];
5497 
5498 	u8         reserved_1[0x10];
5499 	u8         op_mod[0x10];
5500 
5501 	u8         reserved_2[0x8];
5502 	u8         tirn[0x18];
5503 
5504 	u8         reserved_3[0x20];
5505 
5506 	u8         modify_bitmask[0x40];
5507 
5508 	u8         reserved_4[0x40];
5509 
5510 	struct mlx5_ifc_tirc_bits tir_context;
5511 };
5512 
5513 struct mlx5_ifc_modify_sq_out_bits {
5514 	u8         status[0x8];
5515 	u8         reserved_0[0x18];
5516 
5517 	u8         syndrome[0x20];
5518 
5519 	u8         reserved_1[0x40];
5520 };
5521 
5522 struct mlx5_ifc_modify_sq_in_bits {
5523 	u8         opcode[0x10];
5524 	u8         reserved_0[0x10];
5525 
5526 	u8         reserved_1[0x10];
5527 	u8         op_mod[0x10];
5528 
5529 	u8         sq_state[0x4];
5530 	u8         reserved_2[0x4];
5531 	u8         sqn[0x18];
5532 
5533 	u8         reserved_3[0x20];
5534 
5535 	u8         modify_bitmask[0x40];
5536 
5537 	u8         reserved_4[0x40];
5538 
5539 	struct mlx5_ifc_sqc_bits ctx;
5540 };
5541 
5542 struct mlx5_ifc_modify_scheduling_element_out_bits {
5543 	u8         status[0x8];
5544 	u8         reserved_at_8[0x18];
5545 
5546 	u8         syndrome[0x20];
5547 
5548 	u8         reserved_at_40[0x1c0];
5549 };
5550 
5551 enum {
5552 	MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
5553 };
5554 
5555 enum {
5556 	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
5557 	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
5558 };
5559 
5560 struct mlx5_ifc_modify_scheduling_element_in_bits {
5561 	u8         opcode[0x10];
5562 	u8         reserved_at_10[0x10];
5563 
5564 	u8         reserved_at_20[0x10];
5565 	u8         op_mod[0x10];
5566 
5567 	u8         scheduling_hierarchy[0x8];
5568 	u8         reserved_at_48[0x18];
5569 
5570 	u8         scheduling_element_id[0x20];
5571 
5572 	u8         reserved_at_80[0x20];
5573 
5574 	u8         modify_bitmask[0x20];
5575 
5576 	u8         reserved_at_c0[0x40];
5577 
5578 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5579 
5580 	u8         reserved_at_300[0x100];
5581 };
5582 
5583 struct mlx5_ifc_modify_rqt_out_bits {
5584 	u8         status[0x8];
5585 	u8         reserved_0[0x18];
5586 
5587 	u8         syndrome[0x20];
5588 
5589 	u8         reserved_1[0x40];
5590 };
5591 
5592 struct mlx5_ifc_rqt_bitmask_bits {
5593 	u8         reserved_at_0[0x20];
5594 
5595 	u8         reserved_at_20[0x1f];
5596 	u8         rqn_list[0x1];
5597 };
5598 
5599 
5600 struct mlx5_ifc_modify_rqt_in_bits {
5601 	u8         opcode[0x10];
5602 	u8         reserved_0[0x10];
5603 
5604 	u8         reserved_1[0x10];
5605 	u8         op_mod[0x10];
5606 
5607 	u8         reserved_2[0x8];
5608 	u8         rqtn[0x18];
5609 
5610 	u8         reserved_3[0x20];
5611 
5612 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
5613 
5614 	u8         reserved_4[0x40];
5615 
5616 	struct mlx5_ifc_rqtc_bits ctx;
5617 };
5618 
5619 struct mlx5_ifc_modify_rq_out_bits {
5620 	u8         status[0x8];
5621 	u8         reserved_0[0x18];
5622 
5623 	u8         syndrome[0x20];
5624 
5625 	u8         reserved_1[0x40];
5626 };
5627 
5628 enum {
5629 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5630 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5631 };
5632 
5633 struct mlx5_ifc_modify_rq_in_bits {
5634 	u8         opcode[0x10];
5635 	u8         reserved_0[0x10];
5636 
5637 	u8         reserved_1[0x10];
5638 	u8         op_mod[0x10];
5639 
5640 	u8         rq_state[0x4];
5641 	u8         reserved_2[0x4];
5642 	u8         rqn[0x18];
5643 
5644 	u8         reserved_3[0x20];
5645 
5646 	u8         modify_bitmask[0x40];
5647 
5648 	u8         reserved_4[0x40];
5649 
5650 	struct mlx5_ifc_rqc_bits ctx;
5651 };
5652 
5653 struct mlx5_ifc_modify_rmp_out_bits {
5654 	u8         status[0x8];
5655 	u8         reserved_0[0x18];
5656 
5657 	u8         syndrome[0x20];
5658 
5659 	u8         reserved_1[0x40];
5660 };
5661 
5662 struct mlx5_ifc_rmp_bitmask_bits {
5663 	u8	   reserved[0x20];
5664 
5665 	u8         reserved1[0x1f];
5666 	u8         lwm[0x1];
5667 };
5668 
5669 struct mlx5_ifc_modify_rmp_in_bits {
5670 	u8         opcode[0x10];
5671 	u8         reserved_0[0x10];
5672 
5673 	u8         reserved_1[0x10];
5674 	u8         op_mod[0x10];
5675 
5676 	u8         rmp_state[0x4];
5677 	u8         reserved_2[0x4];
5678 	u8         rmpn[0x18];
5679 
5680 	u8         reserved_3[0x20];
5681 
5682 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
5683 
5684 	u8         reserved_4[0x40];
5685 
5686 	struct mlx5_ifc_rmpc_bits ctx;
5687 };
5688 
5689 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5690 	u8         status[0x8];
5691 	u8         reserved_0[0x18];
5692 
5693 	u8         syndrome[0x20];
5694 
5695 	u8         reserved_1[0x40];
5696 };
5697 
5698 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5699 	u8         reserved_0[0x14];
5700 	u8         disable_uc_local_lb[0x1];
5701 	u8         disable_mc_local_lb[0x1];
5702 	u8         node_guid[0x1];
5703 	u8         port_guid[0x1];
5704 	u8         min_wqe_inline_mode[0x1];
5705 	u8         mtu[0x1];
5706 	u8         change_event[0x1];
5707 	u8         promisc[0x1];
5708 	u8         permanent_address[0x1];
5709 	u8         addresses_list[0x1];
5710 	u8         roce_en[0x1];
5711 	u8         reserved_1[0x1];
5712 };
5713 
5714 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5715 	u8         opcode[0x10];
5716 	u8         reserved_0[0x10];
5717 
5718 	u8         reserved_1[0x10];
5719 	u8         op_mod[0x10];
5720 
5721 	u8         other_vport[0x1];
5722 	u8         reserved_2[0xf];
5723 	u8         vport_number[0x10];
5724 
5725 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5726 
5727 	u8         reserved_3[0x780];
5728 
5729 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5730 };
5731 
5732 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5733 	u8         status[0x8];
5734 	u8         reserved_0[0x18];
5735 
5736 	u8         syndrome[0x20];
5737 
5738 	u8         reserved_1[0x40];
5739 };
5740 
5741 struct mlx5_ifc_grh_bits {
5742 	u8	ip_version[4];
5743 	u8	traffic_class[8];
5744 	u8	flow_label[20];
5745 	u8	payload_length[16];
5746 	u8	next_header[8];
5747 	u8	hop_limit[8];
5748 	u8	sgid[128];
5749 	u8	dgid[128];
5750 };
5751 
5752 struct mlx5_ifc_bth_bits {
5753 	u8	opcode[8];
5754 	u8	se[1];
5755 	u8	migreq[1];
5756 	u8	pad_count[2];
5757 	u8	tver[4];
5758 	u8	p_key[16];
5759 	u8	reserved8[8];
5760 	u8	dest_qp[24];
5761 	u8	ack_req[1];
5762 	u8	reserved7[7];
5763 	u8	psn[24];
5764 };
5765 
5766 struct mlx5_ifc_aeth_bits {
5767 	u8	syndrome[8];
5768 	u8	msn[24];
5769 };
5770 
5771 struct mlx5_ifc_dceth_bits {
5772 	u8	reserved0[8];
5773 	u8	session_id[24];
5774 	u8	reserved1[8];
5775 	u8	dci_dct[24];
5776 };
5777 
5778 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5779 	u8         opcode[0x10];
5780 	u8         reserved_0[0x10];
5781 
5782 	u8         reserved_1[0x10];
5783 	u8         op_mod[0x10];
5784 
5785 	u8         other_vport[0x1];
5786 	u8         reserved_2[0xb];
5787 	u8         port_num[0x4];
5788 	u8         vport_number[0x10];
5789 
5790 	u8         reserved_3[0x20];
5791 
5792 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5793 };
5794 
5795 struct mlx5_ifc_modify_flow_table_out_bits {
5796 	u8         status[0x8];
5797 	u8         reserved_at_8[0x18];
5798 
5799 	u8         syndrome[0x20];
5800 
5801 	u8         reserved_at_40[0x40];
5802 };
5803 
5804 enum {
5805 	MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
5806 	MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
5807 };
5808 
5809 struct mlx5_ifc_modify_flow_table_in_bits {
5810 	u8         opcode[0x10];
5811 	u8         reserved_at_10[0x10];
5812 
5813 	u8         reserved_at_20[0x10];
5814 	u8         op_mod[0x10];
5815 
5816 	u8         other_vport[0x1];
5817 	u8         reserved_at_41[0xf];
5818 	u8         vport_number[0x10];
5819 
5820 	u8         reserved_at_60[0x10];
5821 	u8         modify_field_select[0x10];
5822 
5823 	u8         table_type[0x8];
5824 	u8         reserved_at_88[0x18];
5825 
5826 	u8         reserved_at_a0[0x8];
5827 	u8         table_id[0x18];
5828 
5829 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5830 };
5831 
5832 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5833 	u8         status[0x8];
5834 	u8         reserved_0[0x18];
5835 
5836 	u8         syndrome[0x20];
5837 
5838 	u8         reserved_1[0x40];
5839 };
5840 
5841 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5842 	u8         reserved[0x1c];
5843 	u8         vport_cvlan_insert[0x1];
5844 	u8         vport_svlan_insert[0x1];
5845 	u8         vport_cvlan_strip[0x1];
5846 	u8         vport_svlan_strip[0x1];
5847 };
5848 
5849 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5850 	u8         opcode[0x10];
5851 	u8         reserved_0[0x10];
5852 
5853 	u8         reserved_1[0x10];
5854 	u8         op_mod[0x10];
5855 
5856 	u8         other_vport[0x1];
5857 	u8         reserved_2[0xf];
5858 	u8         vport_number[0x10];
5859 
5860 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5861 
5862 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5863 };
5864 
5865 struct mlx5_ifc_modify_cq_out_bits {
5866 	u8         status[0x8];
5867 	u8         reserved_0[0x18];
5868 
5869 	u8         syndrome[0x20];
5870 
5871 	u8         reserved_1[0x40];
5872 };
5873 
5874 enum {
5875 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5876 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5877 };
5878 
5879 struct mlx5_ifc_modify_cq_in_bits {
5880 	u8         opcode[0x10];
5881 	u8         reserved_0[0x10];
5882 
5883 	u8         reserved_1[0x10];
5884 	u8         op_mod[0x10];
5885 
5886 	u8         reserved_2[0x8];
5887 	u8         cqn[0x18];
5888 
5889 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5890 
5891 	struct mlx5_ifc_cqc_bits cq_context;
5892 
5893 	u8         reserved_3[0x600];
5894 
5895 	u8         pas[0][0x40];
5896 };
5897 
5898 struct mlx5_ifc_modify_cong_status_out_bits {
5899 	u8         status[0x8];
5900 	u8         reserved_0[0x18];
5901 
5902 	u8         syndrome[0x20];
5903 
5904 	u8         reserved_1[0x40];
5905 };
5906 
5907 struct mlx5_ifc_modify_cong_status_in_bits {
5908 	u8         opcode[0x10];
5909 	u8         reserved_0[0x10];
5910 
5911 	u8         reserved_1[0x10];
5912 	u8         op_mod[0x10];
5913 
5914 	u8         reserved_2[0x18];
5915 	u8         priority[0x4];
5916 	u8         cong_protocol[0x4];
5917 
5918 	u8         enable[0x1];
5919 	u8         tag_enable[0x1];
5920 	u8         reserved_3[0x1e];
5921 };
5922 
5923 struct mlx5_ifc_modify_cong_params_out_bits {
5924 	u8         status[0x8];
5925 	u8         reserved_0[0x18];
5926 
5927 	u8         syndrome[0x20];
5928 
5929 	u8         reserved_1[0x40];
5930 };
5931 
5932 struct mlx5_ifc_modify_cong_params_in_bits {
5933 	u8         opcode[0x10];
5934 	u8         reserved_0[0x10];
5935 
5936 	u8         reserved_1[0x10];
5937 	u8         op_mod[0x10];
5938 
5939 	u8         reserved_2[0x1c];
5940 	u8         cong_protocol[0x4];
5941 
5942 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5943 
5944 	u8         reserved_3[0x80];
5945 
5946 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5947 };
5948 
5949 struct mlx5_ifc_manage_pages_out_bits {
5950 	u8         status[0x8];
5951 	u8         reserved_0[0x18];
5952 
5953 	u8         syndrome[0x20];
5954 
5955 	u8         output_num_entries[0x20];
5956 
5957 	u8         reserved_1[0x20];
5958 
5959 	u8         pas[0][0x40];
5960 };
5961 
5962 enum {
5963 	MLX5_PAGES_CANT_GIVE                            = 0x0,
5964 	MLX5_PAGES_GIVE                                 = 0x1,
5965 	MLX5_PAGES_TAKE                                 = 0x2,
5966 };
5967 
5968 struct mlx5_ifc_manage_pages_in_bits {
5969 	u8         opcode[0x10];
5970 	u8         reserved_0[0x10];
5971 
5972 	u8         reserved_1[0x10];
5973 	u8         op_mod[0x10];
5974 
5975 	u8         reserved_2[0x10];
5976 	u8         function_id[0x10];
5977 
5978 	u8         input_num_entries[0x20];
5979 
5980 	u8         pas[0][0x40];
5981 };
5982 
5983 struct mlx5_ifc_mad_ifc_out_bits {
5984 	u8         status[0x8];
5985 	u8         reserved_0[0x18];
5986 
5987 	u8         syndrome[0x20];
5988 
5989 	u8         reserved_1[0x40];
5990 
5991 	u8         response_mad_packet[256][0x8];
5992 };
5993 
5994 struct mlx5_ifc_mad_ifc_in_bits {
5995 	u8         opcode[0x10];
5996 	u8         reserved_0[0x10];
5997 
5998 	u8         reserved_1[0x10];
5999 	u8         op_mod[0x10];
6000 
6001 	u8         remote_lid[0x10];
6002 	u8         reserved_2[0x8];
6003 	u8         port[0x8];
6004 
6005 	u8         reserved_3[0x20];
6006 
6007 	u8         mad[256][0x8];
6008 };
6009 
6010 struct mlx5_ifc_init_hca_out_bits {
6011 	u8         status[0x8];
6012 	u8         reserved_0[0x18];
6013 
6014 	u8         syndrome[0x20];
6015 
6016 	u8         reserved_1[0x40];
6017 };
6018 
6019 enum {
6020 	MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
6021 	MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
6022 };
6023 
6024 struct mlx5_ifc_init_hca_in_bits {
6025 	u8         opcode[0x10];
6026 	u8         reserved_0[0x10];
6027 
6028 	u8         reserved_1[0x10];
6029 	u8         op_mod[0x10];
6030 
6031 	u8         reserved_2[0x40];
6032 };
6033 
6034 struct mlx5_ifc_init2rtr_qp_out_bits {
6035 	u8         status[0x8];
6036 	u8         reserved_0[0x18];
6037 
6038 	u8         syndrome[0x20];
6039 
6040 	u8         reserved_1[0x40];
6041 };
6042 
6043 struct mlx5_ifc_init2rtr_qp_in_bits {
6044 	u8         opcode[0x10];
6045 	u8         uid[0x10];
6046 
6047 	u8         reserved_1[0x10];
6048 	u8         op_mod[0x10];
6049 
6050 	u8         reserved_2[0x8];
6051 	u8         qpn[0x18];
6052 
6053 	u8         reserved_3[0x20];
6054 
6055 	u8         opt_param_mask[0x20];
6056 
6057 	u8         reserved_4[0x20];
6058 
6059 	struct mlx5_ifc_qpc_bits qpc;
6060 
6061 	u8         reserved_5[0x80];
6062 };
6063 
6064 struct mlx5_ifc_init2init_qp_out_bits {
6065 	u8         status[0x8];
6066 	u8         reserved_0[0x18];
6067 
6068 	u8         syndrome[0x20];
6069 
6070 	u8         reserved_1[0x40];
6071 };
6072 
6073 struct mlx5_ifc_init2init_qp_in_bits {
6074 	u8         opcode[0x10];
6075 	u8         uid[0x10];
6076 
6077 	u8         reserved_1[0x10];
6078 	u8         op_mod[0x10];
6079 
6080 	u8         reserved_2[0x8];
6081 	u8         qpn[0x18];
6082 
6083 	u8         reserved_3[0x20];
6084 
6085 	u8         opt_param_mask[0x20];
6086 
6087 	u8         reserved_4[0x20];
6088 
6089 	struct mlx5_ifc_qpc_bits qpc;
6090 
6091 	u8         reserved_5[0x80];
6092 };
6093 
6094 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6095 	u8         status[0x8];
6096 	u8         reserved_0[0x18];
6097 
6098 	u8         syndrome[0x20];
6099 
6100 	u8         reserved_1[0x40];
6101 
6102 	u8         packet_headers_log[128][0x8];
6103 
6104 	u8         packet_syndrome[64][0x8];
6105 };
6106 
6107 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6108 	u8         opcode[0x10];
6109 	u8         reserved_0[0x10];
6110 
6111 	u8         reserved_1[0x10];
6112 	u8         op_mod[0x10];
6113 
6114 	u8         reserved_2[0x40];
6115 };
6116 
6117 struct mlx5_ifc_encryption_key_obj_bits {
6118 	u8         modify_field_select[0x40];
6119 
6120 	u8         reserved_at_40[0x14];
6121 	u8         key_size[0x4];
6122 	u8         reserved_at_58[0x4];
6123 	u8         key_type[0x4];
6124 
6125 	u8         reserved_at_60[0x8];
6126 	u8         pd[0x18];
6127 
6128 	u8         reserved_at_80[0x180];
6129 
6130 	u8         key[8][0x20];
6131 
6132 	u8         reserved_at_300[0x500];
6133 };
6134 
6135 struct mlx5_ifc_gen_eqe_in_bits {
6136 	u8         opcode[0x10];
6137 	u8         reserved_0[0x10];
6138 
6139 	u8         reserved_1[0x10];
6140 	u8         op_mod[0x10];
6141 
6142 	u8         reserved_2[0x18];
6143 	u8         eq_number[0x8];
6144 
6145 	u8         reserved_3[0x20];
6146 
6147 	u8         eqe[64][0x8];
6148 };
6149 
6150 struct mlx5_ifc_gen_eq_out_bits {
6151 	u8         status[0x8];
6152 	u8         reserved_0[0x18];
6153 
6154 	u8         syndrome[0x20];
6155 
6156 	u8         reserved_1[0x40];
6157 };
6158 
6159 struct mlx5_ifc_enable_hca_out_bits {
6160 	u8         status[0x8];
6161 	u8         reserved_0[0x18];
6162 
6163 	u8         syndrome[0x20];
6164 
6165 	u8         reserved_1[0x20];
6166 };
6167 
6168 struct mlx5_ifc_enable_hca_in_bits {
6169 	u8         opcode[0x10];
6170 	u8         reserved_0[0x10];
6171 
6172 	u8         reserved_1[0x10];
6173 	u8         op_mod[0x10];
6174 
6175 	u8         reserved_2[0x10];
6176 	u8         function_id[0x10];
6177 
6178 	u8         reserved_3[0x20];
6179 };
6180 
6181 struct mlx5_ifc_drain_dct_out_bits {
6182 	u8         status[0x8];
6183 	u8         reserved_0[0x18];
6184 
6185 	u8         syndrome[0x20];
6186 
6187 	u8         reserved_1[0x40];
6188 };
6189 
6190 struct mlx5_ifc_drain_dct_in_bits {
6191 	u8         opcode[0x10];
6192 	u8         uid[0x10];
6193 
6194 	u8         reserved_1[0x10];
6195 	u8         op_mod[0x10];
6196 
6197 	u8         reserved_2[0x8];
6198 	u8         dctn[0x18];
6199 
6200 	u8         reserved_3[0x20];
6201 };
6202 
6203 struct mlx5_ifc_disable_hca_out_bits {
6204 	u8         status[0x8];
6205 	u8         reserved_0[0x18];
6206 
6207 	u8         syndrome[0x20];
6208 
6209 	u8         reserved_1[0x20];
6210 };
6211 
6212 struct mlx5_ifc_disable_hca_in_bits {
6213 	u8         opcode[0x10];
6214 	u8         reserved_0[0x10];
6215 
6216 	u8         reserved_1[0x10];
6217 	u8         op_mod[0x10];
6218 
6219 	u8         reserved_2[0x10];
6220 	u8         function_id[0x10];
6221 
6222 	u8         reserved_3[0x20];
6223 };
6224 
6225 struct mlx5_ifc_detach_from_mcg_out_bits {
6226 	u8         status[0x8];
6227 	u8         reserved_0[0x18];
6228 
6229 	u8         syndrome[0x20];
6230 
6231 	u8         reserved_1[0x40];
6232 };
6233 
6234 struct mlx5_ifc_detach_from_mcg_in_bits {
6235 	u8         opcode[0x10];
6236 	u8         reserved_0[0x10];
6237 
6238 	u8         reserved_1[0x10];
6239 	u8         op_mod[0x10];
6240 
6241 	u8         reserved_2[0x8];
6242 	u8         qpn[0x18];
6243 
6244 	u8         reserved_3[0x20];
6245 
6246 	u8         multicast_gid[16][0x8];
6247 };
6248 
6249 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6250 	u8         status[0x8];
6251 	u8         reserved_0[0x18];
6252 
6253 	u8         syndrome[0x20];
6254 
6255 	u8         reserved_1[0x40];
6256 };
6257 
6258 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6259 	u8         opcode[0x10];
6260 	u8         reserved_0[0x10];
6261 
6262 	u8         reserved_1[0x10];
6263 	u8         op_mod[0x10];
6264 
6265 	u8         reserved_2[0x8];
6266 	u8         xrc_srqn[0x18];
6267 
6268 	u8         reserved_3[0x20];
6269 };
6270 
6271 struct mlx5_ifc_destroy_tis_out_bits {
6272 	u8         status[0x8];
6273 	u8         reserved_0[0x18];
6274 
6275 	u8         syndrome[0x20];
6276 
6277 	u8         reserved_1[0x40];
6278 };
6279 
6280 struct mlx5_ifc_destroy_tis_in_bits {
6281 	u8         opcode[0x10];
6282 	u8         reserved_0[0x10];
6283 
6284 	u8         reserved_1[0x10];
6285 	u8         op_mod[0x10];
6286 
6287 	u8         reserved_2[0x8];
6288 	u8         tisn[0x18];
6289 
6290 	u8         reserved_3[0x20];
6291 };
6292 
6293 struct mlx5_ifc_destroy_tir_out_bits {
6294 	u8         status[0x8];
6295 	u8         reserved_0[0x18];
6296 
6297 	u8         syndrome[0x20];
6298 
6299 	u8         reserved_1[0x40];
6300 };
6301 
6302 struct mlx5_ifc_destroy_tir_in_bits {
6303 	u8         opcode[0x10];
6304 	u8         reserved_0[0x10];
6305 
6306 	u8         reserved_1[0x10];
6307 	u8         op_mod[0x10];
6308 
6309 	u8         reserved_2[0x8];
6310 	u8         tirn[0x18];
6311 
6312 	u8         reserved_3[0x20];
6313 };
6314 
6315 struct mlx5_ifc_destroy_srq_out_bits {
6316 	u8         status[0x8];
6317 	u8         reserved_0[0x18];
6318 
6319 	u8         syndrome[0x20];
6320 
6321 	u8         reserved_1[0x40];
6322 };
6323 
6324 struct mlx5_ifc_destroy_srq_in_bits {
6325 	u8         opcode[0x10];
6326 	u8         reserved_0[0x10];
6327 
6328 	u8         reserved_1[0x10];
6329 	u8         op_mod[0x10];
6330 
6331 	u8         reserved_2[0x8];
6332 	u8         srqn[0x18];
6333 
6334 	u8         reserved_3[0x20];
6335 };
6336 
6337 struct mlx5_ifc_destroy_sq_out_bits {
6338 	u8         status[0x8];
6339 	u8         reserved_0[0x18];
6340 
6341 	u8         syndrome[0x20];
6342 
6343 	u8         reserved_1[0x40];
6344 };
6345 
6346 struct mlx5_ifc_destroy_sq_in_bits {
6347 	u8         opcode[0x10];
6348 	u8         uid[0x10];
6349 
6350 	u8         reserved_1[0x10];
6351 	u8         op_mod[0x10];
6352 
6353 	u8         reserved_2[0x8];
6354 	u8         sqn[0x18];
6355 
6356 	u8         reserved_3[0x20];
6357 };
6358 
6359 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6360 	u8         status[0x8];
6361 	u8         reserved_at_8[0x18];
6362 
6363 	u8         syndrome[0x20];
6364 
6365 	u8         reserved_at_40[0x1c0];
6366 };
6367 
6368 enum {
6369 	MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
6370 };
6371 
6372 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6373 	u8         opcode[0x10];
6374 	u8         reserved_at_10[0x10];
6375 
6376 	u8         reserved_at_20[0x10];
6377 	u8         op_mod[0x10];
6378 
6379 	u8         scheduling_hierarchy[0x8];
6380 	u8         reserved_at_48[0x18];
6381 
6382 	u8         scheduling_element_id[0x20];
6383 
6384 	u8         reserved_at_80[0x180];
6385 };
6386 
6387 struct mlx5_ifc_destroy_rqt_out_bits {
6388 	u8         status[0x8];
6389 	u8         reserved_0[0x18];
6390 
6391 	u8         syndrome[0x20];
6392 
6393 	u8         reserved_1[0x40];
6394 };
6395 
6396 struct mlx5_ifc_destroy_rqt_in_bits {
6397 	u8         opcode[0x10];
6398 	u8         reserved_0[0x10];
6399 
6400 	u8         reserved_1[0x10];
6401 	u8         op_mod[0x10];
6402 
6403 	u8         reserved_2[0x8];
6404 	u8         rqtn[0x18];
6405 
6406 	u8         reserved_3[0x20];
6407 };
6408 
6409 struct mlx5_ifc_destroy_rq_out_bits {
6410 	u8         status[0x8];
6411 	u8         reserved_0[0x18];
6412 
6413 	u8         syndrome[0x20];
6414 
6415 	u8         reserved_1[0x40];
6416 };
6417 
6418 struct mlx5_ifc_destroy_rq_in_bits {
6419 	u8         opcode[0x10];
6420 	u8         uid[0x10];
6421 
6422 	u8         reserved_1[0x10];
6423 	u8         op_mod[0x10];
6424 
6425 	u8         reserved_2[0x8];
6426 	u8         rqn[0x18];
6427 
6428 	u8         reserved_3[0x20];
6429 };
6430 
6431 struct mlx5_ifc_destroy_rmp_out_bits {
6432 	u8         status[0x8];
6433 	u8         reserved_0[0x18];
6434 
6435 	u8         syndrome[0x20];
6436 
6437 	u8         reserved_1[0x40];
6438 };
6439 
6440 struct mlx5_ifc_destroy_rmp_in_bits {
6441 	u8         opcode[0x10];
6442 	u8         reserved_0[0x10];
6443 
6444 	u8         reserved_1[0x10];
6445 	u8         op_mod[0x10];
6446 
6447 	u8         reserved_2[0x8];
6448 	u8         rmpn[0x18];
6449 
6450 	u8         reserved_3[0x20];
6451 };
6452 
6453 struct mlx5_ifc_destroy_qp_out_bits {
6454 	u8         status[0x8];
6455 	u8         reserved_0[0x18];
6456 
6457 	u8         syndrome[0x20];
6458 
6459 	u8         reserved_1[0x40];
6460 };
6461 
6462 struct mlx5_ifc_destroy_qp_in_bits {
6463 	u8         opcode[0x10];
6464 	u8         uid[0x10];
6465 
6466 	u8         reserved_1[0x10];
6467 	u8         op_mod[0x10];
6468 
6469 	u8         reserved_2[0x8];
6470 	u8         qpn[0x18];
6471 
6472 	u8         reserved_3[0x20];
6473 };
6474 
6475 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
6476 	u8         status[0x8];
6477 	u8         reserved_at_8[0x18];
6478 
6479 	u8         syndrome[0x20];
6480 
6481 	u8         reserved_at_40[0x1c0];
6482 };
6483 
6484 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
6485 	u8         opcode[0x10];
6486 	u8         reserved_at_10[0x10];
6487 
6488 	u8         reserved_at_20[0x10];
6489 	u8         op_mod[0x10];
6490 
6491 	u8         reserved_at_40[0x20];
6492 
6493 	u8         reserved_at_60[0x10];
6494 	u8         qos_para_vport_number[0x10];
6495 
6496 	u8         reserved_at_80[0x180];
6497 };
6498 
6499 struct mlx5_ifc_destroy_psv_out_bits {
6500 	u8         status[0x8];
6501 	u8         reserved_0[0x18];
6502 
6503 	u8         syndrome[0x20];
6504 
6505 	u8         reserved_1[0x40];
6506 };
6507 
6508 struct mlx5_ifc_destroy_psv_in_bits {
6509 	u8         opcode[0x10];
6510 	u8         reserved_0[0x10];
6511 
6512 	u8         reserved_1[0x10];
6513 	u8         op_mod[0x10];
6514 
6515 	u8         reserved_2[0x8];
6516 	u8         psvn[0x18];
6517 
6518 	u8         reserved_3[0x20];
6519 };
6520 
6521 struct mlx5_ifc_destroy_mkey_out_bits {
6522 	u8         status[0x8];
6523 	u8         reserved_0[0x18];
6524 
6525 	u8         syndrome[0x20];
6526 
6527 	u8         reserved_1[0x40];
6528 };
6529 
6530 struct mlx5_ifc_destroy_mkey_in_bits {
6531 	u8         opcode[0x10];
6532 	u8         reserved_0[0x10];
6533 
6534 	u8         reserved_1[0x10];
6535 	u8         op_mod[0x10];
6536 
6537 	u8         reserved_2[0x8];
6538 	u8         mkey_index[0x18];
6539 
6540 	u8         reserved_3[0x20];
6541 };
6542 
6543 struct mlx5_ifc_destroy_flow_table_out_bits {
6544 	u8         status[0x8];
6545 	u8         reserved_0[0x18];
6546 
6547 	u8         syndrome[0x20];
6548 
6549 	u8         reserved_1[0x40];
6550 };
6551 
6552 struct mlx5_ifc_destroy_flow_table_in_bits {
6553 	u8         opcode[0x10];
6554 	u8         reserved_0[0x10];
6555 
6556 	u8         reserved_1[0x10];
6557 	u8         op_mod[0x10];
6558 
6559 	u8         other_vport[0x1];
6560 	u8         reserved_2[0xf];
6561 	u8         vport_number[0x10];
6562 
6563 	u8         reserved_3[0x20];
6564 
6565 	u8         table_type[0x8];
6566 	u8         reserved_4[0x18];
6567 
6568 	u8         reserved_5[0x8];
6569 	u8         table_id[0x18];
6570 
6571 	u8         reserved_6[0x140];
6572 };
6573 
6574 struct mlx5_ifc_destroy_flow_group_out_bits {
6575 	u8         status[0x8];
6576 	u8         reserved_0[0x18];
6577 
6578 	u8         syndrome[0x20];
6579 
6580 	u8         reserved_1[0x40];
6581 };
6582 
6583 struct mlx5_ifc_destroy_flow_group_in_bits {
6584 	u8         opcode[0x10];
6585 	u8         reserved_0[0x10];
6586 
6587 	u8         reserved_1[0x10];
6588 	u8         op_mod[0x10];
6589 
6590 	u8         other_vport[0x1];
6591 	u8         reserved_2[0xf];
6592 	u8         vport_number[0x10];
6593 
6594 	u8         reserved_3[0x20];
6595 
6596 	u8         table_type[0x8];
6597 	u8         reserved_4[0x18];
6598 
6599 	u8         reserved_5[0x8];
6600 	u8         table_id[0x18];
6601 
6602 	u8         group_id[0x20];
6603 
6604 	u8         reserved_6[0x120];
6605 };
6606 
6607 struct mlx5_ifc_destroy_encryption_key_out_bits {
6608 	u8         status[0x8];
6609 	u8         reserved_at_8[0x18];
6610 
6611 	u8         syndrome[0x20];
6612 
6613 	u8         reserved_at_40[0x40];
6614 };
6615 
6616 struct mlx5_ifc_destroy_encryption_key_in_bits {
6617 	u8         opcode[0x10];
6618 	u8         reserved_at_10[0x10];
6619 
6620 	u8         reserved_at_20[0x10];
6621 	u8         obj_type[0x10];
6622 
6623 	u8         obj_id[0x20];
6624 
6625 	u8         reserved_at_60[0x20];
6626 };
6627 
6628 struct mlx5_ifc_destroy_eq_out_bits {
6629 	u8         status[0x8];
6630 	u8         reserved_0[0x18];
6631 
6632 	u8         syndrome[0x20];
6633 
6634 	u8         reserved_1[0x40];
6635 };
6636 
6637 struct mlx5_ifc_destroy_eq_in_bits {
6638 	u8         opcode[0x10];
6639 	u8         reserved_0[0x10];
6640 
6641 	u8         reserved_1[0x10];
6642 	u8         op_mod[0x10];
6643 
6644 	u8         reserved_2[0x18];
6645 	u8         eq_number[0x8];
6646 
6647 	u8         reserved_3[0x20];
6648 };
6649 
6650 struct mlx5_ifc_destroy_dct_out_bits {
6651 	u8         status[0x8];
6652 	u8         reserved_0[0x18];
6653 
6654 	u8         syndrome[0x20];
6655 
6656 	u8         reserved_1[0x40];
6657 };
6658 
6659 struct mlx5_ifc_destroy_dct_in_bits {
6660 	u8         opcode[0x10];
6661 	u8         uid[0x10];
6662 
6663 	u8         reserved_1[0x10];
6664 	u8         op_mod[0x10];
6665 
6666 	u8         reserved_2[0x8];
6667 	u8         dctn[0x18];
6668 
6669 	u8         reserved_3[0x20];
6670 };
6671 
6672 struct mlx5_ifc_destroy_cq_out_bits {
6673 	u8         status[0x8];
6674 	u8         reserved_0[0x18];
6675 
6676 	u8         syndrome[0x20];
6677 
6678 	u8         reserved_1[0x40];
6679 };
6680 
6681 struct mlx5_ifc_destroy_cq_in_bits {
6682 	u8         opcode[0x10];
6683 	u8         reserved_0[0x10];
6684 
6685 	u8         reserved_1[0x10];
6686 	u8         op_mod[0x10];
6687 
6688 	u8         reserved_2[0x8];
6689 	u8         cqn[0x18];
6690 
6691 	u8         reserved_3[0x20];
6692 };
6693 
6694 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6695 	u8         status[0x8];
6696 	u8         reserved_0[0x18];
6697 
6698 	u8         syndrome[0x20];
6699 
6700 	u8         reserved_1[0x40];
6701 };
6702 
6703 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6704 	u8         opcode[0x10];
6705 	u8         reserved_0[0x10];
6706 
6707 	u8         reserved_1[0x10];
6708 	u8         op_mod[0x10];
6709 
6710 	u8         reserved_2[0x20];
6711 
6712 	u8         reserved_3[0x10];
6713 	u8         vxlan_udp_port[0x10];
6714 };
6715 
6716 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6717 	u8         status[0x8];
6718 	u8         reserved_0[0x18];
6719 
6720 	u8         syndrome[0x20];
6721 
6722 	u8         reserved_1[0x40];
6723 };
6724 
6725 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6726 	u8         opcode[0x10];
6727 	u8         reserved_0[0x10];
6728 
6729 	u8         reserved_1[0x10];
6730 	u8         op_mod[0x10];
6731 
6732 	u8         reserved_2[0x60];
6733 
6734 	u8         reserved_3[0x8];
6735 	u8         table_index[0x18];
6736 
6737 	u8         reserved_4[0x140];
6738 };
6739 
6740 struct mlx5_ifc_delete_fte_out_bits {
6741 	u8         status[0x8];
6742 	u8         reserved_0[0x18];
6743 
6744 	u8         syndrome[0x20];
6745 
6746 	u8         reserved_1[0x40];
6747 };
6748 
6749 struct mlx5_ifc_delete_fte_in_bits {
6750 	u8         opcode[0x10];
6751 	u8         reserved_0[0x10];
6752 
6753 	u8         reserved_1[0x10];
6754 	u8         op_mod[0x10];
6755 
6756 	u8         other_vport[0x1];
6757 	u8         reserved_2[0xf];
6758 	u8         vport_number[0x10];
6759 
6760 	u8         reserved_3[0x20];
6761 
6762 	u8         table_type[0x8];
6763 	u8         reserved_4[0x18];
6764 
6765 	u8         reserved_5[0x8];
6766 	u8         table_id[0x18];
6767 
6768 	u8         reserved_6[0x40];
6769 
6770 	u8         flow_index[0x20];
6771 
6772 	u8         reserved_7[0xe0];
6773 };
6774 
6775 struct mlx5_ifc_dealloc_xrcd_out_bits {
6776 	u8         status[0x8];
6777 	u8         reserved_0[0x18];
6778 
6779 	u8         syndrome[0x20];
6780 
6781 	u8         reserved_1[0x40];
6782 };
6783 
6784 struct mlx5_ifc_dealloc_xrcd_in_bits {
6785 	u8         opcode[0x10];
6786 	u8         reserved_0[0x10];
6787 
6788 	u8         reserved_1[0x10];
6789 	u8         op_mod[0x10];
6790 
6791 	u8         reserved_2[0x8];
6792 	u8         xrcd[0x18];
6793 
6794 	u8         reserved_3[0x20];
6795 };
6796 
6797 struct mlx5_ifc_dealloc_uar_out_bits {
6798 	u8         status[0x8];
6799 	u8         reserved_0[0x18];
6800 
6801 	u8         syndrome[0x20];
6802 
6803 	u8         reserved_1[0x40];
6804 };
6805 
6806 struct mlx5_ifc_dealloc_uar_in_bits {
6807 	u8         opcode[0x10];
6808 	u8         reserved_0[0x10];
6809 
6810 	u8         reserved_1[0x10];
6811 	u8         op_mod[0x10];
6812 
6813 	u8         reserved_2[0x8];
6814 	u8         uar[0x18];
6815 
6816 	u8         reserved_3[0x20];
6817 };
6818 
6819 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6820 	u8         status[0x8];
6821 	u8         reserved_0[0x18];
6822 
6823 	u8         syndrome[0x20];
6824 
6825 	u8         reserved_1[0x40];
6826 };
6827 
6828 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6829 	u8         opcode[0x10];
6830 	u8         reserved_0[0x10];
6831 
6832 	u8         reserved_1[0x10];
6833 	u8         op_mod[0x10];
6834 
6835 	u8         reserved_2[0x8];
6836 	u8         transport_domain[0x18];
6837 
6838 	u8         reserved_3[0x20];
6839 };
6840 
6841 struct mlx5_ifc_dealloc_q_counter_out_bits {
6842 	u8         status[0x8];
6843 	u8         reserved_0[0x18];
6844 
6845 	u8         syndrome[0x20];
6846 
6847 	u8         reserved_1[0x40];
6848 };
6849 
6850 struct mlx5_ifc_counter_id_bits {
6851 	u8         reserved[0x10];
6852 	u8         counter_id[0x10];
6853 };
6854 
6855 struct mlx5_ifc_diagnostic_params_context_bits {
6856 	u8         num_of_counters[0x10];
6857 	u8         reserved_2[0x8];
6858 	u8         log_num_of_samples[0x8];
6859 
6860 	u8         single[0x1];
6861 	u8         repetitive[0x1];
6862 	u8         sync[0x1];
6863 	u8         clear[0x1];
6864 	u8         on_demand[0x1];
6865 	u8         enable[0x1];
6866 	u8         reserved_3[0x12];
6867 	u8         log_sample_period[0x8];
6868 
6869 	u8         reserved_4[0x80];
6870 
6871 	struct mlx5_ifc_counter_id_bits counter_id[0];
6872 };
6873 
6874 struct mlx5_ifc_query_diagnostic_params_in_bits {
6875 	u8         opcode[0x10];
6876 	u8         reserved_at_10[0x10];
6877 
6878 	u8         reserved_at_20[0x10];
6879 	u8         op_mod[0x10];
6880 
6881 	u8         reserved_at_40[0x40];
6882 };
6883 
6884 struct mlx5_ifc_query_diagnostic_params_out_bits {
6885 	u8         status[0x8];
6886 	u8         reserved_at_8[0x18];
6887 
6888 	u8         syndrome[0x20];
6889 
6890 	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6891 };
6892 
6893 struct mlx5_ifc_set_diagnostic_params_in_bits {
6894 	u8         opcode[0x10];
6895 	u8         reserved_0[0x10];
6896 
6897 	u8         reserved_1[0x10];
6898 	u8         op_mod[0x10];
6899 
6900 	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
6901 };
6902 
6903 struct mlx5_ifc_set_diagnostic_params_out_bits {
6904 	u8         status[0x8];
6905 	u8         reserved_0[0x18];
6906 
6907 	u8         syndrome[0x20];
6908 
6909 	u8         reserved_1[0x40];
6910 };
6911 
6912 struct mlx5_ifc_query_diagnostic_counters_in_bits {
6913 	u8         opcode[0x10];
6914 	u8         reserved_0[0x10];
6915 
6916 	u8         reserved_1[0x10];
6917 	u8         op_mod[0x10];
6918 
6919 	u8         num_of_samples[0x10];
6920 	u8         sample_index[0x10];
6921 
6922 	u8         reserved_2[0x20];
6923 };
6924 
6925 struct mlx5_ifc_diagnostic_counter_bits {
6926 	u8         counter_id[0x10];
6927 	u8         sample_id[0x10];
6928 
6929 	u8         time_stamp_31_0[0x20];
6930 
6931 	u8         counter_value_h[0x20];
6932 
6933 	u8         counter_value_l[0x20];
6934 };
6935 
6936 struct mlx5_ifc_query_diagnostic_counters_out_bits {
6937 	u8         status[0x8];
6938 	u8         reserved_0[0x18];
6939 
6940 	u8         syndrome[0x20];
6941 
6942 	u8         reserved_1[0x40];
6943 
6944 	struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
6945 };
6946 
6947 struct mlx5_ifc_dealloc_q_counter_in_bits {
6948 	u8         opcode[0x10];
6949 	u8         reserved_0[0x10];
6950 
6951 	u8         reserved_1[0x10];
6952 	u8         op_mod[0x10];
6953 
6954 	u8         reserved_2[0x18];
6955 	u8         counter_set_id[0x8];
6956 
6957 	u8         reserved_3[0x20];
6958 };
6959 
6960 struct mlx5_ifc_dealloc_pd_out_bits {
6961 	u8         status[0x8];
6962 	u8         reserved_0[0x18];
6963 
6964 	u8         syndrome[0x20];
6965 
6966 	u8         reserved_1[0x40];
6967 };
6968 
6969 struct mlx5_ifc_dealloc_pd_in_bits {
6970 	u8         opcode[0x10];
6971 	u8         reserved_0[0x10];
6972 
6973 	u8         reserved_1[0x10];
6974 	u8         op_mod[0x10];
6975 
6976 	u8         reserved_2[0x8];
6977 	u8         pd[0x18];
6978 
6979 	u8         reserved_3[0x20];
6980 };
6981 
6982 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6983 	u8         status[0x8];
6984 	u8         reserved_0[0x18];
6985 
6986 	u8         syndrome[0x20];
6987 
6988 	u8         reserved_1[0x40];
6989 };
6990 
6991 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6992 	u8         opcode[0x10];
6993 	u8         reserved_0[0x10];
6994 
6995 	u8         reserved_1[0x10];
6996 	u8         op_mod[0x10];
6997 
6998 	u8         reserved_2[0x10];
6999 	u8         flow_counter_id[0x10];
7000 
7001 	u8         reserved_3[0x20];
7002 };
7003 
7004 struct mlx5_ifc_deactivate_tracer_out_bits {
7005 	u8         status[0x8];
7006 	u8         reserved_0[0x18];
7007 
7008 	u8         syndrome[0x20];
7009 
7010 	u8         reserved_1[0x40];
7011 };
7012 
7013 struct mlx5_ifc_deactivate_tracer_in_bits {
7014 	u8         opcode[0x10];
7015 	u8         reserved_0[0x10];
7016 
7017 	u8         reserved_1[0x10];
7018 	u8         op_mod[0x10];
7019 
7020 	u8         mkey[0x20];
7021 
7022 	u8         reserved_2[0x20];
7023 };
7024 
7025 struct mlx5_ifc_create_xrc_srq_out_bits {
7026 	u8         status[0x8];
7027 	u8         reserved_0[0x18];
7028 
7029 	u8         syndrome[0x20];
7030 
7031 	u8         reserved_1[0x8];
7032 	u8         xrc_srqn[0x18];
7033 
7034 	u8         reserved_2[0x20];
7035 };
7036 
7037 struct mlx5_ifc_create_xrc_srq_in_bits {
7038 	u8         opcode[0x10];
7039 	u8         reserved_0[0x10];
7040 
7041 	u8         reserved_1[0x10];
7042 	u8         op_mod[0x10];
7043 
7044 	u8         reserved_2[0x40];
7045 
7046 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7047 
7048 	u8         reserved_3[0x600];
7049 
7050 	u8         pas[0][0x40];
7051 };
7052 
7053 struct mlx5_ifc_create_tis_out_bits {
7054 	u8         status[0x8];
7055 	u8         reserved_0[0x18];
7056 
7057 	u8         syndrome[0x20];
7058 
7059 	u8         reserved_1[0x8];
7060 	u8         tisn[0x18];
7061 
7062 	u8         reserved_2[0x20];
7063 };
7064 
7065 struct mlx5_ifc_create_tis_in_bits {
7066 	u8         opcode[0x10];
7067 	u8         reserved_0[0x10];
7068 
7069 	u8         reserved_1[0x10];
7070 	u8         op_mod[0x10];
7071 
7072 	u8         reserved_2[0xc0];
7073 
7074 	struct mlx5_ifc_tisc_bits ctx;
7075 };
7076 
7077 struct mlx5_ifc_create_tir_out_bits {
7078 	u8         status[0x8];
7079 	u8         reserved_0[0x18];
7080 
7081 	u8         syndrome[0x20];
7082 
7083 	u8         reserved_1[0x8];
7084 	u8         tirn[0x18];
7085 
7086 	u8         reserved_2[0x20];
7087 };
7088 
7089 struct mlx5_ifc_create_tir_in_bits {
7090 	u8         opcode[0x10];
7091 	u8         reserved_0[0x10];
7092 
7093 	u8         reserved_1[0x10];
7094 	u8         op_mod[0x10];
7095 
7096 	u8         reserved_2[0xc0];
7097 
7098 	struct mlx5_ifc_tirc_bits tir_context;
7099 };
7100 
7101 struct mlx5_ifc_create_srq_out_bits {
7102 	u8         status[0x8];
7103 	u8         reserved_0[0x18];
7104 
7105 	u8         syndrome[0x20];
7106 
7107 	u8         reserved_1[0x8];
7108 	u8         srqn[0x18];
7109 
7110 	u8         reserved_2[0x20];
7111 };
7112 
7113 struct mlx5_ifc_create_srq_in_bits {
7114 	u8         opcode[0x10];
7115 	u8         reserved_0[0x10];
7116 
7117 	u8         reserved_1[0x10];
7118 	u8         op_mod[0x10];
7119 
7120 	u8         reserved_2[0x40];
7121 
7122 	struct mlx5_ifc_srqc_bits srq_context_entry;
7123 
7124 	u8         reserved_3[0x600];
7125 
7126 	u8         pas[0][0x40];
7127 };
7128 
7129 struct mlx5_ifc_create_sq_out_bits {
7130 	u8         status[0x8];
7131 	u8         reserved_0[0x18];
7132 
7133 	u8         syndrome[0x20];
7134 
7135 	u8         reserved_1[0x8];
7136 	u8         sqn[0x18];
7137 
7138 	u8         reserved_2[0x20];
7139 };
7140 
7141 struct mlx5_ifc_create_sq_in_bits {
7142 	u8         opcode[0x10];
7143 	u8         uid[0x10];
7144 
7145 	u8         reserved_1[0x10];
7146 	u8         op_mod[0x10];
7147 
7148 	u8         reserved_2[0xc0];
7149 
7150 	struct mlx5_ifc_sqc_bits ctx;
7151 };
7152 
7153 struct mlx5_ifc_create_scheduling_element_out_bits {
7154 	u8         status[0x8];
7155 	u8         reserved_at_8[0x18];
7156 
7157 	u8         syndrome[0x20];
7158 
7159 	u8         reserved_at_40[0x40];
7160 
7161 	u8         scheduling_element_id[0x20];
7162 
7163 	u8         reserved_at_a0[0x160];
7164 };
7165 
7166 enum {
7167 	MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
7168 };
7169 
7170 struct mlx5_ifc_create_scheduling_element_in_bits {
7171 	u8         opcode[0x10];
7172 	u8         reserved_at_10[0x10];
7173 
7174 	u8         reserved_at_20[0x10];
7175 	u8         op_mod[0x10];
7176 
7177 	u8         scheduling_hierarchy[0x8];
7178 	u8         reserved_at_48[0x18];
7179 
7180 	u8         reserved_at_60[0xa0];
7181 
7182 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7183 
7184 	u8         reserved_at_300[0x100];
7185 };
7186 
7187 struct mlx5_ifc_create_rqt_out_bits {
7188 	u8         status[0x8];
7189 	u8         reserved_0[0x18];
7190 
7191 	u8         syndrome[0x20];
7192 
7193 	u8         reserved_1[0x8];
7194 	u8         rqtn[0x18];
7195 
7196 	u8         reserved_2[0x20];
7197 };
7198 
7199 struct mlx5_ifc_create_rqt_in_bits {
7200 	u8         opcode[0x10];
7201 	u8         reserved_0[0x10];
7202 
7203 	u8         reserved_1[0x10];
7204 	u8         op_mod[0x10];
7205 
7206 	u8         reserved_2[0xc0];
7207 
7208 	struct mlx5_ifc_rqtc_bits rqt_context;
7209 };
7210 
7211 struct mlx5_ifc_create_rq_out_bits {
7212 	u8         status[0x8];
7213 	u8         reserved_0[0x18];
7214 
7215 	u8         syndrome[0x20];
7216 
7217 	u8         reserved_1[0x8];
7218 	u8         rqn[0x18];
7219 
7220 	u8         reserved_2[0x20];
7221 };
7222 
7223 struct mlx5_ifc_create_rq_in_bits {
7224 	u8         opcode[0x10];
7225 	u8         uid[0x10];
7226 
7227 	u8         reserved_1[0x10];
7228 	u8         op_mod[0x10];
7229 
7230 	u8         reserved_2[0xc0];
7231 
7232 	struct mlx5_ifc_rqc_bits ctx;
7233 };
7234 
7235 struct mlx5_ifc_create_rmp_out_bits {
7236 	u8         status[0x8];
7237 	u8         reserved_0[0x18];
7238 
7239 	u8         syndrome[0x20];
7240 
7241 	u8         reserved_1[0x8];
7242 	u8         rmpn[0x18];
7243 
7244 	u8         reserved_2[0x20];
7245 };
7246 
7247 struct mlx5_ifc_create_rmp_in_bits {
7248 	u8         opcode[0x10];
7249 	u8         reserved_0[0x10];
7250 
7251 	u8         reserved_1[0x10];
7252 	u8         op_mod[0x10];
7253 
7254 	u8         reserved_2[0xc0];
7255 
7256 	struct mlx5_ifc_rmpc_bits ctx;
7257 };
7258 
7259 struct mlx5_ifc_create_qp_out_bits {
7260 	u8         status[0x8];
7261 	u8         reserved_0[0x18];
7262 
7263 	u8         syndrome[0x20];
7264 
7265 	u8         reserved_1[0x8];
7266 	u8         qpn[0x18];
7267 
7268 	u8         reserved_2[0x20];
7269 };
7270 
7271 struct mlx5_ifc_create_qp_in_bits {
7272 	u8         opcode[0x10];
7273 	u8         uid[0x10];
7274 
7275 	u8         reserved_1[0x10];
7276 	u8         op_mod[0x10];
7277 
7278 	u8         reserved_2[0x8];
7279 	u8         input_qpn[0x18];
7280 
7281 	u8         reserved_3[0x20];
7282 
7283 	u8         opt_param_mask[0x20];
7284 
7285 	u8         reserved_4[0x20];
7286 
7287 	struct mlx5_ifc_qpc_bits qpc;
7288 
7289 	u8         reserved_5[0x80];
7290 
7291 	u8         pas[0][0x40];
7292 };
7293 
7294 struct mlx5_ifc_create_qos_para_vport_out_bits {
7295 	u8         status[0x8];
7296 	u8         reserved_at_8[0x18];
7297 
7298 	u8         syndrome[0x20];
7299 
7300 	u8         reserved_at_40[0x20];
7301 
7302 	u8         reserved_at_60[0x10];
7303 	u8         qos_para_vport_number[0x10];
7304 
7305 	u8         reserved_at_80[0x180];
7306 };
7307 
7308 struct mlx5_ifc_create_qos_para_vport_in_bits {
7309 	u8         opcode[0x10];
7310 	u8         reserved_at_10[0x10];
7311 
7312 	u8         reserved_at_20[0x10];
7313 	u8         op_mod[0x10];
7314 
7315 	u8         reserved_at_40[0x1c0];
7316 };
7317 
7318 struct mlx5_ifc_create_psv_out_bits {
7319 	u8         status[0x8];
7320 	u8         reserved_0[0x18];
7321 
7322 	u8         syndrome[0x20];
7323 
7324 	u8         reserved_1[0x40];
7325 
7326 	u8         reserved_2[0x8];
7327 	u8         psv0_index[0x18];
7328 
7329 	u8         reserved_3[0x8];
7330 	u8         psv1_index[0x18];
7331 
7332 	u8         reserved_4[0x8];
7333 	u8         psv2_index[0x18];
7334 
7335 	u8         reserved_5[0x8];
7336 	u8         psv3_index[0x18];
7337 };
7338 
7339 struct mlx5_ifc_create_psv_in_bits {
7340 	u8         opcode[0x10];
7341 	u8         reserved_0[0x10];
7342 
7343 	u8         reserved_1[0x10];
7344 	u8         op_mod[0x10];
7345 
7346 	u8         num_psv[0x4];
7347 	u8         reserved_2[0x4];
7348 	u8         pd[0x18];
7349 
7350 	u8         reserved_3[0x20];
7351 };
7352 
7353 struct mlx5_ifc_create_mkey_out_bits {
7354 	u8         status[0x8];
7355 	u8         reserved_0[0x18];
7356 
7357 	u8         syndrome[0x20];
7358 
7359 	u8         reserved_1[0x8];
7360 	u8         mkey_index[0x18];
7361 
7362 	u8         reserved_2[0x20];
7363 };
7364 
7365 struct mlx5_ifc_create_mkey_in_bits {
7366 	u8         opcode[0x10];
7367 	u8         reserved_0[0x10];
7368 
7369 	u8         reserved_1[0x10];
7370 	u8         op_mod[0x10];
7371 
7372 	u8         reserved_2[0x20];
7373 
7374 	u8         pg_access[0x1];
7375 	u8         reserved_3[0x1f];
7376 
7377 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7378 
7379 	u8         reserved_4[0x80];
7380 
7381 	u8         translations_octword_actual_size[0x20];
7382 
7383 	u8         reserved_5[0x560];
7384 
7385 	u8         klm_pas_mtt[0][0x20];
7386 };
7387 
7388 struct mlx5_ifc_create_flow_table_out_bits {
7389 	u8         status[0x8];
7390 	u8         reserved_0[0x18];
7391 
7392 	u8         syndrome[0x20];
7393 
7394 	u8         reserved_1[0x8];
7395 	u8         table_id[0x18];
7396 
7397 	u8         reserved_2[0x20];
7398 };
7399 
7400 struct mlx5_ifc_create_flow_table_in_bits {
7401 	u8         opcode[0x10];
7402 	u8         reserved_at_10[0x10];
7403 
7404 	u8         reserved_at_20[0x10];
7405 	u8         op_mod[0x10];
7406 
7407 	u8         other_vport[0x1];
7408 	u8         reserved_at_41[0xf];
7409 	u8         vport_number[0x10];
7410 
7411 	u8         reserved_at_60[0x20];
7412 
7413 	u8         table_type[0x8];
7414 	u8         reserved_at_88[0x18];
7415 
7416 	u8         reserved_at_a0[0x20];
7417 
7418 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
7419 };
7420 
7421 struct mlx5_ifc_create_flow_group_out_bits {
7422 	u8         status[0x8];
7423 	u8         reserved_0[0x18];
7424 
7425 	u8         syndrome[0x20];
7426 
7427 	u8         reserved_1[0x8];
7428 	u8         group_id[0x18];
7429 
7430 	u8         reserved_2[0x20];
7431 };
7432 
7433 enum {
7434 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
7435 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
7436 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
7437 };
7438 
7439 struct mlx5_ifc_create_flow_group_in_bits {
7440 	u8         opcode[0x10];
7441 	u8         reserved_0[0x10];
7442 
7443 	u8         reserved_1[0x10];
7444 	u8         op_mod[0x10];
7445 
7446 	u8         other_vport[0x1];
7447 	u8         reserved_2[0xf];
7448 	u8         vport_number[0x10];
7449 
7450 	u8         reserved_3[0x20];
7451 
7452 	u8         table_type[0x8];
7453 	u8         reserved_4[0x18];
7454 
7455 	u8         reserved_5[0x8];
7456 	u8         table_id[0x18];
7457 
7458 	u8         reserved_6[0x20];
7459 
7460 	u8         start_flow_index[0x20];
7461 
7462 	u8         reserved_7[0x20];
7463 
7464 	u8         end_flow_index[0x20];
7465 
7466 	u8         reserved_8[0xa0];
7467 
7468 	u8         reserved_9[0x18];
7469 	u8         match_criteria_enable[0x8];
7470 
7471 	struct mlx5_ifc_fte_match_param_bits match_criteria;
7472 
7473 	u8         reserved_10[0xe00];
7474 };
7475 
7476 struct mlx5_ifc_create_encryption_key_out_bits {
7477 	u8         status[0x8];
7478 	u8         reserved_at_8[0x18];
7479 
7480 	u8         syndrome[0x20];
7481 
7482 	u8         obj_id[0x20];
7483 
7484 	u8         reserved_at_60[0x20];
7485 };
7486 
7487 struct mlx5_ifc_create_encryption_key_in_bits {
7488 	u8         opcode[0x10];
7489 	u8         reserved_at_10[0x10];
7490 
7491 	u8         reserved_at_20[0x10];
7492 	u8         obj_type[0x10];
7493 
7494 	u8         reserved_at_40[0x40];
7495 
7496 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
7497 };
7498 
7499 struct mlx5_ifc_create_eq_out_bits {
7500 	u8         status[0x8];
7501 	u8         reserved_0[0x18];
7502 
7503 	u8         syndrome[0x20];
7504 
7505 	u8         reserved_1[0x18];
7506 	u8         eq_number[0x8];
7507 
7508 	u8         reserved_2[0x20];
7509 };
7510 
7511 struct mlx5_ifc_create_eq_in_bits {
7512 	u8         opcode[0x10];
7513 	u8         reserved_0[0x10];
7514 
7515 	u8         reserved_1[0x10];
7516 	u8         op_mod[0x10];
7517 
7518 	u8         reserved_2[0x40];
7519 
7520 	struct mlx5_ifc_eqc_bits eq_context_entry;
7521 
7522 	u8         reserved_3[0x40];
7523 
7524 	u8         event_bitmask[0x40];
7525 
7526 	u8         reserved_4[0x580];
7527 
7528 	u8         pas[0][0x40];
7529 };
7530 
7531 struct mlx5_ifc_create_dct_out_bits {
7532 	u8         status[0x8];
7533 	u8         reserved_0[0x18];
7534 
7535 	u8         syndrome[0x20];
7536 
7537 	u8         reserved_1[0x8];
7538 	u8         dctn[0x18];
7539 
7540 	u8         reserved_2[0x20];
7541 };
7542 
7543 struct mlx5_ifc_create_dct_in_bits {
7544 	u8         opcode[0x10];
7545 	u8         uid[0x10];
7546 
7547 	u8         reserved_1[0x10];
7548 	u8         op_mod[0x10];
7549 
7550 	u8         reserved_2[0x40];
7551 
7552 	struct mlx5_ifc_dctc_bits dct_context_entry;
7553 
7554 	u8         reserved_3[0x180];
7555 };
7556 
7557 struct mlx5_ifc_create_cq_out_bits {
7558 	u8         status[0x8];
7559 	u8         reserved_0[0x18];
7560 
7561 	u8         syndrome[0x20];
7562 
7563 	u8         reserved_1[0x8];
7564 	u8         cqn[0x18];
7565 
7566 	u8         reserved_2[0x20];
7567 };
7568 
7569 struct mlx5_ifc_create_cq_in_bits {
7570 	u8         opcode[0x10];
7571 	u8         reserved_0[0x10];
7572 
7573 	u8         reserved_1[0x10];
7574 	u8         op_mod[0x10];
7575 
7576 	u8         reserved_2[0x40];
7577 
7578 	struct mlx5_ifc_cqc_bits cq_context;
7579 
7580 	u8         reserved_3[0x600];
7581 
7582 	u8         pas[0][0x40];
7583 };
7584 
7585 struct mlx5_ifc_config_int_moderation_out_bits {
7586 	u8         status[0x8];
7587 	u8         reserved_0[0x18];
7588 
7589 	u8         syndrome[0x20];
7590 
7591 	u8         reserved_1[0x4];
7592 	u8         min_delay[0xc];
7593 	u8         int_vector[0x10];
7594 
7595 	u8         reserved_2[0x20];
7596 };
7597 
7598 enum {
7599 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7600 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7601 };
7602 
7603 struct mlx5_ifc_config_int_moderation_in_bits {
7604 	u8         opcode[0x10];
7605 	u8         reserved_0[0x10];
7606 
7607 	u8         reserved_1[0x10];
7608 	u8         op_mod[0x10];
7609 
7610 	u8         reserved_2[0x4];
7611 	u8         min_delay[0xc];
7612 	u8         int_vector[0x10];
7613 
7614 	u8         reserved_3[0x20];
7615 };
7616 
7617 struct mlx5_ifc_attach_to_mcg_out_bits {
7618 	u8         status[0x8];
7619 	u8         reserved_0[0x18];
7620 
7621 	u8         syndrome[0x20];
7622 
7623 	u8         reserved_1[0x40];
7624 };
7625 
7626 struct mlx5_ifc_attach_to_mcg_in_bits {
7627 	u8         opcode[0x10];
7628 	u8         reserved_0[0x10];
7629 
7630 	u8         reserved_1[0x10];
7631 	u8         op_mod[0x10];
7632 
7633 	u8         reserved_2[0x8];
7634 	u8         qpn[0x18];
7635 
7636 	u8         reserved_3[0x20];
7637 
7638 	u8         multicast_gid[16][0x8];
7639 };
7640 
7641 struct mlx5_ifc_arm_xrc_srq_out_bits {
7642 	u8         status[0x8];
7643 	u8         reserved_0[0x18];
7644 
7645 	u8         syndrome[0x20];
7646 
7647 	u8         reserved_1[0x40];
7648 };
7649 
7650 enum {
7651 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7652 };
7653 
7654 struct mlx5_ifc_arm_xrc_srq_in_bits {
7655 	u8         opcode[0x10];
7656 	u8         reserved_0[0x10];
7657 
7658 	u8         reserved_1[0x10];
7659 	u8         op_mod[0x10];
7660 
7661 	u8         reserved_2[0x8];
7662 	u8         xrc_srqn[0x18];
7663 
7664 	u8         reserved_3[0x10];
7665 	u8         lwm[0x10];
7666 };
7667 
7668 struct mlx5_ifc_arm_rq_out_bits {
7669 	u8         status[0x8];
7670 	u8         reserved_0[0x18];
7671 
7672 	u8         syndrome[0x20];
7673 
7674 	u8         reserved_1[0x40];
7675 };
7676 
7677 enum {
7678 	MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
7679 };
7680 
7681 struct mlx5_ifc_arm_rq_in_bits {
7682 	u8         opcode[0x10];
7683 	u8         reserved_0[0x10];
7684 
7685 	u8         reserved_1[0x10];
7686 	u8         op_mod[0x10];
7687 
7688 	u8         reserved_2[0x8];
7689 	u8         srq_number[0x18];
7690 
7691 	u8         reserved_3[0x10];
7692 	u8         lwm[0x10];
7693 };
7694 
7695 struct mlx5_ifc_arm_dct_out_bits {
7696 	u8         status[0x8];
7697 	u8         reserved_0[0x18];
7698 
7699 	u8         syndrome[0x20];
7700 
7701 	u8         reserved_1[0x40];
7702 };
7703 
7704 struct mlx5_ifc_arm_dct_in_bits {
7705 	u8         opcode[0x10];
7706 	u8         reserved_0[0x10];
7707 
7708 	u8         reserved_1[0x10];
7709 	u8         op_mod[0x10];
7710 
7711 	u8         reserved_2[0x8];
7712 	u8         dctn[0x18];
7713 
7714 	u8         reserved_3[0x20];
7715 };
7716 
7717 struct mlx5_ifc_alloc_xrcd_out_bits {
7718 	u8         status[0x8];
7719 	u8         reserved_0[0x18];
7720 
7721 	u8         syndrome[0x20];
7722 
7723 	u8         reserved_1[0x8];
7724 	u8         xrcd[0x18];
7725 
7726 	u8         reserved_2[0x20];
7727 };
7728 
7729 struct mlx5_ifc_alloc_xrcd_in_bits {
7730 	u8         opcode[0x10];
7731 	u8         reserved_0[0x10];
7732 
7733 	u8         reserved_1[0x10];
7734 	u8         op_mod[0x10];
7735 
7736 	u8         reserved_2[0x40];
7737 };
7738 
7739 struct mlx5_ifc_alloc_uar_out_bits {
7740 	u8         status[0x8];
7741 	u8         reserved_0[0x18];
7742 
7743 	u8         syndrome[0x20];
7744 
7745 	u8         reserved_1[0x8];
7746 	u8         uar[0x18];
7747 
7748 	u8         reserved_2[0x20];
7749 };
7750 
7751 struct mlx5_ifc_alloc_uar_in_bits {
7752 	u8         opcode[0x10];
7753 	u8         reserved_0[0x10];
7754 
7755 	u8         reserved_1[0x10];
7756 	u8         op_mod[0x10];
7757 
7758 	u8         reserved_2[0x40];
7759 };
7760 
7761 struct mlx5_ifc_alloc_transport_domain_out_bits {
7762 	u8         status[0x8];
7763 	u8         reserved_0[0x18];
7764 
7765 	u8         syndrome[0x20];
7766 
7767 	u8         reserved_1[0x8];
7768 	u8         transport_domain[0x18];
7769 
7770 	u8         reserved_2[0x20];
7771 };
7772 
7773 struct mlx5_ifc_alloc_transport_domain_in_bits {
7774 	u8         opcode[0x10];
7775 	u8         reserved_0[0x10];
7776 
7777 	u8         reserved_1[0x10];
7778 	u8         op_mod[0x10];
7779 
7780 	u8         reserved_2[0x40];
7781 };
7782 
7783 struct mlx5_ifc_alloc_q_counter_out_bits {
7784 	u8         status[0x8];
7785 	u8         reserved_0[0x18];
7786 
7787 	u8         syndrome[0x20];
7788 
7789 	u8         reserved_1[0x18];
7790 	u8         counter_set_id[0x8];
7791 
7792 	u8         reserved_2[0x20];
7793 };
7794 
7795 struct mlx5_ifc_alloc_q_counter_in_bits {
7796 	u8         opcode[0x10];
7797 	u8         reserved_0[0x10];
7798 
7799 	u8         reserved_1[0x10];
7800 	u8         op_mod[0x10];
7801 
7802 	u8         reserved_2[0x40];
7803 };
7804 
7805 struct mlx5_ifc_alloc_pd_out_bits {
7806 	u8         status[0x8];
7807 	u8         reserved_0[0x18];
7808 
7809 	u8         syndrome[0x20];
7810 
7811 	u8         reserved_1[0x8];
7812 	u8         pd[0x18];
7813 
7814 	u8         reserved_2[0x20];
7815 };
7816 
7817 struct mlx5_ifc_alloc_pd_in_bits {
7818 	u8         opcode[0x10];
7819 	u8         reserved_0[0x10];
7820 
7821 	u8         reserved_1[0x10];
7822 	u8         op_mod[0x10];
7823 
7824 	u8         reserved_2[0x40];
7825 };
7826 
7827 struct mlx5_ifc_alloc_flow_counter_out_bits {
7828 	u8         status[0x8];
7829 	u8         reserved_0[0x18];
7830 
7831 	u8         syndrome[0x20];
7832 
7833 	u8         reserved_1[0x10];
7834 	u8         flow_counter_id[0x10];
7835 
7836 	u8         reserved_2[0x20];
7837 };
7838 
7839 struct mlx5_ifc_alloc_flow_counter_in_bits {
7840 	u8         opcode[0x10];
7841 	u8         reserved_0[0x10];
7842 
7843 	u8         reserved_1[0x10];
7844 	u8         op_mod[0x10];
7845 
7846 	u8         reserved_2[0x40];
7847 };
7848 
7849 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7850 	u8         status[0x8];
7851 	u8         reserved_0[0x18];
7852 
7853 	u8         syndrome[0x20];
7854 
7855 	u8         reserved_1[0x40];
7856 };
7857 
7858 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7859 	u8         opcode[0x10];
7860 	u8         reserved_0[0x10];
7861 
7862 	u8         reserved_1[0x10];
7863 	u8         op_mod[0x10];
7864 
7865 	u8         reserved_2[0x20];
7866 
7867 	u8         reserved_3[0x10];
7868 	u8         vxlan_udp_port[0x10];
7869 };
7870 
7871 struct mlx5_ifc_activate_tracer_out_bits {
7872 	u8         status[0x8];
7873 	u8         reserved_0[0x18];
7874 
7875 	u8         syndrome[0x20];
7876 
7877 	u8         reserved_1[0x40];
7878 };
7879 
7880 struct mlx5_ifc_activate_tracer_in_bits {
7881 	u8         opcode[0x10];
7882 	u8         reserved_0[0x10];
7883 
7884 	u8         reserved_1[0x10];
7885 	u8         op_mod[0x10];
7886 
7887 	u8         mkey[0x20];
7888 
7889 	u8         reserved_2[0x20];
7890 };
7891 
7892 struct mlx5_ifc_set_rate_limit_out_bits {
7893 	u8         status[0x8];
7894 	u8         reserved_at_8[0x18];
7895 
7896 	u8         syndrome[0x20];
7897 
7898 	u8         reserved_at_40[0x40];
7899 };
7900 
7901 struct mlx5_ifc_set_rate_limit_in_bits {
7902 	u8         opcode[0x10];
7903 	u8         reserved_at_10[0x10];
7904 
7905 	u8         reserved_at_20[0x10];
7906 	u8         op_mod[0x10];
7907 
7908 	u8         reserved_at_40[0x10];
7909 	u8         rate_limit_index[0x10];
7910 
7911 	u8         reserved_at_60[0x20];
7912 
7913 	u8         rate_limit[0x20];
7914 
7915 	u8         burst_upper_bound[0x20];
7916 
7917 	u8         reserved_at_c0[0x10];
7918 	u8         typical_packet_size[0x10];
7919 
7920 	u8         reserved_at_e0[0x120];
7921 };
7922 
7923 struct mlx5_ifc_access_register_out_bits {
7924 	u8         status[0x8];
7925 	u8         reserved_0[0x18];
7926 
7927 	u8         syndrome[0x20];
7928 
7929 	u8         reserved_1[0x40];
7930 
7931 	u8         register_data[0][0x20];
7932 };
7933 
7934 enum {
7935 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7936 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7937 };
7938 
7939 struct mlx5_ifc_access_register_in_bits {
7940 	u8         opcode[0x10];
7941 	u8         reserved_0[0x10];
7942 
7943 	u8         reserved_1[0x10];
7944 	u8         op_mod[0x10];
7945 
7946 	u8         reserved_2[0x10];
7947 	u8         register_id[0x10];
7948 
7949 	u8         argument[0x20];
7950 
7951 	u8         register_data[0][0x20];
7952 };
7953 
7954 struct mlx5_ifc_sltp_reg_bits {
7955 	u8         status[0x4];
7956 	u8         version[0x4];
7957 	u8         local_port[0x8];
7958 	u8         pnat[0x2];
7959 	u8         reserved_0[0x2];
7960 	u8         lane[0x4];
7961 	u8         reserved_1[0x8];
7962 
7963 	u8         reserved_2[0x20];
7964 
7965 	u8         reserved_3[0x7];
7966 	u8         polarity[0x1];
7967 	u8         ob_tap0[0x8];
7968 	u8         ob_tap1[0x8];
7969 	u8         ob_tap2[0x8];
7970 
7971 	u8         reserved_4[0xc];
7972 	u8         ob_preemp_mode[0x4];
7973 	u8         ob_reg[0x8];
7974 	u8         ob_bias[0x8];
7975 
7976 	u8         reserved_5[0x20];
7977 };
7978 
7979 struct mlx5_ifc_slrp_reg_bits {
7980 	u8         status[0x4];
7981 	u8         version[0x4];
7982 	u8         local_port[0x8];
7983 	u8         pnat[0x2];
7984 	u8         reserved_0[0x2];
7985 	u8         lane[0x4];
7986 	u8         reserved_1[0x8];
7987 
7988 	u8         ib_sel[0x2];
7989 	u8         reserved_2[0x11];
7990 	u8         dp_sel[0x1];
7991 	u8         dp90sel[0x4];
7992 	u8         mix90phase[0x8];
7993 
7994 	u8         ffe_tap0[0x8];
7995 	u8         ffe_tap1[0x8];
7996 	u8         ffe_tap2[0x8];
7997 	u8         ffe_tap3[0x8];
7998 
7999 	u8         ffe_tap4[0x8];
8000 	u8         ffe_tap5[0x8];
8001 	u8         ffe_tap6[0x8];
8002 	u8         ffe_tap7[0x8];
8003 
8004 	u8         ffe_tap8[0x8];
8005 	u8         mixerbias_tap_amp[0x8];
8006 	u8         reserved_3[0x7];
8007 	u8         ffe_tap_en[0x9];
8008 
8009 	u8         ffe_tap_offset0[0x8];
8010 	u8         ffe_tap_offset1[0x8];
8011 	u8         slicer_offset0[0x10];
8012 
8013 	u8         mixer_offset0[0x10];
8014 	u8         mixer_offset1[0x10];
8015 
8016 	u8         mixerbgn_inp[0x8];
8017 	u8         mixerbgn_inn[0x8];
8018 	u8         mixerbgn_refp[0x8];
8019 	u8         mixerbgn_refn[0x8];
8020 
8021 	u8         sel_slicer_lctrl_h[0x1];
8022 	u8         sel_slicer_lctrl_l[0x1];
8023 	u8         reserved_4[0x1];
8024 	u8         ref_mixer_vreg[0x5];
8025 	u8         slicer_gctrl[0x8];
8026 	u8         lctrl_input[0x8];
8027 	u8         mixer_offset_cm1[0x8];
8028 
8029 	u8         common_mode[0x6];
8030 	u8         reserved_5[0x1];
8031 	u8         mixer_offset_cm0[0x9];
8032 	u8         reserved_6[0x7];
8033 	u8         slicer_offset_cm[0x9];
8034 };
8035 
8036 struct mlx5_ifc_slrg_reg_bits {
8037 	u8         status[0x4];
8038 	u8         version[0x4];
8039 	u8         local_port[0x8];
8040 	u8         pnat[0x2];
8041 	u8         reserved_0[0x2];
8042 	u8         lane[0x4];
8043 	u8         reserved_1[0x8];
8044 
8045 	u8         time_to_link_up[0x10];
8046 	u8         reserved_2[0xc];
8047 	u8         grade_lane_speed[0x4];
8048 
8049 	u8         grade_version[0x8];
8050 	u8         grade[0x18];
8051 
8052 	u8         reserved_3[0x4];
8053 	u8         height_grade_type[0x4];
8054 	u8         height_grade[0x18];
8055 
8056 	u8         height_dz[0x10];
8057 	u8         height_dv[0x10];
8058 
8059 	u8         reserved_4[0x10];
8060 	u8         height_sigma[0x10];
8061 
8062 	u8         reserved_5[0x20];
8063 
8064 	u8         reserved_6[0x4];
8065 	u8         phase_grade_type[0x4];
8066 	u8         phase_grade[0x18];
8067 
8068 	u8         reserved_7[0x8];
8069 	u8         phase_eo_pos[0x8];
8070 	u8         reserved_8[0x8];
8071 	u8         phase_eo_neg[0x8];
8072 
8073 	u8         ffe_set_tested[0x10];
8074 	u8         test_errors_per_lane[0x10];
8075 };
8076 
8077 struct mlx5_ifc_pvlc_reg_bits {
8078 	u8         reserved_0[0x8];
8079 	u8         local_port[0x8];
8080 	u8         reserved_1[0x10];
8081 
8082 	u8         reserved_2[0x1c];
8083 	u8         vl_hw_cap[0x4];
8084 
8085 	u8         reserved_3[0x1c];
8086 	u8         vl_admin[0x4];
8087 
8088 	u8         reserved_4[0x1c];
8089 	u8         vl_operational[0x4];
8090 };
8091 
8092 struct mlx5_ifc_pude_reg_bits {
8093 	u8         swid[0x8];
8094 	u8         local_port[0x8];
8095 	u8         reserved_0[0x4];
8096 	u8         admin_status[0x4];
8097 	u8         reserved_1[0x4];
8098 	u8         oper_status[0x4];
8099 
8100 	u8         reserved_2[0x60];
8101 };
8102 
8103 enum {
8104 	MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
8105 	MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
8106 };
8107 
8108 struct mlx5_ifc_ptys_reg_bits {
8109 	u8         reserved_0[0x1];
8110 	u8         an_disable_admin[0x1];
8111 	u8         an_disable_cap[0x1];
8112 	u8         reserved_1[0x4];
8113 	u8         force_tx_aba_param[0x1];
8114 	u8         local_port[0x8];
8115 	u8         reserved_2[0xd];
8116 	u8         proto_mask[0x3];
8117 
8118 	u8         an_status[0x4];
8119 	u8         reserved_3[0xc];
8120 	u8         data_rate_oper[0x10];
8121 
8122 	u8         ext_eth_proto_capability[0x20];
8123 
8124 	u8         eth_proto_capability[0x20];
8125 
8126 	u8         ib_link_width_capability[0x10];
8127 	u8         ib_proto_capability[0x10];
8128 
8129 	u8         ext_eth_proto_admin[0x20];
8130 
8131 	u8         eth_proto_admin[0x20];
8132 
8133 	u8         ib_link_width_admin[0x10];
8134 	u8         ib_proto_admin[0x10];
8135 
8136 	u8         ext_eth_proto_oper[0x20];
8137 
8138 	u8         eth_proto_oper[0x20];
8139 
8140 	u8         ib_link_width_oper[0x10];
8141 	u8         ib_proto_oper[0x10];
8142 
8143 	u8         reserved_4[0x1c];
8144 	u8         connector_type[0x4];
8145 
8146 	u8         eth_proto_lp_advertise[0x20];
8147 
8148 	u8         reserved_5[0x60];
8149 };
8150 
8151 struct mlx5_ifc_ptas_reg_bits {
8152 	u8         reserved_0[0x20];
8153 
8154 	u8         algorithm_options[0x10];
8155 	u8         reserved_1[0x4];
8156 	u8         repetitions_mode[0x4];
8157 	u8         num_of_repetitions[0x8];
8158 
8159 	u8         grade_version[0x8];
8160 	u8         height_grade_type[0x4];
8161 	u8         phase_grade_type[0x4];
8162 	u8         height_grade_weight[0x8];
8163 	u8         phase_grade_weight[0x8];
8164 
8165 	u8         gisim_measure_bits[0x10];
8166 	u8         adaptive_tap_measure_bits[0x10];
8167 
8168 	u8         ber_bath_high_error_threshold[0x10];
8169 	u8         ber_bath_mid_error_threshold[0x10];
8170 
8171 	u8         ber_bath_low_error_threshold[0x10];
8172 	u8         one_ratio_high_threshold[0x10];
8173 
8174 	u8         one_ratio_high_mid_threshold[0x10];
8175 	u8         one_ratio_low_mid_threshold[0x10];
8176 
8177 	u8         one_ratio_low_threshold[0x10];
8178 	u8         ndeo_error_threshold[0x10];
8179 
8180 	u8         mixer_offset_step_size[0x10];
8181 	u8         reserved_2[0x8];
8182 	u8         mix90_phase_for_voltage_bath[0x8];
8183 
8184 	u8         mixer_offset_start[0x10];
8185 	u8         mixer_offset_end[0x10];
8186 
8187 	u8         reserved_3[0x15];
8188 	u8         ber_test_time[0xb];
8189 };
8190 
8191 struct mlx5_ifc_pspa_reg_bits {
8192 	u8         swid[0x8];
8193 	u8         local_port[0x8];
8194 	u8         sub_port[0x8];
8195 	u8         reserved_0[0x8];
8196 
8197 	u8         reserved_1[0x20];
8198 };
8199 
8200 struct mlx5_ifc_ppsc_reg_bits {
8201 	u8         reserved_0[0x8];
8202 	u8         local_port[0x8];
8203 	u8         reserved_1[0x10];
8204 
8205 	u8         reserved_2[0x60];
8206 
8207 	u8         reserved_3[0x1c];
8208 	u8         wrps_admin[0x4];
8209 
8210 	u8         reserved_4[0x1c];
8211 	u8         wrps_status[0x4];
8212 
8213 	u8         up_th_vld[0x1];
8214 	u8         down_th_vld[0x1];
8215 	u8         reserved_5[0x6];
8216 	u8         up_threshold[0x8];
8217 	u8         reserved_6[0x8];
8218 	u8         down_threshold[0x8];
8219 
8220 	u8         reserved_7[0x20];
8221 
8222 	u8         reserved_8[0x1c];
8223 	u8         srps_admin[0x4];
8224 
8225 	u8         reserved_9[0x60];
8226 };
8227 
8228 struct mlx5_ifc_pplr_reg_bits {
8229 	u8         reserved_0[0x8];
8230 	u8         local_port[0x8];
8231 	u8         reserved_1[0x10];
8232 
8233 	u8         reserved_2[0x8];
8234 	u8         lb_cap[0x8];
8235 	u8         reserved_3[0x8];
8236 	u8         lb_en[0x8];
8237 };
8238 
8239 struct mlx5_ifc_pplm_reg_bits {
8240 	u8         reserved_at_0[0x8];
8241 	u8	   local_port[0x8];
8242 	u8	   reserved_at_10[0x10];
8243 
8244 	u8	   reserved_at_20[0x20];
8245 
8246 	u8	   port_profile_mode[0x8];
8247 	u8	   static_port_profile[0x8];
8248 	u8	   active_port_profile[0x8];
8249 	u8	   reserved_at_58[0x8];
8250 
8251 	u8	   retransmission_active[0x8];
8252 	u8	   fec_mode_active[0x18];
8253 
8254 	u8	   rs_fec_correction_bypass_cap[0x4];
8255 	u8	   reserved_at_84[0x8];
8256 	u8	   fec_override_cap_56g[0x4];
8257 	u8	   fec_override_cap_100g[0x4];
8258 	u8	   fec_override_cap_50g[0x4];
8259 	u8	   fec_override_cap_25g[0x4];
8260 	u8	   fec_override_cap_10g_40g[0x4];
8261 
8262 	u8	   rs_fec_correction_bypass_admin[0x4];
8263 	u8	   reserved_at_a4[0x8];
8264 	u8	   fec_override_admin_56g[0x4];
8265 	u8	   fec_override_admin_100g[0x4];
8266 	u8	   fec_override_admin_50g[0x4];
8267 	u8	   fec_override_admin_25g[0x4];
8268 	u8	   fec_override_admin_10g_40g[0x4];
8269 
8270 	u8	   fec_override_cap_400g_8x[0x10];
8271 	u8	   fec_override_cap_200g_4x[0x10];
8272 	u8	   fec_override_cap_100g_2x[0x10];
8273 	u8	   fec_override_cap_50g_1x[0x10];
8274 
8275 	u8	   fec_override_admin_400g_8x[0x10];
8276 	u8	   fec_override_admin_200g_4x[0x10];
8277 	u8	   fec_override_admin_100g_2x[0x10];
8278 	u8	   fec_override_admin_50g_1x[0x10];
8279 
8280 	u8	   reserved_at_140[0x140];
8281 };
8282 
8283 struct mlx5_ifc_ppll_reg_bits {
8284 	u8         num_pll_groups[0x8];
8285 	u8         pll_group[0x8];
8286 	u8         reserved_0[0x4];
8287 	u8         num_plls[0x4];
8288 	u8         reserved_1[0x8];
8289 
8290 	u8         reserved_2[0x1f];
8291 	u8         ae[0x1];
8292 
8293 	u8         pll_status[4][0x40];
8294 };
8295 
8296 struct mlx5_ifc_ppad_reg_bits {
8297 	u8         reserved_0[0x3];
8298 	u8         single_mac[0x1];
8299 	u8         reserved_1[0x4];
8300 	u8         local_port[0x8];
8301 	u8         mac_47_32[0x10];
8302 
8303 	u8         mac_31_0[0x20];
8304 
8305 	u8         reserved_2[0x40];
8306 };
8307 
8308 struct mlx5_ifc_pmtu_reg_bits {
8309 	u8         reserved_0[0x8];
8310 	u8         local_port[0x8];
8311 	u8         reserved_1[0x10];
8312 
8313 	u8         max_mtu[0x10];
8314 	u8         reserved_2[0x10];
8315 
8316 	u8         admin_mtu[0x10];
8317 	u8         reserved_3[0x10];
8318 
8319 	u8         oper_mtu[0x10];
8320 	u8         reserved_4[0x10];
8321 };
8322 
8323 struct mlx5_ifc_pmpr_reg_bits {
8324 	u8         reserved_0[0x8];
8325 	u8         module[0x8];
8326 	u8         reserved_1[0x10];
8327 
8328 	u8         reserved_2[0x18];
8329 	u8         attenuation_5g[0x8];
8330 
8331 	u8         reserved_3[0x18];
8332 	u8         attenuation_7g[0x8];
8333 
8334 	u8         reserved_4[0x18];
8335 	u8         attenuation_12g[0x8];
8336 };
8337 
8338 struct mlx5_ifc_pmpe_reg_bits {
8339 	u8         reserved_0[0x8];
8340 	u8         module[0x8];
8341 	u8         reserved_1[0xc];
8342 	u8         module_status[0x4];
8343 
8344 	u8         reserved_2[0x14];
8345 	u8         error_type[0x4];
8346 	u8         reserved_3[0x8];
8347 
8348 	u8         reserved_4[0x40];
8349 };
8350 
8351 struct mlx5_ifc_pmpc_reg_bits {
8352 	u8         module_state_updated[32][0x8];
8353 };
8354 
8355 struct mlx5_ifc_pmlpn_reg_bits {
8356 	u8         reserved_0[0x4];
8357 	u8         mlpn_status[0x4];
8358 	u8         local_port[0x8];
8359 	u8         reserved_1[0x10];
8360 
8361 	u8         e[0x1];
8362 	u8         reserved_2[0x1f];
8363 };
8364 
8365 struct mlx5_ifc_pmlp_reg_bits {
8366 	u8         rxtx[0x1];
8367 	u8         reserved_0[0x7];
8368 	u8         local_port[0x8];
8369 	u8         reserved_1[0x8];
8370 	u8         width[0x8];
8371 
8372 	u8         lane0_module_mapping[0x20];
8373 
8374 	u8         lane1_module_mapping[0x20];
8375 
8376 	u8         lane2_module_mapping[0x20];
8377 
8378 	u8         lane3_module_mapping[0x20];
8379 
8380 	u8         reserved_2[0x160];
8381 };
8382 
8383 struct mlx5_ifc_pmaos_reg_bits {
8384 	u8         reserved_0[0x8];
8385 	u8         module[0x8];
8386 	u8         reserved_1[0x4];
8387 	u8         admin_status[0x4];
8388 	u8         reserved_2[0x4];
8389 	u8         oper_status[0x4];
8390 
8391 	u8         ase[0x1];
8392 	u8         ee[0x1];
8393 	u8         reserved_3[0x12];
8394 	u8         error_type[0x4];
8395 	u8         reserved_4[0x6];
8396 	u8         e[0x2];
8397 
8398 	u8         reserved_5[0x40];
8399 };
8400 
8401 struct mlx5_ifc_plpc_reg_bits {
8402 	u8         reserved_0[0x4];
8403 	u8         profile_id[0xc];
8404 	u8         reserved_1[0x4];
8405 	u8         proto_mask[0x4];
8406 	u8         reserved_2[0x8];
8407 
8408 	u8         reserved_3[0x10];
8409 	u8         lane_speed[0x10];
8410 
8411 	u8         reserved_4[0x17];
8412 	u8         lpbf[0x1];
8413 	u8         fec_mode_policy[0x8];
8414 
8415 	u8         retransmission_capability[0x8];
8416 	u8         fec_mode_capability[0x18];
8417 
8418 	u8         retransmission_support_admin[0x8];
8419 	u8         fec_mode_support_admin[0x18];
8420 
8421 	u8         retransmission_request_admin[0x8];
8422 	u8         fec_mode_request_admin[0x18];
8423 
8424 	u8         reserved_5[0x80];
8425 };
8426 
8427 struct mlx5_ifc_pll_status_data_bits {
8428 	u8         reserved_0[0x1];
8429 	u8         lock_cal[0x1];
8430 	u8         lock_status[0x2];
8431 	u8         reserved_1[0x2];
8432 	u8         algo_f_ctrl[0xa];
8433 	u8         analog_algo_num_var[0x6];
8434 	u8         f_ctrl_measure[0xa];
8435 
8436 	u8         reserved_2[0x2];
8437 	u8         analog_var[0x6];
8438 	u8         reserved_3[0x2];
8439 	u8         high_var[0x6];
8440 	u8         reserved_4[0x2];
8441 	u8         low_var[0x6];
8442 	u8         reserved_5[0x2];
8443 	u8         mid_val[0x6];
8444 };
8445 
8446 struct mlx5_ifc_plib_reg_bits {
8447 	u8         reserved_0[0x8];
8448 	u8         local_port[0x8];
8449 	u8         reserved_1[0x8];
8450 	u8         ib_port[0x8];
8451 
8452 	u8         reserved_2[0x60];
8453 };
8454 
8455 struct mlx5_ifc_plbf_reg_bits {
8456 	u8         reserved_0[0x8];
8457 	u8         local_port[0x8];
8458 	u8         reserved_1[0xd];
8459 	u8         lbf_mode[0x3];
8460 
8461 	u8         reserved_2[0x20];
8462 };
8463 
8464 struct mlx5_ifc_pipg_reg_bits {
8465 	u8         reserved_0[0x8];
8466 	u8         local_port[0x8];
8467 	u8         reserved_1[0x10];
8468 
8469 	u8         dic[0x1];
8470 	u8         reserved_2[0x19];
8471 	u8         ipg[0x4];
8472 	u8         reserved_3[0x2];
8473 };
8474 
8475 struct mlx5_ifc_pifr_reg_bits {
8476 	u8         reserved_0[0x8];
8477 	u8         local_port[0x8];
8478 	u8         reserved_1[0x10];
8479 
8480 	u8         reserved_2[0xe0];
8481 
8482 	u8         port_filter[8][0x20];
8483 
8484 	u8         port_filter_update_en[8][0x20];
8485 };
8486 
8487 struct mlx5_ifc_phys_layer_cntrs_bits {
8488 	u8         time_since_last_clear_high[0x20];
8489 
8490 	u8         time_since_last_clear_low[0x20];
8491 
8492 	u8         symbol_errors_high[0x20];
8493 
8494 	u8         symbol_errors_low[0x20];
8495 
8496 	u8         sync_headers_errors_high[0x20];
8497 
8498 	u8         sync_headers_errors_low[0x20];
8499 
8500 	u8         edpl_bip_errors_lane0_high[0x20];
8501 
8502 	u8         edpl_bip_errors_lane0_low[0x20];
8503 
8504 	u8         edpl_bip_errors_lane1_high[0x20];
8505 
8506 	u8         edpl_bip_errors_lane1_low[0x20];
8507 
8508 	u8         edpl_bip_errors_lane2_high[0x20];
8509 
8510 	u8         edpl_bip_errors_lane2_low[0x20];
8511 
8512 	u8         edpl_bip_errors_lane3_high[0x20];
8513 
8514 	u8         edpl_bip_errors_lane3_low[0x20];
8515 
8516 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
8517 
8518 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
8519 
8520 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
8521 
8522 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
8523 
8524 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
8525 
8526 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
8527 
8528 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
8529 
8530 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
8531 
8532 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
8533 
8534 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
8535 
8536 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
8537 
8538 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
8539 
8540 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
8541 
8542 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
8543 
8544 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
8545 
8546 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
8547 
8548 	u8         rs_fec_corrected_blocks_high[0x20];
8549 
8550 	u8         rs_fec_corrected_blocks_low[0x20];
8551 
8552 	u8         rs_fec_uncorrectable_blocks_high[0x20];
8553 
8554 	u8         rs_fec_uncorrectable_blocks_low[0x20];
8555 
8556 	u8         rs_fec_no_errors_blocks_high[0x20];
8557 
8558 	u8         rs_fec_no_errors_blocks_low[0x20];
8559 
8560 	u8         rs_fec_single_error_blocks_high[0x20];
8561 
8562 	u8         rs_fec_single_error_blocks_low[0x20];
8563 
8564 	u8         rs_fec_corrected_symbols_total_high[0x20];
8565 
8566 	u8         rs_fec_corrected_symbols_total_low[0x20];
8567 
8568 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
8569 
8570 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
8571 
8572 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
8573 
8574 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
8575 
8576 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
8577 
8578 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
8579 
8580 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
8581 
8582 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
8583 
8584 	u8         link_down_events[0x20];
8585 
8586 	u8         successful_recovery_events[0x20];
8587 
8588 	u8         reserved_0[0x180];
8589 };
8590 
8591 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
8592 	u8	   symbol_error_counter[0x10];
8593 
8594 	u8         link_error_recovery_counter[0x8];
8595 
8596 	u8         link_downed_counter[0x8];
8597 
8598 	u8         port_rcv_errors[0x10];
8599 
8600 	u8         port_rcv_remote_physical_errors[0x10];
8601 
8602 	u8         port_rcv_switch_relay_errors[0x10];
8603 
8604 	u8         port_xmit_discards[0x10];
8605 
8606 	u8         port_xmit_constraint_errors[0x8];
8607 
8608 	u8         port_rcv_constraint_errors[0x8];
8609 
8610 	u8         reserved_at_70[0x8];
8611 
8612 	u8         link_overrun_errors[0x8];
8613 
8614 	u8	   reserved_at_80[0x10];
8615 
8616 	u8         vl_15_dropped[0x10];
8617 
8618 	u8	   reserved_at_a0[0xa0];
8619 };
8620 
8621 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
8622 	u8         time_since_last_clear_high[0x20];
8623 
8624 	u8         time_since_last_clear_low[0x20];
8625 
8626 	u8         phy_received_bits_high[0x20];
8627 
8628 	u8         phy_received_bits_low[0x20];
8629 
8630 	u8         phy_symbol_errors_high[0x20];
8631 
8632 	u8         phy_symbol_errors_low[0x20];
8633 
8634 	u8         phy_corrected_bits_high[0x20];
8635 
8636 	u8         phy_corrected_bits_low[0x20];
8637 
8638 	u8         phy_corrected_bits_lane0_high[0x20];
8639 
8640 	u8         phy_corrected_bits_lane0_low[0x20];
8641 
8642 	u8         phy_corrected_bits_lane1_high[0x20];
8643 
8644 	u8         phy_corrected_bits_lane1_low[0x20];
8645 
8646 	u8         phy_corrected_bits_lane2_high[0x20];
8647 
8648 	u8         phy_corrected_bits_lane2_low[0x20];
8649 
8650 	u8         phy_corrected_bits_lane3_high[0x20];
8651 
8652 	u8         phy_corrected_bits_lane3_low[0x20];
8653 
8654 	u8         reserved_at_200[0x5c0];
8655 };
8656 
8657 struct mlx5_ifc_infiniband_port_cntrs_bits {
8658 	u8         symbol_error_counter[0x10];
8659 	u8         link_error_recovery_counter[0x8];
8660 	u8         link_downed_counter[0x8];
8661 
8662 	u8         port_rcv_errors[0x10];
8663 	u8         port_rcv_remote_physical_errors[0x10];
8664 
8665 	u8         port_rcv_switch_relay_errors[0x10];
8666 	u8         port_xmit_discards[0x10];
8667 
8668 	u8         port_xmit_constraint_errors[0x8];
8669 	u8         port_rcv_constraint_errors[0x8];
8670 	u8         reserved_0[0x8];
8671 	u8         local_link_integrity_errors[0x4];
8672 	u8         excessive_buffer_overrun_errors[0x4];
8673 
8674 	u8         reserved_1[0x10];
8675 	u8         vl_15_dropped[0x10];
8676 
8677 	u8         port_xmit_data[0x20];
8678 
8679 	u8         port_rcv_data[0x20];
8680 
8681 	u8         port_xmit_pkts[0x20];
8682 
8683 	u8         port_rcv_pkts[0x20];
8684 
8685 	u8         port_xmit_wait[0x20];
8686 
8687 	u8         reserved_2[0x680];
8688 };
8689 
8690 struct mlx5_ifc_phrr_reg_bits {
8691 	u8         clr[0x1];
8692 	u8         reserved_0[0x7];
8693 	u8         local_port[0x8];
8694 	u8         reserved_1[0x10];
8695 
8696 	u8         hist_group[0x8];
8697 	u8         reserved_2[0x10];
8698 	u8         hist_id[0x8];
8699 
8700 	u8         reserved_3[0x40];
8701 
8702 	u8         time_since_last_clear_high[0x20];
8703 
8704 	u8         time_since_last_clear_low[0x20];
8705 
8706 	u8         bin[10][0x20];
8707 };
8708 
8709 struct mlx5_ifc_phbr_for_prio_reg_bits {
8710 	u8         reserved_0[0x18];
8711 	u8         prio[0x8];
8712 };
8713 
8714 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
8715 	u8         reserved_0[0x18];
8716 	u8         tclass[0x8];
8717 };
8718 
8719 struct mlx5_ifc_phbr_binding_reg_bits {
8720 	u8         opcode[0x4];
8721 	u8         reserved_0[0x4];
8722 	u8         local_port[0x8];
8723 	u8         pnat[0x2];
8724 	u8         reserved_1[0xe];
8725 
8726 	u8         hist_group[0x8];
8727 	u8         reserved_2[0x10];
8728 	u8         hist_id[0x8];
8729 
8730 	u8         reserved_3[0x10];
8731 	u8         hist_type[0x10];
8732 
8733 	u8         hist_parameters[0x20];
8734 
8735 	u8         hist_min_value[0x20];
8736 
8737 	u8         hist_max_value[0x20];
8738 
8739 	u8         sample_time[0x20];
8740 };
8741 
8742 enum {
8743 	MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
8744 	MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
8745 };
8746 
8747 struct mlx5_ifc_pfcc_reg_bits {
8748 	u8         dcbx_operation_type[0x2];
8749 	u8         cap_local_admin[0x1];
8750 	u8         cap_remote_admin[0x1];
8751 	u8         reserved_0[0x4];
8752 	u8         local_port[0x8];
8753 	u8         pnat[0x2];
8754 	u8         reserved_1[0xc];
8755 	u8         shl_cap[0x1];
8756 	u8         shl_opr[0x1];
8757 
8758 	u8         ppan[0x4];
8759 	u8         reserved_2[0x4];
8760 	u8         prio_mask_tx[0x8];
8761 	u8         reserved_3[0x8];
8762 	u8         prio_mask_rx[0x8];
8763 
8764 	u8         pptx[0x1];
8765 	u8         aptx[0x1];
8766 	u8         reserved_4[0x6];
8767 	u8         pfctx[0x8];
8768 	u8         reserved_5[0x8];
8769 	u8         cbftx[0x8];
8770 
8771 	u8         pprx[0x1];
8772 	u8         aprx[0x1];
8773 	u8         reserved_6[0x6];
8774 	u8         pfcrx[0x8];
8775 	u8         reserved_7[0x8];
8776 	u8         cbfrx[0x8];
8777 
8778 	u8         device_stall_minor_watermark[0x10];
8779 	u8         device_stall_critical_watermark[0x10];
8780 
8781 	u8         reserved_8[0x60];
8782 };
8783 
8784 struct mlx5_ifc_pelc_reg_bits {
8785 	u8         op[0x4];
8786 	u8         reserved_0[0x4];
8787 	u8         local_port[0x8];
8788 	u8         reserved_1[0x10];
8789 
8790 	u8         op_admin[0x8];
8791 	u8         op_capability[0x8];
8792 	u8         op_request[0x8];
8793 	u8         op_active[0x8];
8794 
8795 	u8         admin[0x40];
8796 
8797 	u8         capability[0x40];
8798 
8799 	u8         request[0x40];
8800 
8801 	u8         active[0x40];
8802 
8803 	u8         reserved_2[0x80];
8804 };
8805 
8806 struct mlx5_ifc_peir_reg_bits {
8807 	u8         reserved_0[0x8];
8808 	u8         local_port[0x8];
8809 	u8         reserved_1[0x10];
8810 
8811 	u8         reserved_2[0xc];
8812 	u8         error_count[0x4];
8813 	u8         reserved_3[0x10];
8814 
8815 	u8         reserved_4[0xc];
8816 	u8         lane[0x4];
8817 	u8         reserved_5[0x8];
8818 	u8         error_type[0x8];
8819 };
8820 
8821 struct mlx5_ifc_qcam_access_reg_cap_mask {
8822 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8823 	u8         qpdpm[0x1];
8824 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8825 	u8         qdpm[0x1];
8826 	u8         qpts[0x1];
8827 	u8         qcap[0x1];
8828 	u8         qcam_access_reg_cap_mask_0[0x1];
8829 };
8830 
8831 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8832 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8833 	u8         qpts_trust_both[0x1];
8834 };
8835 
8836 struct mlx5_ifc_qcam_reg_bits {
8837 	u8         reserved_at_0[0x8];
8838 	u8         feature_group[0x8];
8839 	u8         reserved_at_10[0x8];
8840 	u8         access_reg_group[0x8];
8841 	u8         reserved_at_20[0x20];
8842 
8843 	union {
8844 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8845 		u8  reserved_at_0[0x80];
8846 	} qos_access_reg_cap_mask;
8847 
8848 	u8         reserved_at_c0[0x80];
8849 
8850 	union {
8851 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8852 		u8  reserved_at_0[0x80];
8853 	} qos_feature_cap_mask;
8854 
8855 	u8         reserved_at_1c0[0x80];
8856 };
8857 
8858 struct mlx5_ifc_pcam_enhanced_features_bits {
8859 	u8         reserved_at_0[0x6d];
8860 	u8         rx_icrc_encapsulated_counter[0x1];
8861 	u8	   reserved_at_6e[0x4];
8862 	u8         ptys_extended_ethernet[0x1];
8863 	u8	   reserved_at_73[0x3];
8864 	u8         pfcc_mask[0x1];
8865 	u8         reserved_at_77[0x3];
8866 	u8         per_lane_error_counters[0x1];
8867 	u8         rx_buffer_fullness_counters[0x1];
8868 	u8         ptys_connector_type[0x1];
8869 	u8         reserved_at_7d[0x1];
8870 	u8         ppcnt_discard_group[0x1];
8871 	u8         ppcnt_statistical_group[0x1];
8872 };
8873 
8874 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8875 	u8         port_access_reg_cap_mask_127_to_96[0x20];
8876 	u8         port_access_reg_cap_mask_95_to_64[0x20];
8877 
8878 	u8         reserved_at_40[0xe];
8879 	u8         pddr[0x1];
8880 	u8         reserved_at_4f[0xd];
8881 
8882 	u8         pplm[0x1];
8883 	u8         port_access_reg_cap_mask_34_to_32[0x3];
8884 
8885 	u8         port_access_reg_cap_mask_31_to_13[0x13];
8886 	u8         pbmc[0x1];
8887 	u8         pptb[0x1];
8888 	u8         port_access_reg_cap_mask_10_to_09[0x2];
8889 	u8         ppcnt[0x1];
8890 	u8         port_access_reg_cap_mask_07_to_00[0x8];
8891 };
8892 
8893 struct mlx5_ifc_pcam_reg_bits {
8894 	u8         reserved_at_0[0x8];
8895 	u8         feature_group[0x8];
8896 	u8         reserved_at_10[0x8];
8897 	u8         access_reg_group[0x8];
8898 
8899 	u8         reserved_at_20[0x20];
8900 
8901 	union {
8902 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8903 		u8         reserved_at_0[0x80];
8904 	} port_access_reg_cap_mask;
8905 
8906 	u8         reserved_at_c0[0x80];
8907 
8908 	union {
8909 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8910 		u8         reserved_at_0[0x80];
8911 	} feature_cap_mask;
8912 
8913 	u8         reserved_at_1c0[0xc0];
8914 };
8915 
8916 struct mlx5_ifc_mcam_enhanced_features_bits {
8917 	u8         reserved_at_0[0x6e];
8918 	u8         pcie_status_and_power[0x1];
8919 	u8         reserved_at_111[0x10];
8920 	u8         pcie_performance_group[0x1];
8921 };
8922 
8923 struct mlx5_ifc_mcam_access_reg_bits {
8924 	u8         reserved_at_0[0x1c];
8925 	u8         mcda[0x1];
8926 	u8         mcc[0x1];
8927 	u8         mcqi[0x1];
8928 	u8         reserved_at_1f[0x1];
8929 
8930 	u8         regs_95_to_64[0x20];
8931 	u8         regs_63_to_32[0x20];
8932 	u8         regs_31_to_0[0x20];
8933 };
8934 
8935 struct mlx5_ifc_mcam_reg_bits {
8936 	u8         reserved_at_0[0x8];
8937 	u8         feature_group[0x8];
8938 	u8         reserved_at_10[0x8];
8939 	u8         access_reg_group[0x8];
8940 
8941 	u8         reserved_at_20[0x20];
8942 
8943 	union {
8944 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
8945 		u8         reserved_at_0[0x80];
8946 	} mng_access_reg_cap_mask;
8947 
8948 	u8         reserved_at_c0[0x80];
8949 
8950 	union {
8951 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8952 		u8         reserved_at_0[0x80];
8953 	} mng_feature_cap_mask;
8954 
8955 	u8         reserved_at_1c0[0x80];
8956 };
8957 
8958 struct mlx5_ifc_pcap_reg_bits {
8959 	u8         reserved_0[0x8];
8960 	u8         local_port[0x8];
8961 	u8         reserved_1[0x10];
8962 
8963 	u8         port_capability_mask[4][0x20];
8964 };
8965 
8966 struct mlx5_ifc_pbmc_reg_bits {
8967 	u8         reserved_at_0[0x8];
8968 	u8         local_port[0x8];
8969 	u8         reserved_at_10[0x10];
8970 
8971 	u8         xoff_timer_value[0x10];
8972 	u8         xoff_refresh[0x10];
8973 
8974 	u8         reserved_at_40[0x9];
8975 	u8         fullness_threshold[0x7];
8976 	u8         port_buffer_size[0x10];
8977 
8978 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
8979 
8980 	u8         reserved_at_2e0[0x80];
8981 };
8982 
8983 struct mlx5_ifc_paos_reg_bits {
8984 	u8         swid[0x8];
8985 	u8         local_port[0x8];
8986 	u8         reserved_0[0x4];
8987 	u8         admin_status[0x4];
8988 	u8         reserved_1[0x4];
8989 	u8         oper_status[0x4];
8990 
8991 	u8         ase[0x1];
8992 	u8         ee[0x1];
8993 	u8         reserved_2[0x1c];
8994 	u8         e[0x2];
8995 
8996 	u8         reserved_3[0x40];
8997 };
8998 
8999 struct mlx5_ifc_pamp_reg_bits {
9000 	u8         reserved_0[0x8];
9001 	u8         opamp_group[0x8];
9002 	u8         reserved_1[0xc];
9003 	u8         opamp_group_type[0x4];
9004 
9005 	u8         start_index[0x10];
9006 	u8         reserved_2[0x4];
9007 	u8         num_of_indices[0xc];
9008 
9009 	u8         index_data[18][0x10];
9010 };
9011 
9012 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
9013 	u8         llr_rx_cells_high[0x20];
9014 
9015 	u8         llr_rx_cells_low[0x20];
9016 
9017 	u8         llr_rx_error_high[0x20];
9018 
9019 	u8         llr_rx_error_low[0x20];
9020 
9021 	u8         llr_rx_crc_error_high[0x20];
9022 
9023 	u8         llr_rx_crc_error_low[0x20];
9024 
9025 	u8         llr_tx_cells_high[0x20];
9026 
9027 	u8         llr_tx_cells_low[0x20];
9028 
9029 	u8         llr_tx_ret_cells_high[0x20];
9030 
9031 	u8         llr_tx_ret_cells_low[0x20];
9032 
9033 	u8         llr_tx_ret_events_high[0x20];
9034 
9035 	u8         llr_tx_ret_events_low[0x20];
9036 
9037 	u8         reserved_0[0x640];
9038 };
9039 
9040 struct mlx5_ifc_mtmp_reg_bits {
9041 	u8         i[0x1];
9042 	u8         reserved_at_1[0x18];
9043 	u8         sensor_index[0x7];
9044 
9045 	u8         reserved_at_20[0x10];
9046 	u8         temperature[0x10];
9047 
9048 	u8         mte[0x1];
9049 	u8         mtr[0x1];
9050 	u8         reserved_at_42[0x0e];
9051 	u8         max_temperature[0x10];
9052 
9053 	u8         tee[0x2];
9054 	u8         reserved_at_62[0x0e];
9055 	u8         temperature_threshold_hi[0x10];
9056 
9057 	u8         reserved_at_80[0x10];
9058 	u8         temperature_threshold_lo[0x10];
9059 
9060 	u8         reserved_at_100[0x20];
9061 
9062 	u8         sensor_name[0x40];
9063 };
9064 
9065 struct mlx5_ifc_lane_2_module_mapping_bits {
9066 	u8         reserved_0[0x6];
9067 	u8         rx_lane[0x2];
9068 	u8         reserved_1[0x6];
9069 	u8         tx_lane[0x2];
9070 	u8         reserved_2[0x8];
9071 	u8         module[0x8];
9072 };
9073 
9074 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
9075 	u8         transmit_queue_high[0x20];
9076 
9077 	u8         transmit_queue_low[0x20];
9078 
9079 	u8         reserved_0[0x780];
9080 };
9081 
9082 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
9083 	u8         no_buffer_discard_uc_high[0x20];
9084 
9085 	u8         no_buffer_discard_uc_low[0x20];
9086 
9087 	u8         wred_discard_high[0x20];
9088 
9089 	u8         wred_discard_low[0x20];
9090 
9091 	u8         reserved_0[0x740];
9092 };
9093 
9094 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
9095 	u8         rx_octets_high[0x20];
9096 
9097 	u8         rx_octets_low[0x20];
9098 
9099 	u8         reserved_0[0xc0];
9100 
9101 	u8         rx_frames_high[0x20];
9102 
9103 	u8         rx_frames_low[0x20];
9104 
9105 	u8         tx_octets_high[0x20];
9106 
9107 	u8         tx_octets_low[0x20];
9108 
9109 	u8         reserved_1[0xc0];
9110 
9111 	u8         tx_frames_high[0x20];
9112 
9113 	u8         tx_frames_low[0x20];
9114 
9115 	u8         rx_pause_high[0x20];
9116 
9117 	u8         rx_pause_low[0x20];
9118 
9119 	u8         rx_pause_duration_high[0x20];
9120 
9121 	u8         rx_pause_duration_low[0x20];
9122 
9123 	u8         tx_pause_high[0x20];
9124 
9125 	u8         tx_pause_low[0x20];
9126 
9127 	u8         tx_pause_duration_high[0x20];
9128 
9129 	u8         tx_pause_duration_low[0x20];
9130 
9131 	u8         rx_pause_transition_high[0x20];
9132 
9133 	u8         rx_pause_transition_low[0x20];
9134 
9135 	u8         rx_discards_high[0x20];
9136 
9137 	u8         rx_discards_low[0x20];
9138 
9139 	u8         device_stall_minor_watermark_cnt_high[0x20];
9140 
9141 	u8         device_stall_minor_watermark_cnt_low[0x20];
9142 
9143 	u8         device_stall_critical_watermark_cnt_high[0x20];
9144 
9145 	u8         device_stall_critical_watermark_cnt_low[0x20];
9146 
9147 	u8         reserved_2[0x340];
9148 };
9149 
9150 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
9151 	u8         port_transmit_wait_high[0x20];
9152 
9153 	u8         port_transmit_wait_low[0x20];
9154 
9155 	u8         ecn_marked_high[0x20];
9156 
9157 	u8         ecn_marked_low[0x20];
9158 
9159 	u8         no_buffer_discard_mc_high[0x20];
9160 
9161 	u8         no_buffer_discard_mc_low[0x20];
9162 
9163 	u8         rx_ebp_high[0x20];
9164 
9165 	u8         rx_ebp_low[0x20];
9166 
9167 	u8         tx_ebp_high[0x20];
9168 
9169 	u8         tx_ebp_low[0x20];
9170 
9171         u8         rx_buffer_almost_full_high[0x20];
9172 
9173         u8         rx_buffer_almost_full_low[0x20];
9174 
9175         u8         rx_buffer_full_high[0x20];
9176 
9177         u8         rx_buffer_full_low[0x20];
9178 
9179         u8         rx_icrc_encapsulated_high[0x20];
9180 
9181         u8         rx_icrc_encapsulated_low[0x20];
9182 
9183 	u8         reserved_0[0x80];
9184 
9185         u8         tx_stats_pkts64octets_high[0x20];
9186 
9187         u8         tx_stats_pkts64octets_low[0x20];
9188 
9189         u8         tx_stats_pkts65to127octets_high[0x20];
9190 
9191         u8         tx_stats_pkts65to127octets_low[0x20];
9192 
9193         u8         tx_stats_pkts128to255octets_high[0x20];
9194 
9195         u8         tx_stats_pkts128to255octets_low[0x20];
9196 
9197         u8         tx_stats_pkts256to511octets_high[0x20];
9198 
9199         u8         tx_stats_pkts256to511octets_low[0x20];
9200 
9201         u8         tx_stats_pkts512to1023octets_high[0x20];
9202 
9203         u8         tx_stats_pkts512to1023octets_low[0x20];
9204 
9205         u8         tx_stats_pkts1024to1518octets_high[0x20];
9206 
9207         u8         tx_stats_pkts1024to1518octets_low[0x20];
9208 
9209         u8         tx_stats_pkts1519to2047octets_high[0x20];
9210 
9211         u8         tx_stats_pkts1519to2047octets_low[0x20];
9212 
9213         u8         tx_stats_pkts2048to4095octets_high[0x20];
9214 
9215         u8         tx_stats_pkts2048to4095octets_low[0x20];
9216 
9217         u8         tx_stats_pkts4096to8191octets_high[0x20];
9218 
9219         u8         tx_stats_pkts4096to8191octets_low[0x20];
9220 
9221         u8         tx_stats_pkts8192to10239octets_high[0x20];
9222 
9223         u8         tx_stats_pkts8192to10239octets_low[0x20];
9224 
9225 	u8         reserved_1[0x2C0];
9226 };
9227 
9228 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
9229 	u8         a_frames_transmitted_ok_high[0x20];
9230 
9231 	u8         a_frames_transmitted_ok_low[0x20];
9232 
9233 	u8         a_frames_received_ok_high[0x20];
9234 
9235 	u8         a_frames_received_ok_low[0x20];
9236 
9237 	u8         a_frame_check_sequence_errors_high[0x20];
9238 
9239 	u8         a_frame_check_sequence_errors_low[0x20];
9240 
9241 	u8         a_alignment_errors_high[0x20];
9242 
9243 	u8         a_alignment_errors_low[0x20];
9244 
9245 	u8         a_octets_transmitted_ok_high[0x20];
9246 
9247 	u8         a_octets_transmitted_ok_low[0x20];
9248 
9249 	u8         a_octets_received_ok_high[0x20];
9250 
9251 	u8         a_octets_received_ok_low[0x20];
9252 
9253 	u8         a_multicast_frames_xmitted_ok_high[0x20];
9254 
9255 	u8         a_multicast_frames_xmitted_ok_low[0x20];
9256 
9257 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
9258 
9259 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
9260 
9261 	u8         a_multicast_frames_received_ok_high[0x20];
9262 
9263 	u8         a_multicast_frames_received_ok_low[0x20];
9264 
9265 	u8         a_broadcast_frames_recieved_ok_high[0x20];
9266 
9267 	u8         a_broadcast_frames_recieved_ok_low[0x20];
9268 
9269 	u8         a_in_range_length_errors_high[0x20];
9270 
9271 	u8         a_in_range_length_errors_low[0x20];
9272 
9273 	u8         a_out_of_range_length_field_high[0x20];
9274 
9275 	u8         a_out_of_range_length_field_low[0x20];
9276 
9277 	u8         a_frame_too_long_errors_high[0x20];
9278 
9279 	u8         a_frame_too_long_errors_low[0x20];
9280 
9281 	u8         a_symbol_error_during_carrier_high[0x20];
9282 
9283 	u8         a_symbol_error_during_carrier_low[0x20];
9284 
9285 	u8         a_mac_control_frames_transmitted_high[0x20];
9286 
9287 	u8         a_mac_control_frames_transmitted_low[0x20];
9288 
9289 	u8         a_mac_control_frames_received_high[0x20];
9290 
9291 	u8         a_mac_control_frames_received_low[0x20];
9292 
9293 	u8         a_unsupported_opcodes_received_high[0x20];
9294 
9295 	u8         a_unsupported_opcodes_received_low[0x20];
9296 
9297 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
9298 
9299 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
9300 
9301 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
9302 
9303 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
9304 
9305 	u8         reserved_0[0x300];
9306 };
9307 
9308 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
9309 	u8         dot3stats_alignment_errors_high[0x20];
9310 
9311 	u8         dot3stats_alignment_errors_low[0x20];
9312 
9313 	u8         dot3stats_fcs_errors_high[0x20];
9314 
9315 	u8         dot3stats_fcs_errors_low[0x20];
9316 
9317 	u8         dot3stats_single_collision_frames_high[0x20];
9318 
9319 	u8         dot3stats_single_collision_frames_low[0x20];
9320 
9321 	u8         dot3stats_multiple_collision_frames_high[0x20];
9322 
9323 	u8         dot3stats_multiple_collision_frames_low[0x20];
9324 
9325 	u8         dot3stats_sqe_test_errors_high[0x20];
9326 
9327 	u8         dot3stats_sqe_test_errors_low[0x20];
9328 
9329 	u8         dot3stats_deferred_transmissions_high[0x20];
9330 
9331 	u8         dot3stats_deferred_transmissions_low[0x20];
9332 
9333 	u8         dot3stats_late_collisions_high[0x20];
9334 
9335 	u8         dot3stats_late_collisions_low[0x20];
9336 
9337 	u8         dot3stats_excessive_collisions_high[0x20];
9338 
9339 	u8         dot3stats_excessive_collisions_low[0x20];
9340 
9341 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
9342 
9343 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
9344 
9345 	u8         dot3stats_carrier_sense_errors_high[0x20];
9346 
9347 	u8         dot3stats_carrier_sense_errors_low[0x20];
9348 
9349 	u8         dot3stats_frame_too_longs_high[0x20];
9350 
9351 	u8         dot3stats_frame_too_longs_low[0x20];
9352 
9353 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
9354 
9355 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
9356 
9357 	u8         dot3stats_symbol_errors_high[0x20];
9358 
9359 	u8         dot3stats_symbol_errors_low[0x20];
9360 
9361 	u8         dot3control_in_unknown_opcodes_high[0x20];
9362 
9363 	u8         dot3control_in_unknown_opcodes_low[0x20];
9364 
9365 	u8         dot3in_pause_frames_high[0x20];
9366 
9367 	u8         dot3in_pause_frames_low[0x20];
9368 
9369 	u8         dot3out_pause_frames_high[0x20];
9370 
9371 	u8         dot3out_pause_frames_low[0x20];
9372 
9373 	u8         reserved_0[0x3c0];
9374 };
9375 
9376 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
9377 	u8         if_in_octets_high[0x20];
9378 
9379 	u8         if_in_octets_low[0x20];
9380 
9381 	u8         if_in_ucast_pkts_high[0x20];
9382 
9383 	u8         if_in_ucast_pkts_low[0x20];
9384 
9385 	u8         if_in_discards_high[0x20];
9386 
9387 	u8         if_in_discards_low[0x20];
9388 
9389 	u8         if_in_errors_high[0x20];
9390 
9391 	u8         if_in_errors_low[0x20];
9392 
9393 	u8         if_in_unknown_protos_high[0x20];
9394 
9395 	u8         if_in_unknown_protos_low[0x20];
9396 
9397 	u8         if_out_octets_high[0x20];
9398 
9399 	u8         if_out_octets_low[0x20];
9400 
9401 	u8         if_out_ucast_pkts_high[0x20];
9402 
9403 	u8         if_out_ucast_pkts_low[0x20];
9404 
9405 	u8         if_out_discards_high[0x20];
9406 
9407 	u8         if_out_discards_low[0x20];
9408 
9409 	u8         if_out_errors_high[0x20];
9410 
9411 	u8         if_out_errors_low[0x20];
9412 
9413 	u8         if_in_multicast_pkts_high[0x20];
9414 
9415 	u8         if_in_multicast_pkts_low[0x20];
9416 
9417 	u8         if_in_broadcast_pkts_high[0x20];
9418 
9419 	u8         if_in_broadcast_pkts_low[0x20];
9420 
9421 	u8         if_out_multicast_pkts_high[0x20];
9422 
9423 	u8         if_out_multicast_pkts_low[0x20];
9424 
9425 	u8         if_out_broadcast_pkts_high[0x20];
9426 
9427 	u8         if_out_broadcast_pkts_low[0x20];
9428 
9429 	u8         reserved_0[0x480];
9430 };
9431 
9432 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
9433 	u8         ether_stats_drop_events_high[0x20];
9434 
9435 	u8         ether_stats_drop_events_low[0x20];
9436 
9437 	u8         ether_stats_octets_high[0x20];
9438 
9439 	u8         ether_stats_octets_low[0x20];
9440 
9441 	u8         ether_stats_pkts_high[0x20];
9442 
9443 	u8         ether_stats_pkts_low[0x20];
9444 
9445 	u8         ether_stats_broadcast_pkts_high[0x20];
9446 
9447 	u8         ether_stats_broadcast_pkts_low[0x20];
9448 
9449 	u8         ether_stats_multicast_pkts_high[0x20];
9450 
9451 	u8         ether_stats_multicast_pkts_low[0x20];
9452 
9453 	u8         ether_stats_crc_align_errors_high[0x20];
9454 
9455 	u8         ether_stats_crc_align_errors_low[0x20];
9456 
9457 	u8         ether_stats_undersize_pkts_high[0x20];
9458 
9459 	u8         ether_stats_undersize_pkts_low[0x20];
9460 
9461 	u8         ether_stats_oversize_pkts_high[0x20];
9462 
9463 	u8         ether_stats_oversize_pkts_low[0x20];
9464 
9465 	u8         ether_stats_fragments_high[0x20];
9466 
9467 	u8         ether_stats_fragments_low[0x20];
9468 
9469 	u8         ether_stats_jabbers_high[0x20];
9470 
9471 	u8         ether_stats_jabbers_low[0x20];
9472 
9473 	u8         ether_stats_collisions_high[0x20];
9474 
9475 	u8         ether_stats_collisions_low[0x20];
9476 
9477 	u8         ether_stats_pkts64octets_high[0x20];
9478 
9479 	u8         ether_stats_pkts64octets_low[0x20];
9480 
9481 	u8         ether_stats_pkts65to127octets_high[0x20];
9482 
9483 	u8         ether_stats_pkts65to127octets_low[0x20];
9484 
9485 	u8         ether_stats_pkts128to255octets_high[0x20];
9486 
9487 	u8         ether_stats_pkts128to255octets_low[0x20];
9488 
9489 	u8         ether_stats_pkts256to511octets_high[0x20];
9490 
9491 	u8         ether_stats_pkts256to511octets_low[0x20];
9492 
9493 	u8         ether_stats_pkts512to1023octets_high[0x20];
9494 
9495 	u8         ether_stats_pkts512to1023octets_low[0x20];
9496 
9497 	u8         ether_stats_pkts1024to1518octets_high[0x20];
9498 
9499 	u8         ether_stats_pkts1024to1518octets_low[0x20];
9500 
9501 	u8         ether_stats_pkts1519to2047octets_high[0x20];
9502 
9503 	u8         ether_stats_pkts1519to2047octets_low[0x20];
9504 
9505 	u8         ether_stats_pkts2048to4095octets_high[0x20];
9506 
9507 	u8         ether_stats_pkts2048to4095octets_low[0x20];
9508 
9509 	u8         ether_stats_pkts4096to8191octets_high[0x20];
9510 
9511 	u8         ether_stats_pkts4096to8191octets_low[0x20];
9512 
9513 	u8         ether_stats_pkts8192to10239octets_high[0x20];
9514 
9515 	u8         ether_stats_pkts8192to10239octets_low[0x20];
9516 
9517 	u8         reserved_0[0x280];
9518 };
9519 
9520 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
9521 	u8         symbol_error_counter[0x10];
9522 	u8         link_error_recovery_counter[0x8];
9523 	u8         link_downed_counter[0x8];
9524 
9525 	u8         port_rcv_errors[0x10];
9526 	u8         port_rcv_remote_physical_errors[0x10];
9527 
9528 	u8         port_rcv_switch_relay_errors[0x10];
9529 	u8         port_xmit_discards[0x10];
9530 
9531 	u8         port_xmit_constraint_errors[0x8];
9532 	u8         port_rcv_constraint_errors[0x8];
9533 	u8         reserved_0[0x8];
9534 	u8         local_link_integrity_errors[0x4];
9535 	u8         excessive_buffer_overrun_errors[0x4];
9536 
9537 	u8         reserved_1[0x10];
9538 	u8         vl_15_dropped[0x10];
9539 
9540 	u8         port_xmit_data[0x20];
9541 
9542 	u8         port_rcv_data[0x20];
9543 
9544 	u8         port_xmit_pkts[0x20];
9545 
9546 	u8         port_rcv_pkts[0x20];
9547 
9548 	u8         port_xmit_wait[0x20];
9549 
9550 	u8         reserved_2[0x680];
9551 };
9552 
9553 struct mlx5_ifc_trc_tlb_reg_bits {
9554 	u8         reserved_0[0x80];
9555 
9556 	u8         tlb_addr[0][0x40];
9557 };
9558 
9559 struct mlx5_ifc_trc_read_fifo_reg_bits {
9560 	u8         reserved_0[0x10];
9561 	u8         requested_event_num[0x10];
9562 
9563 	u8         reserved_1[0x20];
9564 
9565 	u8         reserved_2[0x10];
9566 	u8         acual_event_num[0x10];
9567 
9568 	u8         reserved_3[0x20];
9569 
9570 	u8         event[0][0x40];
9571 };
9572 
9573 struct mlx5_ifc_trc_lock_reg_bits {
9574 	u8         reserved_0[0x1f];
9575 	u8         lock[0x1];
9576 
9577 	u8         reserved_1[0x60];
9578 };
9579 
9580 struct mlx5_ifc_trc_filter_reg_bits {
9581 	u8         status[0x1];
9582 	u8         reserved_0[0xf];
9583 	u8         filter_index[0x10];
9584 
9585 	u8         reserved_1[0x20];
9586 
9587 	u8         filter_val[0x20];
9588 
9589 	u8         reserved_2[0x1a0];
9590 };
9591 
9592 struct mlx5_ifc_trc_event_reg_bits {
9593 	u8         status[0x1];
9594 	u8         reserved_0[0xf];
9595 	u8         event_index[0x10];
9596 
9597 	u8         reserved_1[0x20];
9598 
9599 	u8         event_id[0x20];
9600 
9601 	u8         event_selector_val[0x10];
9602 	u8         event_selector_size[0x10];
9603 
9604 	u8         reserved_2[0x180];
9605 };
9606 
9607 struct mlx5_ifc_trc_conf_reg_bits {
9608 	u8         limit_en[0x1];
9609 	u8         reserved_0[0x3];
9610 	u8         dump_mode[0x4];
9611 	u8         reserved_1[0x15];
9612 	u8         state[0x3];
9613 
9614 	u8         reserved_2[0x20];
9615 
9616 	u8         limit_event_index[0x20];
9617 
9618 	u8         mkey[0x20];
9619 
9620 	u8         fifo_ready_ev_num[0x20];
9621 
9622 	u8         reserved_3[0x160];
9623 };
9624 
9625 struct mlx5_ifc_trc_cap_reg_bits {
9626 	u8         reserved_0[0x18];
9627 	u8         dump_mode[0x8];
9628 
9629 	u8         reserved_1[0x20];
9630 
9631 	u8         num_of_events[0x10];
9632 	u8         num_of_filters[0x10];
9633 
9634 	u8         fifo_size[0x20];
9635 
9636 	u8         tlb_size[0x10];
9637 	u8         event_size[0x10];
9638 
9639 	u8         reserved_2[0x160];
9640 };
9641 
9642 struct mlx5_ifc_set_node_in_bits {
9643 	u8         node_description[64][0x8];
9644 };
9645 
9646 struct mlx5_ifc_register_power_settings_bits {
9647 	u8         reserved_0[0x18];
9648 	u8         power_settings_level[0x8];
9649 
9650 	u8         reserved_1[0x60];
9651 };
9652 
9653 struct mlx5_ifc_register_host_endianess_bits {
9654 	u8         he[0x1];
9655 	u8         reserved_0[0x1f];
9656 
9657 	u8         reserved_1[0x60];
9658 };
9659 
9660 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
9661 	u8         physical_address[0x40];
9662 };
9663 
9664 struct mlx5_ifc_qtct_reg_bits {
9665 	u8         operation_type[0x2];
9666 	u8         cap_local_admin[0x1];
9667 	u8         cap_remote_admin[0x1];
9668 	u8         reserved_0[0x4];
9669 	u8         port_number[0x8];
9670 	u8         reserved_1[0xd];
9671 	u8         prio[0x3];
9672 
9673 	u8         reserved_2[0x1d];
9674 	u8         tclass[0x3];
9675 };
9676 
9677 struct mlx5_ifc_qpdp_reg_bits {
9678 	u8         reserved_0[0x8];
9679 	u8         port_number[0x8];
9680 	u8         reserved_1[0x10];
9681 
9682 	u8         reserved_2[0x1d];
9683 	u8         pprio[0x3];
9684 };
9685 
9686 struct mlx5_ifc_port_info_ro_fields_param_bits {
9687 	u8         reserved_0[0x8];
9688 	u8         port[0x8];
9689 	u8         max_gid[0x10];
9690 
9691 	u8         reserved_1[0x20];
9692 
9693 	u8         port_guid[0x40];
9694 };
9695 
9696 struct mlx5_ifc_nvqc_reg_bits {
9697 	u8         type[0x20];
9698 
9699 	u8         reserved_0[0x18];
9700 	u8         version[0x4];
9701 	u8         reserved_1[0x2];
9702 	u8         support_wr[0x1];
9703 	u8         support_rd[0x1];
9704 };
9705 
9706 struct mlx5_ifc_nvia_reg_bits {
9707 	u8         reserved_0[0x1d];
9708 	u8         target[0x3];
9709 
9710 	u8         reserved_1[0x20];
9711 };
9712 
9713 struct mlx5_ifc_nvdi_reg_bits {
9714 	struct mlx5_ifc_config_item_bits configuration_item_header;
9715 };
9716 
9717 struct mlx5_ifc_nvda_reg_bits {
9718 	struct mlx5_ifc_config_item_bits configuration_item_header;
9719 
9720 	u8         configuration_item_data[0x20];
9721 };
9722 
9723 struct mlx5_ifc_node_info_ro_fields_param_bits {
9724 	u8         system_image_guid[0x40];
9725 
9726 	u8         reserved_0[0x40];
9727 
9728 	u8         node_guid[0x40];
9729 
9730 	u8         reserved_1[0x10];
9731 	u8         max_pkey[0x10];
9732 
9733 	u8         reserved_2[0x20];
9734 };
9735 
9736 struct mlx5_ifc_ets_tcn_config_reg_bits {
9737 	u8         g[0x1];
9738 	u8         b[0x1];
9739 	u8         r[0x1];
9740 	u8         reserved_0[0x9];
9741 	u8         group[0x4];
9742 	u8         reserved_1[0x9];
9743 	u8         bw_allocation[0x7];
9744 
9745 	u8         reserved_2[0xc];
9746 	u8         max_bw_units[0x4];
9747 	u8         reserved_3[0x8];
9748 	u8         max_bw_value[0x8];
9749 };
9750 
9751 struct mlx5_ifc_ets_global_config_reg_bits {
9752 	u8         reserved_0[0x2];
9753 	u8         r[0x1];
9754 	u8         reserved_1[0x1d];
9755 
9756 	u8         reserved_2[0xc];
9757 	u8         max_bw_units[0x4];
9758 	u8         reserved_3[0x8];
9759 	u8         max_bw_value[0x8];
9760 };
9761 
9762 struct mlx5_ifc_qetc_reg_bits {
9763 	u8                                         reserved_at_0[0x8];
9764 	u8                                         port_number[0x8];
9765 	u8                                         reserved_at_10[0x30];
9766 
9767 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9768 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9769 };
9770 
9771 struct mlx5_ifc_nodnic_mac_filters_bits {
9772 	struct mlx5_ifc_mac_address_layout_bits mac_filter0;
9773 
9774 	struct mlx5_ifc_mac_address_layout_bits mac_filter1;
9775 
9776 	struct mlx5_ifc_mac_address_layout_bits mac_filter2;
9777 
9778 	struct mlx5_ifc_mac_address_layout_bits mac_filter3;
9779 
9780 	struct mlx5_ifc_mac_address_layout_bits mac_filter4;
9781 
9782 	u8         reserved_0[0xc0];
9783 };
9784 
9785 struct mlx5_ifc_nodnic_gid_filters_bits {
9786 	u8         mgid_filter0[16][0x8];
9787 
9788 	u8         mgid_filter1[16][0x8];
9789 
9790 	u8         mgid_filter2[16][0x8];
9791 
9792 	u8         mgid_filter3[16][0x8];
9793 };
9794 
9795 enum {
9796 	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
9797 	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
9798 };
9799 
9800 enum {
9801 	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
9802 	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
9803 };
9804 
9805 struct mlx5_ifc_nodnic_config_reg_bits {
9806 	u8         no_dram_nic_revision[0x8];
9807 	u8         hardware_format[0x8];
9808 	u8         support_receive_filter[0x1];
9809 	u8         support_promisc_filter[0x1];
9810 	u8         support_promisc_multicast_filter[0x1];
9811 	u8         reserved_0[0x2];
9812 	u8         log_working_buffer_size[0x3];
9813 	u8         log_pkey_table_size[0x4];
9814 	u8         reserved_1[0x3];
9815 	u8         num_ports[0x1];
9816 
9817 	u8         reserved_2[0x2];
9818 	u8         log_max_ring_size[0x6];
9819 	u8         reserved_3[0x18];
9820 
9821 	u8         lkey[0x20];
9822 
9823 	u8         cqe_format[0x4];
9824 	u8         reserved_4[0x1c];
9825 
9826 	u8         node_guid[0x40];
9827 
9828 	u8         reserved_5[0x740];
9829 
9830 	struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
9831 
9832 	struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
9833 };
9834 
9835 struct mlx5_ifc_vlan_layout_bits {
9836 	u8         reserved_0[0x14];
9837 	u8         vlan[0xc];
9838 
9839 	u8         reserved_1[0x20];
9840 };
9841 
9842 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9843 	u8         reserved_0[0x20];
9844 
9845 	u8         mkey[0x20];
9846 
9847 	u8         addressh_63_32[0x20];
9848 
9849 	u8         addressl_31_0[0x20];
9850 };
9851 
9852 struct mlx5_ifc_ud_adrs_vector_bits {
9853 	u8         dc_key[0x40];
9854 
9855 	u8         ext[0x1];
9856 	u8         reserved_0[0x7];
9857 	u8         destination_qp_dct[0x18];
9858 
9859 	u8         static_rate[0x4];
9860 	u8         sl_eth_prio[0x4];
9861 	u8         fl[0x1];
9862 	u8         mlid[0x7];
9863 	u8         rlid_udp_sport[0x10];
9864 
9865 	u8         reserved_1[0x20];
9866 
9867 	u8         rmac_47_16[0x20];
9868 
9869 	u8         rmac_15_0[0x10];
9870 	u8         tclass[0x8];
9871 	u8         hop_limit[0x8];
9872 
9873 	u8         reserved_2[0x1];
9874 	u8         grh[0x1];
9875 	u8         reserved_3[0x2];
9876 	u8         src_addr_index[0x8];
9877 	u8         flow_label[0x14];
9878 
9879 	u8         rgid_rip[16][0x8];
9880 };
9881 
9882 struct mlx5_ifc_port_module_event_bits {
9883 	u8         reserved_0[0x8];
9884 	u8         module[0x8];
9885 	u8         reserved_1[0xc];
9886 	u8         module_status[0x4];
9887 
9888 	u8         reserved_2[0x14];
9889 	u8         error_type[0x4];
9890 	u8         reserved_3[0x8];
9891 
9892 	u8         reserved_4[0xa0];
9893 };
9894 
9895 struct mlx5_ifc_icmd_control_bits {
9896 	u8         opcode[0x10];
9897 	u8         status[0x8];
9898 	u8         reserved_0[0x7];
9899 	u8         busy[0x1];
9900 };
9901 
9902 struct mlx5_ifc_eqe_bits {
9903 	u8         reserved_0[0x8];
9904 	u8         event_type[0x8];
9905 	u8         reserved_1[0x8];
9906 	u8         event_sub_type[0x8];
9907 
9908 	u8         reserved_2[0xe0];
9909 
9910 	union mlx5_ifc_event_auto_bits event_data;
9911 
9912 	u8         reserved_3[0x10];
9913 	u8         signature[0x8];
9914 	u8         reserved_4[0x7];
9915 	u8         owner[0x1];
9916 };
9917 
9918 enum {
9919 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9920 };
9921 
9922 struct mlx5_ifc_cmd_queue_entry_bits {
9923 	u8         type[0x8];
9924 	u8         reserved_0[0x18];
9925 
9926 	u8         input_length[0x20];
9927 
9928 	u8         input_mailbox_pointer_63_32[0x20];
9929 
9930 	u8         input_mailbox_pointer_31_9[0x17];
9931 	u8         reserved_1[0x9];
9932 
9933 	u8         command_input_inline_data[16][0x8];
9934 
9935 	u8         command_output_inline_data[16][0x8];
9936 
9937 	u8         output_mailbox_pointer_63_32[0x20];
9938 
9939 	u8         output_mailbox_pointer_31_9[0x17];
9940 	u8         reserved_2[0x9];
9941 
9942 	u8         output_length[0x20];
9943 
9944 	u8         token[0x8];
9945 	u8         signature[0x8];
9946 	u8         reserved_3[0x8];
9947 	u8         status[0x7];
9948 	u8         ownership[0x1];
9949 };
9950 
9951 struct mlx5_ifc_cmd_out_bits {
9952 	u8         status[0x8];
9953 	u8         reserved_0[0x18];
9954 
9955 	u8         syndrome[0x20];
9956 
9957 	u8         command_output[0x20];
9958 };
9959 
9960 struct mlx5_ifc_cmd_in_bits {
9961 	u8         opcode[0x10];
9962 	u8         reserved_0[0x10];
9963 
9964 	u8         reserved_1[0x10];
9965 	u8         op_mod[0x10];
9966 
9967 	u8         command[0][0x20];
9968 };
9969 
9970 struct mlx5_ifc_cmd_if_box_bits {
9971 	u8         mailbox_data[512][0x8];
9972 
9973 	u8         reserved_0[0x180];
9974 
9975 	u8         next_pointer_63_32[0x20];
9976 
9977 	u8         next_pointer_31_10[0x16];
9978 	u8         reserved_1[0xa];
9979 
9980 	u8         block_number[0x20];
9981 
9982 	u8         reserved_2[0x8];
9983 	u8         token[0x8];
9984 	u8         ctrl_signature[0x8];
9985 	u8         signature[0x8];
9986 };
9987 
9988 struct mlx5_ifc_mtt_bits {
9989 	u8         ptag_63_32[0x20];
9990 
9991 	u8         ptag_31_8[0x18];
9992 	u8         reserved_0[0x6];
9993 	u8         wr_en[0x1];
9994 	u8         rd_en[0x1];
9995 };
9996 
9997 struct mlx5_ifc_tls_progress_params_bits {
9998 	u8         valid[0x1];
9999 	u8         reserved_at_1[0x7];
10000 	u8         pd[0x18];
10001 
10002 	u8         next_record_tcp_sn[0x20];
10003 
10004 	u8         hw_resync_tcp_sn[0x20];
10005 
10006 	u8         record_tracker_state[0x2];
10007 	u8         auth_state[0x2];
10008 	u8         reserved_at_64[0x4];
10009 	u8         hw_offset_record_number[0x18];
10010 };
10011 
10012 struct mlx5_ifc_tls_static_params_bits {
10013 	u8         const_2[0x2];
10014 	u8         tls_version[0x4];
10015 	u8         const_1[0x2];
10016 	u8         reserved_at_8[0x14];
10017 	u8         encryption_standard[0x4];
10018 
10019 	u8         reserved_at_20[0x20];
10020 
10021 	u8         initial_record_number[0x40];
10022 
10023 	u8         resync_tcp_sn[0x20];
10024 
10025 	u8         gcm_iv[0x20];
10026 
10027 	u8         implicit_iv[0x40];
10028 
10029 	u8         reserved_at_100[0x8];
10030 	u8         dek_index[0x18];
10031 
10032 	u8         reserved_at_120[0xe0];
10033 };
10034 
10035 /* Vendor Specific Capabilities, VSC */
10036 enum {
10037 	MLX5_VSC_DOMAIN_ICMD			= 0x1,
10038 	MLX5_VSC_DOMAIN_PROTECTED_CRSPACE	= 0x6,
10039 	MLX5_VSC_DOMAIN_SCAN_CRSPACE		= 0x7,
10040 	MLX5_VSC_DOMAIN_SEMAPHORES		= 0xA,
10041 };
10042 
10043 struct mlx5_ifc_vendor_specific_cap_bits {
10044 	u8         type[0x8];
10045 	u8         length[0x8];
10046 	u8         next_pointer[0x8];
10047 	u8         capability_id[0x8];
10048 
10049 	u8         status[0x3];
10050 	u8         reserved_0[0xd];
10051 	u8         space[0x10];
10052 
10053 	u8         counter[0x20];
10054 
10055 	u8         semaphore[0x20];
10056 
10057 	u8         flag[0x1];
10058 	u8         reserved_1[0x1];
10059 	u8         address[0x1e];
10060 
10061 	u8         data[0x20];
10062 };
10063 
10064 struct mlx5_ifc_vsc_space_bits {
10065 	u8 status[0x3];
10066 	u8 reserved0[0xd];
10067 	u8 space[0x10];
10068 };
10069 
10070 struct mlx5_ifc_vsc_addr_bits {
10071 	u8 flag[0x1];
10072 	u8 reserved0[0x1];
10073 	u8 address[0x1e];
10074 };
10075 
10076 enum {
10077 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10078 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10079 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10080 };
10081 
10082 enum {
10083 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10084 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10085 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10086 };
10087 
10088 enum {
10089 	MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
10090 	MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
10091 	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
10092 	MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
10093 	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
10094 	MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
10095 	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
10096 	MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
10097 	MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
10098 	MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
10099 	MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
10100 };
10101 
10102 struct mlx5_ifc_initial_seg_bits {
10103 	u8         fw_rev_minor[0x10];
10104 	u8         fw_rev_major[0x10];
10105 
10106 	u8         cmd_interface_rev[0x10];
10107 	u8         fw_rev_subminor[0x10];
10108 
10109 	u8         reserved_0[0x40];
10110 
10111 	u8         cmdq_phy_addr_63_32[0x20];
10112 
10113 	u8         cmdq_phy_addr_31_12[0x14];
10114 	u8         reserved_1[0x2];
10115 	u8         nic_interface[0x2];
10116 	u8         log_cmdq_size[0x4];
10117 	u8         log_cmdq_stride[0x4];
10118 
10119 	u8         command_doorbell_vector[0x20];
10120 
10121 	u8         reserved_2[0xf00];
10122 
10123 	u8         initializing[0x1];
10124 	u8         reserved_3[0x4];
10125 	u8         nic_interface_supported[0x3];
10126 	u8         reserved_4[0x18];
10127 
10128 	struct mlx5_ifc_health_buffer_bits health_buffer;
10129 
10130 	u8         no_dram_nic_offset[0x20];
10131 
10132 	u8         reserved_5[0x6de0];
10133 
10134 	u8         internal_timer_h[0x20];
10135 
10136 	u8         internal_timer_l[0x20];
10137 
10138 	u8         reserved_6[0x20];
10139 
10140 	u8         reserved_7[0x1f];
10141 	u8         clear_int[0x1];
10142 
10143 	u8         health_syndrome[0x8];
10144 	u8         health_counter[0x18];
10145 
10146 	u8         reserved_8[0x17fc0];
10147 };
10148 
10149 union mlx5_ifc_icmd_interface_document_bits {
10150 	struct mlx5_ifc_fw_version_bits fw_version;
10151 	struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
10152 	struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
10153 	struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
10154 	struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
10155 	struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
10156 	struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
10157 	struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
10158 	struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
10159 	struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
10160 	struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
10161 	struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
10162 	struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
10163 	struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
10164 	u8         reserved_0[0x42c0];
10165 };
10166 
10167 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
10168 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10169 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10170 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10171 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10172 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10173 	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10174 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10175 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10176 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
10177 	struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
10178 	u8         reserved_0[0x7c0];
10179 };
10180 
10181 struct mlx5_ifc_ppcnt_reg_bits {
10182 	u8         swid[0x8];
10183 	u8         local_port[0x8];
10184 	u8         pnat[0x2];
10185 	u8         reserved_0[0x8];
10186 	u8         grp[0x6];
10187 
10188 	u8         clr[0x1];
10189 	u8         reserved_1[0x1c];
10190 	u8         prio_tc[0x3];
10191 
10192 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10193 };
10194 
10195 struct mlx5_ifc_pcie_lanes_counters_bits {
10196 	u8         life_time_counter_high[0x20];
10197 
10198 	u8         life_time_counter_low[0x20];
10199 
10200 	u8         error_counter_lane0[0x20];
10201 
10202 	u8         error_counter_lane1[0x20];
10203 
10204 	u8         error_counter_lane2[0x20];
10205 
10206 	u8         error_counter_lane3[0x20];
10207 
10208 	u8         error_counter_lane4[0x20];
10209 
10210 	u8         error_counter_lane5[0x20];
10211 
10212 	u8         error_counter_lane6[0x20];
10213 
10214 	u8         error_counter_lane7[0x20];
10215 
10216 	u8         error_counter_lane8[0x20];
10217 
10218 	u8         error_counter_lane9[0x20];
10219 
10220 	u8         error_counter_lane10[0x20];
10221 
10222 	u8         error_counter_lane11[0x20];
10223 
10224 	u8         error_counter_lane12[0x20];
10225 
10226 	u8         error_counter_lane13[0x20];
10227 
10228 	u8         error_counter_lane14[0x20];
10229 
10230 	u8         error_counter_lane15[0x20];
10231 
10232 	u8         reserved_at_240[0x580];
10233 };
10234 
10235 struct mlx5_ifc_pcie_lanes_counters_ext_bits {
10236 	u8         reserved_at_0[0x40];
10237 
10238 	u8         error_counter_lane0[0x20];
10239 
10240 	u8         error_counter_lane1[0x20];
10241 
10242 	u8         error_counter_lane2[0x20];
10243 
10244 	u8         error_counter_lane3[0x20];
10245 
10246 	u8         error_counter_lane4[0x20];
10247 
10248 	u8         error_counter_lane5[0x20];
10249 
10250 	u8         error_counter_lane6[0x20];
10251 
10252 	u8         error_counter_lane7[0x20];
10253 
10254 	u8         error_counter_lane8[0x20];
10255 
10256 	u8         error_counter_lane9[0x20];
10257 
10258 	u8         error_counter_lane10[0x20];
10259 
10260 	u8         error_counter_lane11[0x20];
10261 
10262 	u8         error_counter_lane12[0x20];
10263 
10264 	u8         error_counter_lane13[0x20];
10265 
10266 	u8         error_counter_lane14[0x20];
10267 
10268 	u8         error_counter_lane15[0x20];
10269 
10270 	u8         reserved_at_240[0x580];
10271 };
10272 
10273 struct mlx5_ifc_pcie_perf_counters_bits {
10274 	u8         life_time_counter_high[0x20];
10275 
10276 	u8         life_time_counter_low[0x20];
10277 
10278 	u8         rx_errors[0x20];
10279 
10280 	u8         tx_errors[0x20];
10281 
10282 	u8         l0_to_recovery_eieos[0x20];
10283 
10284 	u8         l0_to_recovery_ts[0x20];
10285 
10286 	u8         l0_to_recovery_framing[0x20];
10287 
10288 	u8         l0_to_recovery_retrain[0x20];
10289 
10290 	u8         crc_error_dllp[0x20];
10291 
10292 	u8         crc_error_tlp[0x20];
10293 
10294 	u8         tx_overflow_buffer_pkt[0x40];
10295 
10296 	u8         outbound_stalled_reads[0x20];
10297 
10298 	u8         outbound_stalled_writes[0x20];
10299 
10300 	u8         outbound_stalled_reads_events[0x20];
10301 
10302 	u8         outbound_stalled_writes_events[0x20];
10303 
10304 	u8         tx_overflow_buffer_marked_pkt[0x40];
10305 
10306 	u8         reserved_at_240[0x580];
10307 };
10308 
10309 struct mlx5_ifc_pcie_perf_counters_ext_bits {
10310 	u8         reserved_at_0[0x40];
10311 
10312 	u8         rx_errors[0x20];
10313 
10314 	u8         tx_errors[0x20];
10315 
10316 	u8         reserved_at_80[0xc0];
10317 
10318 	u8         tx_overflow_buffer_pkt[0x40];
10319 
10320 	u8         outbound_stalled_reads[0x20];
10321 
10322 	u8         outbound_stalled_writes[0x20];
10323 
10324 	u8         outbound_stalled_reads_events[0x20];
10325 
10326 	u8         outbound_stalled_writes_events[0x20];
10327 
10328 	u8         tx_overflow_buffer_marked_pkt[0x40];
10329 
10330 	u8         reserved_at_240[0x580];
10331 };
10332 
10333 struct mlx5_ifc_pcie_timers_states_bits {
10334 	u8         life_time_counter_high[0x20];
10335 
10336 	u8         life_time_counter_low[0x20];
10337 
10338 	u8         time_to_boot_image_start[0x20];
10339 
10340 	u8         time_to_link_image[0x20];
10341 
10342 	u8         calibration_time[0x20];
10343 
10344 	u8         time_to_first_perst[0x20];
10345 
10346 	u8         time_to_detect_state[0x20];
10347 
10348 	u8         time_to_l0[0x20];
10349 
10350 	u8         time_to_crs_en[0x20];
10351 
10352 	u8         time_to_plastic_image_start[0x20];
10353 
10354 	u8         time_to_iron_image_start[0x20];
10355 
10356 	u8         perst_handler[0x20];
10357 
10358 	u8         times_in_l1[0x20];
10359 
10360 	u8         times_in_l23[0x20];
10361 
10362 	u8         dl_down[0x20];
10363 
10364 	u8         config_cycle1usec[0x20];
10365 
10366 	u8         config_cycle2to7usec[0x20];
10367 
10368 	u8         config_cycle8to15usec[0x20];
10369 
10370 	u8         config_cycle16to63usec[0x20];
10371 
10372 	u8         config_cycle64usec[0x20];
10373 
10374 	u8         correctable_err_msg_sent[0x20];
10375 
10376 	u8         non_fatal_err_msg_sent[0x20];
10377 
10378 	u8         fatal_err_msg_sent[0x20];
10379 
10380 	u8         reserved_at_2e0[0x4e0];
10381 };
10382 
10383 struct mlx5_ifc_pcie_timers_states_ext_bits {
10384 	u8         reserved_at_0[0x40];
10385 
10386 	u8         time_to_boot_image_start[0x20];
10387 
10388 	u8         time_to_link_image[0x20];
10389 
10390 	u8         calibration_time[0x20];
10391 
10392 	u8         time_to_first_perst[0x20];
10393 
10394 	u8         time_to_detect_state[0x20];
10395 
10396 	u8         time_to_l0[0x20];
10397 
10398 	u8         time_to_crs_en[0x20];
10399 
10400 	u8         time_to_plastic_image_start[0x20];
10401 
10402 	u8         time_to_iron_image_start[0x20];
10403 
10404 	u8         perst_handler[0x20];
10405 
10406 	u8         times_in_l1[0x20];
10407 
10408 	u8         times_in_l23[0x20];
10409 
10410 	u8         dl_down[0x20];
10411 
10412 	u8         config_cycle1usec[0x20];
10413 
10414 	u8         config_cycle2to7usec[0x20];
10415 
10416 	u8         config_cycle8to15usec[0x20];
10417 
10418 	u8         config_cycle16to63usec[0x20];
10419 
10420 	u8         config_cycle64usec[0x20];
10421 
10422 	u8         correctable_err_msg_sent[0x20];
10423 
10424 	u8         non_fatal_err_msg_sent[0x20];
10425 
10426 	u8         fatal_err_msg_sent[0x20];
10427 
10428 	u8         reserved_at_2e0[0x4e0];
10429 };
10430 
10431 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits {
10432 	struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters;
10433 	struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters;
10434 	struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states;
10435 	u8         reserved_at_0[0x7c0];
10436 };
10437 
10438 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits {
10439 	struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext;
10440 	struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext;
10441 	struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext;
10442 	u8         reserved_at_0[0x7c0];
10443 };
10444 
10445 struct mlx5_ifc_mpcnt_reg_bits {
10446 	u8         reserved_at_0[0x2];
10447 	u8         depth[0x6];
10448 	u8         pcie_index[0x8];
10449 	u8         node[0x8];
10450 	u8         reserved_at_18[0x2];
10451 	u8         grp[0x6];
10452 
10453 	u8         clr[0x1];
10454 	u8         reserved_at_21[0x1f];
10455 
10456 	union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set;
10457 };
10458 
10459 struct mlx5_ifc_mpcnt_reg_ext_bits {
10460 	u8         reserved_at_0[0x2];
10461 	u8         depth[0x6];
10462 	u8         pcie_index[0x8];
10463 	u8         node[0x8];
10464 	u8         reserved_at_18[0x2];
10465 	u8         grp[0x6];
10466 
10467 	u8         clr[0x1];
10468 	u8         reserved_at_21[0x1f];
10469 
10470 	union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set;
10471 };
10472 
10473 struct mlx5_ifc_monitor_opcodes_layout_bits {
10474 	u8         reserved_at_0[0x10];
10475 	u8         monitor_opcode[0x10];
10476 };
10477 
10478 union mlx5_ifc_pddr_status_opcode_bits {
10479 	struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes;
10480 	u8         reserved_at_0[0x20];
10481 };
10482 
10483 struct mlx5_ifc_troubleshooting_info_page_layout_bits {
10484 	u8         reserved_at_0[0x10];
10485 	u8         group_opcode[0x10];
10486 
10487 	union mlx5_ifc_pddr_status_opcode_bits status_opcode;
10488 
10489 	u8         user_feedback_data[0x10];
10490 	u8         user_feedback_index[0x10];
10491 
10492 	u8         status_message[0x760];
10493 };
10494 
10495 union mlx5_ifc_pddr_page_data_bits {
10496 	struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page;
10497 	struct mlx5_ifc_pddr_module_info_bits pddr_module_info;
10498 	u8         reserved_at_0[0x7c0];
10499 };
10500 
10501 struct mlx5_ifc_pddr_reg_bits {
10502 	u8         reserved_at_0[0x8];
10503 	u8         local_port[0x8];
10504 	u8         pnat[0x2];
10505 	u8         reserved_at_12[0xe];
10506 
10507 	u8         reserved_at_20[0x18];
10508 	u8         page_select[0x8];
10509 
10510 	union mlx5_ifc_pddr_page_data_bits page_data;
10511 };
10512 
10513 enum {
10514 	MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
10515 	MLX5_MPEIN_PWR_STATUS_INVALID = 0,
10516 	MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1,
10517 	MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2,
10518 };
10519 
10520 struct mlx5_ifc_mpein_reg_bits {
10521 	u8         reserved_at_0[0x2];
10522 	u8         depth[0x6];
10523 	u8         pcie_index[0x8];
10524 	u8         node[0x8];
10525 	u8         reserved_at_18[0x8];
10526 
10527 	u8         capability_mask[0x20];
10528 
10529 	u8         reserved_at_40[0x8];
10530 	u8         link_width_enabled[0x8];
10531 	u8         link_speed_enabled[0x10];
10532 
10533 	u8         lane0_physical_position[0x8];
10534 	u8         link_width_active[0x8];
10535 	u8         link_speed_active[0x10];
10536 
10537 	u8         num_of_pfs[0x10];
10538 	u8         num_of_vfs[0x10];
10539 
10540 	u8         bdf0[0x10];
10541 	u8         reserved_at_b0[0x10];
10542 
10543 	u8         max_read_request_size[0x4];
10544 	u8         max_payload_size[0x4];
10545 	u8         reserved_at_c8[0x5];
10546 	u8         pwr_status[0x3];
10547 	u8         port_type[0x4];
10548 	u8         reserved_at_d4[0xb];
10549 	u8         lane_reversal[0x1];
10550 
10551 	u8         reserved_at_e0[0x14];
10552 	u8         pci_power[0xc];
10553 
10554 	u8         reserved_at_100[0x20];
10555 
10556 	u8         device_status[0x10];
10557 	u8         port_state[0x8];
10558 	u8         reserved_at_138[0x8];
10559 
10560 	u8         reserved_at_140[0x10];
10561 	u8         receiver_detect_result[0x10];
10562 
10563 	u8         reserved_at_160[0x20];
10564 };
10565 
10566 struct mlx5_ifc_mpein_reg_ext_bits {
10567 	u8         reserved_at_0[0x2];
10568 	u8         depth[0x6];
10569 	u8         pcie_index[0x8];
10570 	u8         node[0x8];
10571 	u8         reserved_at_18[0x8];
10572 
10573 	u8         reserved_at_20[0x20];
10574 
10575 	u8         reserved_at_40[0x8];
10576 	u8         link_width_enabled[0x8];
10577 	u8         link_speed_enabled[0x10];
10578 
10579 	u8         lane0_physical_position[0x8];
10580 	u8         link_width_active[0x8];
10581 	u8         link_speed_active[0x10];
10582 
10583 	u8         num_of_pfs[0x10];
10584 	u8         num_of_vfs[0x10];
10585 
10586 	u8         bdf0[0x10];
10587 	u8         reserved_at_b0[0x10];
10588 
10589 	u8         max_read_request_size[0x4];
10590 	u8         max_payload_size[0x4];
10591 	u8         reserved_at_c8[0x5];
10592 	u8         pwr_status[0x3];
10593 	u8         port_type[0x4];
10594 	u8         reserved_at_d4[0xb];
10595 	u8         lane_reversal[0x1];
10596 };
10597 
10598 struct mlx5_ifc_mcqi_cap_bits {
10599 	u8         supported_info_bitmask[0x20];
10600 
10601 	u8         component_size[0x20];
10602 
10603 	u8         max_component_size[0x20];
10604 
10605 	u8         log_mcda_word_size[0x4];
10606 	u8         reserved_at_64[0xc];
10607 	u8         mcda_max_write_size[0x10];
10608 
10609 	u8         rd_en[0x1];
10610 	u8         reserved_at_81[0x1];
10611 	u8         match_chip_id[0x1];
10612 	u8         match_psid[0x1];
10613 	u8         check_user_timestamp[0x1];
10614 	u8         match_base_guid_mac[0x1];
10615 	u8         reserved_at_86[0x1a];
10616 };
10617 
10618 struct mlx5_ifc_mcqi_reg_bits {
10619 	u8         read_pending_component[0x1];
10620 	u8         reserved_at_1[0xf];
10621 	u8         component_index[0x10];
10622 
10623 	u8         reserved_at_20[0x20];
10624 
10625 	u8         reserved_at_40[0x1b];
10626 	u8         info_type[0x5];
10627 
10628 	u8         info_size[0x20];
10629 
10630 	u8         offset[0x20];
10631 
10632 	u8         reserved_at_a0[0x10];
10633 	u8         data_size[0x10];
10634 
10635 	u8         data[0][0x20];
10636 };
10637 
10638 struct mlx5_ifc_mcc_reg_bits {
10639 	u8         reserved_at_0[0x4];
10640 	u8         time_elapsed_since_last_cmd[0xc];
10641 	u8         reserved_at_10[0x8];
10642 	u8         instruction[0x8];
10643 
10644 	u8         reserved_at_20[0x10];
10645 	u8         component_index[0x10];
10646 
10647 	u8         reserved_at_40[0x8];
10648 	u8         update_handle[0x18];
10649 
10650 	u8         handle_owner_type[0x4];
10651 	u8         handle_owner_host_id[0x4];
10652 	u8         reserved_at_68[0x1];
10653 	u8         control_progress[0x7];
10654 	u8         error_code[0x8];
10655 	u8         reserved_at_78[0x4];
10656 	u8         control_state[0x4];
10657 
10658 	u8         component_size[0x20];
10659 
10660 	u8         reserved_at_a0[0x60];
10661 };
10662 
10663 struct mlx5_ifc_mcda_reg_bits {
10664 	u8         reserved_at_0[0x8];
10665 	u8         update_handle[0x18];
10666 
10667 	u8         offset[0x20];
10668 
10669 	u8         reserved_at_40[0x10];
10670 	u8         size[0x10];
10671 
10672 	u8         reserved_at_60[0x20];
10673 
10674 	u8         data[0][0x20];
10675 };
10676 
10677 union mlx5_ifc_ports_control_registers_document_bits {
10678 	struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
10679 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10680 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10681 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10682 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10683 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10684 	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
10685 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10686 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10687 	struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
10688 	struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
10689 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10690 	struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
10691 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
10692 	struct mlx5_ifc_paos_reg_bits paos_reg;
10693 	struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
10694 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
10695 	struct mlx5_ifc_peir_reg_bits peir_reg;
10696 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
10697 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10698 	struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
10699 	struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
10700 	struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
10701 	struct mlx5_ifc_phrr_reg_bits phrr_reg;
10702 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10703 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
10704 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
10705 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
10706 	struct mlx5_ifc_plib_reg_bits plib_reg;
10707 	struct mlx5_ifc_pll_status_data_bits pll_status_data;
10708 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
10709 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10710 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10711 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10712 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10713 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10714 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10715 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10716 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
10717 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10718 	struct mlx5_ifc_ppll_reg_bits ppll_reg;
10719 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
10720 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
10721 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10722 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
10723 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
10724 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
10725 	struct mlx5_ifc_pude_reg_bits pude_reg;
10726 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10727 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
10728 	struct mlx5_ifc_slrp_reg_bits slrp_reg;
10729 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
10730 	u8         reserved_0[0x7880];
10731 };
10732 
10733 union mlx5_ifc_debug_enhancements_document_bits {
10734 	struct mlx5_ifc_health_buffer_bits health_buffer;
10735 	u8         reserved_0[0x200];
10736 };
10737 
10738 union mlx5_ifc_no_dram_nic_document_bits {
10739 	struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
10740 	struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
10741 	struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
10742 	struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
10743 	struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
10744 	struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
10745 	struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
10746 	struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
10747 	u8         reserved_0[0x3160];
10748 };
10749 
10750 union mlx5_ifc_uplink_pci_interface_document_bits {
10751 	struct mlx5_ifc_initial_seg_bits initial_seg;
10752 	struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
10753 	u8         reserved_0[0x20120];
10754 };
10755 
10756 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10757 	u8         e[0x1];
10758 	u8         reserved_at_01[0x0b];
10759 	u8         prio[0x04];
10760 };
10761 
10762 struct mlx5_ifc_qpdpm_reg_bits {
10763 	u8                                     reserved_at_0[0x8];
10764 	u8                                     local_port[0x8];
10765 	u8                                     reserved_at_10[0x10];
10766 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10767 };
10768 
10769 struct mlx5_ifc_qpts_reg_bits {
10770 	u8         reserved_at_0[0x8];
10771 	u8         local_port[0x8];
10772 	u8         reserved_at_10[0x2d];
10773 	u8         trust_state[0x3];
10774 };
10775 
10776 struct mlx5_ifc_mfrl_reg_bits {
10777 	u8         reserved_at_0[0x38];
10778 	u8         reset_level[0x8];
10779 };
10780 
10781 enum {
10782       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP	= 0x9009,
10783       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR	= 0x9109,
10784       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP	= 0x900a,
10785       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE	= 0x900b,
10786       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR	= 0x900f,
10787       MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE	= 0x910b,
10788       MLX5_MAX_TEMPERATURE = 16,
10789 };
10790 
10791 struct mlx5_ifc_mtbr_temp_record_bits {
10792 	u8         max_temperature[0x10];
10793 	u8         temperature[0x10];
10794 };
10795 
10796 struct mlx5_ifc_mtbr_reg_bits {
10797 	u8         reserved_at_0[0x14];
10798 	u8         base_sensor_index[0xc];
10799 
10800 	u8         reserved_at_20[0x18];
10801 	u8         num_rec[0x8];
10802 
10803 	u8         reserved_at_40[0x40];
10804 
10805 	struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10806 };
10807 
10808 struct mlx5_ifc_mtbr_reg_ext_bits {
10809 	u8         reserved_at_0[0x14];
10810 	u8         base_sensor_index[0xc];
10811 
10812 	u8         reserved_at_20[0x18];
10813 	u8         num_rec[0x8];
10814 
10815 	u8         reserved_at_40[0x40];
10816 
10817     struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE];
10818 };
10819 
10820 struct mlx5_ifc_mtcap_bits {
10821 	u8         reserved_at_0[0x19];
10822 	u8         sensor_count[0x7];
10823 
10824 	u8         reserved_at_20[0x19];
10825 	u8         internal_sensor_count[0x7];
10826 
10827 	u8         sensor_map[0x40];
10828 };
10829 
10830 struct mlx5_ifc_mtcap_ext_bits {
10831 	u8         reserved_at_0[0x19];
10832 	u8         sensor_count[0x7];
10833 
10834 	u8         reserved_at_20[0x20];
10835 
10836 	u8         sensor_map[0x40];
10837 };
10838 
10839 struct mlx5_ifc_mtecr_bits {
10840 	u8         reserved_at_0[0x4];
10841 	u8         last_sensor[0xc];
10842 	u8         reserved_at_10[0x4];
10843 	u8         sensor_count[0xc];
10844 
10845 	u8         reserved_at_20[0x19];
10846 	u8         internal_sensor_count[0x7];
10847 
10848 	u8         sensor_map_0[0x20];
10849 
10850 	u8         reserved_at_60[0x2a0];
10851 };
10852 
10853 struct mlx5_ifc_mtecr_ext_bits {
10854 	u8         reserved_at_0[0x4];
10855 	u8         last_sensor[0xc];
10856 	u8         reserved_at_10[0x4];
10857 	u8         sensor_count[0xc];
10858 
10859 	u8         reserved_at_20[0x20];
10860 
10861 	u8         sensor_map_0[0x20];
10862 
10863 	u8         reserved_at_60[0x2a0];
10864 };
10865 
10866 struct mlx5_ifc_mtewe_bits {
10867 	u8         reserved_at_0[0x4];
10868 	u8         last_sensor[0xc];
10869 	u8         reserved_at_10[0x4];
10870 	u8         sensor_count[0xc];
10871 
10872 	u8         sensor_warning_0[0x20];
10873 
10874 	u8         reserved_at_40[0x2a0];
10875 };
10876 
10877 struct mlx5_ifc_mtewe_ext_bits {
10878 	u8         reserved_at_0[0x4];
10879 	u8         last_sensor[0xc];
10880 	u8         reserved_at_10[0x4];
10881 	u8         sensor_count[0xc];
10882 
10883 	u8         sensor_warning_0[0x20];
10884 
10885 	u8         reserved_at_40[0x2a0];
10886 };
10887 
10888 struct mlx5_ifc_mtmp_bits {
10889 	u8         reserved_at_0[0x14];
10890 	u8         sensor_index[0xc];
10891 
10892 	u8         reserved_at_20[0x10];
10893 	u8         temperature[0x10];
10894 
10895 	u8         mte[0x1];
10896 	u8         mtr[0x1];
10897 	u8         reserved_at_42[0xe];
10898 	u8         max_temperature[0x10];
10899 
10900 	u8         tee[0x2];
10901 	u8         reserved_at_62[0xe];
10902 	u8         temperature_threshold_hi[0x10];
10903 
10904 	u8         reserved_at_80[0x10];
10905 	u8         temperature_threshold_lo[0x10];
10906 
10907 	u8         reserved_at_a0[0x20];
10908 
10909 	u8         sensor_name_hi[0x20];
10910 
10911 	u8         sensor_name_lo[0x20];
10912 };
10913 
10914 struct mlx5_ifc_mtmp_ext_bits {
10915 	u8         reserved_at_0[0x14];
10916 	u8         sensor_index[0xc];
10917 
10918 	u8         reserved_at_20[0x10];
10919 	u8         temperature[0x10];
10920 
10921 	u8         mte[0x1];
10922 	u8         mtr[0x1];
10923 	u8         reserved_at_42[0xe];
10924 	u8         max_temperature[0x10];
10925 
10926 	u8         tee[0x2];
10927 	u8         reserved_at_62[0xe];
10928 	u8         temperature_threshold_hi[0x10];
10929 
10930 	u8         reserved_at_80[0x10];
10931 	u8         temperature_threshold_lo[0x10];
10932 
10933 	u8         reserved_at_a0[0x20];
10934 
10935 	u8         sensor_name_hi[0x20];
10936 
10937 	u8         sensor_name_lo[0x20];
10938 };
10939 
10940 #endif /* MLX5_IFC_H */
10941