1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * This file is available to you under your choice of the following two
7 * licenses:
8 *
9 * License 1: GPLv2
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Redistribution and use in source and binary forms, with or without
60 * modification, are permitted provided that the following conditions are met:
61 * * Redistributions of source code must retain the above copyright
62 * notice, this list of conditions and the following disclaimer.
63 * * Redistributions in binary form must reproduce the above copyright
64 * notice, this list of conditions and the following disclaimer in the
65 * documentation and/or other materials provided with the distribution.
66 * * Neither the name of Advanced Micro Devices, Inc. nor the
67 * names of its contributors may be used to endorse or promote products
68 * derived from this software without specific prior written permission.
69 *
70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 *
81 * This file incorporates work covered by the following copyright and
82 * permission notice:
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
86 * and you.
87 *
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
97 *
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
100 *
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
112 */
113
114 #include <sys/cdefs.h>
115 #include "xgbe.h"
116 #include "xgbe-common.h"
117
118 struct mtx xgbe_phy_comm_lock;
119
120 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
121 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
122 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
123 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
124
125 #define XGBE_MUTEX_RELEASE 0x80000000
126
127 #define XGBE_SFP_DIRECT 7
128 #define GPIO_MASK_WIDTH 4
129
130 /* I2C target addresses */
131 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
132 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
133 #define XGBE_SFP_PHY_ADDRESS 0x56
134 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
135
136 /* SFP sideband signal indicators */
137 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
138 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
139 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
140 #define XGBE_GPIO_NO_RX_LOS BIT(3)
141
142 /* Rate-change complete wait/retry count */
143 #define XGBE_RATECHANGE_COUNT 500
144
145 /* CDR delay values for KR support (in usec) */
146 #define XGBE_CDR_DELAY_INIT 10000
147 #define XGBE_CDR_DELAY_INC 10000
148 #define XGBE_CDR_DELAY_MAX 100000
149
150 /* RRC frequency during link status check */
151 #define XGBE_RRC_FREQUENCY 10
152
153 enum xgbe_port_mode {
154 XGBE_PORT_MODE_RSVD = 0,
155 XGBE_PORT_MODE_BACKPLANE,
156 XGBE_PORT_MODE_BACKPLANE_2500,
157 XGBE_PORT_MODE_1000BASE_T,
158 XGBE_PORT_MODE_1000BASE_X,
159 XGBE_PORT_MODE_NBASE_T,
160 XGBE_PORT_MODE_10GBASE_T,
161 XGBE_PORT_MODE_10GBASE_R,
162 XGBE_PORT_MODE_SFP,
163 XGBE_PORT_MODE_MAX,
164 };
165
166 enum xgbe_conn_type {
167 XGBE_CONN_TYPE_NONE = 0,
168 XGBE_CONN_TYPE_SFP,
169 XGBE_CONN_TYPE_MDIO,
170 XGBE_CONN_TYPE_RSVD1,
171 XGBE_CONN_TYPE_BACKPLANE,
172 XGBE_CONN_TYPE_MAX,
173 };
174
175 /* SFP/SFP+ related definitions */
176 enum xgbe_sfp_comm {
177 XGBE_SFP_COMM_DIRECT = 0,
178 XGBE_SFP_COMM_PCA9545,
179 };
180
181 enum xgbe_sfp_cable {
182 XGBE_SFP_CABLE_UNKNOWN = 0,
183 XGBE_SFP_CABLE_ACTIVE,
184 XGBE_SFP_CABLE_PASSIVE,
185 };
186
187 enum xgbe_sfp_base {
188 XGBE_SFP_BASE_UNKNOWN = 0,
189 XGBE_SFP_BASE_1000_T,
190 XGBE_SFP_BASE_1000_SX,
191 XGBE_SFP_BASE_1000_LX,
192 XGBE_SFP_BASE_1000_CX,
193 XGBE_SFP_BASE_10000_SR,
194 XGBE_SFP_BASE_10000_LR,
195 XGBE_SFP_BASE_10000_LRM,
196 XGBE_SFP_BASE_10000_ER,
197 XGBE_SFP_BASE_10000_CR,
198 };
199
200 enum xgbe_sfp_speed {
201 XGBE_SFP_SPEED_UNKNOWN = 0,
202 XGBE_SFP_SPEED_100_1000,
203 XGBE_SFP_SPEED_1000,
204 XGBE_SFP_SPEED_10000,
205 };
206
207 /* SFP Serial ID Base ID values relative to an offset of 0 */
208 #define XGBE_SFP_BASE_ID 0
209 #define XGBE_SFP_ID_SFP 0x03
210
211 #define XGBE_SFP_BASE_EXT_ID 1
212 #define XGBE_SFP_EXT_ID_SFP 0x04
213
214 #define XGBE_SFP_BASE_CV 2
215 #define XGBE_SFP_BASE_CV_CP 0x21
216
217 #define XGBE_SFP_BASE_10GBE_CC 3
218 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
219 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
220 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
221 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
222
223 #define XGBE_SFP_BASE_1GBE_CC 6
224 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
225 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
226 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
227 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
228
229 #define XGBE_SFP_BASE_CABLE 8
230 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
231 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
232
233 #define XGBE_SFP_BASE_BR 12
234 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
235 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
236 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
237 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
238
239 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
240
241 #define XGBE_SFP_BASE_VENDOR_NAME 20
242 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
243 #define XGBE_SFP_BASE_VENDOR_PN 40
244 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
245 #define XGBE_SFP_BASE_VENDOR_REV 56
246 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
247
248 #define XGBE_SFP_BASE_CC 63
249
250 /* SFP Serial ID Extended ID values relative to an offset of 64 */
251 #define XGBE_SFP_BASE_VENDOR_SN 4
252 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
253
254 #define XGBE_SFP_EXTD_OPT1 1
255 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
256 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
257
258 #define XGBE_SFP_EXTD_DIAG 28
259 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
260
261 #define XGBE_SFP_EXTD_SFF_8472 30
262
263 #define XGBE_SFP_EXTD_CC 31
264
265 struct xgbe_sfp_eeprom {
266 uint8_t base[64];
267 uint8_t extd[32];
268 uint8_t vendor[32];
269 };
270
271 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
272 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
273 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
274
275 #define XGBE_SFP_EEPROM_BASE_LEN 256
276 #define XGBE_SFP_EEPROM_DIAG_LEN 256
277 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
278 XGBE_SFP_EEPROM_DIAG_LEN)
279
280 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
281 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
282
283 struct xgbe_sfp_ascii {
284 union {
285 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
286 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
287 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
288 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
289 } u;
290 };
291
292 /* MDIO PHY reset types */
293 enum xgbe_mdio_reset {
294 XGBE_MDIO_RESET_NONE = 0,
295 XGBE_MDIO_RESET_I2C_GPIO,
296 XGBE_MDIO_RESET_INT_GPIO,
297 XGBE_MDIO_RESET_MAX,
298 };
299
300 /* Re-driver related definitions */
301 enum xgbe_phy_redrv_if {
302 XGBE_PHY_REDRV_IF_MDIO = 0,
303 XGBE_PHY_REDRV_IF_I2C,
304 XGBE_PHY_REDRV_IF_MAX,
305 };
306
307 enum xgbe_phy_redrv_model {
308 XGBE_PHY_REDRV_MODEL_4223 = 0,
309 XGBE_PHY_REDRV_MODEL_4227,
310 XGBE_PHY_REDRV_MODEL_MAX,
311 };
312
313 enum xgbe_phy_redrv_mode {
314 XGBE_PHY_REDRV_MODE_CX = 5,
315 XGBE_PHY_REDRV_MODE_SR = 9,
316 };
317
318 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
319
320 /* PHY related configuration information */
321 struct xgbe_phy_data {
322 enum xgbe_port_mode port_mode;
323
324 unsigned int port_id;
325
326 unsigned int port_speeds;
327
328 enum xgbe_conn_type conn_type;
329
330 enum xgbe_mode cur_mode;
331 enum xgbe_mode start_mode;
332
333 unsigned int rrc_count;
334
335 unsigned int mdio_addr;
336
337 /* SFP Support */
338 enum xgbe_sfp_comm sfp_comm;
339 unsigned int sfp_mux_address;
340 unsigned int sfp_mux_channel;
341
342 unsigned int sfp_gpio_address;
343 unsigned int sfp_gpio_mask;
344 unsigned int sfp_gpio_inputs;
345 unsigned int sfp_gpio_rx_los;
346 unsigned int sfp_gpio_tx_fault;
347 unsigned int sfp_gpio_mod_absent;
348 unsigned int sfp_gpio_rate_select;
349
350 unsigned int sfp_rx_los;
351 unsigned int sfp_tx_fault;
352 unsigned int sfp_mod_absent;
353 unsigned int sfp_changed;
354 unsigned int sfp_phy_avail;
355 unsigned int sfp_cable_len;
356 enum xgbe_sfp_base sfp_base;
357 enum xgbe_sfp_cable sfp_cable;
358 enum xgbe_sfp_speed sfp_speed;
359 struct xgbe_sfp_eeprom sfp_eeprom;
360
361 /* External PHY support */
362 enum xgbe_mdio_mode phydev_mode;
363 uint32_t phy_id;
364 int phydev;
365 enum xgbe_mdio_reset mdio_reset;
366 unsigned int mdio_reset_addr;
367 unsigned int mdio_reset_gpio;
368
369 /* Re-driver support */
370 unsigned int redrv;
371 unsigned int redrv_if;
372 unsigned int redrv_addr;
373 unsigned int redrv_lane;
374 unsigned int redrv_model;
375
376 /* KR AN support */
377 unsigned int phy_cdr_notrack;
378 unsigned int phy_cdr_delay;
379
380 uint8_t port_sfp_inputs;
381 };
382
383 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
384 static int xgbe_phy_reset(struct xgbe_prv_data *pdata);
385
386 static int
xgbe_phy_i2c_xfer(struct xgbe_prv_data * pdata,struct xgbe_i2c_op * i2c_op)387 xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *i2c_op)
388 {
389 return (pdata->i2c_if.i2c_xfer(pdata, i2c_op));
390 }
391
392 static int
xgbe_phy_redrv_write(struct xgbe_prv_data * pdata,unsigned int reg,unsigned int val)393 xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
394 unsigned int val)
395 {
396 struct xgbe_phy_data *phy_data = pdata->phy_data;
397 struct xgbe_i2c_op i2c_op;
398 __be16 *redrv_val;
399 uint8_t redrv_data[5], csum;
400 unsigned int i, retry;
401 int ret;
402
403 /* High byte of register contains read/write indicator */
404 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
405 redrv_data[1] = reg & 0xff;
406 redrv_val = (__be16 *)&redrv_data[2];
407 *redrv_val = cpu_to_be16(val);
408
409 /* Calculate 1 byte checksum */
410 csum = 0;
411 for (i = 0; i < 4; i++) {
412 csum += redrv_data[i];
413 if (redrv_data[i] > csum)
414 csum++;
415 }
416 redrv_data[4] = ~csum;
417
418 retry = 1;
419 again1:
420 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
421 i2c_op.target = phy_data->redrv_addr;
422 i2c_op.len = sizeof(redrv_data);
423 i2c_op.buf = redrv_data;
424 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
425 if (ret) {
426 if ((ret == -EAGAIN) && retry--)
427 goto again1;
428
429 return (ret);
430 }
431
432 retry = 1;
433 again2:
434 i2c_op.cmd = XGBE_I2C_CMD_READ;
435 i2c_op.target = phy_data->redrv_addr;
436 i2c_op.len = 1;
437 i2c_op.buf = redrv_data;
438 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
439 if (ret) {
440 if ((ret == -EAGAIN) && retry--)
441 goto again2;
442
443 return (ret);
444 }
445
446 if (redrv_data[0] != 0xff) {
447 axgbe_error("Redriver write checksum error\n");
448 ret = -EIO;
449 }
450
451 return (ret);
452 }
453
454 static int
xgbe_phy_i2c_write(struct xgbe_prv_data * pdata,unsigned int target,void * val,unsigned int val_len)455 xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, void *val,
456 unsigned int val_len)
457 {
458 struct xgbe_i2c_op i2c_op;
459 int retry, ret;
460
461 retry = 1;
462 again:
463 /* Write the specified register */
464 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
465 i2c_op.target = target;
466 i2c_op.len = val_len;
467 i2c_op.buf = val;
468 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
469 if ((ret == -EAGAIN) && retry--)
470 goto again;
471
472 return (ret);
473 }
474
475 static int
xgbe_phy_i2c_read(struct xgbe_prv_data * pdata,unsigned int target,void * reg,unsigned int reg_len,void * val,unsigned int val_len)476 xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, void *reg,
477 unsigned int reg_len, void *val, unsigned int val_len)
478 {
479 struct xgbe_i2c_op i2c_op;
480 int retry, ret;
481
482 axgbe_printf(3, "%s: target 0x%x reg_len %d val_len %d\n", __func__,
483 target, reg_len, val_len);
484 retry = 1;
485 again1:
486 /* Set the specified register to read */
487 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
488 i2c_op.target = target;
489 i2c_op.len = reg_len;
490 i2c_op.buf = reg;
491 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
492 axgbe_printf(3, "%s: ret1 %d retry %d\n", __func__, ret, retry);
493 if (ret) {
494 if ((ret == -EAGAIN) && retry--)
495 goto again1;
496
497 return (ret);
498 }
499
500 retry = 1;
501 again2:
502 /* Read the specified register */
503 i2c_op.cmd = XGBE_I2C_CMD_READ;
504 i2c_op.target = target;
505 i2c_op.len = val_len;
506 i2c_op.buf = val;
507 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
508 axgbe_printf(3, "%s: ret2 %d retry %d\n", __func__, ret, retry);
509 if ((ret == -EAGAIN) && retry--)
510 goto again2;
511
512 return (ret);
513 }
514
515 static int
xgbe_phy_sfp_put_mux(struct xgbe_prv_data * pdata)516 xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
517 {
518 struct xgbe_phy_data *phy_data = pdata->phy_data;
519 struct xgbe_i2c_op i2c_op;
520 uint8_t mux_channel;
521
522 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
523 return (0);
524
525 /* Select no mux channels */
526 mux_channel = 0;
527 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
528 i2c_op.target = phy_data->sfp_mux_address;
529 i2c_op.len = sizeof(mux_channel);
530 i2c_op.buf = &mux_channel;
531
532 return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
533 }
534
535 static int
xgbe_phy_sfp_get_mux(struct xgbe_prv_data * pdata)536 xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
537 {
538 struct xgbe_phy_data *phy_data = pdata->phy_data;
539 struct xgbe_i2c_op i2c_op;
540 uint8_t mux_channel;
541
542 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
543 return (0);
544
545 /* Select desired mux channel */
546 mux_channel = 1 << phy_data->sfp_mux_channel;
547 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
548 i2c_op.target = phy_data->sfp_mux_address;
549 i2c_op.len = sizeof(mux_channel);
550 i2c_op.buf = &mux_channel;
551
552 return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
553 }
554
555 static void
xgbe_phy_put_comm_ownership(struct xgbe_prv_data * pdata)556 xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
557 {
558 mtx_unlock(&xgbe_phy_comm_lock);
559 }
560
561 static int
xgbe_phy_get_comm_ownership(struct xgbe_prv_data * pdata)562 xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
563 {
564 struct xgbe_phy_data *phy_data = pdata->phy_data;
565 unsigned long timeout;
566 unsigned int mutex_id;
567
568 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
569 * the driver needs to take the software mutex and then the hardware
570 * mutexes before being able to use the busses.
571 */
572 mtx_lock(&xgbe_phy_comm_lock);
573
574 /* Clear the mutexes */
575 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
576 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
577
578 /* Mutex formats are the same for I2C and MDIO/GPIO */
579 mutex_id = 0;
580 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
581 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
582
583 timeout = ticks + (5 * hz);
584 while (ticks < timeout) {
585 /* Must be all zeroes in order to obtain the mutex */
586 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
587 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
588 DELAY(200);
589 continue;
590 }
591
592 /* Obtain the mutex */
593 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
594 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
595
596 return (0);
597 }
598
599 mtx_unlock(&xgbe_phy_comm_lock);
600
601 axgbe_error("unable to obtain hardware mutexes\n");
602
603 return (-ETIMEDOUT);
604 }
605
606 static int
xgbe_phy_mdio_mii_write(struct xgbe_prv_data * pdata,int addr,int reg,uint16_t val)607 xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,
608 uint16_t val)
609 {
610 struct xgbe_phy_data *phy_data = pdata->phy_data;
611
612 if (reg & MII_ADDR_C45) {
613 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
614 return (-ENOTSUP);
615 } else {
616 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
617 return (-ENOTSUP);
618 }
619
620 return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val));
621 }
622
623 static int
xgbe_phy_i2c_mii_write(struct xgbe_prv_data * pdata,int reg,uint16_t val)624 xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, uint16_t val)
625 {
626 __be16 *mii_val;
627 uint8_t mii_data[3];
628 int ret;
629
630 ret = xgbe_phy_sfp_get_mux(pdata);
631 if (ret)
632 return (ret);
633
634 mii_data[0] = reg & 0xff;
635 mii_val = (__be16 *)&mii_data[1];
636 *mii_val = cpu_to_be16(val);
637
638 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
639 mii_data, sizeof(mii_data));
640
641 xgbe_phy_sfp_put_mux(pdata);
642
643 return (ret);
644 }
645
646 int
xgbe_phy_mii_write(struct xgbe_prv_data * pdata,int addr,int reg,uint16_t val)647 xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, uint16_t val)
648 {
649 struct xgbe_phy_data *phy_data = pdata->phy_data;
650 int ret;
651
652 axgbe_printf(3, "%s: addr %d reg %d val %#x\n", __func__, addr, reg, val);
653 ret = xgbe_phy_get_comm_ownership(pdata);
654 if (ret)
655 return (ret);
656
657 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
658 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
659 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
660 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
661 else
662 ret = -ENOTSUP;
663
664 xgbe_phy_put_comm_ownership(pdata);
665
666 return (ret);
667 }
668
669 static int
xgbe_phy_mdio_mii_read(struct xgbe_prv_data * pdata,int addr,int reg)670 xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
671 {
672 struct xgbe_phy_data *phy_data = pdata->phy_data;
673
674 if (reg & MII_ADDR_C45) {
675 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
676 return (-ENOTSUP);
677 } else {
678 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
679 return (-ENOTSUP);
680 }
681
682 return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg));
683 }
684
685 static int
xgbe_phy_i2c_mii_read(struct xgbe_prv_data * pdata,int reg)686 xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
687 {
688 __be16 mii_val;
689 uint8_t mii_reg;
690 int ret;
691
692 ret = xgbe_phy_sfp_get_mux(pdata);
693 if (ret)
694 return (ret);
695
696 mii_reg = reg;
697 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
698 &mii_reg, sizeof(mii_reg),
699 &mii_val, sizeof(mii_val));
700 if (!ret)
701 ret = be16_to_cpu(mii_val);
702
703 xgbe_phy_sfp_put_mux(pdata);
704
705 return (ret);
706 }
707
708 int
xgbe_phy_mii_read(struct xgbe_prv_data * pdata,int addr,int reg)709 xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
710 {
711 struct xgbe_phy_data *phy_data = pdata->phy_data;
712 int ret;
713
714 axgbe_printf(3, "%s: addr %d reg %d\n", __func__, addr, reg);
715 ret = xgbe_phy_get_comm_ownership(pdata);
716 if (ret)
717 return (ret);
718
719 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
720 ret = xgbe_phy_i2c_mii_read(pdata, reg);
721 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
722 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
723 else
724 ret = -ENOTSUP;
725
726 xgbe_phy_put_comm_ownership(pdata);
727
728 return (ret);
729 }
730
731 static void
xgbe_phy_sfp_phy_settings(struct xgbe_prv_data * pdata)732 xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
733 {
734 struct xgbe_phy_data *phy_data = pdata->phy_data;
735
736 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
737 return;
738
739 XGBE_ZERO_SUP(&pdata->phy);
740
741 if (phy_data->sfp_mod_absent) {
742 pdata->phy.speed = SPEED_UNKNOWN;
743 pdata->phy.duplex = DUPLEX_UNKNOWN;
744 pdata->phy.autoneg = AUTONEG_ENABLE;
745 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
746
747 XGBE_SET_SUP(&pdata->phy, Autoneg);
748 XGBE_SET_SUP(&pdata->phy, Pause);
749 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
750 XGBE_SET_SUP(&pdata->phy, TP);
751 XGBE_SET_SUP(&pdata->phy, FIBRE);
752
753 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
754
755 return;
756 }
757
758 switch (phy_data->sfp_base) {
759 case XGBE_SFP_BASE_1000_T:
760 case XGBE_SFP_BASE_1000_SX:
761 case XGBE_SFP_BASE_1000_LX:
762 case XGBE_SFP_BASE_1000_CX:
763 pdata->phy.speed = SPEED_UNKNOWN;
764 pdata->phy.duplex = DUPLEX_UNKNOWN;
765 pdata->phy.autoneg = AUTONEG_ENABLE;
766 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
767 XGBE_SET_SUP(&pdata->phy, Autoneg);
768 XGBE_SET_SUP(&pdata->phy, Pause);
769 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
770 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
771 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
772 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
773 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
774 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
775 } else {
776 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
777 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
778 }
779 break;
780 case XGBE_SFP_BASE_10000_SR:
781 case XGBE_SFP_BASE_10000_LR:
782 case XGBE_SFP_BASE_10000_LRM:
783 case XGBE_SFP_BASE_10000_ER:
784 case XGBE_SFP_BASE_10000_CR:
785 pdata->phy.speed = SPEED_10000;
786 pdata->phy.duplex = DUPLEX_FULL;
787 pdata->phy.autoneg = AUTONEG_DISABLE;
788 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
789 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
790 switch (phy_data->sfp_base) {
791 case XGBE_SFP_BASE_10000_SR:
792 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
793 break;
794 case XGBE_SFP_BASE_10000_LR:
795 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
796 break;
797 case XGBE_SFP_BASE_10000_LRM:
798 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
799 break;
800 case XGBE_SFP_BASE_10000_ER:
801 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
802 break;
803 case XGBE_SFP_BASE_10000_CR:
804 XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full);
805 break;
806 default:
807 break;
808 }
809 }
810 break;
811 default:
812 pdata->phy.speed = SPEED_UNKNOWN;
813 pdata->phy.duplex = DUPLEX_UNKNOWN;
814 pdata->phy.autoneg = AUTONEG_DISABLE;
815 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
816 break;
817 }
818
819 switch (phy_data->sfp_base) {
820 case XGBE_SFP_BASE_1000_T:
821 case XGBE_SFP_BASE_1000_CX:
822 case XGBE_SFP_BASE_10000_CR:
823 XGBE_SET_SUP(&pdata->phy, TP);
824 break;
825 default:
826 XGBE_SET_SUP(&pdata->phy, FIBRE);
827 break;
828 }
829
830 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
831
832 axgbe_printf(1, "%s: link speed %d spf_base 0x%x pause_autoneg %d "
833 "advert 0x%x support 0x%x\n", __func__, pdata->phy.speed,
834 phy_data->sfp_base, pdata->phy.pause_autoneg,
835 pdata->phy.advertising, pdata->phy.supported);
836 }
837
838 static bool
xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom * sfp_eeprom,enum xgbe_sfp_speed sfp_speed)839 xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
840 enum xgbe_sfp_speed sfp_speed)
841 {
842 uint8_t *sfp_base, min, max;
843
844 sfp_base = sfp_eeprom->base;
845
846 switch (sfp_speed) {
847 case XGBE_SFP_SPEED_1000:
848 min = XGBE_SFP_BASE_BR_1GBE_MIN;
849 max = XGBE_SFP_BASE_BR_1GBE_MAX;
850 break;
851 case XGBE_SFP_SPEED_10000:
852 min = XGBE_SFP_BASE_BR_10GBE_MIN;
853 max = XGBE_SFP_BASE_BR_10GBE_MAX;
854 break;
855 default:
856 return (false);
857 }
858
859 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
860 (sfp_base[XGBE_SFP_BASE_BR] <= max));
861 }
862
863 static void
xgbe_phy_free_phy_device(struct xgbe_prv_data * pdata)864 xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
865 {
866 struct xgbe_phy_data *phy_data = pdata->phy_data;
867
868 if (phy_data->phydev)
869 phy_data->phydev = 0;
870 }
871
872 static bool
xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data * pdata)873 xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
874 {
875 struct xgbe_phy_data *phy_data = pdata->phy_data;
876 unsigned int phy_id = phy_data->phy_id;
877
878 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
879 return (false);
880
881 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
882 return (false);
883
884 /* Enable Base-T AN */
885 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001);
886 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
887 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000);
888
889 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
890 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084);
891 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00);
892 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140);
893 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01);
894 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
895
896 axgbe_printf(3, "Finisar PHY quirk in place\n");
897
898 return (true);
899 }
900
901 static bool
xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data * pdata)902 xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
903 {
904 struct xgbe_phy_data *phy_data = pdata->phy_data;
905 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
906 unsigned int phy_id = phy_data->phy_id;
907 int reg;
908
909 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
910 return (false);
911
912 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
913 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
914 return (false);
915
916 /* For Bel-Fuse, use the extra AN flag */
917 pdata->an_again = 1;
918
919 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
920 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
921 return (false);
922
923 if ((phy_id & 0xfffffff0) != 0x03625d10)
924 return (false);
925
926 /* Disable RGMII mode */
927 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007);
928 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18);
929 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080);
930
931 /* Enable fiber register bank */
932 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
933 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
934 reg &= 0x03ff;
935 reg &= ~0x0001;
936 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
937 reg | 0x0001);
938
939 /* Power down SerDes */
940 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
941 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800);
942
943 /* Configure SGMII-to-Copper mode */
944 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
945 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
946 reg &= 0x03ff;
947 reg &= ~0x0006;
948 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
949 reg | 0x0004);
950
951 /* Power up SerDes */
952 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
953 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
954
955 /* Enable copper register bank */
956 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
957 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
958 reg &= 0x03ff;
959 reg &= ~0x0001;
960 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
961 reg);
962
963 /* Power up SerDes */
964 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
965 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
966
967 axgbe_printf(3, "BelFuse PHY quirk in place\n");
968
969 return (true);
970 }
971
972 static void
xgbe_phy_external_phy_quirks(struct xgbe_prv_data * pdata)973 xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
974 {
975 if (xgbe_phy_belfuse_phy_quirks(pdata))
976 return;
977
978 if (xgbe_phy_finisar_phy_quirks(pdata))
979 return;
980 }
981
982 static int
xgbe_get_phy_id(struct xgbe_prv_data * pdata)983 xgbe_get_phy_id(struct xgbe_prv_data *pdata)
984 {
985 struct xgbe_phy_data *phy_data = pdata->phy_data;
986 uint32_t oui, model, phy_id1, phy_id2;
987 int phy_reg;
988
989 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02);
990 if (phy_reg < 0)
991 return (-EIO);
992
993 phy_id1 = (phy_reg & 0xffff);
994 phy_data->phy_id = (phy_reg & 0xffff) << 16;
995
996 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03);
997 if (phy_reg < 0)
998 return (-EIO);
999
1000 phy_id2 = (phy_reg & 0xffff);
1001 phy_data->phy_id |= (phy_reg & 0xffff);
1002
1003 oui = MII_OUI(phy_id1, phy_id2);
1004 model = MII_MODEL(phy_id2);
1005
1006 axgbe_printf(2, "%s: phy_id1: 0x%x phy_id2: 0x%x oui: %#x model %#x\n",
1007 __func__, phy_id1, phy_id2, oui, model);
1008
1009 return (0);
1010 }
1011
1012 static int
xgbe_phy_start_aneg(struct xgbe_prv_data * pdata)1013 xgbe_phy_start_aneg(struct xgbe_prv_data *pdata)
1014 {
1015 uint16_t ctl = 0;
1016 int changed = 0;
1017 int ret;
1018
1019 if (AUTONEG_ENABLE != pdata->phy.autoneg) {
1020 if (SPEED_1000 == pdata->phy.speed)
1021 ctl |= BMCR_SPEED1;
1022 else if (SPEED_100 == pdata->phy.speed)
1023 ctl |= BMCR_SPEED100;
1024
1025 if (DUPLEX_FULL == pdata->phy.duplex)
1026 ctl |= BMCR_FDX;
1027
1028 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
1029 if (ret)
1030 return (ret);
1031
1032 ret = xgbe_phy_mii_write(pdata, pdata->mdio_addr, MII_BMCR,
1033 (ret & ~(~(BMCR_LOOP | BMCR_ISO | BMCR_PDOWN))) | ctl);
1034 }
1035
1036 ctl = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
1037 if (ctl < 0)
1038 return (ctl);
1039
1040 if (!(ctl & BMCR_AUTOEN) || (ctl & BMCR_ISO))
1041 changed = 1;
1042
1043 if (changed > 0) {
1044 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
1045 if (ret)
1046 return (ret);
1047
1048 ret = xgbe_phy_mii_write(pdata, pdata->mdio_addr, MII_BMCR,
1049 (ret & ~(BMCR_ISO)) | (BMCR_AUTOEN | BMCR_STARTNEG));
1050 }
1051
1052 return (0);
1053 }
1054
1055 static int
xgbe_phy_find_phy_device(struct xgbe_prv_data * pdata)1056 xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
1057 {
1058 struct xgbe_phy_data *phy_data = pdata->phy_data;
1059 int ret;
1060
1061 axgbe_printf(2, "%s: phydev %d phydev_mode %d sfp_phy_avail %d phy_id "
1062 "0x%08x\n", __func__, phy_data->phydev, phy_data->phydev_mode,
1063 phy_data->sfp_phy_avail, phy_data->phy_id);
1064
1065 /* If we already have a PHY, just return */
1066 if (phy_data->phydev) {
1067 axgbe_printf(3, "%s: phy present already\n", __func__);
1068 return (0);
1069 }
1070
1071 /* Clear the extra AN flag */
1072 pdata->an_again = 0;
1073
1074 /* Check for the use of an external PHY */
1075 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
1076 axgbe_printf(3, "%s: phydev_mode %d\n", __func__,
1077 phy_data->phydev_mode);
1078 return (0);
1079 }
1080
1081 /* For SFP, only use an external PHY if available */
1082 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1083 !phy_data->sfp_phy_avail) {
1084 axgbe_printf(3, "%s: port_mode %d avail %d\n", __func__,
1085 phy_data->port_mode, phy_data->sfp_phy_avail);
1086 return (0);
1087 }
1088
1089 /* Set the proper MDIO mode for the PHY */
1090 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1091 phy_data->phydev_mode);
1092 if (ret) {
1093 axgbe_error("mdio port/clause not compatible (%u/%u) ret %d\n",
1094 phy_data->mdio_addr, phy_data->phydev_mode, ret);
1095 return (ret);
1096 }
1097
1098 ret = xgbe_get_phy_id(pdata);
1099 if (ret)
1100 return (ret);
1101 axgbe_printf(2, "Get phy_id 0x%08x\n", phy_data->phy_id);
1102
1103 phy_data->phydev = 1;
1104 xgbe_phy_external_phy_quirks(pdata);
1105 xgbe_phy_start_aneg(pdata);
1106
1107 return (0);
1108 }
1109
1110 static void
xgbe_phy_sfp_external_phy(struct xgbe_prv_data * pdata)1111 xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1112 {
1113 struct xgbe_phy_data *phy_data = pdata->phy_data;
1114 int ret;
1115
1116 axgbe_printf(3, "%s: sfp_changed: 0x%x\n", __func__,
1117 phy_data->sfp_changed);
1118 if (!phy_data->sfp_changed)
1119 return;
1120
1121 phy_data->sfp_phy_avail = 0;
1122
1123 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1124 return;
1125
1126 /* Check access to the PHY by reading CTRL1 */
1127 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1128 if (ret < 0) {
1129 axgbe_error("%s: ext phy fail %d\n", __func__, ret);
1130 return;
1131 }
1132
1133 /* Successfully accessed the PHY */
1134 phy_data->sfp_phy_avail = 1;
1135 axgbe_printf(3, "Successfully accessed External PHY\n");
1136 }
1137
1138 static bool
xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data * phy_data)1139 xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1140 {
1141 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1142
1143 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1144 return (false);
1145
1146 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1147 return (false);
1148
1149 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1150 return (true);
1151
1152 return (false);
1153 }
1154
1155 static bool
xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data * phy_data)1156 xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1157 {
1158 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1159
1160 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1161 return (false);
1162
1163 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1164 return (false);
1165
1166 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1167 return (true);
1168
1169 return (false);
1170 }
1171
1172 static bool
xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data * phy_data)1173 xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1174 {
1175 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1176 return (false);
1177
1178 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1179 return (true);
1180
1181 return (false);
1182 }
1183
1184 static void
xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data * pdata)1185 xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1186 {
1187 struct xgbe_phy_data *phy_data = pdata->phy_data;
1188 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1189 uint8_t *sfp_base;
1190
1191 sfp_base = sfp_eeprom->base;
1192
1193 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) {
1194 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_ID]);
1195 return;
1196 }
1197
1198 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) {
1199 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_EXT_ID]);
1200 return;
1201 }
1202
1203 /* Update transceiver signals (eeprom extd/options) */
1204 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1205 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1206
1207 /* Assume ACTIVE cable unless told it is PASSIVE */
1208 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1209 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1210 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1211 } else
1212 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1213
1214 /*
1215 * Determine the type of SFP. Certain 10G SFP+ modules read as
1216 * 1000BASE-CX. To prevent 10G DAC cables to be recognized as
1217 * 1G, we first check if it is a DAC and the bitrate is 10G.
1218 */
1219 if (((sfp_base[XGBE_SFP_BASE_CV] & XGBE_SFP_BASE_CV_CP) ||
1220 (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE)) &&
1221 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1222 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1223 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1224 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1225 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1226 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1227 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1228 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1229 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1230 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1231 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1232 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1233 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1234 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1235 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1236 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1237 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1238 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1239
1240 switch (phy_data->sfp_base) {
1241 case XGBE_SFP_BASE_1000_T:
1242 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1243 break;
1244 case XGBE_SFP_BASE_1000_SX:
1245 case XGBE_SFP_BASE_1000_LX:
1246 case XGBE_SFP_BASE_1000_CX:
1247 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1248 break;
1249 case XGBE_SFP_BASE_10000_SR:
1250 case XGBE_SFP_BASE_10000_LR:
1251 case XGBE_SFP_BASE_10000_LRM:
1252 case XGBE_SFP_BASE_10000_ER:
1253 case XGBE_SFP_BASE_10000_CR:
1254 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1255 break;
1256 default:
1257 break;
1258 }
1259 axgbe_printf(3, "%s: sfp_base: 0x%x sfp_speed: 0x%x sfp_cable: 0x%x "
1260 "rx_los 0x%x tx_fault 0x%x\n", __func__, phy_data->sfp_base,
1261 phy_data->sfp_speed, phy_data->sfp_cable, phy_data->sfp_rx_los,
1262 phy_data->sfp_tx_fault);
1263 }
1264
1265 static void
xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data * pdata,struct xgbe_sfp_eeprom * sfp_eeprom)1266 xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1267 struct xgbe_sfp_eeprom *sfp_eeprom)
1268 {
1269 struct xgbe_sfp_ascii sfp_ascii;
1270 char *sfp_data = (char *)&sfp_ascii;
1271
1272 axgbe_printf(3, "SFP detected:\n");
1273 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1274 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1275 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1276 axgbe_printf(3, " vendor: %s\n",
1277 sfp_data);
1278
1279 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1280 XGBE_SFP_BASE_VENDOR_PN_LEN);
1281 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1282 axgbe_printf(3, " part number: %s\n",
1283 sfp_data);
1284
1285 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1286 XGBE_SFP_BASE_VENDOR_REV_LEN);
1287 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1288 axgbe_printf(3, " revision level: %s\n",
1289 sfp_data);
1290
1291 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1292 XGBE_SFP_BASE_VENDOR_SN_LEN);
1293 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1294 axgbe_printf(3, " serial number: %s\n",
1295 sfp_data);
1296 }
1297
1298 static bool
xgbe_phy_sfp_verify_eeprom(uint8_t cc_in,uint8_t * buf,unsigned int len)1299 xgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, unsigned int len)
1300 {
1301 uint8_t cc;
1302
1303 for (cc = 0; len; buf++, len--)
1304 cc += *buf;
1305
1306 return ((cc == cc_in) ? true : false);
1307 }
1308
1309 static void
dump_sfp_eeprom(struct xgbe_prv_data * pdata,uint8_t * sfp_base)1310 dump_sfp_eeprom(struct xgbe_prv_data *pdata, uint8_t *sfp_base)
1311 {
1312 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_ID] : 0x%04x\n",
1313 sfp_base[XGBE_SFP_BASE_ID]);
1314 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_EXT_ID] : 0x%04x\n",
1315 sfp_base[XGBE_SFP_BASE_EXT_ID]);
1316 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_CABLE] : 0x%04x\n",
1317 sfp_base[XGBE_SFP_BASE_CABLE]);
1318 }
1319
1320 static int
xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data * pdata)1321 xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1322 {
1323 struct xgbe_phy_data *phy_data = pdata->phy_data;
1324 struct xgbe_sfp_eeprom sfp_eeprom, *eeprom;
1325 uint8_t eeprom_addr, *base;
1326 int ret;
1327
1328 ret = xgbe_phy_sfp_get_mux(pdata);
1329 if (ret) {
1330 axgbe_error("I2C error setting SFP MUX\n");
1331 return (ret);
1332 }
1333
1334 /* Read the SFP serial ID eeprom */
1335 eeprom_addr = 0;
1336 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1337 &eeprom_addr, sizeof(eeprom_addr),
1338 &sfp_eeprom, sizeof(sfp_eeprom));
1339
1340 eeprom = &sfp_eeprom;
1341 base = eeprom->base;
1342 dump_sfp_eeprom(pdata, base);
1343 if (ret) {
1344 axgbe_error("I2C error reading SFP EEPROM\n");
1345 goto put;
1346 }
1347
1348 /* Validate the contents read */
1349 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1350 sfp_eeprom.base, sizeof(sfp_eeprom.base) - 1)) {
1351 axgbe_error("verify eeprom base failed\n");
1352 ret = -EINVAL;
1353 goto put;
1354 }
1355
1356 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1357 sfp_eeprom.extd, sizeof(sfp_eeprom.extd) - 1)) {
1358 axgbe_error("verify eeprom extd failed\n");
1359 ret = -EINVAL;
1360 goto put;
1361 }
1362
1363 /* Check for an added or changed SFP */
1364 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1365 phy_data->sfp_changed = 1;
1366
1367 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1368
1369 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1370
1371 xgbe_phy_free_phy_device(pdata);
1372 } else
1373 phy_data->sfp_changed = 0;
1374
1375 put:
1376 xgbe_phy_sfp_put_mux(pdata);
1377
1378 return (ret);
1379 }
1380
1381 static void
xgbe_phy_sfp_signals(struct xgbe_prv_data * pdata)1382 xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1383 {
1384 struct xgbe_phy_data *phy_data = pdata->phy_data;
1385 uint8_t gpio_reg, gpio_ports[2];
1386 int ret, prev_sfp_inputs = phy_data->port_sfp_inputs;
1387 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
1388
1389 /* Read the input port registers */
1390 axgbe_printf(3, "%s: befor sfp_mod:%d sfp_gpio_address:0x%x\n",
1391 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_address);
1392
1393 gpio_reg = 0;
1394 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg,
1395 sizeof(gpio_reg), gpio_ports, sizeof(gpio_ports));
1396 if (ret) {
1397 axgbe_error("%s: I2C error reading SFP GPIO addr:0x%x\n",
1398 __func__, phy_data->sfp_gpio_address);
1399 return;
1400 }
1401
1402 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1403 phy_data->port_sfp_inputs = (phy_data->sfp_gpio_inputs >> shift) & 0x0F;
1404
1405 if (prev_sfp_inputs != phy_data->port_sfp_inputs)
1406 axgbe_printf(0, "%s: port_sfp_inputs: 0x%0x\n", __func__,
1407 phy_data->port_sfp_inputs);
1408
1409 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1410
1411 axgbe_printf(3, "%s: after sfp_mod:%d sfp_gpio_inputs:0x%x\n",
1412 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_inputs);
1413 }
1414
1415 static void
xgbe_phy_sfp_mod_absent(struct xgbe_prv_data * pdata)1416 xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1417 {
1418 struct xgbe_phy_data *phy_data = pdata->phy_data;
1419
1420 xgbe_phy_free_phy_device(pdata);
1421
1422 phy_data->sfp_mod_absent = 1;
1423 phy_data->sfp_phy_avail = 0;
1424 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1425 }
1426
1427 static void
xgbe_phy_sfp_reset(struct xgbe_phy_data * phy_data)1428 xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1429 {
1430 phy_data->sfp_rx_los = 0;
1431 phy_data->sfp_tx_fault = 0;
1432 phy_data->sfp_mod_absent = 1;
1433 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1434 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1435 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1436 }
1437
1438 static void
xgbe_phy_sfp_detect(struct xgbe_prv_data * pdata)1439 xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1440 {
1441 struct xgbe_phy_data *phy_data = pdata->phy_data;
1442 int ret, prev_sfp_state = phy_data->sfp_mod_absent;
1443
1444 /* Reset the SFP signals and info */
1445 xgbe_phy_sfp_reset(phy_data);
1446
1447 ret = xgbe_phy_get_comm_ownership(pdata);
1448 if (ret)
1449 return;
1450
1451 /* Read the SFP signals and check for module presence */
1452 xgbe_phy_sfp_signals(pdata);
1453 if (phy_data->sfp_mod_absent) {
1454 if (prev_sfp_state != phy_data->sfp_mod_absent)
1455 axgbe_error("%s: mod absent\n", __func__);
1456 xgbe_phy_sfp_mod_absent(pdata);
1457 goto put;
1458 }
1459
1460 ret = xgbe_phy_sfp_read_eeprom(pdata);
1461 if (ret) {
1462 /* Treat any error as if there isn't an SFP plugged in */
1463 axgbe_error("%s: eeprom read failed\n", __func__);
1464 xgbe_phy_sfp_reset(phy_data);
1465 xgbe_phy_sfp_mod_absent(pdata);
1466 goto put;
1467 }
1468
1469 xgbe_phy_sfp_parse_eeprom(pdata);
1470
1471 xgbe_phy_sfp_external_phy(pdata);
1472
1473 put:
1474 xgbe_phy_sfp_phy_settings(pdata);
1475
1476 axgbe_printf(3, "%s: phy speed: 0x%x duplex: 0x%x autoneg: 0x%x "
1477 "pause_autoneg: 0x%x\n", __func__, pdata->phy.speed,
1478 pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg);
1479
1480 xgbe_phy_put_comm_ownership(pdata);
1481 }
1482
1483 static int
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata)1484 xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata)
1485 {
1486 struct xgbe_phy_data *phy_data = pdata->phy_data;
1487 uint8_t eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1488 struct xgbe_sfp_eeprom *sfp_eeprom;
1489 int ret;
1490
1491 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1492 ret = -ENXIO;
1493 goto done;
1494 }
1495
1496 if (phy_data->sfp_mod_absent) {
1497 ret = -EIO;
1498 goto done;
1499 }
1500
1501 ret = xgbe_phy_get_comm_ownership(pdata);
1502 if (ret) {
1503 ret = -EIO;
1504 goto done;
1505 }
1506
1507 ret = xgbe_phy_sfp_get_mux(pdata);
1508 if (ret) {
1509 axgbe_error("I2C error setting SFP MUX\n");
1510 ret = -EIO;
1511 goto put_own;
1512 }
1513
1514 /* Read the SFP serial ID eeprom */
1515 eeprom_addr = 0;
1516 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1517 &eeprom_addr, sizeof(eeprom_addr),
1518 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1519 if (ret) {
1520 axgbe_error("I2C error reading SFP EEPROM\n");
1521 ret = -EIO;
1522 goto put_mux;
1523 }
1524
1525 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1526
1527 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1528 /* Read the SFP diagnostic eeprom */
1529 eeprom_addr = 0;
1530 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1531 &eeprom_addr, sizeof(eeprom_addr),
1532 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1533 XGBE_SFP_EEPROM_DIAG_LEN);
1534 if (ret) {
1535 axgbe_error("I2C error reading SFP DIAGS\n");
1536 ret = -EIO;
1537 goto put_mux;
1538 }
1539 }
1540
1541 put_mux:
1542 xgbe_phy_sfp_put_mux(pdata);
1543
1544 put_own:
1545 xgbe_phy_put_comm_ownership(pdata);
1546
1547 done:
1548 return (ret);
1549 }
1550
1551 static int
xgbe_phy_module_info(struct xgbe_prv_data * pdata)1552 xgbe_phy_module_info(struct xgbe_prv_data *pdata)
1553 {
1554 struct xgbe_phy_data *phy_data = pdata->phy_data;
1555
1556 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1557 return (-ENXIO);
1558
1559 if (phy_data->sfp_mod_absent)
1560 return (-EIO);
1561
1562 return (0);
1563 }
1564
1565 static void
xgbe_phy_phydev_flowctrl(struct xgbe_prv_data * pdata)1566 xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1567 {
1568 struct xgbe_phy_data *phy_data = pdata->phy_data;
1569
1570 pdata->phy.tx_pause = 0;
1571 pdata->phy.rx_pause = 0;
1572
1573 if (!phy_data->phydev)
1574 return;
1575
1576 if (pdata->phy.pause)
1577 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1578
1579 if (pdata->phy.asym_pause)
1580 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1581
1582 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__,
1583 pdata->phy.tx_pause, pdata->phy.rx_pause);
1584 }
1585
1586 static enum xgbe_mode
xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data * pdata)1587 xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1588 {
1589 enum xgbe_mode mode;
1590
1591 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1592 XGBE_SET_LP_ADV(&pdata->phy, TP);
1593
1594 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__,
1595 pdata->phy.pause_autoneg);
1596
1597 /* Use external PHY to determine flow control */
1598 if (pdata->phy.pause_autoneg)
1599 xgbe_phy_phydev_flowctrl(pdata);
1600
1601 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1602 case XGBE_SGMII_AN_LINK_SPEED_100:
1603 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1604 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full);
1605 mode = XGBE_MODE_SGMII_100;
1606 } else {
1607 /* Half-duplex not supported */
1608 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half);
1609 mode = XGBE_MODE_UNKNOWN;
1610 }
1611 break;
1612 case XGBE_SGMII_AN_LINK_SPEED_1000:
1613 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1614 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full);
1615 mode = XGBE_MODE_SGMII_1000;
1616 } else {
1617 /* Half-duplex not supported */
1618 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half);
1619 mode = XGBE_MODE_UNKNOWN;
1620 }
1621 break;
1622 default:
1623 mode = XGBE_MODE_UNKNOWN;
1624 }
1625
1626 return (mode);
1627 }
1628
1629 static enum xgbe_mode
xgbe_phy_an37_outcome(struct xgbe_prv_data * pdata)1630 xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1631 {
1632 enum xgbe_mode mode;
1633 unsigned int ad_reg, lp_reg;
1634
1635 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1636 XGBE_SET_LP_ADV(&pdata->phy, FIBRE);
1637
1638 /* Compare Advertisement and Link Partner register */
1639 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1640 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1641 if (lp_reg & 0x100)
1642 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1643 if (lp_reg & 0x80)
1644 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1645
1646 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
1647 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1648
1649 if (pdata->phy.pause_autoneg) {
1650 /* Set flow control based on auto-negotiation result */
1651 pdata->phy.tx_pause = 0;
1652 pdata->phy.rx_pause = 0;
1653
1654 if (ad_reg & lp_reg & 0x100) {
1655 pdata->phy.tx_pause = 1;
1656 pdata->phy.rx_pause = 1;
1657 } else if (ad_reg & lp_reg & 0x80) {
1658 if (ad_reg & 0x100)
1659 pdata->phy.rx_pause = 1;
1660 else if (lp_reg & 0x100)
1661 pdata->phy.tx_pause = 1;
1662 }
1663 }
1664
1665 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
1666 pdata->phy.rx_pause);
1667
1668 if (lp_reg & 0x20)
1669 XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full);
1670
1671 /* Half duplex is not supported */
1672 ad_reg &= lp_reg;
1673 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1674
1675 return (mode);
1676 }
1677
1678 static enum xgbe_mode
xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data * pdata)1679 xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1680 {
1681 struct xgbe_phy_data *phy_data = pdata->phy_data;
1682 enum xgbe_mode mode;
1683 unsigned int ad_reg, lp_reg;
1684
1685 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1686 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1687
1688 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__,
1689 pdata->phy.pause_autoneg);
1690
1691 /* Use external PHY to determine flow control */
1692 if (pdata->phy.pause_autoneg)
1693 xgbe_phy_phydev_flowctrl(pdata);
1694
1695 /* Compare Advertisement and Link Partner register 2 */
1696 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1697 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1698 if (lp_reg & 0x80)
1699 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
1700 if (lp_reg & 0x20)
1701 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
1702
1703 ad_reg &= lp_reg;
1704 if (ad_reg & 0x80) {
1705 switch (phy_data->port_mode) {
1706 case XGBE_PORT_MODE_BACKPLANE:
1707 mode = XGBE_MODE_KR;
1708 break;
1709 default:
1710 mode = XGBE_MODE_SFI;
1711 break;
1712 }
1713 } else if (ad_reg & 0x20) {
1714 switch (phy_data->port_mode) {
1715 case XGBE_PORT_MODE_BACKPLANE:
1716 mode = XGBE_MODE_KX_1000;
1717 break;
1718 case XGBE_PORT_MODE_1000BASE_X:
1719 mode = XGBE_MODE_X;
1720 break;
1721 case XGBE_PORT_MODE_SFP:
1722 switch (phy_data->sfp_base) {
1723 case XGBE_SFP_BASE_1000_T:
1724 if ((phy_data->phydev) &&
1725 (pdata->phy.speed == SPEED_100))
1726 mode = XGBE_MODE_SGMII_100;
1727 else
1728 mode = XGBE_MODE_SGMII_1000;
1729 break;
1730 case XGBE_SFP_BASE_1000_SX:
1731 case XGBE_SFP_BASE_1000_LX:
1732 case XGBE_SFP_BASE_1000_CX:
1733 default:
1734 mode = XGBE_MODE_X;
1735 break;
1736 }
1737 break;
1738 default:
1739 if ((phy_data->phydev) &&
1740 (pdata->phy.speed == SPEED_100))
1741 mode = XGBE_MODE_SGMII_100;
1742 else
1743 mode = XGBE_MODE_SGMII_1000;
1744 break;
1745 }
1746 } else {
1747 mode = XGBE_MODE_UNKNOWN;
1748 }
1749
1750 /* Compare Advertisement and Link Partner register 3 */
1751 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1752 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1753 if (lp_reg & 0xc000)
1754 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
1755
1756 return (mode);
1757 }
1758
1759 static enum xgbe_mode
xgbe_phy_an73_outcome(struct xgbe_prv_data * pdata)1760 xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1761 {
1762 enum xgbe_mode mode;
1763 unsigned int ad_reg, lp_reg;
1764
1765 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1766 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1767
1768 /* Compare Advertisement and Link Partner register 1 */
1769 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1770 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1771 if (lp_reg & 0x400)
1772 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1773 if (lp_reg & 0x800)
1774 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1775
1776 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
1777 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1778
1779 if (pdata->phy.pause_autoneg) {
1780 /* Set flow control based on auto-negotiation result */
1781 pdata->phy.tx_pause = 0;
1782 pdata->phy.rx_pause = 0;
1783
1784 if (ad_reg & lp_reg & 0x400) {
1785 pdata->phy.tx_pause = 1;
1786 pdata->phy.rx_pause = 1;
1787 } else if (ad_reg & lp_reg & 0x800) {
1788 if (ad_reg & 0x400)
1789 pdata->phy.rx_pause = 1;
1790 else if (lp_reg & 0x400)
1791 pdata->phy.tx_pause = 1;
1792 }
1793 }
1794
1795 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
1796 pdata->phy.rx_pause);
1797
1798 /* Compare Advertisement and Link Partner register 2 */
1799 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1800 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1801 if (lp_reg & 0x80)
1802 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
1803 if (lp_reg & 0x20)
1804 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
1805
1806 ad_reg &= lp_reg;
1807 if (ad_reg & 0x80)
1808 mode = XGBE_MODE_KR;
1809 else if (ad_reg & 0x20)
1810 mode = XGBE_MODE_KX_1000;
1811 else
1812 mode = XGBE_MODE_UNKNOWN;
1813
1814 /* Compare Advertisement and Link Partner register 3 */
1815 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1816 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1817 if (lp_reg & 0xc000)
1818 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
1819
1820 return (mode);
1821 }
1822
1823 static enum xgbe_mode
xgbe_phy_an_outcome(struct xgbe_prv_data * pdata)1824 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1825 {
1826 switch (pdata->an_mode) {
1827 case XGBE_AN_MODE_CL73:
1828 return (xgbe_phy_an73_outcome(pdata));
1829 case XGBE_AN_MODE_CL73_REDRV:
1830 return (xgbe_phy_an73_redrv_outcome(pdata));
1831 case XGBE_AN_MODE_CL37:
1832 return (xgbe_phy_an37_outcome(pdata));
1833 case XGBE_AN_MODE_CL37_SGMII:
1834 return (xgbe_phy_an37_sgmii_outcome(pdata));
1835 default:
1836 return (XGBE_MODE_UNKNOWN);
1837 }
1838 }
1839
1840 static void
xgbe_phy_an_advertising(struct xgbe_prv_data * pdata,struct xgbe_phy * dphy)1841 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy)
1842 {
1843 struct xgbe_phy_data *phy_data = pdata->phy_data;
1844
1845 XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);
1846
1847 /* Without a re-driver, just return current advertising */
1848 if (!phy_data->redrv)
1849 return;
1850
1851 /* With the KR re-driver we need to advertise a single speed */
1852 XGBE_CLR_ADV(dphy, 1000baseKX_Full);
1853 XGBE_CLR_ADV(dphy, 10000baseKR_Full);
1854
1855 /* Advertise FEC support is present */
1856 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1857 XGBE_SET_ADV(dphy, 10000baseR_FEC);
1858
1859 switch (phy_data->port_mode) {
1860 case XGBE_PORT_MODE_BACKPLANE:
1861 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1862 break;
1863 case XGBE_PORT_MODE_BACKPLANE_2500:
1864 XGBE_SET_ADV(dphy, 1000baseKX_Full);
1865 break;
1866 case XGBE_PORT_MODE_1000BASE_T:
1867 case XGBE_PORT_MODE_1000BASE_X:
1868 case XGBE_PORT_MODE_NBASE_T:
1869 XGBE_SET_ADV(dphy, 1000baseKX_Full);
1870 break;
1871 case XGBE_PORT_MODE_10GBASE_T:
1872 if ((phy_data->phydev) &&
1873 (pdata->phy.speed == SPEED_10000))
1874 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1875 else
1876 XGBE_SET_ADV(dphy, 1000baseKX_Full);
1877 break;
1878 case XGBE_PORT_MODE_10GBASE_R:
1879 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1880 break;
1881 case XGBE_PORT_MODE_SFP:
1882 switch (phy_data->sfp_base) {
1883 case XGBE_SFP_BASE_1000_T:
1884 case XGBE_SFP_BASE_1000_SX:
1885 case XGBE_SFP_BASE_1000_LX:
1886 case XGBE_SFP_BASE_1000_CX:
1887 XGBE_SET_ADV(dphy, 1000baseKX_Full);
1888 break;
1889 default:
1890 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1891 break;
1892 }
1893 break;
1894 default:
1895 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1896 break;
1897 }
1898 }
1899
1900 static int
xgbe_phy_an_config(struct xgbe_prv_data * pdata)1901 xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1902 {
1903 struct xgbe_phy_data *phy_data = pdata->phy_data;
1904 int ret;
1905
1906 ret = xgbe_phy_find_phy_device(pdata);
1907 if (ret)
1908 return (ret);
1909
1910 axgbe_printf(2, "%s: find_phy_device return %s.\n", __func__,
1911 ret ? "Failure" : "Success");
1912
1913 if (!phy_data->phydev)
1914 return (0);
1915
1916 ret = xgbe_phy_start_aneg(pdata);
1917 return (ret);
1918 }
1919
1920 static enum xgbe_an_mode
xgbe_phy_an_sfp_mode(struct xgbe_phy_data * phy_data)1921 xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1922 {
1923 switch (phy_data->sfp_base) {
1924 case XGBE_SFP_BASE_1000_T:
1925 return (XGBE_AN_MODE_CL37_SGMII);
1926 case XGBE_SFP_BASE_1000_SX:
1927 case XGBE_SFP_BASE_1000_LX:
1928 case XGBE_SFP_BASE_1000_CX:
1929 return (XGBE_AN_MODE_CL37);
1930 default:
1931 return (XGBE_AN_MODE_NONE);
1932 }
1933 }
1934
1935 static enum xgbe_an_mode
xgbe_phy_an_mode(struct xgbe_prv_data * pdata)1936 xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1937 {
1938 struct xgbe_phy_data *phy_data = pdata->phy_data;
1939
1940 /* A KR re-driver will always require CL73 AN */
1941 if (phy_data->redrv)
1942 return (XGBE_AN_MODE_CL73_REDRV);
1943
1944 switch (phy_data->port_mode) {
1945 case XGBE_PORT_MODE_BACKPLANE:
1946 return (XGBE_AN_MODE_CL73);
1947 case XGBE_PORT_MODE_BACKPLANE_2500:
1948 return (XGBE_AN_MODE_NONE);
1949 case XGBE_PORT_MODE_1000BASE_T:
1950 return (XGBE_AN_MODE_CL37_SGMII);
1951 case XGBE_PORT_MODE_1000BASE_X:
1952 return (XGBE_AN_MODE_CL37);
1953 case XGBE_PORT_MODE_NBASE_T:
1954 return (XGBE_AN_MODE_CL37_SGMII);
1955 case XGBE_PORT_MODE_10GBASE_T:
1956 return (XGBE_AN_MODE_CL73);
1957 case XGBE_PORT_MODE_10GBASE_R:
1958 return (XGBE_AN_MODE_NONE);
1959 case XGBE_PORT_MODE_SFP:
1960 return (xgbe_phy_an_sfp_mode(phy_data));
1961 default:
1962 return (XGBE_AN_MODE_NONE);
1963 }
1964 }
1965
1966 static int
xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1967 xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1968 enum xgbe_phy_redrv_mode mode)
1969 {
1970 struct xgbe_phy_data *phy_data = pdata->phy_data;
1971 uint16_t redrv_reg, redrv_val;
1972
1973 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1974 redrv_val = (uint16_t)mode;
1975
1976 return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1977 redrv_reg, redrv_val));
1978 }
1979
1980 static int
xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1981 xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1982 enum xgbe_phy_redrv_mode mode)
1983 {
1984 struct xgbe_phy_data *phy_data = pdata->phy_data;
1985 unsigned int redrv_reg;
1986 int ret;
1987
1988 /* Calculate the register to write */
1989 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1990
1991 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1992
1993 return (ret);
1994 }
1995
1996 static void
xgbe_phy_set_redrv_mode(struct xgbe_prv_data * pdata)1997 xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1998 {
1999 struct xgbe_phy_data *phy_data = pdata->phy_data;
2000 enum xgbe_phy_redrv_mode mode;
2001 int ret;
2002
2003 if (!phy_data->redrv)
2004 return;
2005
2006 mode = XGBE_PHY_REDRV_MODE_CX;
2007 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
2008 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
2009 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
2010 mode = XGBE_PHY_REDRV_MODE_SR;
2011
2012 ret = xgbe_phy_get_comm_ownership(pdata);
2013 if (ret)
2014 return;
2015
2016 axgbe_printf(2, "%s: redrv_if set: %d\n", __func__, phy_data->redrv_if);
2017 if (phy_data->redrv_if)
2018 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
2019 else
2020 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
2021
2022 xgbe_phy_put_comm_ownership(pdata);
2023 }
2024
2025 static void
xgbe_phy_perform_ratechange(struct xgbe_prv_data * pdata,unsigned int cmd,unsigned int sub_cmd)2026 xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, unsigned int cmd,
2027 unsigned int sub_cmd)
2028 {
2029 unsigned int s0 = 0;
2030 unsigned int wait;
2031
2032 /* Log if a previous command did not complete */
2033 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2034 axgbe_error("firmware mailbox not ready for command\n");
2035
2036 /* Construct the command */
2037 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2038 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2039
2040 /* Issue the command */
2041 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2042 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2043 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2044
2045 /* Wait for command to complete */
2046 wait = XGBE_RATECHANGE_COUNT;
2047 while (wait--) {
2048 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2049 axgbe_printf(3, "%s: Rate change done\n", __func__);
2050 return;
2051 }
2052
2053 DELAY(2000);
2054 }
2055
2056 axgbe_printf(3, "firmware mailbox command did not complete\n");
2057 }
2058
2059 static void
xgbe_phy_rrc(struct xgbe_prv_data * pdata)2060 xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2061 {
2062 /* Receiver Reset Cycle */
2063 xgbe_phy_perform_ratechange(pdata, 5, 0);
2064
2065 axgbe_printf(3, "receiver reset complete\n");
2066 }
2067
2068 static void
xgbe_phy_power_off(struct xgbe_prv_data * pdata)2069 xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2070 {
2071 struct xgbe_phy_data *phy_data = pdata->phy_data;
2072
2073 /* Power off */
2074 xgbe_phy_perform_ratechange(pdata, 0, 0);
2075
2076 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2077
2078 axgbe_printf(3, "phy powered off\n");
2079 }
2080
2081 static void
xgbe_phy_sfi_mode(struct xgbe_prv_data * pdata)2082 xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2083 {
2084 struct xgbe_phy_data *phy_data = pdata->phy_data;
2085
2086 xgbe_phy_set_redrv_mode(pdata);
2087
2088 /* 10G/SFI */
2089 axgbe_printf(3, "%s: cable %d len %d\n", __func__, phy_data->sfp_cable,
2090 phy_data->sfp_cable_len);
2091
2092 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE)
2093 xgbe_phy_perform_ratechange(pdata, 3, 0);
2094 else {
2095 if (phy_data->sfp_cable_len <= 1)
2096 xgbe_phy_perform_ratechange(pdata, 3, 1);
2097 else if (phy_data->sfp_cable_len <= 3)
2098 xgbe_phy_perform_ratechange(pdata, 3, 2);
2099 else
2100 xgbe_phy_perform_ratechange(pdata, 3, 3);
2101 }
2102
2103 phy_data->cur_mode = XGBE_MODE_SFI;
2104
2105 axgbe_printf(3, "10GbE SFI mode set\n");
2106 }
2107
2108 static void
xgbe_phy_x_mode(struct xgbe_prv_data * pdata)2109 xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2110 {
2111 struct xgbe_phy_data *phy_data = pdata->phy_data;
2112
2113 xgbe_phy_set_redrv_mode(pdata);
2114
2115 /* 1G/X */
2116 xgbe_phy_perform_ratechange(pdata, 1, 3);
2117
2118 phy_data->cur_mode = XGBE_MODE_X;
2119
2120 axgbe_printf(3, "1GbE X mode set\n");
2121 }
2122
2123 static void
xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data * pdata)2124 xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2125 {
2126 struct xgbe_phy_data *phy_data = pdata->phy_data;
2127
2128 xgbe_phy_set_redrv_mode(pdata);
2129
2130 /* 1G/SGMII */
2131 xgbe_phy_perform_ratechange(pdata, 1, 2);
2132
2133 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2134
2135 axgbe_printf(2, "1GbE SGMII mode set\n");
2136 }
2137
2138 static void
xgbe_phy_sgmii_100_mode(struct xgbe_prv_data * pdata)2139 xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2140 {
2141 struct xgbe_phy_data *phy_data = pdata->phy_data;
2142
2143 xgbe_phy_set_redrv_mode(pdata);
2144
2145 /* 100M/SGMII */
2146 xgbe_phy_perform_ratechange(pdata, 1, 1);
2147
2148 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2149
2150 axgbe_printf(3, "100MbE SGMII mode set\n");
2151 }
2152
2153 static void
xgbe_phy_kr_mode(struct xgbe_prv_data * pdata)2154 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2155 {
2156 struct xgbe_phy_data *phy_data = pdata->phy_data;
2157
2158 xgbe_phy_set_redrv_mode(pdata);
2159
2160 /* 10G/KR */
2161 xgbe_phy_perform_ratechange(pdata, 4, 0);
2162
2163 phy_data->cur_mode = XGBE_MODE_KR;
2164
2165 axgbe_printf(3, "10GbE KR mode set\n");
2166 }
2167
2168 static void
xgbe_phy_kx_2500_mode(struct xgbe_prv_data * pdata)2169 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2170 {
2171 struct xgbe_phy_data *phy_data = pdata->phy_data;
2172
2173 xgbe_phy_set_redrv_mode(pdata);
2174
2175 /* 2.5G/KX */
2176 xgbe_phy_perform_ratechange(pdata, 2, 0);
2177
2178 phy_data->cur_mode = XGBE_MODE_KX_2500;
2179
2180 axgbe_printf(3, "2.5GbE KX mode set\n");
2181 }
2182
2183 static void
xgbe_phy_kx_1000_mode(struct xgbe_prv_data * pdata)2184 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2185 {
2186 struct xgbe_phy_data *phy_data = pdata->phy_data;
2187
2188 xgbe_phy_set_redrv_mode(pdata);
2189
2190 /* 1G/KX */
2191 xgbe_phy_perform_ratechange(pdata, 1, 3);
2192
2193 phy_data->cur_mode = XGBE_MODE_KX_1000;
2194
2195 axgbe_printf(3, "1GbE KX mode set\n");
2196 }
2197
2198 static enum xgbe_mode
xgbe_phy_cur_mode(struct xgbe_prv_data * pdata)2199 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2200 {
2201 struct xgbe_phy_data *phy_data = pdata->phy_data;
2202
2203 return (phy_data->cur_mode);
2204 }
2205
2206 static enum xgbe_mode
xgbe_phy_switch_baset_mode(struct xgbe_prv_data * pdata)2207 xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2208 {
2209 struct xgbe_phy_data *phy_data = pdata->phy_data;
2210
2211 /* No switching if not 10GBase-T */
2212 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2213 return (xgbe_phy_cur_mode(pdata));
2214
2215 switch (xgbe_phy_cur_mode(pdata)) {
2216 case XGBE_MODE_SGMII_100:
2217 case XGBE_MODE_SGMII_1000:
2218 return (XGBE_MODE_KR);
2219 case XGBE_MODE_KR:
2220 default:
2221 return (XGBE_MODE_SGMII_1000);
2222 }
2223 }
2224
2225 static enum xgbe_mode
xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data * pdata)2226 xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2227 {
2228 return (XGBE_MODE_KX_2500);
2229 }
2230
2231 static enum xgbe_mode
xgbe_phy_switch_bp_mode(struct xgbe_prv_data * pdata)2232 xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2233 {
2234 /* If we are in KR switch to KX, and vice-versa */
2235 switch (xgbe_phy_cur_mode(pdata)) {
2236 case XGBE_MODE_KX_1000:
2237 return (XGBE_MODE_KR);
2238 case XGBE_MODE_KR:
2239 default:
2240 return (XGBE_MODE_KX_1000);
2241 }
2242 }
2243
2244 static enum xgbe_mode
xgbe_phy_switch_mode(struct xgbe_prv_data * pdata)2245 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2246 {
2247 struct xgbe_phy_data *phy_data = pdata->phy_data;
2248
2249 switch (phy_data->port_mode) {
2250 case XGBE_PORT_MODE_BACKPLANE:
2251 return (xgbe_phy_switch_bp_mode(pdata));
2252 case XGBE_PORT_MODE_BACKPLANE_2500:
2253 return (xgbe_phy_switch_bp_2500_mode(pdata));
2254 case XGBE_PORT_MODE_1000BASE_T:
2255 case XGBE_PORT_MODE_NBASE_T:
2256 case XGBE_PORT_MODE_10GBASE_T:
2257 return (xgbe_phy_switch_baset_mode(pdata));
2258 case XGBE_PORT_MODE_1000BASE_X:
2259 case XGBE_PORT_MODE_10GBASE_R:
2260 case XGBE_PORT_MODE_SFP:
2261 /* No switching, so just return current mode */
2262 return (xgbe_phy_cur_mode(pdata));
2263 default:
2264 return (XGBE_MODE_UNKNOWN);
2265 }
2266 }
2267
2268 static enum xgbe_mode
xgbe_phy_get_basex_mode(struct xgbe_phy_data * phy_data,int speed)2269 xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, int speed)
2270 {
2271 switch (speed) {
2272 case SPEED_1000:
2273 return (XGBE_MODE_X);
2274 case SPEED_10000:
2275 return (XGBE_MODE_KR);
2276 default:
2277 return (XGBE_MODE_UNKNOWN);
2278 }
2279 }
2280
2281 static enum xgbe_mode
xgbe_phy_get_baset_mode(struct xgbe_phy_data * phy_data,int speed)2282 xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, int speed)
2283 {
2284 switch (speed) {
2285 case SPEED_100:
2286 return (XGBE_MODE_SGMII_100);
2287 case SPEED_1000:
2288 return (XGBE_MODE_SGMII_1000);
2289 case SPEED_2500:
2290 return (XGBE_MODE_KX_2500);
2291 case SPEED_10000:
2292 return (XGBE_MODE_KR);
2293 default:
2294 return (XGBE_MODE_UNKNOWN);
2295 }
2296 }
2297
2298 static enum xgbe_mode
xgbe_phy_get_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2299 xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
2300 {
2301 switch (speed) {
2302 case SPEED_100:
2303 return (XGBE_MODE_SGMII_100);
2304 case SPEED_1000:
2305 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2306 return (XGBE_MODE_SGMII_1000);
2307 else
2308 return (XGBE_MODE_X);
2309 case SPEED_10000:
2310 case SPEED_UNKNOWN:
2311 return (XGBE_MODE_SFI);
2312 default:
2313 return (XGBE_MODE_UNKNOWN);
2314 }
2315 }
2316
2317 static enum xgbe_mode
xgbe_phy_get_bp_2500_mode(int speed)2318 xgbe_phy_get_bp_2500_mode(int speed)
2319 {
2320 switch (speed) {
2321 case SPEED_2500:
2322 return (XGBE_MODE_KX_2500);
2323 default:
2324 return (XGBE_MODE_UNKNOWN);
2325 }
2326 }
2327
2328 static enum xgbe_mode
xgbe_phy_get_bp_mode(int speed)2329 xgbe_phy_get_bp_mode(int speed)
2330 {
2331 switch (speed) {
2332 case SPEED_1000:
2333 return (XGBE_MODE_KX_1000);
2334 case SPEED_10000:
2335 return (XGBE_MODE_KR);
2336 default:
2337 return (XGBE_MODE_UNKNOWN);
2338 }
2339 }
2340
2341 static enum xgbe_mode
xgbe_phy_get_mode(struct xgbe_prv_data * pdata,int speed)2342 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed)
2343 {
2344 struct xgbe_phy_data *phy_data = pdata->phy_data;
2345
2346 switch (phy_data->port_mode) {
2347 case XGBE_PORT_MODE_BACKPLANE:
2348 return (xgbe_phy_get_bp_mode(speed));
2349 case XGBE_PORT_MODE_BACKPLANE_2500:
2350 return (xgbe_phy_get_bp_2500_mode(speed));
2351 case XGBE_PORT_MODE_1000BASE_T:
2352 case XGBE_PORT_MODE_NBASE_T:
2353 case XGBE_PORT_MODE_10GBASE_T:
2354 return (xgbe_phy_get_baset_mode(phy_data, speed));
2355 case XGBE_PORT_MODE_1000BASE_X:
2356 case XGBE_PORT_MODE_10GBASE_R:
2357 return (xgbe_phy_get_basex_mode(phy_data, speed));
2358 case XGBE_PORT_MODE_SFP:
2359 return (xgbe_phy_get_sfp_mode(phy_data, speed));
2360 default:
2361 return (XGBE_MODE_UNKNOWN);
2362 }
2363 }
2364
2365 static void
xgbe_phy_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2366 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2367 {
2368 switch (mode) {
2369 case XGBE_MODE_KX_1000:
2370 xgbe_phy_kx_1000_mode(pdata);
2371 break;
2372 case XGBE_MODE_KX_2500:
2373 xgbe_phy_kx_2500_mode(pdata);
2374 break;
2375 case XGBE_MODE_KR:
2376 xgbe_phy_kr_mode(pdata);
2377 break;
2378 case XGBE_MODE_SGMII_100:
2379 xgbe_phy_sgmii_100_mode(pdata);
2380 break;
2381 case XGBE_MODE_SGMII_1000:
2382 xgbe_phy_sgmii_1000_mode(pdata);
2383 break;
2384 case XGBE_MODE_X:
2385 xgbe_phy_x_mode(pdata);
2386 break;
2387 case XGBE_MODE_SFI:
2388 xgbe_phy_sfi_mode(pdata);
2389 break;
2390 default:
2391 break;
2392 }
2393 }
2394
2395 static void
xgbe_phy_get_type(struct xgbe_prv_data * pdata,struct ifmediareq * ifmr)2396 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr)
2397 {
2398 struct xgbe_phy_data *phy_data = pdata->phy_data;
2399
2400 switch (pdata->phy.speed) {
2401 case SPEED_10000:
2402 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2403 ifmr->ifm_active |= IFM_10G_KR;
2404 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T)
2405 ifmr->ifm_active |= IFM_10G_T;
2406 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R)
2407 ifmr->ifm_active |= IFM_10G_KR;
2408 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2409 ifmr->ifm_active |= IFM_10G_SFI;
2410 else
2411 ifmr->ifm_active |= IFM_OTHER;
2412 break;
2413 case SPEED_2500:
2414 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE_2500)
2415 ifmr->ifm_active |= IFM_2500_KX;
2416 else
2417 ifmr->ifm_active |= IFM_OTHER;
2418 break;
2419 case SPEED_1000:
2420 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2421 ifmr->ifm_active |= IFM_1000_KX;
2422 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_T)
2423 ifmr->ifm_active |= IFM_1000_T;
2424 #if 0
2425 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X)
2426 ifmr->ifm_active |= IFM_1000_SX;
2427 ifmr->ifm_active |= IFM_1000_LX;
2428 ifmr->ifm_active |= IFM_1000_CX;
2429 #endif
2430 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2431 ifmr->ifm_active |= IFM_1000_SGMII;
2432 else
2433 ifmr->ifm_active |= IFM_OTHER;
2434 break;
2435 case SPEED_100:
2436 if(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T)
2437 ifmr->ifm_active |= IFM_100_T;
2438 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2439 ifmr->ifm_active |= IFM_1000_SGMII;
2440 else
2441 ifmr->ifm_active |= IFM_OTHER;
2442 break;
2443 default:
2444 ifmr->ifm_active |= IFM_OTHER;
2445 axgbe_printf(1, "Unknown mode detected\n");
2446 break;
2447 }
2448 }
2449
2450 static bool
xgbe_phy_check_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode,bool advert)2451 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode,
2452 bool advert)
2453 {
2454
2455 if (pdata->phy.autoneg == AUTONEG_ENABLE)
2456 return (advert);
2457 else {
2458 enum xgbe_mode cur_mode;
2459
2460 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2461 if (cur_mode == mode)
2462 return (true);
2463 }
2464
2465 return (false);
2466 }
2467
2468 static bool
xgbe_phy_use_basex_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2469 xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2470 {
2471
2472 switch (mode) {
2473 case XGBE_MODE_X:
2474 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2475 1000baseX_Full)));
2476 case XGBE_MODE_KR:
2477 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2478 10000baseKR_Full)));
2479 default:
2480 return (false);
2481 }
2482 }
2483
2484 static bool
xgbe_phy_use_baset_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2485 xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2486 {
2487
2488 axgbe_printf(3, "%s: check mode %d\n", __func__, mode);
2489 switch (mode) {
2490 case XGBE_MODE_SGMII_100:
2491 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2492 100baseT_Full)));
2493 case XGBE_MODE_SGMII_1000:
2494 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2495 1000baseT_Full)));
2496 case XGBE_MODE_KX_2500:
2497 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2498 2500baseT_Full)));
2499 case XGBE_MODE_KR:
2500 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2501 10000baseT_Full)));
2502 default:
2503 return (false);
2504 }
2505 }
2506
2507 static bool
xgbe_phy_use_sfp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2508 xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2509 {
2510 struct xgbe_phy_data *phy_data = pdata->phy_data;
2511
2512 switch (mode) {
2513 case XGBE_MODE_X:
2514 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2515 return (false);
2516 return (xgbe_phy_check_mode(pdata, mode,
2517 XGBE_ADV(&pdata->phy, 1000baseX_Full)));
2518 case XGBE_MODE_SGMII_100:
2519 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2520 return (false);
2521 return (xgbe_phy_check_mode(pdata, mode,
2522 XGBE_ADV(&pdata->phy, 100baseT_Full)));
2523 case XGBE_MODE_SGMII_1000:
2524 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2525 return (false);
2526 return (xgbe_phy_check_mode(pdata, mode,
2527 XGBE_ADV(&pdata->phy, 1000baseT_Full)));
2528 case XGBE_MODE_SFI:
2529 if (phy_data->sfp_mod_absent)
2530 return (true);
2531 return (xgbe_phy_check_mode(pdata, mode,
2532 XGBE_ADV(&pdata->phy, 10000baseSR_Full) ||
2533 XGBE_ADV(&pdata->phy, 10000baseLR_Full) ||
2534 XGBE_ADV(&pdata->phy, 10000baseLRM_Full) ||
2535 XGBE_ADV(&pdata->phy, 10000baseER_Full) ||
2536 XGBE_ADV(&pdata->phy, 10000baseCR_Full)));
2537 default:
2538 return (false);
2539 }
2540 }
2541
2542 static bool
xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2543 xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2544 {
2545
2546 switch (mode) {
2547 case XGBE_MODE_KX_2500:
2548 return (xgbe_phy_check_mode(pdata, mode,
2549 XGBE_ADV(&pdata->phy, 2500baseX_Full)));
2550 default:
2551 return (false);
2552 }
2553 }
2554
2555 static bool
xgbe_phy_use_bp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2556 xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2557 {
2558
2559 switch (mode) {
2560 case XGBE_MODE_KX_1000:
2561 return (xgbe_phy_check_mode(pdata, mode,
2562 XGBE_ADV(&pdata->phy, 1000baseKX_Full)));
2563 case XGBE_MODE_KR:
2564 return (xgbe_phy_check_mode(pdata, mode,
2565 XGBE_ADV(&pdata->phy, 10000baseKR_Full)));
2566 default:
2567 return (false);
2568 }
2569 }
2570
2571 static bool
xgbe_phy_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2572 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2573 {
2574 struct xgbe_phy_data *phy_data = pdata->phy_data;
2575
2576 switch (phy_data->port_mode) {
2577 case XGBE_PORT_MODE_BACKPLANE:
2578 return (xgbe_phy_use_bp_mode(pdata, mode));
2579 case XGBE_PORT_MODE_BACKPLANE_2500:
2580 return (xgbe_phy_use_bp_2500_mode(pdata, mode));
2581 case XGBE_PORT_MODE_1000BASE_T:
2582 axgbe_printf(3, "use_mode %s\n",
2583 xgbe_phy_use_baset_mode(pdata, mode) ? "found" : "Not found");
2584 case XGBE_PORT_MODE_NBASE_T:
2585 case XGBE_PORT_MODE_10GBASE_T:
2586 return (xgbe_phy_use_baset_mode(pdata, mode));
2587 case XGBE_PORT_MODE_1000BASE_X:
2588 case XGBE_PORT_MODE_10GBASE_R:
2589 return (xgbe_phy_use_basex_mode(pdata, mode));
2590 case XGBE_PORT_MODE_SFP:
2591 return (xgbe_phy_use_sfp_mode(pdata, mode));
2592 default:
2593 return (false);
2594 }
2595 }
2596
2597 static bool
xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data * phy_data,int speed)2598 xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, int speed)
2599 {
2600
2601 switch (speed) {
2602 case SPEED_1000:
2603 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2604 case SPEED_10000:
2605 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2606 default:
2607 return (false);
2608 }
2609 }
2610
2611 static bool
xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data * phy_data,int speed)2612 xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, int speed)
2613 {
2614
2615 switch (speed) {
2616 case SPEED_100:
2617 case SPEED_1000:
2618 return (true);
2619 case SPEED_2500:
2620 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2621 case SPEED_10000:
2622 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2623 default:
2624 return (false);
2625 }
2626 }
2627
2628 static bool
xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2629 xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
2630 {
2631
2632 switch (speed) {
2633 case SPEED_100:
2634 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2635 case SPEED_1000:
2636 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2637 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2638 case SPEED_10000:
2639 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2640 default:
2641 return (false);
2642 }
2643 }
2644
2645 static bool
xgbe_phy_valid_speed_bp_2500_mode(int speed)2646 xgbe_phy_valid_speed_bp_2500_mode(int speed)
2647 {
2648
2649 switch (speed) {
2650 case SPEED_2500:
2651 return (true);
2652 default:
2653 return (false);
2654 }
2655 }
2656
2657 static bool
xgbe_phy_valid_speed_bp_mode(int speed)2658 xgbe_phy_valid_speed_bp_mode(int speed)
2659 {
2660
2661 switch (speed) {
2662 case SPEED_1000:
2663 case SPEED_10000:
2664 return (true);
2665 default:
2666 return (false);
2667 }
2668 }
2669
2670 static bool
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)2671 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2672 {
2673 struct xgbe_phy_data *phy_data = pdata->phy_data;
2674
2675 switch (phy_data->port_mode) {
2676 case XGBE_PORT_MODE_BACKPLANE:
2677 return (xgbe_phy_valid_speed_bp_mode(speed));
2678 case XGBE_PORT_MODE_BACKPLANE_2500:
2679 return (xgbe_phy_valid_speed_bp_2500_mode(speed));
2680 case XGBE_PORT_MODE_1000BASE_T:
2681 case XGBE_PORT_MODE_NBASE_T:
2682 case XGBE_PORT_MODE_10GBASE_T:
2683 return (xgbe_phy_valid_speed_baset_mode(phy_data, speed));
2684 case XGBE_PORT_MODE_1000BASE_X:
2685 case XGBE_PORT_MODE_10GBASE_R:
2686 return (xgbe_phy_valid_speed_basex_mode(phy_data, speed));
2687 case XGBE_PORT_MODE_SFP:
2688 return (xgbe_phy_valid_speed_sfp_mode(phy_data, speed));
2689 default:
2690 return (false);
2691 }
2692 }
2693
2694 static int
xgbe_upd_link(struct xgbe_prv_data * pdata)2695 xgbe_upd_link(struct xgbe_prv_data *pdata)
2696 {
2697 int reg;
2698
2699 axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);
2700 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2701 if (reg < 0)
2702 return (reg);
2703
2704 if ((reg & BMSR_LINK) == 0)
2705 pdata->phy.link = 0;
2706 else
2707 pdata->phy.link = 1;
2708
2709 axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg);
2710 return (0);
2711 }
2712
2713 static int
xgbe_phy_read_status(struct xgbe_prv_data * pdata)2714 xgbe_phy_read_status(struct xgbe_prv_data *pdata)
2715 {
2716 int common_adv_gb = 0;
2717 int common_adv;
2718 int lpagb = 0;
2719 int adv, lpa;
2720 int ret;
2721
2722 ret = xgbe_upd_link(pdata);
2723 if (ret) {
2724 axgbe_printf(2, "Link Update return %d\n", ret);
2725 return (ret);
2726 }
2727
2728 if (AUTONEG_ENABLE == pdata->phy.autoneg) {
2729 if (pdata->phy.supported == SUPPORTED_1000baseT_Half ||
2730 pdata->phy.supported == SUPPORTED_1000baseT_Full) {
2731 lpagb = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
2732 MII_100T2SR);
2733 if (lpagb < 0)
2734 return (lpagb);
2735
2736 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
2737 MII_100T2CR);
2738 if (adv < 0)
2739 return (adv);
2740
2741 if (lpagb & GTSR_MAN_MS_FLT) {
2742 if (adv & GTCR_MAN_MS)
2743 axgbe_printf(2, "Master/Slave Resolution "
2744 "failed, maybe conflicting manual settings\n");
2745 else
2746 axgbe_printf(2, "Master/Slave Resolution failed\n");
2747 return (-ENOLINK);
2748 }
2749
2750 if (pdata->phy.supported == SUPPORTED_1000baseT_Half)
2751 XGBE_SET_ADV(&pdata->phy, 1000baseT_Half);
2752 else if (pdata->phy.supported == SUPPORTED_1000baseT_Full)
2753 XGBE_SET_ADV(&pdata->phy, 1000baseT_Full);
2754
2755 common_adv_gb = lpagb & adv << 2;
2756 }
2757
2758 lpa = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANLPAR);
2759 if (lpa < 0)
2760 return (lpa);
2761
2762 if (pdata->phy.supported == SUPPORTED_Autoneg)
2763 XGBE_SET_ADV(&pdata->phy, Autoneg);
2764
2765 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANAR);
2766 if (adv < 0)
2767 return (adv);
2768
2769 common_adv = lpa & adv;
2770
2771 pdata->phy.speed = SPEED_10;
2772 pdata->phy.duplex = DUPLEX_HALF;
2773 pdata->phy.pause = 0;
2774 pdata->phy.asym_pause = 0;
2775
2776 axgbe_printf(2, "%s: lpa %#x adv %#x common_adv_gb %#x "
2777 "common_adv %#x\n", __func__, lpa, adv, common_adv_gb,
2778 common_adv);
2779 if (common_adv_gb & (GTSR_LP_1000TFDX | GTSR_LP_1000THDX)) {
2780 axgbe_printf(2, "%s: SPEED 1000\n", __func__);
2781 pdata->phy.speed = SPEED_1000;
2782
2783 if (common_adv_gb & GTSR_LP_1000TFDX)
2784 pdata->phy.duplex = DUPLEX_FULL;
2785 } else if (common_adv & (ANLPAR_TX_FD | ANLPAR_TX)) {
2786 axgbe_printf(2, "%s: SPEED 100\n", __func__);
2787 pdata->phy.speed = SPEED_100;
2788
2789 if (common_adv & ANLPAR_TX_FD)
2790 pdata->phy.duplex = DUPLEX_FULL;
2791 } else
2792 if (common_adv & ANLPAR_10_FD)
2793 pdata->phy.duplex = DUPLEX_FULL;
2794
2795 if (pdata->phy.duplex == DUPLEX_FULL) {
2796 pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0;
2797 pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
2798 }
2799 } else {
2800 int bmcr = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
2801 if (bmcr < 0)
2802 return (bmcr);
2803
2804 if (bmcr & BMCR_FDX)
2805 pdata->phy.duplex = DUPLEX_FULL;
2806 else
2807 pdata->phy.duplex = DUPLEX_HALF;
2808
2809 if (bmcr & BMCR_SPEED1)
2810 pdata->phy.speed = SPEED_1000;
2811 else if (bmcr & BMCR_SPEED100)
2812 pdata->phy.speed = SPEED_100;
2813 else
2814 pdata->phy.speed = SPEED_10;
2815
2816 pdata->phy.pause = 0;
2817 pdata->phy.asym_pause = 0;
2818 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x "
2819 "autoneg %#x\n", __func__, pdata->phy.speed,
2820 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
2821 }
2822
2823 return (0);
2824 }
2825
2826 static int
xgbe_phy_link_status(struct xgbe_prv_data * pdata,int * an_restart)2827 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2828 {
2829 struct xgbe_phy_data *phy_data = pdata->phy_data;
2830 struct mii_data *mii = NULL;
2831 unsigned int reg;
2832 int ret;
2833
2834 *an_restart = 0;
2835
2836 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2837 /* Check SFP signals */
2838 axgbe_printf(3, "%s: calling phy detect\n", __func__);
2839 xgbe_phy_sfp_detect(pdata);
2840
2841 if (phy_data->sfp_changed) {
2842 axgbe_printf(1, "%s: SFP changed observed\n", __func__);
2843 *an_restart = 1;
2844 return (0);
2845 }
2846
2847 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
2848 axgbe_printf(1, "%s: SFP absent 0x%x & sfp_rx_los 0x%x\n",
2849 __func__, phy_data->sfp_mod_absent,
2850 phy_data->sfp_rx_los);
2851 return (0);
2852 }
2853 } else {
2854 mii = device_get_softc(pdata->axgbe_miibus);
2855 mii_tick(mii);
2856
2857 ret = xgbe_phy_read_status(pdata);
2858 if (ret) {
2859 axgbe_printf(2, "Link: Read status returned %d\n", ret);
2860 return (ret);
2861 }
2862
2863 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x "
2864 "autoneg %#x\n", __func__, pdata->phy.speed,
2865 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
2866 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2867 ret = (ret < 0) ? ret : (ret & BMSR_ACOMP);
2868 axgbe_printf(2, "Link: BMCR returned %d\n", ret);
2869 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret)
2870 return (0);
2871
2872 return (pdata->phy.link);
2873 }
2874
2875 /* Link status is latched low, so read once to clear
2876 * and then read again to get current state
2877 */
2878 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2879 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2880 axgbe_printf(1, "%s: link_status reg: 0x%x\n", __func__, reg);
2881 if (reg & MDIO_STAT1_LSTATUS)
2882 return (1);
2883
2884 /* No link, attempt a receiver reset cycle */
2885 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2886 axgbe_printf(1, "ENTERED RRC: rrc_count: %d\n",
2887 phy_data->rrc_count);
2888 phy_data->rrc_count = 0;
2889 if (pdata->link_workaround) {
2890 ret = xgbe_phy_reset(pdata);
2891 if (ret)
2892 axgbe_error("Error resetting phy\n");
2893 } else
2894 xgbe_phy_rrc(pdata);
2895 }
2896
2897 return (0);
2898 }
2899
2900 static void
xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data * pdata)2901 xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2902 {
2903 struct xgbe_phy_data *phy_data = pdata->phy_data;
2904
2905 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2906 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR);
2907 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2908 GPIO_MASK);
2909 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2910 GPIO_RX_LOS);
2911 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2912 GPIO_TX_FAULT);
2913 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2914 GPIO_MOD_ABS);
2915 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2916 GPIO_RATE_SELECT);
2917
2918 DBGPR("SFP: gpio_address=%#x\n", phy_data->sfp_gpio_address);
2919 DBGPR("SFP: gpio_mask=%#x\n", phy_data->sfp_gpio_mask);
2920 DBGPR("SFP: gpio_rx_los=%u\n", phy_data->sfp_gpio_rx_los);
2921 DBGPR("SFP: gpio_tx_fault=%u\n", phy_data->sfp_gpio_tx_fault);
2922 DBGPR("SFP: gpio_mod_absent=%u\n",
2923 phy_data->sfp_gpio_mod_absent);
2924 DBGPR("SFP: gpio_rate_select=%u\n",
2925 phy_data->sfp_gpio_rate_select);
2926 }
2927
2928 static void
xgbe_phy_sfp_comm_setup(struct xgbe_prv_data * pdata)2929 xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2930 {
2931 struct xgbe_phy_data *phy_data = pdata->phy_data;
2932 unsigned int mux_addr_hi, mux_addr_lo;
2933
2934 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2935 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2936 if (mux_addr_lo == XGBE_SFP_DIRECT)
2937 return;
2938
2939 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2940 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2941 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2942 MUX_CHAN);
2943
2944 DBGPR("SFP: mux_address=%#x\n", phy_data->sfp_mux_address);
2945 DBGPR("SFP: mux_channel=%u\n", phy_data->sfp_mux_channel);
2946 }
2947
2948 static void
xgbe_phy_sfp_setup(struct xgbe_prv_data * pdata)2949 xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2950 {
2951 xgbe_phy_sfp_comm_setup(pdata);
2952 xgbe_phy_sfp_gpio_setup(pdata);
2953 }
2954
2955 static int
xgbe_phy_int_mdio_reset(struct xgbe_prv_data * pdata)2956 xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2957 {
2958 struct xgbe_phy_data *phy_data = pdata->phy_data;
2959 unsigned int ret;
2960
2961 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2962 if (ret)
2963 return (ret);
2964
2965 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2966
2967 return (ret);
2968 }
2969
2970 static int
xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data * pdata)2971 xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2972 {
2973 struct xgbe_phy_data *phy_data = pdata->phy_data;
2974 uint8_t gpio_reg, gpio_ports[2], gpio_data[3];
2975 int ret;
2976
2977 /* Read the output port registers */
2978 gpio_reg = 2;
2979 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2980 &gpio_reg, sizeof(gpio_reg),
2981 gpio_ports, sizeof(gpio_ports));
2982 if (ret)
2983 return (ret);
2984
2985 /* Prepare to write the GPIO data */
2986 gpio_data[0] = 2;
2987 gpio_data[1] = gpio_ports[0];
2988 gpio_data[2] = gpio_ports[1];
2989
2990 /* Set the GPIO pin */
2991 if (phy_data->mdio_reset_gpio < 8)
2992 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2993 else
2994 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2995
2996 /* Write the output port registers */
2997 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2998 gpio_data, sizeof(gpio_data));
2999 if (ret)
3000 return (ret);
3001
3002 /* Clear the GPIO pin */
3003 if (phy_data->mdio_reset_gpio < 8)
3004 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3005 else
3006 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3007
3008 /* Write the output port registers */
3009 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3010 gpio_data, sizeof(gpio_data));
3011
3012 return (ret);
3013 }
3014
3015 static int
xgbe_phy_mdio_reset(struct xgbe_prv_data * pdata)3016 xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
3017 {
3018 struct xgbe_phy_data *phy_data = pdata->phy_data;
3019 int ret;
3020
3021 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3022 return (0);
3023
3024 ret = xgbe_phy_get_comm_ownership(pdata);
3025 if (ret)
3026 return (ret);
3027
3028 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
3029 ret = xgbe_phy_i2c_mdio_reset(pdata);
3030 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3031 ret = xgbe_phy_int_mdio_reset(pdata);
3032
3033 xgbe_phy_put_comm_ownership(pdata);
3034
3035 return (ret);
3036 }
3037
3038 static bool
xgbe_phy_redrv_error(struct xgbe_phy_data * phy_data)3039 xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
3040 {
3041 if (!phy_data->redrv)
3042 return (false);
3043
3044 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
3045 return (true);
3046
3047 switch (phy_data->redrv_model) {
3048 case XGBE_PHY_REDRV_MODEL_4223:
3049 if (phy_data->redrv_lane > 3)
3050 return (true);
3051 break;
3052 case XGBE_PHY_REDRV_MODEL_4227:
3053 if (phy_data->redrv_lane > 1)
3054 return (true);
3055 break;
3056 default:
3057 return (true);
3058 }
3059
3060 return (false);
3061 }
3062
3063 static int
xgbe_phy_mdio_reset_setup(struct xgbe_prv_data * pdata)3064 xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
3065 {
3066 struct xgbe_phy_data *phy_data = pdata->phy_data;
3067
3068 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3069 return (0);
3070
3071 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3072 switch (phy_data->mdio_reset) {
3073 case XGBE_MDIO_RESET_NONE:
3074 case XGBE_MDIO_RESET_I2C_GPIO:
3075 case XGBE_MDIO_RESET_INT_GPIO:
3076 break;
3077 default:
3078 axgbe_error("unsupported MDIO reset (%#x)\n",
3079 phy_data->mdio_reset);
3080 return (-EINVAL);
3081 }
3082
3083 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3084 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3085 XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR);
3086 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3087 MDIO_RESET_I2C_GPIO);
3088 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3089 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3090 MDIO_RESET_INT_GPIO);
3091
3092 return (0);
3093 }
3094
3095 static bool
xgbe_phy_port_mode_mismatch(struct xgbe_prv_data * pdata)3096 xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
3097 {
3098 struct xgbe_phy_data *phy_data = pdata->phy_data;
3099
3100 switch (phy_data->port_mode) {
3101 case XGBE_PORT_MODE_BACKPLANE:
3102 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3103 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3104 return (false);
3105 break;
3106 case XGBE_PORT_MODE_BACKPLANE_2500:
3107 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3108 return (false);
3109 break;
3110 case XGBE_PORT_MODE_1000BASE_T:
3111 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3112 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3113 return (false);
3114 break;
3115 case XGBE_PORT_MODE_1000BASE_X:
3116 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3117 return (false);
3118 break;
3119 case XGBE_PORT_MODE_NBASE_T:
3120 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3121 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3122 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3123 return (false);
3124 break;
3125 case XGBE_PORT_MODE_10GBASE_T:
3126 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3127 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3128 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3129 return (false);
3130 break;
3131 case XGBE_PORT_MODE_10GBASE_R:
3132 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3133 return (false);
3134 break;
3135 case XGBE_PORT_MODE_SFP:
3136 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3137 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3138 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3139 return (false);
3140 break;
3141 default:
3142 break;
3143 }
3144
3145 return (true);
3146 }
3147
3148 static bool
xgbe_phy_conn_type_mismatch(struct xgbe_prv_data * pdata)3149 xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
3150 {
3151 struct xgbe_phy_data *phy_data = pdata->phy_data;
3152
3153 switch (phy_data->port_mode) {
3154 case XGBE_PORT_MODE_BACKPLANE:
3155 case XGBE_PORT_MODE_BACKPLANE_2500:
3156 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3157 return (false);
3158 break;
3159 case XGBE_PORT_MODE_1000BASE_T:
3160 case XGBE_PORT_MODE_1000BASE_X:
3161 case XGBE_PORT_MODE_NBASE_T:
3162 case XGBE_PORT_MODE_10GBASE_T:
3163 case XGBE_PORT_MODE_10GBASE_R:
3164 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3165 return (false);
3166 break;
3167 case XGBE_PORT_MODE_SFP:
3168 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3169 return (false);
3170 break;
3171 default:
3172 break;
3173 }
3174
3175 return (true);
3176 }
3177
3178 static bool
xgbe_phy_port_enabled(struct xgbe_prv_data * pdata)3179 xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
3180 {
3181
3182 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3183 return (false);
3184 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3185 return (false);
3186
3187 return (true);
3188 }
3189
3190 static void
xgbe_phy_cdr_track(struct xgbe_prv_data * pdata)3191 xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
3192 {
3193 struct xgbe_phy_data *phy_data = pdata->phy_data;
3194
3195 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n",
3196 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3197
3198 if (!pdata->sysctl_an_cdr_workaround)
3199 return;
3200
3201 if (!phy_data->phy_cdr_notrack)
3202 return;
3203
3204 DELAY(phy_data->phy_cdr_delay + 500);
3205
3206 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3207 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_ON);
3208
3209 phy_data->phy_cdr_notrack = 0;
3210
3211 axgbe_printf(2, "CDR TRACK DONE\n");
3212 }
3213
3214 static void
xgbe_phy_cdr_notrack(struct xgbe_prv_data * pdata)3215 xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
3216 {
3217 struct xgbe_phy_data *phy_data = pdata->phy_data;
3218
3219 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n",
3220 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3221
3222 if (!pdata->sysctl_an_cdr_workaround)
3223 return;
3224
3225 if (phy_data->phy_cdr_notrack)
3226 return;
3227
3228 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3229 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_OFF);
3230
3231 xgbe_phy_rrc(pdata);
3232
3233 phy_data->phy_cdr_notrack = 1;
3234 }
3235
3236 static void
xgbe_phy_kr_training_post(struct xgbe_prv_data * pdata)3237 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3238 {
3239 if (!pdata->sysctl_an_cdr_track_early)
3240 xgbe_phy_cdr_track(pdata);
3241 }
3242
3243 static void
xgbe_phy_kr_training_pre(struct xgbe_prv_data * pdata)3244 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3245 {
3246 if (pdata->sysctl_an_cdr_track_early)
3247 xgbe_phy_cdr_track(pdata);
3248 }
3249
3250 static void
xgbe_phy_an_post(struct xgbe_prv_data * pdata)3251 xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3252 {
3253 struct xgbe_phy_data *phy_data = pdata->phy_data;
3254
3255 switch (pdata->an_mode) {
3256 case XGBE_AN_MODE_CL73:
3257 case XGBE_AN_MODE_CL73_REDRV:
3258 if (phy_data->cur_mode != XGBE_MODE_KR)
3259 break;
3260
3261 xgbe_phy_cdr_track(pdata);
3262
3263 switch (pdata->an_result) {
3264 case XGBE_AN_READY:
3265 case XGBE_AN_COMPLETE:
3266 break;
3267 default:
3268 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3269 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3270 else
3271 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3272 break;
3273 }
3274 break;
3275 default:
3276 break;
3277 }
3278 }
3279
3280 static void
xgbe_phy_an_pre(struct xgbe_prv_data * pdata)3281 xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3282 {
3283 struct xgbe_phy_data *phy_data = pdata->phy_data;
3284
3285 switch (pdata->an_mode) {
3286 case XGBE_AN_MODE_CL73:
3287 case XGBE_AN_MODE_CL73_REDRV:
3288 if (phy_data->cur_mode != XGBE_MODE_KR)
3289 break;
3290
3291 xgbe_phy_cdr_notrack(pdata);
3292 break;
3293 default:
3294 break;
3295 }
3296 }
3297
3298 static void
xgbe_phy_stop(struct xgbe_prv_data * pdata)3299 xgbe_phy_stop(struct xgbe_prv_data *pdata)
3300 {
3301 struct xgbe_phy_data *phy_data = pdata->phy_data;
3302
3303 /* If we have an external PHY, free it */
3304 xgbe_phy_free_phy_device(pdata);
3305
3306 /* Reset SFP data */
3307 xgbe_phy_sfp_reset(phy_data);
3308 xgbe_phy_sfp_mod_absent(pdata);
3309
3310 /* Reset CDR support */
3311 xgbe_phy_cdr_track(pdata);
3312
3313 /* Power off the PHY */
3314 xgbe_phy_power_off(pdata);
3315
3316 /* Stop the I2C controller */
3317 pdata->i2c_if.i2c_stop(pdata);
3318 }
3319
3320 static int
xgbe_phy_start(struct xgbe_prv_data * pdata)3321 xgbe_phy_start(struct xgbe_prv_data *pdata)
3322 {
3323 struct xgbe_phy_data *phy_data = pdata->phy_data;
3324 int ret;
3325
3326 axgbe_printf(2, "%s: redrv %d redrv_if %d start_mode %d\n", __func__,
3327 phy_data->redrv, phy_data->redrv_if, phy_data->start_mode);
3328
3329 /* Start the I2C controller */
3330 ret = pdata->i2c_if.i2c_start(pdata);
3331 if (ret) {
3332 axgbe_error("%s: impl i2c start ret %d\n", __func__, ret);
3333 return (ret);
3334 }
3335
3336 /* Set the proper MDIO mode for the re-driver */
3337 if (phy_data->redrv && !phy_data->redrv_if) {
3338 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3339 XGBE_MDIO_MODE_CL22);
3340 if (ret) {
3341 axgbe_error("redriver mdio port not compatible (%u)\n",
3342 phy_data->redrv_addr);
3343 return (ret);
3344 }
3345 }
3346
3347 /* Start in highest supported mode */
3348 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3349
3350 /* Reset CDR support */
3351 xgbe_phy_cdr_track(pdata);
3352
3353 /* After starting the I2C controller, we can check for an SFP */
3354 switch (phy_data->port_mode) {
3355 case XGBE_PORT_MODE_SFP:
3356 axgbe_printf(3, "%s: calling phy detect\n", __func__);
3357 xgbe_phy_sfp_detect(pdata);
3358 break;
3359 default:
3360 break;
3361 }
3362
3363 /* If we have an external PHY, start it */
3364 ret = xgbe_phy_find_phy_device(pdata);
3365 if (ret) {
3366 axgbe_error("%s: impl find phy dev ret %d\n", __func__, ret);
3367 goto err_i2c;
3368 }
3369
3370 axgbe_printf(3, "%s: impl return success\n", __func__);
3371 return (0);
3372
3373 err_i2c:
3374 pdata->i2c_if.i2c_stop(pdata);
3375
3376 return (ret);
3377 }
3378
3379 static int
xgbe_phy_reset(struct xgbe_prv_data * pdata)3380 xgbe_phy_reset(struct xgbe_prv_data *pdata)
3381 {
3382 struct xgbe_phy_data *phy_data = pdata->phy_data;
3383 enum xgbe_mode cur_mode;
3384 int ret;
3385
3386 /* Reset by power cycling the PHY */
3387 cur_mode = phy_data->cur_mode;
3388 xgbe_phy_power_off(pdata);
3389 xgbe_phy_set_mode(pdata, cur_mode);
3390
3391 axgbe_printf(3, "%s: mode %d\n", __func__, cur_mode);
3392 if (!phy_data->phydev) {
3393 axgbe_printf(1, "%s: no phydev\n", __func__);
3394 return (0);
3395 }
3396
3397 /* Reset the external PHY */
3398 ret = xgbe_phy_mdio_reset(pdata);
3399 if (ret) {
3400 axgbe_error("%s: mdio reset %d\n", __func__, ret);
3401 return (ret);
3402 }
3403
3404 axgbe_printf(3, "%s: return success\n", __func__);
3405
3406 return (0);
3407 }
3408
3409 static void
axgbe_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)3410 axgbe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3411 {
3412 struct axgbe_if_softc *sc;
3413 struct xgbe_prv_data *pdata;
3414 struct mii_data *mii;
3415
3416 sc = ifp->if_softc;
3417 pdata = &sc->pdata;
3418
3419 axgbe_printf(2, "%s: Invoked\n", __func__);
3420 mtx_lock_spin(&pdata->mdio_mutex);
3421 mii = device_get_softc(pdata->axgbe_miibus);
3422 axgbe_printf(2, "%s: media_active %#x media_status %#x\n", __func__,
3423 mii->mii_media_active, mii->mii_media_status);
3424 mii_pollstat(mii);
3425 ifmr->ifm_active = mii->mii_media_active;
3426 ifmr->ifm_status = mii->mii_media_status;
3427 mtx_unlock_spin(&pdata->mdio_mutex);
3428 }
3429
3430 static int
axgbe_ifmedia_upd(struct ifnet * ifp)3431 axgbe_ifmedia_upd(struct ifnet *ifp)
3432 {
3433 struct xgbe_prv_data *pdata;
3434 struct axgbe_if_softc *sc;
3435 struct mii_data *mii;
3436 struct mii_softc *miisc;
3437 int ret;
3438
3439 sc = ifp->if_softc;
3440 pdata = &sc->pdata;
3441
3442 axgbe_printf(2, "%s: Invoked\n", __func__);
3443 mtx_lock_spin(&pdata->mdio_mutex);
3444 mii = device_get_softc(pdata->axgbe_miibus);
3445 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3446 PHY_RESET(miisc);
3447 ret = mii_mediachg(mii);
3448 mtx_unlock_spin(&pdata->mdio_mutex);
3449
3450 return (ret);
3451 }
3452
3453 static void
xgbe_phy_exit(struct xgbe_prv_data * pdata)3454 xgbe_phy_exit(struct xgbe_prv_data *pdata)
3455 {
3456 if (pdata->axgbe_miibus != NULL)
3457 device_delete_child(pdata->dev, pdata->axgbe_miibus);
3458
3459 /* free phy_data structure */
3460 free(pdata->phy_data, M_AXGBE);
3461 }
3462
3463 static int
xgbe_phy_init(struct xgbe_prv_data * pdata)3464 xgbe_phy_init(struct xgbe_prv_data *pdata)
3465 {
3466 struct xgbe_phy_data *phy_data;
3467 int ret;
3468
3469 /* Initialize the global lock */
3470 if (!mtx_initialized(&xgbe_phy_comm_lock))
3471 mtx_init(&xgbe_phy_comm_lock, "xgbe phy common lock", NULL, MTX_DEF);
3472
3473 /* Check if enabled */
3474 if (!xgbe_phy_port_enabled(pdata)) {
3475 axgbe_error("device is not enabled\n");
3476 return (-ENODEV);
3477 }
3478
3479 /* Initialize the I2C controller */
3480 ret = pdata->i2c_if.i2c_init(pdata);
3481 if (ret)
3482 return (ret);
3483
3484 phy_data = malloc(sizeof(*phy_data), M_AXGBE, M_WAITOK | M_ZERO);
3485 pdata->phy_data = phy_data;
3486
3487 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3488 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3489 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3490 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3491 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3492
3493 pdata->mdio_addr = phy_data->mdio_addr;
3494 DBGPR("port mode=%u\n", phy_data->port_mode);
3495 DBGPR("port id=%u\n", phy_data->port_id);
3496 DBGPR("port speeds=%#x\n", phy_data->port_speeds);
3497 DBGPR("conn type=%u\n", phy_data->conn_type);
3498 DBGPR("mdio addr=%u\n", phy_data->mdio_addr);
3499
3500 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3501 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3502 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3503 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3504 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3505
3506 if (phy_data->redrv) {
3507 DBGPR("redrv present\n");
3508 DBGPR("redrv i/f=%u\n", phy_data->redrv_if);
3509 DBGPR("redrv addr=%#x\n", phy_data->redrv_addr);
3510 DBGPR("redrv lane=%u\n", phy_data->redrv_lane);
3511 DBGPR("redrv model=%u\n", phy_data->redrv_model);
3512 }
3513
3514 DBGPR("%s: redrv addr=%#x redrv i/f=%u\n", __func__,
3515 phy_data->redrv_addr, phy_data->redrv_if);
3516 /* Validate the connection requested */
3517 if (xgbe_phy_conn_type_mismatch(pdata)) {
3518 axgbe_error("phy mode/connection mismatch "
3519 "(%#x/%#x)\n", phy_data->port_mode, phy_data->conn_type);
3520 return (-EINVAL);
3521 }
3522
3523 /* Validate the mode requested */
3524 if (xgbe_phy_port_mode_mismatch(pdata)) {
3525 axgbe_error("phy mode/speed mismatch "
3526 "(%#x/%#x)\n", phy_data->port_mode, phy_data->port_speeds);
3527 return (-EINVAL);
3528 }
3529
3530 /* Check for and validate MDIO reset support */
3531 ret = xgbe_phy_mdio_reset_setup(pdata);
3532 if (ret) {
3533 axgbe_error("%s, mdio_reset_setup ret %d\n", __func__, ret);
3534 return (ret);
3535 }
3536
3537 /* Validate the re-driver information */
3538 if (xgbe_phy_redrv_error(phy_data)) {
3539 axgbe_error("phy re-driver settings error\n");
3540 return (-EINVAL);
3541 }
3542 pdata->kr_redrv = phy_data->redrv;
3543
3544 /* Indicate current mode is unknown */
3545 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3546
3547 /* Initialize supported features. Current code does not support ethtool */
3548 XGBE_ZERO_SUP(&pdata->phy);
3549
3550 DBGPR("%s: port mode %d\n", __func__, phy_data->port_mode);
3551 switch (phy_data->port_mode) {
3552 /* Backplane support */
3553 case XGBE_PORT_MODE_BACKPLANE:
3554 XGBE_SET_SUP(&pdata->phy, Autoneg);
3555 XGBE_SET_SUP(&pdata->phy, Pause);
3556 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3557 XGBE_SET_SUP(&pdata->phy, Backplane);
3558 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3559 XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);
3560 phy_data->start_mode = XGBE_MODE_KX_1000;
3561 }
3562 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3563 XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);
3564 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3565 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3566 phy_data->start_mode = XGBE_MODE_KR;
3567 }
3568
3569 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3570 break;
3571 case XGBE_PORT_MODE_BACKPLANE_2500:
3572 XGBE_SET_SUP(&pdata->phy, Pause);
3573 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3574 XGBE_SET_SUP(&pdata->phy, Backplane);
3575 XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);
3576 phy_data->start_mode = XGBE_MODE_KX_2500;
3577
3578 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3579 break;
3580
3581 /* MDIO 1GBase-T support */
3582 case XGBE_PORT_MODE_1000BASE_T:
3583 XGBE_SET_SUP(&pdata->phy, Autoneg);
3584 XGBE_SET_SUP(&pdata->phy, Pause);
3585 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3586 XGBE_SET_SUP(&pdata->phy, TP);
3587 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3588 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3589 phy_data->start_mode = XGBE_MODE_SGMII_100;
3590 }
3591 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3592 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3593 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3594 }
3595
3596 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3597 break;
3598
3599 /* MDIO Base-X support */
3600 case XGBE_PORT_MODE_1000BASE_X:
3601 XGBE_SET_SUP(&pdata->phy, Autoneg);
3602 XGBE_SET_SUP(&pdata->phy, Pause);
3603 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3604 XGBE_SET_SUP(&pdata->phy, FIBRE);
3605 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
3606 phy_data->start_mode = XGBE_MODE_X;
3607
3608 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3609 break;
3610
3611 /* MDIO NBase-T support */
3612 case XGBE_PORT_MODE_NBASE_T:
3613 XGBE_SET_SUP(&pdata->phy, Autoneg);
3614 XGBE_SET_SUP(&pdata->phy, Pause);
3615 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3616 XGBE_SET_SUP(&pdata->phy, TP);
3617 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3618 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3619 phy_data->start_mode = XGBE_MODE_SGMII_100;
3620 }
3621 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3622 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3623 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3624 }
3625 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3626 XGBE_SET_SUP(&pdata->phy, 2500baseT_Full);
3627 phy_data->start_mode = XGBE_MODE_KX_2500;
3628 }
3629
3630 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3631 break;
3632
3633 /* 10GBase-T support */
3634 case XGBE_PORT_MODE_10GBASE_T:
3635 XGBE_SET_SUP(&pdata->phy, Autoneg);
3636 XGBE_SET_SUP(&pdata->phy, Pause);
3637 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3638 XGBE_SET_SUP(&pdata->phy, TP);
3639 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3640 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3641 phy_data->start_mode = XGBE_MODE_SGMII_100;
3642 }
3643 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3644 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3645 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3646 }
3647 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3648 XGBE_SET_SUP(&pdata->phy, 10000baseT_Full);
3649 phy_data->start_mode = XGBE_MODE_KR;
3650 }
3651
3652 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3653 break;
3654
3655 /* 10GBase-R support */
3656 case XGBE_PORT_MODE_10GBASE_R:
3657 XGBE_SET_SUP(&pdata->phy, Autoneg);
3658 XGBE_SET_SUP(&pdata->phy, Pause);
3659 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3660 XGBE_SET_SUP(&pdata->phy, FIBRE);
3661 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
3662 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
3663 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
3664 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
3665 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3666 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3667 phy_data->start_mode = XGBE_MODE_SFI;
3668
3669 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3670 break;
3671
3672 /* SFP support */
3673 case XGBE_PORT_MODE_SFP:
3674 XGBE_SET_SUP(&pdata->phy, Autoneg);
3675 XGBE_SET_SUP(&pdata->phy, Pause);
3676 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3677 XGBE_SET_SUP(&pdata->phy, TP);
3678 XGBE_SET_SUP(&pdata->phy, FIBRE);
3679 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3680 phy_data->start_mode = XGBE_MODE_SGMII_100;
3681 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3682 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3683 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3684 phy_data->start_mode = XGBE_MODE_SFI;
3685
3686 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3687
3688 xgbe_phy_sfp_setup(pdata);
3689 DBGPR("%s: start %d mode %d adv 0x%x\n", __func__,
3690 phy_data->start_mode, phy_data->phydev_mode,
3691 pdata->phy.advertising);
3692 break;
3693 default:
3694 return (-EINVAL);
3695 }
3696
3697 axgbe_printf(2, "%s: start %d mode %d adv 0x%x\n", __func__,
3698 phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising);
3699
3700 DBGPR("%s: conn type %d mode %d\n", __func__,
3701 phy_data->conn_type, phy_data->phydev_mode);
3702 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3703 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3704 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3705 phy_data->phydev_mode);
3706 if (ret) {
3707 axgbe_error("mdio port/clause not compatible (%d/%u)\n",
3708 phy_data->mdio_addr, phy_data->phydev_mode);
3709 return (-EINVAL);
3710 }
3711 }
3712
3713 if (phy_data->redrv && !phy_data->redrv_if) {
3714 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3715 XGBE_MDIO_MODE_CL22);
3716 if (ret) {
3717 axgbe_error("redriver mdio port not compatible (%u)\n",
3718 phy_data->redrv_addr);
3719 return (-EINVAL);
3720 }
3721 }
3722
3723 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3724
3725 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
3726 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
3727 (ifm_change_cb_t)axgbe_ifmedia_upd,
3728 (ifm_stat_cb_t)axgbe_ifmedia_sts, BMSR_DEFCAPMASK,
3729 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
3730
3731 if (ret){
3732 axgbe_printf(2, "mii attach failed with err=(%d)\n", ret);
3733 return (-EINVAL);
3734 }
3735 }
3736
3737 DBGPR("%s: return success\n", __func__);
3738
3739 return (0);
3740 }
3741
3742 void
xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if * phy_if)3743 xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3744 {
3745 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3746
3747 phy_impl->init = xgbe_phy_init;
3748 phy_impl->exit = xgbe_phy_exit;
3749
3750 phy_impl->reset = xgbe_phy_reset;
3751 phy_impl->start = xgbe_phy_start;
3752 phy_impl->stop = xgbe_phy_stop;
3753
3754 phy_impl->link_status = xgbe_phy_link_status;
3755
3756 phy_impl->valid_speed = xgbe_phy_valid_speed;
3757
3758 phy_impl->use_mode = xgbe_phy_use_mode;
3759 phy_impl->set_mode = xgbe_phy_set_mode;
3760 phy_impl->get_mode = xgbe_phy_get_mode;
3761 phy_impl->switch_mode = xgbe_phy_switch_mode;
3762 phy_impl->cur_mode = xgbe_phy_cur_mode;
3763 phy_impl->get_type = xgbe_phy_get_type;
3764
3765 phy_impl->an_mode = xgbe_phy_an_mode;
3766
3767 phy_impl->an_config = xgbe_phy_an_config;
3768
3769 phy_impl->an_advertising = xgbe_phy_an_advertising;
3770
3771 phy_impl->an_outcome = xgbe_phy_an_outcome;
3772
3773 phy_impl->an_pre = xgbe_phy_an_pre;
3774 phy_impl->an_post = xgbe_phy_an_post;
3775
3776 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3777 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3778
3779 phy_impl->module_info = xgbe_phy_module_info;
3780 phy_impl->module_eeprom = xgbe_phy_module_eeprom;
3781 }
3782