1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Contact Information :
28 * Rajesh Kumar <rajesh1.kumar@amd.com>
29 * Shreyank Amartya <Shreyank.Amartya@amd.com>
30 */
31
32 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40 #include <sys/socket.h>
41 #include <sys/sysctl.h>
42 #include <sys/systm.h>
43
44 #include <net/if.h>
45 #include <net/if_media.h>
46
47 #include <dev/mii/mii.h>
48 #include <dev/mii/miivar.h>
49
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52
53 #include "xgbe.h"
54 #include "xgbe-common.h"
55
56 #include "miibus_if.h"
57 #include "ifdi_if.h"
58 #include "opt_inet.h"
59 #include "opt_inet6.h"
60
61 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data");
62
63 extern struct if_txrx axgbe_txrx;
64 static int axgbe_sph_enable;
65
66 /* Function prototypes */
67 static void *axgbe_register(device_t);
68 static int axgbe_if_attach_pre(if_ctx_t);
69 static int axgbe_if_attach_post(if_ctx_t);
70 static int axgbe_if_detach(if_ctx_t);
71 static void axgbe_if_stop(if_ctx_t);
72 static void axgbe_if_init(if_ctx_t);
73
74 /* Queue related routines */
75 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
76 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
77 static int axgbe_alloc_channels(if_ctx_t);
78 static void axgbe_free_channels(struct axgbe_if_softc *);
79 static void axgbe_if_queues_free(if_ctx_t);
80 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
81 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
82
83 /* Interrupt related routines */
84 static void axgbe_if_disable_intr(if_ctx_t);
85 static void axgbe_if_enable_intr(if_ctx_t);
86 static int axgbe_if_msix_intr_assign(if_ctx_t, int);
87 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int);
88
89 /* Init and Iflib routines */
90 static void axgbe_pci_init(struct xgbe_prv_data *);
91 static void axgbe_pci_stop(if_ctx_t);
92 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *);
93 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *);
94 static int axgbe_if_mtu_set(if_ctx_t, uint32_t);
95 static void axgbe_if_update_admin_status(if_ctx_t);
96 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *);
97 static int axgbe_if_media_change(if_ctx_t);
98 static int axgbe_if_promisc_set(if_ctx_t, int);
99 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter);
100 static void axgbe_if_vlan_register(if_ctx_t, uint16_t);
101 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t);
102 #if __FreeBSD_version >= 1300000
103 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
104 #endif
105 static void axgbe_set_counts(if_ctx_t);
106 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *);
107
108 /* MII interface registered functions */
109 static int axgbe_miibus_readreg(device_t, int, int);
110 static int axgbe_miibus_writereg(device_t, int, int, int);
111 static void axgbe_miibus_statchg(device_t);
112
113 /* ISR routines */
114 static int axgbe_dev_isr(void *);
115 static void axgbe_ecc_isr(void *);
116 static void axgbe_i2c_isr(void *);
117 static void axgbe_an_isr(void *);
118 static int axgbe_msix_que(void *);
119
120 /* Timer routines */
121 static void xgbe_service(void *, int);
122 static void xgbe_service_timer(void *);
123 static void xgbe_init_timers(struct xgbe_prv_data *);
124 static void xgbe_stop_timers(struct xgbe_prv_data *);
125
126 /* Dump routines */
127 static void xgbe_dump_prop_registers(struct xgbe_prv_data *);
128
129 /*
130 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the
131 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
132 * table.
133 */
134 static struct resource_spec axgbe_pci_mac_spec[] = {
135 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */
136 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */
137 { -1, 0 }
138 };
139
140 static const pci_vendor_info_t axgbe_vendor_info_array[] =
141 {
142 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
143 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
144 PVID_END
145 };
146
147 static struct xgbe_version_data xgbe_v2a = {
148 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
149 .xpcs_access = XGBE_XPCS_ACCESS_V2,
150 .mmc_64bit = 1,
151 .tx_max_fifo_size = 229376,
152 .rx_max_fifo_size = 229376,
153 .tx_tstamp_workaround = 1,
154 .ecc_support = 1,
155 .i2c_support = 1,
156 .irq_reissue_support = 1,
157 .tx_desc_prefetch = 5,
158 .rx_desc_prefetch = 5,
159 .an_cdr_workaround = 1,
160 };
161
162 static struct xgbe_version_data xgbe_v2b = {
163 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
164 .xpcs_access = XGBE_XPCS_ACCESS_V2,
165 .mmc_64bit = 1,
166 .tx_max_fifo_size = 65536,
167 .rx_max_fifo_size = 65536,
168 .tx_tstamp_workaround = 1,
169 .ecc_support = 1,
170 .i2c_support = 1,
171 .irq_reissue_support = 1,
172 .tx_desc_prefetch = 5,
173 .rx_desc_prefetch = 5,
174 .an_cdr_workaround = 1,
175 };
176
177 /* Device Interface */
178 static device_method_t ax_methods[] = {
179 DEVMETHOD(device_register, axgbe_register),
180 DEVMETHOD(device_probe, iflib_device_probe),
181 DEVMETHOD(device_attach, iflib_device_attach),
182 DEVMETHOD(device_detach, iflib_device_detach),
183
184 /* MII interface */
185 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg),
186 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg),
187 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg),
188
189 DEVMETHOD_END
190 };
191
192 static driver_t ax_driver = {
193 "ax", ax_methods, sizeof(struct axgbe_if_softc),
194 };
195
196 devclass_t ax_devclass;
197 DRIVER_MODULE(axp, pci, ax_driver, ax_devclass, 0, 0);
198 DRIVER_MODULE(miibus, ax, miibus_driver, miibus_devclass, 0, 0);
199 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array);
200
201 MODULE_DEPEND(ax, pci, 1, 1, 1);
202 MODULE_DEPEND(ax, ether, 1, 1, 1);
203 MODULE_DEPEND(ax, iflib, 1, 1, 1);
204 MODULE_DEPEND(ax, miibus, 1, 1, 1);
205
206 /* Iflib Interface */
207 static device_method_t axgbe_if_methods[] = {
208 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre),
209 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post),
210 DEVMETHOD(ifdi_detach, axgbe_if_detach),
211 DEVMETHOD(ifdi_init, axgbe_if_init),
212 DEVMETHOD(ifdi_stop, axgbe_if_stop),
213 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign),
214 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr),
215 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr),
216 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable),
217 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable),
218 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc),
219 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc),
220 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free),
221 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status),
222 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set),
223 DEVMETHOD(ifdi_media_status, axgbe_if_media_status),
224 DEVMETHOD(ifdi_media_change, axgbe_if_media_change),
225 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set),
226 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter),
227 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register),
228 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister),
229 #if __FreeBSD_version >= 1300000
230 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart),
231 #endif
232 DEVMETHOD_END
233 };
234
235 static driver_t axgbe_if_driver = {
236 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc)
237 };
238
239 /* Iflib Shared Context */
240 static struct if_shared_ctx axgbe_sctx_init = {
241 .isc_magic = IFLIB_MAGIC,
242 .isc_driver = &axgbe_if_driver,
243 .isc_q_align = PAGE_SIZE,
244 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
245 .isc_tx_maxsegsize = PAGE_SIZE,
246 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
247 .isc_tso_maxsegsize = PAGE_SIZE,
248 .isc_rx_maxsize = MJUM9BYTES,
249 .isc_rx_maxsegsize = MJUM9BYTES,
250 .isc_rx_nsegments = 1,
251 .isc_admin_intrcnt = 4,
252
253 .isc_vendor_info = axgbe_vendor_info_array,
254 .isc_driver_version = XGBE_DRV_VERSION,
255
256 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN},
257 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT},
258 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX},
259
260 .isc_ntxqs = 1,
261 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH |
262 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD,
263 };
264
265 static void *
axgbe_register(device_t dev)266 axgbe_register(device_t dev)
267 {
268 int axgbe_nfl;
269 int axgbe_nrxqs;
270 int error, i;
271 char *value = NULL;
272
273 value = kern_getenv("dev.ax.sph_enable");
274 if (value) {
275 axgbe_sph_enable = strtol(value, NULL, 10);
276 freeenv(value);
277 } else {
278 /*
279 * No tunable found, generate one with default values
280 * Note: only a reboot will reveal the new kenv
281 */
282 error = kern_setenv("dev.ax.sph_enable", "1");
283 if (error) {
284 printf("Error setting tunable, using default driver values\n");
285 }
286 axgbe_sph_enable = 1;
287 }
288
289 if (!axgbe_sph_enable) {
290 axgbe_nfl = 1;
291 axgbe_nrxqs = 1;
292 } else {
293 axgbe_nfl = 2;
294 axgbe_nrxqs = 2;
295 }
296
297 axgbe_sctx_init.isc_nfl = axgbe_nfl;
298 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs;
299
300 for (i = 0 ; i < axgbe_nrxqs ; i++) {
301 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN;
302 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT;
303 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX;
304 }
305
306 return (&axgbe_sctx_init);
307 }
308
309 /* MII Interface Functions */
310 static int
axgbe_miibus_readreg(device_t dev,int phy,int reg)311 axgbe_miibus_readreg(device_t dev, int phy, int reg)
312 {
313 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
314 struct xgbe_prv_data *pdata = &sc->pdata;
315 int val;
316
317 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);
318
319 val = xgbe_phy_mii_read(pdata, phy, reg);
320
321 axgbe_printf(2, "%s: val 0x%x\n", __func__, val);
322 return (val & 0xFFFF);
323 }
324
325 static int
axgbe_miibus_writereg(device_t dev,int phy,int reg,int val)326 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)
327 {
328 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
329 struct xgbe_prv_data *pdata = &sc->pdata;
330
331 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);
332
333 xgbe_phy_mii_write(pdata, phy, reg, val);
334
335 return(0);
336 }
337
338 static void
axgbe_miibus_statchg(device_t dev)339 axgbe_miibus_statchg(device_t dev)
340 {
341 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
342 struct xgbe_prv_data *pdata = &sc->pdata;
343 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
344 struct ifnet *ifp = pdata->netdev;
345 int bmsr;
346
347 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
348 pdata->phy_link);
349
350 if (mii == NULL || ifp == NULL ||
351 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
352 return;
353
354 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
355 (IFM_ACTIVE | IFM_AVALID)) {
356
357 switch (IFM_SUBTYPE(mii->mii_media_active)) {
358 case IFM_10_T:
359 case IFM_100_TX:
360 pdata->phy.link = 1;
361 break;
362 case IFM_1000_T:
363 case IFM_1000_SX:
364 case IFM_2500_SX:
365 pdata->phy.link = 1;
366 break;
367 default:
368 pdata->phy.link = 0;
369 break;
370 }
371 } else
372 pdata->phy_link = 0;
373
374 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
375 if (bmsr & BMSR_ANEG) {
376
377 axgbe_printf(2, "%s: Autoneg Done\n", __func__);
378
379 /* Raise AN Interrupt */
380 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
381 XGBE_AN_CL73_INT_MASK);
382 }
383 }
384
385 static int
axgbe_if_attach_pre(if_ctx_t ctx)386 axgbe_if_attach_pre(if_ctx_t ctx)
387 {
388 struct axgbe_if_softc *sc;
389 struct xgbe_prv_data *pdata;
390 struct resource *mac_res[2];
391 if_softc_ctx_t scctx;
392 if_shared_ctx_t sctx;
393 device_t dev;
394 unsigned int ma_lo, ma_hi;
395 unsigned int reg;
396 int ret;
397
398 sc = iflib_get_softc(ctx);
399 sc->pdata.dev = dev = iflib_get_dev(ctx);
400 sc->sctx = sctx = iflib_get_sctx(ctx);
401 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
402 sc->media = iflib_get_media(ctx);
403 sc->ctx = ctx;
404 sc->link_status = LINK_STATE_DOWN;
405 pdata = &sc->pdata;
406 pdata->netdev = iflib_get_ifp(ctx);
407
408 spin_lock_init(&pdata->xpcs_lock);
409
410 /* Initialize locks */
411 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
412 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
413
414 /* Allocate VLAN bitmap */
415 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
416 pdata->num_active_vlans = 0;
417
418 /* Get the version data */
419 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev));
420 if (pci_get_device(dev) == 0x1458)
421 sc->pdata.vdata = &xgbe_v2a;
422 else if (pci_get_device(dev) == 0x1459)
423 sc->pdata.vdata = &xgbe_v2b;
424
425 /* PCI setup */
426 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) {
427 axgbe_error("Unable to allocate bus resources\n");
428 ret = ENXIO;
429 goto free_vlans;
430 }
431
432 sc->pdata.xgmac_res = mac_res[0];
433 sc->pdata.xpcs_res = mac_res[1];
434
435 /* Set the PCS indirect addressing definition registers*/
436 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
437 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
438
439 /* Configure the PCS indirect addressing support */
440 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
441 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
442 pdata->xpcs_window <<= 6;
443 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
444 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
445 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
446 DBGPR("xpcs window def : %#010x\n",
447 pdata->xpcs_window_def_reg);
448 DBGPR("xpcs window sel : %#010x\n",
449 pdata->xpcs_window_sel_reg);
450 DBGPR("xpcs window : %#010x\n",
451 pdata->xpcs_window);
452 DBGPR("xpcs window size : %#010x\n",
453 pdata->xpcs_window_size);
454 DBGPR("xpcs window mask : %#010x\n",
455 pdata->xpcs_window_mask);
456
457 /* Enable all interrupts in the hardware */
458 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
459
460 /* Retrieve the MAC address */
461 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
462 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
463 pdata->mac_addr[0] = ma_lo & 0xff;
464 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
465 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
466 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
467 pdata->mac_addr[4] = ma_hi & 0xff;
468 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
469 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) {
470 axgbe_error("Invalid mac address\n");
471 ret = EINVAL;
472 goto release_bus_resource;
473 }
474 iflib_set_mac(ctx, pdata->mac_addr);
475
476 /* Clock settings */
477 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
478 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
479
480 /* Set the DMA coherency values */
481 pdata->coherent = 1;
482 pdata->arcr = XGBE_DMA_PCI_ARCR;
483 pdata->awcr = XGBE_DMA_PCI_AWCR;
484 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
485
486 /* Read the port property registers */
487 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
488 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
489 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
490 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
491 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
492 DBGPR("port property 0 = %#010x\n", pdata->pp0);
493 DBGPR("port property 1 = %#010x\n", pdata->pp1);
494 DBGPR("port property 2 = %#010x\n", pdata->pp2);
495 DBGPR("port property 3 = %#010x\n", pdata->pp3);
496 DBGPR("port property 4 = %#010x\n", pdata->pp4);
497
498 /* Set the maximum channels and queues */
499 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
500 MAX_TX_DMA);
501 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
502 MAX_RX_DMA);
503 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
504 MAX_TX_QUEUES);
505 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
506 MAX_RX_QUEUES);
507 DBGPR("max tx/rx channel count = %u/%u\n",
508 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
509 DBGPR("max tx/rx hw queue count = %u/%u\n",
510 pdata->tx_max_q_count, pdata->rx_max_q_count);
511
512 axgbe_set_counts(ctx);
513
514 /* Set the maximum fifo amounts */
515 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
516 TX_FIFO_SIZE);
517 pdata->tx_max_fifo_size *= 16384;
518 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
519 pdata->vdata->tx_max_fifo_size);
520 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
521 RX_FIFO_SIZE);
522 pdata->rx_max_fifo_size *= 16384;
523 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
524 pdata->vdata->rx_max_fifo_size);
525 DBGPR("max tx/rx max fifo size = %u/%u\n",
526 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
527
528 /* Initialize IFLIB if_softc_ctx_t */
529 axgbe_init_iflib_softc_ctx(sc);
530
531 /* Alloc channels */
532 if (axgbe_alloc_channels(ctx)) {
533 axgbe_error("Unable to allocate channel memory\n");
534 ret = ENOMEM;
535 goto release_bus_resource;
536 }
537
538 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
539
540 /* create the workqueue */
541 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
542 taskqueue_thread_enqueue, &pdata->dev_workqueue);
543 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
544 "axgbe dev taskq");
545 if (ret) {
546 axgbe_error("Unable to start taskqueue\n");
547 ret = ENOMEM;
548 goto free_task_queue;
549 }
550
551 /* Init timers */
552 xgbe_init_timers(pdata);
553
554 return (0);
555
556 free_task_queue:
557 taskqueue_free(pdata->dev_workqueue);
558 axgbe_free_channels(sc);
559
560 release_bus_resource:
561 bus_release_resources(dev, axgbe_pci_mac_spec, mac_res);
562
563 free_vlans:
564 free(pdata->active_vlans, M_AXGBE);
565
566 return (ret);
567 } /* axgbe_if_attach_pre */
568
569 static void
xgbe_init_all_fptrs(struct xgbe_prv_data * pdata)570 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
571 {
572 xgbe_init_function_ptrs_dev(&pdata->hw_if);
573 xgbe_init_function_ptrs_phy(&pdata->phy_if);
574 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
575 xgbe_init_function_ptrs_desc(&pdata->desc_if);
576
577 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
578 }
579
580 static void
axgbe_set_counts(if_ctx_t ctx)581 axgbe_set_counts(if_ctx_t ctx)
582 {
583 struct axgbe_if_softc *sc = iflib_get_softc(ctx);;
584 struct xgbe_prv_data *pdata = &sc->pdata;
585 cpuset_t lcpus;
586 int cpu_count, err;
587 size_t len;
588
589 /* Set all function pointers */
590 xgbe_init_all_fptrs(pdata);
591
592 /* Populate the hardware features */
593 xgbe_get_all_hw_features(pdata);
594
595 if (!pdata->tx_max_channel_count)
596 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
597 if (!pdata->rx_max_channel_count)
598 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
599
600 if (!pdata->tx_max_q_count)
601 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
602 if (!pdata->rx_max_q_count)
603 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
604
605 /*
606 * Calculate the number of Tx and Rx rings to be created
607 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
608 * the number of Tx queues to the number of Tx channels
609 * enabled
610 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
611 * number of Rx queues or maximum allowed
612 */
613
614 /* Get cpu count from sysctl */
615 len = sizeof(cpu_count);
616 err = kernel_sysctlbyname(curthread, "hw.ncpu", &cpu_count, &len, NULL,
617 0, NULL, 0);
618 if (err) {
619 axgbe_error("Unable to fetch number of cpus\n");
620 cpu_count = 1;
621 }
622
623 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
624 axgbe_error("Unable to fetch CPU list\n");
625 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
626 }
627
628 DBGPR("ncpu %d intrcpu %d\n", cpu_count, CPU_COUNT(&lcpus));
629
630 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
631 pdata->tx_ring_count = min(pdata->tx_ring_count,
632 pdata->tx_max_channel_count);
633 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
634
635 pdata->tx_q_count = pdata->tx_ring_count;
636
637 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
638 pdata->rx_ring_count = min(pdata->rx_ring_count,
639 pdata->rx_max_channel_count);
640
641 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
642
643 DBGPR("TX/RX max channel count = %u/%u\n",
644 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
645 DBGPR("TX/RX max queue count = %u/%u\n",
646 pdata->tx_max_q_count, pdata->rx_max_q_count);
647 DBGPR("TX/RX DMA ring count = %u/%u\n",
648 pdata->tx_ring_count, pdata->rx_ring_count);
649 DBGPR("TX/RX hardware queue count = %u/%u\n",
650 pdata->tx_q_count, pdata->rx_q_count);
651 } /* axgbe_set_counts */
652
653 static void
axgbe_init_iflib_softc_ctx(struct axgbe_if_softc * sc)654 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc)
655 {
656 struct xgbe_prv_data *pdata = &sc->pdata;
657 if_softc_ctx_t scctx = sc->scctx;
658 if_shared_ctx_t sctx = sc->sctx;
659 int i;
660
661 scctx->isc_nrxqsets = pdata->rx_q_count;
662 scctx->isc_ntxqsets = pdata->tx_q_count;
663 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
664 scctx->isc_tx_nsegments = 32;
665
666 for (i = 0; i < sctx->isc_ntxqs; i++) {
667 scctx->isc_txqsizes[i] =
668 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
669 128);
670 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
671 }
672
673 for (i = 0; i < sctx->isc_nrxqs; i++) {
674 scctx->isc_rxqsizes[i] =
675 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
676 128);
677 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
678 }
679
680 scctx->isc_tx_tso_segments_max = 32;
681 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
682 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
683
684 /*
685 * Set capabilities
686 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly
687 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in
688 * IFCAP_HWCSUM) is set
689 */
690 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
691 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 |
692 CSUM_TSO);
693 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
694 IFCAP_JUMBO_MTU |
695 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
696 IFCAP_VLAN_HWCSUM |
697 IFCAP_TSO | IFCAP_VLAN_HWTSO);
698 scctx->isc_capabilities = scctx->isc_capenable;
699
700 /*
701 * Set rss_table_size alone when adding RSS support. rss_table_mask
702 * will be set by IFLIB based on rss_table_size
703 */
704 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
705
706 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
707 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
708
709 scctx->isc_txrx = &axgbe_txrx;
710 }
711
712 static int
axgbe_alloc_channels(if_ctx_t ctx)713 axgbe_alloc_channels(if_ctx_t ctx)
714 {
715 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
716 struct xgbe_prv_data *pdata = &sc->pdata;
717 struct xgbe_channel *channel;
718 int i, j, count;
719
720 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
721 pdata->rx_ring_count);
722
723 /* Iflibe sets based on isc_ntxqsets/nrxqsets */
724 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
725
726 /* Allocate channel memory */
727 for (i = 0; i < count ; i++) {
728 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
729 M_AXGBE, M_NOWAIT | M_ZERO);
730
731 if (channel == NULL) {
732 for (j = 0; j < i; j++) {
733 free(pdata->channel[j], M_AXGBE);
734 pdata->channel[j] = NULL;
735 }
736 return (ENOMEM);
737 }
738
739 pdata->channel[i] = channel;
740 }
741
742 pdata->total_channel_count = count;
743 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
744
745 for (i = 0; i < count; i++) {
746
747 channel = pdata->channel[i];
748 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
749
750 channel->pdata = pdata;
751 channel->queue_index = i;
752 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
753 bus_space_subregion(channel->dma_tag,
754 rman_get_bushandle(pdata->xgmac_res),
755 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
756 &channel->dma_handle);
757 channel->tx_ring = NULL;
758 channel->rx_ring = NULL;
759 }
760
761 return (0);
762 } /* axgbe_alloc_channels */
763
764 static void
axgbe_free_channels(struct axgbe_if_softc * sc)765 axgbe_free_channels(struct axgbe_if_softc *sc)
766 {
767 struct xgbe_prv_data *pdata = &sc->pdata;
768 int i;
769
770 for (i = 0; i < pdata->total_channel_count ; i++) {
771 free(pdata->channel[i], M_AXGBE);
772 pdata->channel[i] = NULL;
773 }
774
775 pdata->total_channel_count = 0;
776 pdata->channel_count = 0;
777 }
778
779 static void
xgbe_service(void * ctx,int pending)780 xgbe_service(void *ctx, int pending)
781 {
782 struct xgbe_prv_data *pdata = ctx;
783 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
784 bool prev_state = false;
785
786 /* Get previous link status */
787 prev_state = pdata->phy.link;
788
789 pdata->phy_if.phy_status(pdata);
790
791 if (prev_state != pdata->phy.link) {
792 pdata->phy_link = pdata->phy.link;
793 axgbe_if_update_admin_status(sc->ctx);
794 }
795
796 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
797 }
798
799 static void
xgbe_service_timer(void * data)800 xgbe_service_timer(void *data)
801 {
802 struct xgbe_prv_data *pdata = data;
803
804 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
805 }
806
807 static void
xgbe_init_timers(struct xgbe_prv_data * pdata)808 xgbe_init_timers(struct xgbe_prv_data *pdata)
809 {
810 callout_init(&pdata->service_timer, 1*hz);
811 }
812
813 static void
xgbe_start_timers(struct xgbe_prv_data * pdata)814 xgbe_start_timers(struct xgbe_prv_data *pdata)
815 {
816 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
817 }
818
819 static void
xgbe_stop_timers(struct xgbe_prv_data * pdata)820 xgbe_stop_timers(struct xgbe_prv_data *pdata)
821 {
822 callout_drain(&pdata->service_timer);
823 callout_stop(&pdata->service_timer);
824 }
825
826 static void
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)827 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
828 {
829 axgbe_printf(1, "\n************* PHY Reg dump *********************\n");
830
831 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
832 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
833 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
834 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
835 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
836 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
837 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
838 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
839 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
840 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
841 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
842 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
843 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
844 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
845 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
846 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
847 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
848 MDIO_AN_ADVERTISE,
849 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
850 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
851 MDIO_AN_ADVERTISE + 1,
852 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
853 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
854 MDIO_AN_ADVERTISE + 2,
855 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
856 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
857 MDIO_AN_COMP_STAT,
858 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
859
860 axgbe_printf(1, "\n************************************************\n");
861 }
862
863 static void
xgbe_dump_prop_registers(struct xgbe_prv_data * pdata)864 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
865 {
866 int i;
867
868 axgbe_printf(1, "\n************* PROP Reg dump ********************\n");
869
870 for (i = 0 ; i < 38 ; i++) {
871 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n",
872 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
873 (XP_PROP_0 + (i * 4))));
874 }
875 }
876
877 static void
xgbe_dump_dma_registers(struct xgbe_prv_data * pdata,int ch)878 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
879 {
880 struct xgbe_channel *channel;
881 int i;
882
883 axgbe_printf(1, "\n************* DMA Reg dump *********************\n");
884
885 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR,
886 XGMAC_IOREAD(pdata, DMA_MR));
887 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR,
888 XGMAC_IOREAD(pdata, DMA_SBMR));
889 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR,
890 XGMAC_IOREAD(pdata, DMA_ISR));
891 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR,
892 XGMAC_IOREAD(pdata, DMA_AXIARCR));
893 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR,
894 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
895 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR,
896 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
897 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0,
898 XGMAC_IOREAD(pdata, DMA_DSR0));
899 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1,
900 XGMAC_IOREAD(pdata, DMA_DSR1));
901 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2,
902 XGMAC_IOREAD(pdata, DMA_DSR2));
903 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3,
904 XGMAC_IOREAD(pdata, DMA_DSR3));
905 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4,
906 XGMAC_IOREAD(pdata, DMA_DSR4));
907 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR,
908 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
909 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR,
910 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
911
912 for (i = 0 ; i < 8 ; i++ ) {
913
914 if (ch >= 0) {
915 if (i != ch)
916 continue;
917 }
918
919 channel = pdata->channel[i];
920
921 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i);
922
923 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n",
924 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
925 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n",
926 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
927 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n",
928 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
929 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n",
930 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
931 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n",
932 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
933 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n",
934 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
935 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n",
936 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
937 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n",
938 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
939 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n",
940 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
941 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n",
942 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
943 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n",
944 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
945 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n",
946 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
947 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n",
948 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
949 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n",
950 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
951 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n",
952 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
953 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n",
954 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
955 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n",
956 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
957 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n",
958 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
959 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n",
960 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
961 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n",
962 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
963 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n",
964 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
965 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n",
966 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
967 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n",
968 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
969 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n",
970 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
971 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n",
972 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
973 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n",
974 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
975 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n",
976 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
977 }
978 }
979
980 static void
xgbe_dump_mtl_registers(struct xgbe_prv_data * pdata)981 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
982 {
983 int i;
984
985 axgbe_printf(1, "\n************* MTL Reg dump *********************\n");
986
987 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR,
988 XGMAC_IOREAD(pdata, MTL_OMR));
989 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR,
990 XGMAC_IOREAD(pdata, MTL_FDCR));
991 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR,
992 XGMAC_IOREAD(pdata, MTL_FDSR));
993 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR,
994 XGMAC_IOREAD(pdata, MTL_FDDR));
995 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR,
996 XGMAC_IOREAD(pdata, MTL_ISR));
997 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R,
998 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
999 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R,
1000 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
1001 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R,
1002 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
1003 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R,
1004 XGMAC_IOREAD(pdata, MTL_TCPM0R));
1005 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R,
1006 XGMAC_IOREAD(pdata, MTL_TCPM1R));
1007
1008 for (i = 0 ; i < 8 ; i++ ) {
1009
1010 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i);
1011
1012 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n",
1013 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1014 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n",
1015 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
1016 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n",
1017 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
1018 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n",
1019 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
1020 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n",
1021 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
1022 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n",
1023 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
1024
1025 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n",
1026 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1027 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n",
1028 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
1029 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n",
1030 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
1031 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n",
1032 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
1033 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n",
1034 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1035 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n",
1036 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
1037 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n",
1038 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
1039 }
1040 }
1041
1042 static void
xgbe_dump_mac_registers(struct xgbe_prv_data * pdata)1043 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
1044 {
1045 axgbe_printf(1, "\n************* MAC Reg dump **********************\n");
1046
1047 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR,
1048 XGMAC_IOREAD(pdata, MAC_TCR));
1049 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR,
1050 XGMAC_IOREAD(pdata, MAC_RCR));
1051 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR,
1052 XGMAC_IOREAD(pdata, MAC_PFR));
1053 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR,
1054 XGMAC_IOREAD(pdata, MAC_WTR));
1055 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0,
1056 XGMAC_IOREAD(pdata, MAC_HTR0));
1057 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1,
1058 XGMAC_IOREAD(pdata, MAC_HTR1));
1059 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2,
1060 XGMAC_IOREAD(pdata, MAC_HTR2));
1061 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3,
1062 XGMAC_IOREAD(pdata, MAC_HTR3));
1063 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4,
1064 XGMAC_IOREAD(pdata, MAC_HTR4));
1065 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5,
1066 XGMAC_IOREAD(pdata, MAC_HTR5));
1067 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6,
1068 XGMAC_IOREAD(pdata, MAC_HTR6));
1069 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7,
1070 XGMAC_IOREAD(pdata, MAC_HTR7));
1071 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR,
1072 XGMAC_IOREAD(pdata, MAC_VLANTR));
1073 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR,
1074 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1075 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR,
1076 XGMAC_IOREAD(pdata, MAC_VLANIR));
1077 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR,
1078 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1079 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR,
1080 XGMAC_IOREAD(pdata, MAC_RETMR));
1081 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR,
1082 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1083 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR,
1084 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1085 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR,
1086 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1087 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR,
1088 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1089 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR,
1090 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1091 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR,
1092 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1093 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR,
1094 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1095 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR,
1096 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1097 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR,
1098 XGMAC_IOREAD(pdata, MAC_RFCR));
1099 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R,
1100 XGMAC_IOREAD(pdata, MAC_RQC0R));
1101 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R,
1102 XGMAC_IOREAD(pdata, MAC_RQC1R));
1103 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R,
1104 XGMAC_IOREAD(pdata, MAC_RQC2R));
1105 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R,
1106 XGMAC_IOREAD(pdata, MAC_RQC3R));
1107 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR,
1108 XGMAC_IOREAD(pdata, MAC_ISR));
1109 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER,
1110 XGMAC_IOREAD(pdata, MAC_IER));
1111 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR,
1112 XGMAC_IOREAD(pdata, MAC_RTSR));
1113 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR,
1114 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1115 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR,
1116 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1117 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR,
1118 XGMAC_IOREAD(pdata, MAC_LPICSR));
1119 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR,
1120 XGMAC_IOREAD(pdata, MAC_LPITCR));
1121 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR,
1122 XGMAC_IOREAD(pdata, MAC_TIR));
1123 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR,
1124 XGMAC_IOREAD(pdata, MAC_VR));
1125 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR,
1126 XGMAC_IOREAD(pdata, MAC_DR));
1127 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R,
1128 XGMAC_IOREAD(pdata, MAC_HWF0R));
1129 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R,
1130 XGMAC_IOREAD(pdata, MAC_HWF1R));
1131 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R,
1132 XGMAC_IOREAD(pdata, MAC_HWF2R));
1133 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR,
1134 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1135 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR,
1136 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1137 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR,
1138 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1139 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER,
1140 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1141 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R,
1142 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1143 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR,
1144 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1145 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR,
1146 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1147 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR,
1148 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1149 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR,
1150 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1151 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR,
1152 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1153 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR,
1154 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1155 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR,
1156 XGMAC_IOREAD(pdata, MAC_RSSCR));
1157 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR,
1158 XGMAC_IOREAD(pdata, MAC_RSSDR));
1159 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR,
1160 XGMAC_IOREAD(pdata, MAC_RSSAR));
1161 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR,
1162 XGMAC_IOREAD(pdata, MAC_TSCR));
1163 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR,
1164 XGMAC_IOREAD(pdata, MAC_SSIR));
1165 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR,
1166 XGMAC_IOREAD(pdata, MAC_STSR));
1167 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR,
1168 XGMAC_IOREAD(pdata, MAC_STNR));
1169 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR,
1170 XGMAC_IOREAD(pdata, MAC_STSUR));
1171 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR,
1172 XGMAC_IOREAD(pdata, MAC_STNUR));
1173 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR,
1174 XGMAC_IOREAD(pdata, MAC_TSAR));
1175 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR,
1176 XGMAC_IOREAD(pdata, MAC_TSSR));
1177 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR,
1178 XGMAC_IOREAD(pdata, MAC_TXSNR));
1179 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR,
1180 XGMAC_IOREAD(pdata, MAC_TXSSR));
1181 }
1182
1183 static void
xgbe_dump_rmon_counters(struct xgbe_prv_data * pdata)1184 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1185 {
1186 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1187
1188 axgbe_printf(1, "\n************* RMON counters dump ***************\n");
1189
1190 pdata->hw_if.read_mmc_stats(pdata);
1191
1192 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n",
1193 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1194 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n",
1195 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1196 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n",
1197 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1198 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n",
1199 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1200 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n",
1201 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1202 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n",
1203 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1204 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n",
1205 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1206 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n",
1207 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1208 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n",
1209 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1210 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n",
1211 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1212 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n",
1213 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1214 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n",
1215 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1216 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n",
1217 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1218 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n",
1219 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1220 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n",
1221 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1222 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n",
1223 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1224 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n",
1225 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1226 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n",
1227 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1228 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n",
1229 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1230 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n",
1231 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1232 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n",
1233 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1234 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n",
1235 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1236 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n",
1237 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1238 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n",
1239 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1240 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n",
1241 MMC_RXRUNTERROR, stats->rxrunterror);
1242 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n",
1243 MMC_RXJABBERERROR, stats->rxjabbererror);
1244 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n",
1245 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1246 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n",
1247 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1248 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n",
1249 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1250 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n",
1251 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1252 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n",
1253 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1254 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n",
1255 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1256 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n",
1257 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1258 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n",
1259 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1260 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n",
1261 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1262 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n",
1263 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1264 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n",
1265 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1266 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n",
1267 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1268 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n",
1269 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1270 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n",
1271 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1272 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n",
1273 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1274 }
1275
1276 void
xgbe_dump_i2c_registers(struct xgbe_prv_data * pdata)1277 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1278 {
1279 axgbe_printf(1, "*************** I2C Registers **************\n");
1280 axgbe_printf(1, " IC_CON : %010x\n",
1281 XI2C_IOREAD(pdata, 0x00));
1282 axgbe_printf(1, " IC_TAR : %010x\n",
1283 XI2C_IOREAD(pdata, 0x04));
1284 axgbe_printf(1, " IC_HS_MADDR : %010x\n",
1285 XI2C_IOREAD(pdata, 0x0c));
1286 axgbe_printf(1, " IC_INTR_STAT : %010x\n",
1287 XI2C_IOREAD(pdata, 0x2c));
1288 axgbe_printf(1, " IC_INTR_MASK : %010x\n",
1289 XI2C_IOREAD(pdata, 0x30));
1290 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n",
1291 XI2C_IOREAD(pdata, 0x34));
1292 axgbe_printf(1, " IC_RX_TL : %010x\n",
1293 XI2C_IOREAD(pdata, 0x38));
1294 axgbe_printf(1, " IC_TX_TL : %010x\n",
1295 XI2C_IOREAD(pdata, 0x3c));
1296 axgbe_printf(1, " IC_ENABLE : %010x\n",
1297 XI2C_IOREAD(pdata, 0x6c));
1298 axgbe_printf(1, " IC_STATUS : %010x\n",
1299 XI2C_IOREAD(pdata, 0x70));
1300 axgbe_printf(1, " IC_TXFLR : %010x\n",
1301 XI2C_IOREAD(pdata, 0x74));
1302 axgbe_printf(1, " IC_RXFLR : %010x\n",
1303 XI2C_IOREAD(pdata, 0x78));
1304 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n",
1305 XI2C_IOREAD(pdata, 0x9c));
1306 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n",
1307 XI2C_IOREAD(pdata, 0xf4));
1308 }
1309
1310 static void
xgbe_dump_active_vlans(struct xgbe_prv_data * pdata)1311 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1312 {
1313 int i;
1314
1315 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) {
1316 if (i && (i%8 == 0))
1317 axgbe_printf(1, "\n");
1318 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1319 }
1320 axgbe_printf(1, "\n");
1321 }
1322
1323 static void
xgbe_default_config(struct xgbe_prv_data * pdata)1324 xgbe_default_config(struct xgbe_prv_data *pdata)
1325 {
1326 pdata->blen = DMA_SBMR_BLEN_64;
1327 pdata->pbl = DMA_PBL_128;
1328 pdata->aal = 1;
1329 pdata->rd_osr_limit = 8;
1330 pdata->wr_osr_limit = 8;
1331 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1332 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1333 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1334 pdata->rx_sf_mode = MTL_RSF_DISABLE;
1335 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1336 pdata->pause_autoneg = 1;
1337 pdata->tx_pause = 1;
1338 pdata->rx_pause = 1;
1339 pdata->phy_speed = SPEED_UNKNOWN;
1340 pdata->power_down = 0;
1341 pdata->enable_rss = 1;
1342 }
1343
1344 static void
axgbe_setup_sysctl(struct xgbe_prv_data * pdata)1345 axgbe_setup_sysctl(struct xgbe_prv_data *pdata)
1346 {
1347 struct sysctl_ctx_list *clist;
1348 struct sysctl_oid *parent;
1349 struct sysctl_oid_list *top;
1350
1351 clist = device_get_sysctl_ctx(pdata->dev);
1352 parent = device_get_sysctl_tree(pdata->dev);
1353 top = SYSCTL_CHILDREN(parent);
1354 }
1355
1356 static int
axgbe_if_attach_post(if_ctx_t ctx)1357 axgbe_if_attach_post(if_ctx_t ctx)
1358 {
1359 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1360 struct xgbe_prv_data *pdata = &sc->pdata;
1361 struct ifnet *ifp = pdata->netdev;
1362 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1363 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1364 if_softc_ctx_t scctx = sc->scctx;
1365 int i, ret;
1366
1367 /* set split header support based on tunable */
1368 pdata->sph_enable = axgbe_sph_enable;
1369
1370 /* Initialize ECC timestamps */
1371 pdata->tx_sec_period = ticks;
1372 pdata->tx_ded_period = ticks;
1373 pdata->rx_sec_period = ticks;
1374 pdata->rx_ded_period = ticks;
1375 pdata->desc_sec_period = ticks;
1376 pdata->desc_ded_period = ticks;
1377
1378 /* Reset the hardware */
1379 ret = hw_if->exit(&sc->pdata);
1380 if (ret)
1381 axgbe_error("%s: exit error %d\n", __func__, ret);
1382
1383 /* Configure the defaults */
1384 xgbe_default_config(pdata);
1385
1386 /* Set default max values if not provided */
1387 if (!pdata->tx_max_fifo_size)
1388 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1389 if (!pdata->rx_max_fifo_size)
1390 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1391
1392 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__,
1393 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1394
1395 /* Set and validate the number of descriptors for a ring */
1396 MPASS(powerof2(XGBE_TX_DESC_CNT));
1397 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1398 MPASS(powerof2(XGBE_RX_DESC_CNT));
1399 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1400
1401 /* Adjust the number of queues based on interrupts assigned */
1402 if (pdata->channel_irq_count) {
1403 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1404 pdata->channel_irq_count);
1405 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1406 pdata->channel_irq_count);
1407
1408 DBGPR("adjusted TX %u/%u RX %u/%u\n",
1409 pdata->tx_ring_count, pdata->tx_q_count,
1410 pdata->rx_ring_count, pdata->rx_q_count);
1411 }
1412
1413 /* Set channel count based on interrupts assigned */
1414 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1415 scctx->isc_nrxqsets);
1416 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1417
1418 /* Get RSS key */
1419 #ifdef RSS
1420 rss_getkey((uint8_t *)pdata->rss_key);
1421 #else
1422 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
1423 #endif
1424 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
1425 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
1426 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
1427
1428 /* Initialize the PHY device */
1429 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1430 phy_if->phy_init(pdata);
1431
1432 /* Set the coalescing */
1433 xgbe_init_rx_coalesce(&sc->pdata);
1434 xgbe_init_tx_coalesce(&sc->pdata);
1435
1436 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1437 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1438 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1439 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1440 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1441 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1442 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1443 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1444 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1445 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1446 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1447 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1448 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1449
1450 /* Initialize the phy */
1451 pdata->phy_link = -1;
1452 pdata->phy_speed = SPEED_UNKNOWN;
1453 ret = phy_if->phy_reset(pdata);
1454 if (ret)
1455 return (ret);
1456
1457 /* Calculate the Rx buffer size before allocating rings */
1458 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1459 pdata->rx_buf_size = ret;
1460 DBGPR("%s: rx_buf_size %d\n", __func__, ret);
1461
1462 /* Setup RSS lookup table */
1463 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1464 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1465 i % pdata->rx_ring_count);
1466
1467 /*
1468 * Mark the device down until it is initialized, which happens
1469 * when the device is accessed first (for configuring the iface,
1470 * eg: setting IP)
1471 */
1472 set_bit(XGBE_DOWN, &pdata->dev_state);
1473
1474 DBGPR("mtu %d\n", ifp->if_mtu);
1475 scctx->isc_max_frame_size = ifp->if_mtu + 18;
1476 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1477
1478 axgbe_setup_sysctl(pdata);
1479
1480 axgbe_sysctl_init(pdata);
1481
1482 axgbe_pci_init(pdata);
1483
1484 return (0);
1485 } /* axgbe_if_attach_post */
1486
1487 static void
xgbe_free_intr(struct xgbe_prv_data * pdata,struct resource * res,void * tag,int rid)1488 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1489 int rid)
1490 {
1491 if (tag)
1492 bus_teardown_intr(pdata->dev, res, tag);
1493
1494 if (res)
1495 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1496 }
1497
1498 static void
axgbe_interrupts_free(if_ctx_t ctx)1499 axgbe_interrupts_free(if_ctx_t ctx)
1500 {
1501 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1502 struct xgbe_prv_data *pdata = &sc->pdata;
1503 if_softc_ctx_t scctx = sc->scctx;
1504 struct xgbe_channel *channel;
1505 struct if_irq irq;
1506 int i;
1507
1508 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1509
1510 /* Free dev_irq */
1511 iflib_irq_free(ctx, &pdata->dev_irq);
1512
1513 /* Free ecc_irq */
1514 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1515 pdata->ecc_rid);
1516
1517 /* Free i2c_irq */
1518 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1519 pdata->i2c_rid);
1520
1521 /* Free an_irq */
1522 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1523 pdata->an_rid);
1524
1525 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1526
1527 channel = pdata->channel[i];
1528 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1529 irq.ii_res = channel->dma_irq_res;
1530 irq.ii_tag = channel->dma_irq_tag;
1531 iflib_irq_free(ctx, &irq);
1532 }
1533 }
1534
1535 static int
axgbe_if_detach(if_ctx_t ctx)1536 axgbe_if_detach(if_ctx_t ctx)
1537 {
1538 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1539 struct xgbe_prv_data *pdata = &sc->pdata;
1540 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1541 struct resource *mac_res[2];
1542
1543 mac_res[0] = pdata->xgmac_res;
1544 mac_res[1] = pdata->xpcs_res;
1545
1546 phy_if->phy_exit(pdata);
1547
1548 /* Free Interrupts */
1549 axgbe_interrupts_free(ctx);
1550
1551 /* Free workqueues */
1552 taskqueue_free(pdata->dev_workqueue);
1553
1554 /* Release bus resources */
1555 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res);
1556
1557 /* Free VLAN bitmap */
1558 free(pdata->active_vlans, M_AXGBE);
1559
1560 axgbe_sysctl_exit(pdata);
1561
1562 return (0);
1563 } /* axgbe_if_detach */
1564
1565 static void
axgbe_pci_init(struct xgbe_prv_data * pdata)1566 axgbe_pci_init(struct xgbe_prv_data *pdata)
1567 {
1568 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1569 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1570 int ret = 0;
1571
1572 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1573 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__);
1574 return;
1575 }
1576
1577 hw_if->init(pdata);
1578
1579 ret = phy_if->phy_start(pdata);
1580 if (ret) {
1581 axgbe_error("%s: phy start %d\n", __func__, ret);
1582 ret = hw_if->exit(pdata);
1583 if (ret)
1584 axgbe_error("%s: exit error %d\n", __func__, ret);
1585 return;
1586 }
1587
1588 hw_if->enable_tx(pdata);
1589 hw_if->enable_rx(pdata);
1590
1591 xgbe_start_timers(pdata);
1592
1593 clear_bit(XGBE_DOWN, &pdata->dev_state);
1594
1595 xgbe_dump_phy_registers(pdata);
1596 xgbe_dump_prop_registers(pdata);
1597 xgbe_dump_dma_registers(pdata, -1);
1598 xgbe_dump_mtl_registers(pdata);
1599 xgbe_dump_mac_registers(pdata);
1600 xgbe_dump_rmon_counters(pdata);
1601 }
1602
1603 static void
axgbe_if_init(if_ctx_t ctx)1604 axgbe_if_init(if_ctx_t ctx)
1605 {
1606 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1607 struct xgbe_prv_data *pdata = &sc->pdata;
1608
1609 axgbe_pci_init(pdata);
1610 }
1611
1612 static void
axgbe_pci_stop(if_ctx_t ctx)1613 axgbe_pci_stop(if_ctx_t ctx)
1614 {
1615 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1616 struct xgbe_prv_data *pdata = &sc->pdata;
1617 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1618 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1619 int ret;
1620
1621 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1622 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__);
1623 return;
1624 }
1625
1626 xgbe_stop_timers(pdata);
1627 taskqueue_drain_all(pdata->dev_workqueue);
1628
1629 hw_if->disable_tx(pdata);
1630 hw_if->disable_rx(pdata);
1631
1632 phy_if->phy_stop(pdata);
1633
1634 ret = hw_if->exit(pdata);
1635 if (ret)
1636 axgbe_error("%s: exit error %d\n", __func__, ret);
1637
1638 set_bit(XGBE_DOWN, &pdata->dev_state);
1639 }
1640
1641 static void
axgbe_if_stop(if_ctx_t ctx)1642 axgbe_if_stop(if_ctx_t ctx)
1643 {
1644 axgbe_pci_stop(ctx);
1645 }
1646
1647 static void
axgbe_if_disable_intr(if_ctx_t ctx)1648 axgbe_if_disable_intr(if_ctx_t ctx)
1649 {
1650 /* TODO - implement */
1651 }
1652
1653 static void
axgbe_if_enable_intr(if_ctx_t ctx)1654 axgbe_if_enable_intr(if_ctx_t ctx)
1655 {
1656 /* TODO - implement */
1657 }
1658
1659 static int
axgbe_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int ntxqs,int ntxqsets)1660 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs,
1661 int ntxqsets)
1662 {
1663 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1664 struct xgbe_prv_data *pdata = &sc->pdata;
1665 if_softc_ctx_t scctx = sc->scctx;
1666 struct xgbe_channel *channel;
1667 struct xgbe_ring *tx_ring;
1668 int i, j, k;
1669
1670 MPASS(scctx->isc_ntxqsets > 0);
1671 MPASS(scctx->isc_ntxqsets == ntxqsets);
1672 MPASS(ntxqs == 1);
1673
1674 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__,
1675 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1676
1677 for (i = 0 ; i < ntxqsets; i++) {
1678
1679 channel = pdata->channel[i];
1680
1681 tx_ring = (struct xgbe_ring*)malloc(ntxqs *
1682 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1683
1684 if (tx_ring == NULL) {
1685 axgbe_error("Unable to allocate TX ring memory\n");
1686 goto tx_ring_fail;
1687 }
1688
1689 channel->tx_ring = tx_ring;
1690
1691 for (j = 0; j < ntxqs; j++, tx_ring++) {
1692 tx_ring->rdata =
1693 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1694 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1695
1696 /* Get the virtual & physical address of hw queues */
1697 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1698 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1699 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1700 spin_lock_init(&tx_ring->lock);
1701 }
1702 }
1703
1704 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1705
1706 return (0);
1707
1708 tx_ring_fail:
1709
1710 for (j = 0; j < i ; j++) {
1711
1712 channel = pdata->channel[j];
1713
1714 tx_ring = channel->tx_ring;
1715 for (k = 0; k < ntxqs ; k++, tx_ring++) {
1716 if (tx_ring && tx_ring->rdata)
1717 free(tx_ring->rdata, M_AXGBE);
1718 }
1719 free(channel->tx_ring, M_AXGBE);
1720
1721 channel->tx_ring = NULL;
1722 }
1723
1724 return (ENOMEM);
1725
1726 } /* axgbe_if_tx_queues_alloc */
1727
1728 static int
axgbe_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int nrxqs,int nrxqsets)1729 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs,
1730 int nrxqsets)
1731 {
1732 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1733 struct xgbe_prv_data *pdata = &sc->pdata;
1734 if_softc_ctx_t scctx = sc->scctx;
1735 struct xgbe_channel *channel;
1736 struct xgbe_ring *rx_ring;
1737 int i, j, k;
1738
1739 MPASS(scctx->isc_nrxqsets > 0);
1740 MPASS(scctx->isc_nrxqsets == nrxqsets);
1741 if (!pdata->sph_enable) {
1742 MPASS(nrxqs == 1);
1743 } else {
1744 MPASS(nrxqs == 2);
1745 }
1746
1747 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__,
1748 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1749
1750 for (i = 0 ; i < nrxqsets; i++) {
1751
1752 channel = pdata->channel[i];
1753
1754 rx_ring = (struct xgbe_ring*)malloc(nrxqs *
1755 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1756
1757 if (rx_ring == NULL) {
1758 axgbe_error("Unable to allocate RX ring memory\n");
1759 goto rx_ring_fail;
1760 }
1761
1762 channel->rx_ring = rx_ring;
1763
1764 for (j = 0; j < nrxqs; j++, rx_ring++) {
1765 rx_ring->rdata =
1766 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1767 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1768
1769 /* Get the virtual and physical address of the hw queues */
1770 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1771 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1772 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1773 spin_lock_init(&rx_ring->lock);
1774 }
1775 }
1776
1777 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1778
1779 return (0);
1780
1781 rx_ring_fail:
1782
1783 for (j = 0 ; j < i ; j++) {
1784
1785 channel = pdata->channel[j];
1786
1787 rx_ring = channel->rx_ring;
1788 for (k = 0; k < nrxqs ; k++, rx_ring++) {
1789 if (rx_ring && rx_ring->rdata)
1790 free(rx_ring->rdata, M_AXGBE);
1791 }
1792 free(channel->rx_ring, M_AXGBE);
1793
1794 channel->rx_ring = NULL;
1795 }
1796
1797 return (ENOMEM);
1798
1799 } /* axgbe_if_rx_queues_alloc */
1800
1801 static void
axgbe_if_queues_free(if_ctx_t ctx)1802 axgbe_if_queues_free(if_ctx_t ctx)
1803 {
1804 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1805 struct xgbe_prv_data *pdata = &sc->pdata;
1806 if_softc_ctx_t scctx = sc->scctx;
1807 if_shared_ctx_t sctx = sc->sctx;
1808 struct xgbe_channel *channel;
1809 struct xgbe_ring *tx_ring;
1810 struct xgbe_ring *rx_ring;
1811 int i, j;
1812
1813 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1814
1815 channel = pdata->channel[i];
1816
1817 tx_ring = channel->tx_ring;
1818 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1819 if (tx_ring && tx_ring->rdata)
1820 free(tx_ring->rdata, M_AXGBE);
1821 }
1822 free(channel->tx_ring, M_AXGBE);
1823 channel->tx_ring = NULL;
1824 }
1825
1826 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1827
1828 channel = pdata->channel[i];
1829
1830 rx_ring = channel->rx_ring;
1831 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1832 if (rx_ring && rx_ring->rdata)
1833 free(rx_ring->rdata, M_AXGBE);
1834 }
1835 free(channel->rx_ring, M_AXGBE);
1836 channel->rx_ring = NULL;
1837 }
1838
1839 axgbe_free_channels(sc);
1840 } /* axgbe_if_queues_free */
1841
1842 static void
axgbe_if_vlan_register(if_ctx_t ctx,uint16_t vtag)1843 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag)
1844 {
1845 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1846 struct xgbe_prv_data *pdata = &sc->pdata;
1847 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1848
1849 if (!bit_test(pdata->active_vlans, vtag)) {
1850 axgbe_printf(0, "Registering VLAN %d\n", vtag);
1851
1852 bit_set(pdata->active_vlans, vtag);
1853 hw_if->update_vlan_hash_table(pdata);
1854 pdata->num_active_vlans++;
1855
1856 axgbe_printf(1, "Total active vlans: %d\n",
1857 pdata->num_active_vlans);
1858 } else
1859 axgbe_printf(0, "VLAN %d already registered\n", vtag);
1860
1861 xgbe_dump_active_vlans(pdata);
1862 }
1863
1864 static void
axgbe_if_vlan_unregister(if_ctx_t ctx,uint16_t vtag)1865 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag)
1866 {
1867 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1868 struct xgbe_prv_data *pdata = &sc->pdata;
1869 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1870
1871 if (pdata->num_active_vlans == 0) {
1872 axgbe_printf(1, "No active VLANs to unregister\n");
1873 return;
1874 }
1875
1876 if (bit_test(pdata->active_vlans, vtag)){
1877 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1878
1879 bit_clear(pdata->active_vlans, vtag);
1880 hw_if->update_vlan_hash_table(pdata);
1881 pdata->num_active_vlans--;
1882
1883 axgbe_printf(1, "Total active vlans: %d\n",
1884 pdata->num_active_vlans);
1885 } else
1886 axgbe_printf(0, "VLAN %d already unregistered\n", vtag);
1887
1888 xgbe_dump_active_vlans(pdata);
1889 }
1890
1891 #if __FreeBSD_version >= 1300000
1892 static bool
axgbe_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1893 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1894 {
1895 switch (event) {
1896 case IFLIB_RESTART_VLAN_CONFIG:
1897 default:
1898 return (true);
1899 }
1900 }
1901 #endif
1902
1903 static int
axgbe_if_msix_intr_assign(if_ctx_t ctx,int msix)1904 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
1905 {
1906 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1907 struct xgbe_prv_data *pdata = &sc->pdata;
1908 if_softc_ctx_t scctx = sc->scctx;
1909 struct xgbe_channel *channel;
1910 struct if_irq irq;
1911 int i, error, rid = 0, flags;
1912 char buf[16];
1913
1914 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1915
1916 pdata->isr_as_tasklet = 1;
1917
1918 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1919 pdata->irq_count = 1;
1920 pdata->channel_irq_count = 1;
1921 return (0);
1922 }
1923
1924 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix,
1925 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1926
1927 flags = RF_ACTIVE;
1928
1929 /* DEV INTR SETUP */
1930 rid++;
1931 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1932 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq");
1933 if (error) {
1934 axgbe_error("Failed to register device interrupt rid %d name %s\n",
1935 rid, "dev_irq");
1936 return (error);
1937 }
1938
1939 /* ECC INTR SETUP */
1940 rid++;
1941 pdata->ecc_rid = rid;
1942 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1943 &rid, flags);
1944 if (!pdata->ecc_irq_res) {
1945 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1946 rid, "ecc_irq");
1947 return (ENOMEM);
1948 }
1949
1950 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1951 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1952 if (error) {
1953 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1954 rid, "ecc_irq", error);
1955 return (error);
1956 }
1957
1958 /* I2C INTR SETUP */
1959 rid++;
1960 pdata->i2c_rid = rid;
1961 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1962 &rid, flags);
1963 if (!pdata->i2c_irq_res) {
1964 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1965 rid, "i2c_irq");
1966 return (ENOMEM);
1967 }
1968
1969 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1970 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1971 if (error) {
1972 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1973 rid, "i2c_irq", error);
1974 return (error);
1975 }
1976
1977 /* AN INTR SETUP */
1978 rid++;
1979 pdata->an_rid = rid;
1980 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1981 &rid, flags);
1982 if (!pdata->an_irq_res) {
1983 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1984 rid, "an_irq");
1985 return (ENOMEM);
1986 }
1987
1988 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
1989 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
1990 if (error) {
1991 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1992 rid, "an_irq", error);
1993 return (error);
1994 }
1995
1996 pdata->per_channel_irq = 1;
1997 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
1998 rid++;
1999 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
2000
2001 channel = pdata->channel[i];
2002
2003 snprintf(buf, sizeof(buf), "rxq%d", i);
2004 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX,
2005 axgbe_msix_que, channel, channel->queue_index, buf);
2006
2007 if (error) {
2008 axgbe_error("Failed to allocated que int %d err: %d\n",
2009 i, error);
2010 return (error);
2011 }
2012
2013 channel->dma_irq_rid = rid;
2014 channel->dma_irq_res = irq.ii_res;
2015 channel->dma_irq_tag = irq.ii_tag;
2016 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
2017 __func__, scctx->isc_nrxqsets, i, rid);
2018 }
2019 pdata->irq_count = msix;
2020 pdata->channel_irq_count = scctx->isc_nrxqsets;
2021
2022 for (i = 0; i < scctx->isc_ntxqsets; i++) {
2023
2024 channel = pdata->channel[i];
2025
2026 snprintf(buf, sizeof(buf), "txq%d", i);
2027 irq.ii_res = channel->dma_irq_res;
2028 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
2029 channel->queue_index, buf);
2030 }
2031
2032 return (0);
2033 } /* axgbe_if_msix_intr_assign */
2034
2035 static int
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2036 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2037 {
2038 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2039 enum xgbe_int int_id;
2040
2041 if (channel->tx_ring && channel->rx_ring)
2042 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2043 else if (channel->tx_ring)
2044 int_id = XGMAC_INT_DMA_CH_SR_TI;
2045 else if (channel->rx_ring)
2046 int_id = XGMAC_INT_DMA_CH_SR_RI;
2047 else
2048 return (-1);
2049
2050 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
2051 __func__, channel->queue_index, int_id);
2052 return (hw_if->enable_int(channel, int_id));
2053 }
2054
2055 static void
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2056 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2057 {
2058 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2059 enum xgbe_int int_id;
2060
2061 if (channel->tx_ring && channel->rx_ring)
2062 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2063 else if (channel->tx_ring)
2064 int_id = XGMAC_INT_DMA_CH_SR_TI;
2065 else if (channel->rx_ring)
2066 int_id = XGMAC_INT_DMA_CH_SR_RI;
2067 else
2068 return;
2069
2070 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
2071 __func__, channel->queue_index, int_id);
2072 hw_if->disable_int(channel, int_id);
2073 }
2074
2075 static void
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)2076 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2077 {
2078 unsigned int i;
2079
2080 for (i = 0; i < pdata->channel_count; i++)
2081 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2082 }
2083
2084 static int
axgbe_msix_que(void * arg)2085 axgbe_msix_que(void *arg)
2086 {
2087 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2088 struct xgbe_prv_data *pdata = channel->pdata;
2089 unsigned int dma_ch_isr, dma_status;
2090
2091 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n",
2092 __func__, channel->queue_index,
2093 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2094 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2095 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2096 XGMAC_IOREAD(pdata, DMA_ISR),
2097 XGMAC_IOREAD(pdata, MAC_ISR));
2098
2099 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2100
2101 /* Disable Tx and Rx channel interrupts */
2102 xgbe_disable_rx_tx_int(pdata, channel);
2103
2104 /* Clear the interrupts */
2105 dma_status = 0;
2106 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
2107 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
2108 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2109
2110 return (FILTER_SCHEDULE_THREAD);
2111 }
2112
2113 static int
axgbe_dev_isr(void * arg)2114 axgbe_dev_isr(void *arg)
2115 {
2116 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2117 struct xgbe_prv_data *pdata = &sc->pdata;
2118 struct xgbe_channel *channel;
2119 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2120 unsigned int i, dma_isr, dma_ch_isr;
2121 unsigned int mac_isr, mac_mdioisr;
2122 int ret = FILTER_HANDLED;
2123
2124 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2125 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr);
2126
2127 if (!dma_isr)
2128 return (FILTER_HANDLED);
2129
2130 for (i = 0; i < pdata->channel_count; i++) {
2131
2132 if (!(dma_isr & (1 << i)))
2133 continue;
2134
2135 channel = pdata->channel[i];
2136
2137 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2138 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2139 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2140 DMA_CH_DSR));
2141
2142 /*
2143 * The TI or RI interrupt bits may still be set even if using
2144 * per channel DMA interrupts. Check to be sure those are not
2145 * enabled before using the private data napi structure.
2146 */
2147 if (!pdata->per_channel_irq &&
2148 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
2149 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
2150
2151 /* Disable Tx and Rx interrupts */
2152 xgbe_disable_rx_tx_ints(pdata);
2153 } else {
2154
2155 /*
2156 * Don't clear Rx/Tx status if doing per channel DMA
2157 * interrupts, these will be cleared by the ISR for
2158 * per channel DMA interrupts
2159 */
2160 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
2161 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
2162 }
2163
2164 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
2165 pdata->ext_stats.rx_buffer_unavailable++;
2166
2167 /* Restart the device on a Fatal Bus Error */
2168 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
2169 axgbe_error("%s: Fatal bus error reported 0x%x\n",
2170 __func__, dma_ch_isr);
2171
2172 /* Clear all interrupt signals */
2173 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2174
2175 ret = FILTER_SCHEDULE_THREAD;
2176 }
2177
2178 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
2179
2180 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2181 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr);
2182
2183 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
2184 hw_if->tx_mmc_int(pdata);
2185
2186 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
2187 hw_if->rx_mmc_int(pdata);
2188
2189 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2190 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2191
2192 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
2193 SNGLCOMPINT))
2194 wakeup_one(pdata);
2195 }
2196
2197 }
2198
2199 return (ret);
2200 } /* axgbe_dev_isr */
2201
2202 static void
axgbe_i2c_isr(void * arg)2203 axgbe_i2c_isr(void *arg)
2204 {
2205 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2206
2207 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2208 }
2209
2210 static void
axgbe_ecc_isr(void * arg)2211 axgbe_ecc_isr(void *arg)
2212 {
2213 /* TODO - implement */
2214 }
2215
2216 static void
axgbe_an_isr(void * arg)2217 axgbe_an_isr(void *arg)
2218 {
2219 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2220
2221 sc->pdata.phy_if.an_isr(&sc->pdata);
2222 }
2223
2224 static int
axgbe_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2225 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2226 {
2227 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2228 struct xgbe_prv_data *pdata = &sc->pdata;
2229 int ret;
2230
2231 if (qid < pdata->tx_q_count) {
2232 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2233 if (ret) {
2234 axgbe_error("Enable TX INT failed\n");
2235 return (ret);
2236 }
2237 } else
2238 axgbe_error("Queue ID exceed channel count\n");
2239
2240 return (0);
2241 }
2242
2243 static int
axgbe_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2244 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2245 {
2246 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2247 struct xgbe_prv_data *pdata = &sc->pdata;
2248 int ret;
2249
2250 if (qid < pdata->rx_q_count) {
2251 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2252 if (ret) {
2253 axgbe_error("Enable RX INT failed\n");
2254 return (ret);
2255 }
2256 } else
2257 axgbe_error("Queue ID exceed channel count\n");
2258
2259 return (0);
2260 }
2261
2262 static void
axgbe_if_update_admin_status(if_ctx_t ctx)2263 axgbe_if_update_admin_status(if_ctx_t ctx)
2264 {
2265 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2266 struct xgbe_prv_data *pdata = &sc->pdata;
2267
2268 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__,
2269 pdata->phy_link, sc->link_status, pdata->phy.speed);
2270
2271 if (pdata->phy_link < 0)
2272 return;
2273
2274 if (pdata->phy_link) {
2275 if (sc->link_status == LINK_STATE_DOWN) {
2276 sc->link_status = LINK_STATE_UP;
2277 if (pdata->phy.speed & SPEED_10000)
2278 iflib_link_state_change(ctx, LINK_STATE_UP,
2279 IF_Gbps(10));
2280 else if (pdata->phy.speed & SPEED_2500)
2281 iflib_link_state_change(ctx, LINK_STATE_UP,
2282 IF_Gbps(2.5));
2283 else if (pdata->phy.speed & SPEED_1000)
2284 iflib_link_state_change(ctx, LINK_STATE_UP,
2285 IF_Gbps(1));
2286 else if (pdata->phy.speed & SPEED_100)
2287 iflib_link_state_change(ctx, LINK_STATE_UP,
2288 IF_Mbps(100));
2289 else if (pdata->phy.speed & SPEED_10)
2290 iflib_link_state_change(ctx, LINK_STATE_UP,
2291 IF_Mbps(10));
2292 }
2293 } else {
2294 if (sc->link_status == LINK_STATE_UP) {
2295 sc->link_status = LINK_STATE_DOWN;
2296 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2297 }
2298 }
2299 }
2300
2301 static int
axgbe_if_media_change(if_ctx_t ctx)2302 axgbe_if_media_change(if_ctx_t ctx)
2303 {
2304 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2305 struct ifmedia *ifm = iflib_get_media(ctx);
2306
2307 sx_xlock(&sc->pdata.an_mutex);
2308 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2309 return (EINVAL);
2310
2311 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2312 case IFM_10G_KR:
2313 sc->pdata.phy.speed = SPEED_10000;
2314 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2315 break;
2316 case IFM_2500_KX:
2317 sc->pdata.phy.speed = SPEED_2500;
2318 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2319 break;
2320 case IFM_1000_KX:
2321 sc->pdata.phy.speed = SPEED_1000;
2322 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2323 break;
2324 case IFM_100_TX:
2325 sc->pdata.phy.speed = SPEED_100;
2326 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2327 break;
2328 case IFM_AUTO:
2329 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2330 break;
2331 }
2332 sx_xunlock(&sc->pdata.an_mutex);
2333
2334 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2335 }
2336
2337 static int
axgbe_if_promisc_set(if_ctx_t ctx,int flags)2338 axgbe_if_promisc_set(if_ctx_t ctx, int flags)
2339 {
2340 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2341 struct xgbe_prv_data *pdata = &sc->pdata;
2342 struct ifnet *ifp = pdata->netdev;
2343
2344 axgbe_printf(1, "%s: MAC_PFR 0x%x drv_flags 0x%x if_flags 0x%x\n",
2345 __func__, XGMAC_IOREAD(pdata, MAC_PFR), ifp->if_drv_flags, ifp->if_flags);
2346
2347 if (ifp->if_flags & IFF_PPROMISC) {
2348
2349 axgbe_printf(1, "User requested to enter promisc mode\n");
2350
2351 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) {
2352 axgbe_printf(1, "Already in promisc mode\n");
2353 return (0);
2354 }
2355
2356 axgbe_printf(1, "Entering promisc mode\n");
2357 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
2358 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
2359 } else {
2360
2361 axgbe_printf(1, "User requested to leave promisc mode\n");
2362
2363 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) {
2364 axgbe_printf(1, "Already not in promisc mode\n");
2365 return (0);
2366 }
2367
2368 axgbe_printf(1, "Leaving promisc mode\n");
2369 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
2370 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
2371 }
2372
2373 return (0);
2374 }
2375
2376 static uint64_t
axgbe_if_get_counter(if_ctx_t ctx,ift_counter cnt)2377 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2378 {
2379 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2380 struct ifnet *ifp = iflib_get_ifp(ctx);
2381 struct xgbe_prv_data *pdata = &sc->pdata;
2382 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2383
2384 pdata->hw_if.read_mmc_stats(pdata);
2385
2386 switch(cnt) {
2387 case IFCOUNTER_IPACKETS:
2388 return (pstats->rxframecount_gb);
2389 case IFCOUNTER_IERRORS:
2390 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2391 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2392 case IFCOUNTER_OPACKETS:
2393 return (pstats->txframecount_gb);
2394 case IFCOUNTER_OERRORS:
2395 return (pstats->txframecount_gb - pstats->txframecount_g);
2396 case IFCOUNTER_IBYTES:
2397 return (pstats->rxoctetcount_gb);
2398 case IFCOUNTER_OBYTES:
2399 return (pstats->txoctetcount_gb);
2400 default:
2401 return (if_get_counter_default(ifp, cnt));
2402 }
2403 }
2404
2405 static int
axgbe_if_mtu_set(if_ctx_t ctx,uint32_t mtu)2406 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
2407 {
2408 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2409 struct xgbe_prv_data *pdata = &sc->pdata;
2410 int ret;
2411
2412 if (mtu > XGMAC_JUMBO_PACKET_MTU)
2413 return (EINVAL);
2414
2415 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2416 pdata->rx_buf_size = ret;
2417 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret);
2418
2419 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2420 return (0);
2421 }
2422
2423 static void
axgbe_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)2424 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2425 {
2426 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2427 struct xgbe_prv_data *pdata = &sc->pdata;
2428
2429 ifmr->ifm_status = IFM_AVALID;
2430 if (!sc->pdata.phy.link)
2431 return;
2432
2433 ifmr->ifm_active = IFM_ETHER;
2434 ifmr->ifm_status |= IFM_ACTIVE;
2435
2436 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2437 pdata->phy_if.phy_impl.cur_mode(pdata));
2438 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2439
2440 ifmr->ifm_active |= IFM_FDX;
2441 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2442 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2443 }
2444