1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_IOCTL_H__ 32 #define __T4_IOCTL_H__ 33 34 #include <sys/types.h> 35 #include <net/ethernet.h> 36 #include <net/bpf.h> 37 38 /* 39 * Ioctl commands specific to this driver. 40 */ 41 enum { 42 T4_GETREG = 0x40, /* read register */ 43 T4_SETREG, /* write register */ 44 T4_REGDUMP, /* dump of all registers */ 45 T4_GET_FILTER_MODE, /* get global filter mode */ 46 T4_SET_FILTER_MODE, /* set global filter mode */ 47 T4_GET_FILTER, /* get information about a filter */ 48 T4_SET_FILTER, /* program a filter */ 49 T4_DEL_FILTER, /* delete a filter */ 50 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 51 T4_LOAD_FW, /* flash firmware */ 52 T4_GET_MEM, /* read memory */ 53 T4_GET_I2C, /* read from i2c addressible device */ 54 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 55 T4_SET_OFLD_POLICY, /* Set offload policy */ 56 T4_SET_SCHED_CLASS, /* set sched class */ 57 T4_SET_SCHED_QUEUE, /* set queue class */ 58 T4_GET_TRACER, /* get information about a tracer */ 59 T4_SET_TRACER, /* program a tracer */ 60 T4_LOAD_CFG, /* copy a config file to card's flash */ 61 T4_LOAD_BOOT, /* flash boot rom */ 62 T4_LOAD_BOOTCFG, /* flash bootcfg */ 63 T4_CUDBG_DUMP, /* debug dump of chip state */ 64 }; 65 66 struct t4_reg { 67 uint32_t addr; 68 uint32_t size; 69 uint64_t val; 70 }; 71 72 #define T4_REGDUMP_SIZE (160 * 1024) 73 #define T5_REGDUMP_SIZE (332 * 1024) 74 struct t4_regdump { 75 uint32_t version; 76 uint32_t len; /* bytes */ 77 uint32_t *data; 78 }; 79 80 struct t4_data { 81 uint32_t len; 82 uint8_t *data; 83 }; 84 85 struct t4_bootrom { 86 uint32_t pf_offset; 87 uint32_t pfidx_addr; 88 uint32_t len; 89 uint8_t *data; 90 }; 91 92 struct t4_i2c_data { 93 uint8_t port_id; 94 uint8_t dev_addr; 95 uint8_t offset; 96 uint8_t len; 97 uint8_t data[8]; 98 }; 99 100 /* 101 * A hardware filter is some valid combination of these. 102 */ 103 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 104 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 105 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 106 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 107 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 108 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 109 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 110 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 111 #define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 112 #define T4_FILTER_VLAN 0x200 /* VLAN ID */ 113 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 114 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 115 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 116 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 117 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 118 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 119 120 #define T4_FILTER_IC_VNIC 0x80000000 /* TP Ingress Config's F_VNIC 121 bit. It indicates whether 122 T4_FILTER_VNIC bit means VNIC 123 id (PF/VF) or outer VLAN. 124 0 = oVLAN, 1 = VNIC */ 125 126 /* Filter action */ 127 enum { 128 FILTER_PASS = 0, /* default */ 129 FILTER_DROP, 130 FILTER_SWITCH 131 }; 132 133 /* 802.1q manipulation on FILTER_SWITCH */ 134 enum { 135 VLAN_NOCHANGE = 0, /* default */ 136 VLAN_REMOVE, 137 VLAN_INSERT, 138 VLAN_REWRITE 139 }; 140 141 /* MPS match type */ 142 enum { 143 UCAST_EXACT = 0, /* exact unicast match */ 144 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 145 MCAST_EXACT = 2, /* exact multicast match */ 146 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 147 PROMISC = 4, /* no match but port is promiscuous */ 148 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 149 BCAST = 6, /* broadcast packet */ 150 }; 151 152 /* Rx steering */ 153 enum { 154 DST_MODE_QUEUE, /* queue is directly specified by filter */ 155 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 156 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 157 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 158 RSS subtable */ 159 }; 160 161 enum { 162 NAT_MODE_NONE = 0, /* No NAT performed */ 163 NAT_MODE_DIP, /* NAT on Dst IP */ 164 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 165 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 166 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 167 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 168 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 169 NAT_MODE_ALL /* NAT on entire 4-tuple */ 170 }; 171 172 struct t4_filter_tuple { 173 /* 174 * These are always available. 175 */ 176 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 177 uint8_t dip[16]; /* destination IP address (IPv4 in [3:0]) */ 178 uint16_t sport; /* source port */ 179 uint16_t dport; /* destination port */ 180 181 /* 182 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 183 * is used to select the global mode and all filters are limited to the 184 * set of fields allowed by the global mode. 185 */ 186 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 187 uint16_t vlan; /* VLAN tag */ 188 uint16_t ethtype; /* Ethernet type */ 189 uint8_t tos; /* TOS/Traffic Type */ 190 uint8_t proto; /* protocol type */ 191 uint32_t fcoe:1; /* FCoE packet */ 192 uint32_t iport:3; /* ingress port */ 193 uint32_t matchtype:3; /* MPS match type */ 194 uint32_t frag:1; /* fragmentation extension header */ 195 uint32_t macidx:9; /* exact match MAC index */ 196 uint32_t vlan_vld:1; /* VLAN valid */ 197 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 198 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 199 }; 200 201 struct t4_filter_specification { 202 uint32_t hitcnts:1; /* count filter hits in TCB */ 203 uint32_t prio:1; /* filter has priority over active/server */ 204 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 205 uint32_t hash:1; /* 0 => LE TCAM, 1 => Hash */ 206 uint32_t action:2; /* drop, pass, switch */ 207 uint32_t rpttid:1; /* report TID in RSS hash field */ 208 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 209 uint32_t iq:10; /* ingress queue */ 210 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 211 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 212 /* 1 => TCB contains IQ ID */ 213 214 /* 215 * Switch proxy/rewrite fields. An ingress packet which matches a 216 * filter with "switch" set will be looped back out as an egress 217 * packet -- potentially with some Ethernet header rewriting. 218 */ 219 uint32_t eport:2; /* egress port to switch packet out */ 220 uint32_t newdmac:1; /* rewrite destination MAC address */ 221 uint32_t newsmac:1; /* rewrite source MAC address */ 222 uint32_t swapmac:1; /* swap SMAC/DMAC for loopback packet */ 223 uint32_t newvlan:2; /* rewrite VLAN Tag */ 224 uint32_t nat_mode:3; /* NAT operation mode */ 225 uint32_t nat_flag_chk:1;/* check TCP flags before NAT'ing */ 226 uint32_t nat_seq_chk; /* sequence value to use for NAT check*/ 227 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 228 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 229 uint16_t vlan; /* VLAN Tag to insert */ 230 231 uint8_t nat_dip[16]; /* destination IP to use after NAT'ing */ 232 uint8_t nat_sip[16]; /* source IP to use after NAT'ing */ 233 uint16_t nat_dport; /* destination port to use after NAT'ing */ 234 uint16_t nat_sport; /* source port to use after NAT'ing */ 235 236 /* 237 * Filter rule value/mask pairs. 238 */ 239 struct t4_filter_tuple val; 240 struct t4_filter_tuple mask; 241 }; 242 243 struct t4_filter { 244 uint32_t idx; 245 uint16_t l2tidx; 246 uint16_t smtidx; 247 uint64_t hits; 248 struct t4_filter_specification fs; 249 }; 250 251 /* Tx Scheduling Class parameters */ 252 struct t4_sched_class_params { 253 int8_t level; /* scheduler hierarchy level */ 254 int8_t mode; /* per-class or per-flow */ 255 int8_t rateunit; /* bit or packet rate */ 256 int8_t ratemode; /* %port relative or kbps absolute */ 257 int8_t channel; /* scheduler channel [0..N] */ 258 int8_t cl; /* scheduler class [0..N] */ 259 int32_t minrate; /* minimum rate */ 260 int32_t maxrate; /* maximum rate */ 261 int16_t weight; /* percent weight */ 262 int16_t pktsize; /* average packet size */ 263 }; 264 265 /* 266 * Support for "sched-class" command to allow a TX Scheduling Class to be 267 * programmed with various parameters. 268 */ 269 struct t4_sched_params { 270 int8_t subcmd; /* sub-command */ 271 int8_t type; /* packet or flow */ 272 union { 273 struct { /* sub-command SCHED_CLASS_CONFIG */ 274 int8_t minmax; /* minmax enable */ 275 } config; 276 struct t4_sched_class_params params; 277 uint8_t reserved[6 + 8 * 8]; 278 } u; 279 }; 280 281 enum { 282 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 283 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 284 }; 285 286 enum { 287 SCHED_CLASS_TYPE_PACKET, 288 }; 289 290 enum { 291 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 292 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 293 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 294 }; 295 296 enum { 297 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 298 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 299 }; 300 301 enum { 302 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 303 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 304 }; 305 306 enum { 307 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 308 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 309 }; 310 311 /* 312 * Support for "sched_queue" command to allow one or more NIC TX Queues to be 313 * bound to a TX Scheduling Class. 314 */ 315 struct t4_sched_queue { 316 uint8_t port; 317 int8_t queue; /* queue index; -1 => all queues */ 318 int8_t cl; /* class index; -1 => unbind */ 319 }; 320 321 #define T4_SGE_CONTEXT_SIZE 24 322 enum { 323 SGE_CONTEXT_EGRESS, 324 SGE_CONTEXT_INGRESS, 325 SGE_CONTEXT_FLM, 326 SGE_CONTEXT_CNM 327 }; 328 329 struct t4_sge_context { 330 uint32_t mem_id; 331 uint32_t cid; 332 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 333 }; 334 335 struct t4_mem_range { 336 uint32_t addr; 337 uint32_t len; 338 uint32_t *data; 339 }; 340 341 #define T4_TRACE_LEN 112 342 struct t4_trace_params { 343 uint32_t data[T4_TRACE_LEN / 4]; 344 uint32_t mask[T4_TRACE_LEN / 4]; 345 uint16_t snap_len; 346 uint16_t min_len; 347 uint8_t skip_ofst; 348 uint8_t skip_len; 349 uint8_t invert; 350 uint8_t port; 351 }; 352 353 struct t4_tracer { 354 uint8_t idx; 355 uint8_t enabled; 356 uint8_t valid; 357 struct t4_trace_params tp; 358 }; 359 360 struct t4_cudbg_dump { 361 uint8_t wr_flash; 362 uint8_t bitmap[16]; 363 uint32_t len; 364 uint8_t *data; 365 }; 366 367 enum { 368 OPEN_TYPE_LISTEN = 'L', 369 OPEN_TYPE_ACTIVE = 'A', 370 OPEN_TYPE_PASSIVE = 'P', 371 OPEN_TYPE_DONTCARE = 'D', 372 }; 373 374 struct offload_settings { 375 int8_t offload; 376 int8_t rx_coalesce; 377 int8_t cong_algo; 378 int8_t sched_class; 379 int8_t tstamp; 380 int8_t sack; 381 int8_t nagle; 382 int8_t ecn; 383 int8_t ddp; 384 int8_t tls; 385 int16_t txq; 386 int16_t rxq; 387 int16_t mss; 388 }; 389 390 struct offload_rule { 391 char open_type; 392 struct offload_settings settings; 393 struct bpf_program bpf_prog; /* compiled program/filter */ 394 }; 395 396 /* 397 * An offload policy consists of a set of rules matched in sequence. The 398 * settings of the first rule that matches are applied to that connection. 399 */ 400 struct t4_offload_policy { 401 uint32_t nrules; 402 struct offload_rule *rule; 403 }; 404 405 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 406 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 407 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 408 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 409 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 410 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 411 #define CHELSIO_T4_SET_FILTER _IOWR('f', T4_SET_FILTER, struct t4_filter) 412 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 413 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 414 struct t4_sge_context) 415 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 416 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 417 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 418 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 419 #define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 420 struct t4_sched_params) 421 #define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 422 struct t4_sched_queue) 423 #define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 424 #define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 425 #define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data) 426 #define CHELSIO_T4_LOAD_BOOT _IOW('f', T4_LOAD_BOOT, struct t4_bootrom) 427 #define CHELSIO_T4_LOAD_BOOTCFG _IOW('f', T4_LOAD_BOOTCFG, struct t4_data) 428 #define CHELSIO_T4_CUDBG_DUMP _IOWR('f', T4_CUDBG_DUMP, struct t4_cudbg_dump) 429 #define CHELSIO_T4_SET_OFLD_POLICY _IOW('f', T4_SET_OFLD_POLICY, struct t4_offload_policy) 430 #endif 431