1 /* Common target dependent code for GDB on AArch64 systems. 2 3 Copyright (C) 2009-2024 Free Software Foundation, Inc. 4 Contributed by ARM Ltd. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef AARCH64_TDEP_H 23 #define AARCH64_TDEP_H 24 25 #include "arch/aarch64.h" 26 #include "displaced-stepping.h" 27 #include "infrun.h" 28 #include "gdbarch.h" 29 30 /* Forward declarations. */ 31 struct gdbarch; 32 struct regset; 33 34 /* AArch64 Dwarf register numbering. */ 35 #define AARCH64_DWARF_X0 0 36 #define AARCH64_DWARF_SP 31 37 #define AARCH64_DWARF_PC 32 38 #define AARCH64_DWARF_RA_SIGN_STATE 34 39 #define AARCH64_DWARF_V0 64 40 #define AARCH64_DWARF_SVE_VG 46 41 #define AARCH64_DWARF_SVE_FFR 47 42 #define AARCH64_DWARF_SVE_P0 48 43 #define AARCH64_DWARF_SVE_Z0 96 44 45 /* Size of integer registers. */ 46 #define X_REGISTER_SIZE 8 47 #define B_REGISTER_SIZE 1 48 #define H_REGISTER_SIZE 2 49 #define S_REGISTER_SIZE 4 50 #define D_REGISTER_SIZE 8 51 #define Q_REGISTER_SIZE 16 52 53 /* Total number of general (X) registers. */ 54 #define AARCH64_X_REGISTER_COUNT 32 55 /* Total number of D registers. */ 56 #define AARCH64_D_REGISTER_COUNT 32 57 58 /* The maximum number of modified instructions generated for one 59 single-stepped instruction. */ 60 #define AARCH64_DISPLACED_MODIFIED_INSNS 1 61 62 /* Target-dependent structure in gdbarch. */ 63 struct aarch64_gdbarch_tdep : gdbarch_tdep_base 64 { 65 /* Lowest address at which instructions will appear. */ 66 CORE_ADDR lowest_pc = 0; 67 68 /* Offset to PC value in jump buffer. If this is negative, longjmp 69 support will be disabled. */ 70 int jb_pc = 0; 71 72 /* And the size of each entry in the buf. */ 73 size_t jb_elt_size = 0; 74 75 /* Types for AdvSISD registers. */ 76 struct type *vnq_type = nullptr; 77 struct type *vnd_type = nullptr; 78 struct type *vns_type = nullptr; 79 struct type *vnh_type = nullptr; 80 struct type *vnb_type = nullptr; 81 struct type *vnv_type = nullptr; 82 83 /* Types for SME ZA tiles and tile slices pseudo-registers. */ 84 struct type *sme_tile_type_q = nullptr; 85 struct type *sme_tile_type_d = nullptr; 86 struct type *sme_tile_type_s = nullptr; 87 struct type *sme_tile_type_h = nullptr; 88 struct type *sme_tile_type_b = nullptr; 89 struct type *sme_tile_slice_type_q = nullptr; 90 struct type *sme_tile_slice_type_d = nullptr; 91 struct type *sme_tile_slice_type_s = nullptr; 92 struct type *sme_tile_slice_type_h = nullptr; 93 struct type *sme_tile_slice_type_b = nullptr; 94 95 /* Vector of names for SME pseudo-registers. The number of elements is 96 different for each distinct svl value. */ 97 std::vector<std::string> sme_pseudo_names; 98 99 /* syscall record. */ 100 int (*aarch64_syscall_record) (struct regcache *regcache, 101 unsigned long svc_number) = nullptr; 102 103 /* The VQ value for SVE targets, or zero if SVE is not supported. */ 104 uint64_t vq = 0; 105 106 /* Returns true if the target supports SVE. */ has_sveaarch64_gdbarch_tdep107 bool has_sve () const 108 { 109 return vq != 0; 110 } 111 112 int pauth_reg_base = 0; 113 /* Number of pauth masks. */ 114 int pauth_reg_count = 0; 115 int ra_sign_state_regnum = 0; 116 117 /* Returns true if the target supports pauth. */ has_pauthaarch64_gdbarch_tdep118 bool has_pauth () const 119 { 120 return pauth_reg_base != -1; 121 } 122 123 /* First MTE register. This is -1 if no MTE registers are available. */ 124 int mte_reg_base = 0; 125 126 /* Returns true if the target supports MTE. */ has_mteaarch64_gdbarch_tdep127 bool has_mte () const 128 { 129 return mte_reg_base != -1; 130 } 131 132 /* TLS registers. This is -1 if the TLS registers are not available. */ 133 int tls_regnum_base = 0; 134 int tls_register_count = 0; 135 has_tlsaarch64_gdbarch_tdep136 bool has_tls() const 137 { 138 return tls_regnum_base != -1; 139 } 140 141 /* The W pseudo-registers. */ 142 int w_pseudo_base = 0; 143 int w_pseudo_count = 0; 144 145 /* SME feature fields. */ 146 147 /* Index of the first SME register. This is -1 if SME is not supported. */ 148 int sme_reg_base = 0; 149 /* svg register index. */ 150 int sme_svg_regnum = 0; 151 /* svcr register index. */ 152 int sme_svcr_regnum = 0; 153 /* ZA register index. */ 154 int sme_za_regnum = 0; 155 /* Index of the first SME pseudo-register. This is -1 if SME is not 156 supported. */ 157 int sme_pseudo_base = 0; 158 /* Total number of SME pseudo-registers. */ 159 int sme_pseudo_count = 0; 160 /* First tile slice pseudo-register index. */ 161 int sme_tile_slice_pseudo_base = 0; 162 /* Total number of tile slice pseudo-registers. */ 163 int sme_tile_slice_pseudo_count = 0; 164 /* First tile pseudo-register index. */ 165 int sme_tile_pseudo_base = 0; 166 /* The streaming vector quotient (svq) for SME, or zero if SME is not 167 supported. */ 168 size_t sme_svq = 0; 169 170 /* Return true if the target supports SME, and false otherwise. */ has_smeaarch64_gdbarch_tdep171 bool has_sme () const 172 { 173 return sme_svq != 0; 174 } 175 176 /* Index of the SME2 ZT0 register. This is -1 if SME2 is not 177 supported. */ 178 int sme2_zt0_regnum = -1; 179 180 /* Return true if the target supports SME2, and false otherwise. */ has_sme2aarch64_gdbarch_tdep181 bool has_sme2 () const 182 { 183 return sme2_zt0_regnum > 0; 184 } 185 }; 186 187 const target_desc *aarch64_read_description (const aarch64_features &features); 188 aarch64_features 189 aarch64_features_from_target_desc (const struct target_desc *tdesc); 190 191 extern int aarch64_process_record (struct gdbarch *gdbarch, 192 struct regcache *regcache, CORE_ADDR addr); 193 194 displaced_step_copy_insn_closure_up 195 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, 196 CORE_ADDR from, CORE_ADDR to, 197 struct regcache *regs); 198 199 void aarch64_displaced_step_fixup (struct gdbarch *gdbarch, 200 displaced_step_copy_insn_closure *dsc, 201 CORE_ADDR from, CORE_ADDR to, 202 struct regcache *regs, bool completed_p); 203 204 bool aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch); 205 206 #endif /* aarch64-tdep.h */ 207