1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
26
27 #include <linux/idr.h>
28 #include <linux/kfifo.h>
29 #include <linux/rbtree.h>
30 #include <drm/gpu_scheduler.h>
31 #include <drm/drm_file.h>
32 #include <drm/ttm/ttm_bo.h>
33 #include <linux/sched/mm.h>
34
35 #include "amdgpu_sync.h"
36 #include "amdgpu_ring.h"
37 #include "amdgpu_ids.h"
38
39 struct drm_exec;
40
41 struct amdgpu_bo_va;
42 struct amdgpu_job;
43 struct amdgpu_bo_list_entry;
44 struct amdgpu_bo_vm;
45 struct amdgpu_mem_stats;
46
47 /*
48 * GPUVM handling
49 */
50
51 /* Maximum number of PTEs the hardware can write with one command */
52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
53
54 /* number of entries in page table */
55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
56
57 #define AMDGPU_PTE_VALID (1ULL << 0)
58 #define AMDGPU_PTE_SYSTEM (1ULL << 1)
59 #define AMDGPU_PTE_SNOOPED (1ULL << 2)
60
61 /* RV+ */
62 #define AMDGPU_PTE_TMZ (1ULL << 3)
63
64 /* VI only */
65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
66
67 #define AMDGPU_PTE_READABLE (1ULL << 5)
68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6)
69
70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
71
72 /* TILED for VEGA10, reserved for older ASICs */
73 #define AMDGPU_PTE_PRT (1ULL << 51)
74
75 /* PDE is handled as PTE for VEGA10 */
76 #define AMDGPU_PDE_PTE (1ULL << 54)
77
78 #define AMDGPU_PTE_LOG (1ULL << 55)
79
80 /* PTE is handled as PDE for VEGA10 (Translate Further) */
81 #define AMDGPU_PTE_TF (1ULL << 56)
82
83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */
84 #define AMDGPU_PTE_NOALLOC (1ULL << 58)
85
86 /* PDE Block Fragment Size for VEGA10 */
87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
88
89 /* Flag combination to set no-retry with TF disabled */
90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \
91 AMDGPU_PTE_TF)
92
93 /* Flag combination to set no-retry with TF enabled */
94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \
95 AMDGPU_PTE_PRT)
96 /* For GFX9 */
97 #define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57)
98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL)
99 #define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \
100 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \
101 AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype))
102
103 #define AMDGPU_MTYPE_NC 0
104 #define AMDGPU_MTYPE_CC 2
105
106 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
107 | AMDGPU_PTE_SNOOPED \
108 | AMDGPU_PTE_EXECUTABLE \
109 | AMDGPU_PTE_READABLE \
110 | AMDGPU_PTE_WRITEABLE \
111 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
112
113 /* gfx10 */
114 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48)
115 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL)
116 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \
117 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \
118 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype))
119
120 /* gfx12 */
121 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56)
122 #define AMDGPU_PTE_PRT_FLAG(adev) \
123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT)
124
125 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54)
126 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL)
127 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \
128 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \
129 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype))
130
131 #define AMDGPU_PTE_DCC (1ULL << 58)
132 #define AMDGPU_PTE_IS_PTE (1ULL << 63)
133
134 /* PDE Block Fragment Size for gfx v12 */
135 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58)
136 #define AMDGPU_PDE_BFS_FLAG(adev, a) \
137 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a))
138 /* PDE is handled as PTE for gfx v12 */
139 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63)
140 #define AMDGPU_PDE_PTE_FLAG(adev) \
141 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE)
142
143 /* How to program VM fault handling */
144 #define AMDGPU_VM_FAULT_STOP_NEVER 0
145 #define AMDGPU_VM_FAULT_STOP_FIRST 1
146 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
147
148 /* How much VRAM be reserved for page tables */
149 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20)
150
151 /*
152 * max number of VMHUB
153 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1
154 */
155 #define AMDGPU_MAX_VMHUBS 13
156 #define AMDGPU_GFXHUB_START 0
157 #define AMDGPU_MMHUB0_START 8
158 #define AMDGPU_MMHUB1_START 12
159 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x))
160 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x))
161 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x))
162
163 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START)
164 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START)
165 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS)
166
167 /* Reserve space at top/bottom of address space for kernel use */
168 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20)
169 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
170 << AMDGPU_GPU_PAGE_SHIFT) \
171 - AMDGPU_VA_RESERVED_CSA_SIZE)
172 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20)
173 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \
174 - AMDGPU_VA_RESERVED_SEQ64_SIZE)
175 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12)
176 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \
177 - AMDGPU_VA_RESERVED_TRAP_SIZE)
178 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16)
179 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \
180 AMDGPU_VA_RESERVED_SEQ64_SIZE + \
181 AMDGPU_VA_RESERVED_CSA_SIZE)
182
183 /* See vm_update_mode */
184 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
185 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
186
187 /* VMPT level enumerate, and the hiberachy is:
188 * PDB2->PDB1->PDB0->PTB
189 */
190 enum amdgpu_vm_level {
191 AMDGPU_VM_PDB2,
192 AMDGPU_VM_PDB1,
193 AMDGPU_VM_PDB0,
194 AMDGPU_VM_PTB
195 };
196
197 /* base structure for tracking BO usage in a VM */
198 struct amdgpu_vm_bo_base {
199 /* constant after initialization */
200 struct amdgpu_vm *vm;
201 struct amdgpu_bo *bo;
202
203 /* protected by bo being reserved */
204 struct amdgpu_vm_bo_base *next;
205
206 /* protected by spinlock */
207 struct list_head vm_status;
208
209 /* protected by the BO being reserved */
210 bool moved;
211 };
212
213 /* provided by hw blocks that can write ptes, e.g., sdma */
214 struct amdgpu_vm_pte_funcs {
215 /* number of dw to reserve per operation */
216 unsigned copy_pte_num_dw;
217
218 /* copy pte entries from GART */
219 void (*copy_pte)(struct amdgpu_ib *ib,
220 uint64_t pe, uint64_t src,
221 unsigned count);
222
223 /* write pte one entry at a time with addr mapping */
224 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
225 uint64_t value, unsigned count,
226 uint32_t incr);
227 /* for linear pte/pde updates without addr mapping */
228 void (*set_pte_pde)(struct amdgpu_ib *ib,
229 uint64_t pe,
230 uint64_t addr, unsigned count,
231 uint32_t incr, uint64_t flags);
232 };
233
234 struct amdgpu_task_info {
235 char process_name[TASK_COMM_LEN];
236 char task_name[TASK_COMM_LEN];
237 pid_t pid;
238 pid_t tgid;
239 struct kref refcount;
240 };
241
242 /**
243 * struct amdgpu_vm_update_params
244 *
245 * Encapsulate some VM table update parameters to reduce
246 * the number of function parameters
247 *
248 */
249 struct amdgpu_vm_update_params {
250
251 /**
252 * @adev: amdgpu device we do this update for
253 */
254 struct amdgpu_device *adev;
255
256 /**
257 * @vm: optional amdgpu_vm we do this update for
258 */
259 struct amdgpu_vm *vm;
260
261 /**
262 * @immediate: if changes should be made immediately
263 */
264 bool immediate;
265
266 /**
267 * @unlocked: true if the root BO is not locked
268 */
269 bool unlocked;
270
271 /**
272 * @pages_addr:
273 *
274 * DMA addresses to use for mapping
275 */
276 dma_addr_t *pages_addr;
277
278 /**
279 * @job: job to used for hw submission
280 */
281 struct amdgpu_job *job;
282
283 /**
284 * @num_dw_left: number of dw left for the IB
285 */
286 unsigned int num_dw_left;
287
288 /**
289 * @needs_flush: true whenever we need to invalidate the TLB
290 */
291 bool needs_flush;
292
293 /**
294 * @allow_override: true for memory that is not uncached: allows MTYPE
295 * to be overridden for NUMA local memory.
296 */
297 bool allow_override;
298
299 /**
300 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush
301 */
302 struct list_head tlb_flush_waitlist;
303 };
304
305 struct amdgpu_vm_update_funcs {
306 int (*map_table)(struct amdgpu_bo_vm *bo);
307 int (*prepare)(struct amdgpu_vm_update_params *p,
308 struct amdgpu_sync *sync);
309 int (*update)(struct amdgpu_vm_update_params *p,
310 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
311 unsigned count, uint32_t incr, uint64_t flags);
312 int (*commit)(struct amdgpu_vm_update_params *p,
313 struct dma_fence **fence);
314 };
315
316 struct amdgpu_vm_fault_info {
317 /* fault address */
318 uint64_t addr;
319 /* fault status register */
320 uint32_t status;
321 /* which vmhub? gfxhub, mmhub, etc. */
322 unsigned int vmhub;
323 };
324
325 struct amdgpu_vm_fault {
326 SIMPLEQ_ENTRY(amdgpu_vm_fault) vm_fault_entry;
327 uint64_t val;
328 };
329 SIMPLEQ_HEAD(amdgpu_vm_faults, amdgpu_vm_fault);
330
331 struct amdgpu_vm {
332 /* tree of virtual addresses mapped */
333 struct rb_root_cached va;
334
335 /* Lock to prevent eviction while we are updating page tables
336 * use vm_eviction_lock/unlock(vm)
337 */
338 struct rwlock eviction_lock;
339 bool evicting;
340 unsigned int saved_flags;
341
342 /* Lock to protect vm_bo add/del/move on all lists of vm */
343 spinlock_t status_lock;
344
345 /* Per-VM and PT BOs who needs a validation */
346 struct list_head evicted;
347
348 /* BOs for user mode queues that need a validation */
349 struct list_head evicted_user;
350
351 /* PT BOs which relocated and their parent need an update */
352 struct list_head relocated;
353
354 /* per VM BOs moved, but not yet updated in the PT */
355 struct list_head moved;
356
357 /* All BOs of this VM not currently in the state machine */
358 struct list_head idle;
359
360 /* regular invalidated BOs, but not yet updated in the PT */
361 struct list_head invalidated;
362
363 /* BO mappings freed, but not yet updated in the PT */
364 struct list_head freed;
365
366 /* BOs which are invalidated, has been updated in the PTs */
367 struct list_head done;
368
369 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
370 struct list_head pt_freed;
371 struct work_struct pt_free_work;
372
373 /* contains the page directory */
374 struct amdgpu_vm_bo_base root;
375 struct dma_fence *last_update;
376
377 /* Scheduler entities for page table updates */
378 struct drm_sched_entity immediate;
379 struct drm_sched_entity delayed;
380
381 /* Last finished delayed update */
382 atomic64_t tlb_seq;
383 struct dma_fence *last_tlb_flush;
384 atomic64_t kfd_last_flushed_seq;
385 uint64_t tlb_fence_context;
386
387 /* How many times we had to re-generate the page tables */
388 uint64_t generation;
389
390 /* Last unlocked submission to the scheduler entities */
391 struct dma_fence *last_unlocked;
392
393 unsigned int pasid;
394 bool reserved_vmid[AMDGPU_MAX_VMHUBS];
395
396 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
397 bool use_cpu_for_update;
398
399 /* Functions to use for VM table updates */
400 const struct amdgpu_vm_update_funcs *update_funcs;
401
402 #ifdef __linux__
403 /* Up to 128 pending retry page faults */
404 DECLARE_KFIFO(faults, u64, 128);
405 #else
406 struct amdgpu_vm_faults faults;
407 #endif
408
409 /* Points to the KFD process VM info */
410 struct amdkfd_process_info *process_info;
411
412 /* List node in amdkfd_process_info.vm_list_head */
413 struct list_head vm_list_node;
414
415 /* Valid while the PD is reserved or fenced */
416 uint64_t pd_phys_addr;
417
418 /* Some basic info about the task */
419 struct amdgpu_task_info *task_info;
420
421 /* Store positions of group of BOs */
422 struct ttm_lru_bulk_move lru_bulk_move;
423 /* Flag to indicate if VM is used for compute */
424 bool is_compute_context;
425
426 /* Memory partition number, -1 means any partition */
427 int8_t mem_id;
428
429 /* cached fault info */
430 struct amdgpu_vm_fault_info fault_info;
431 };
432
433 struct amdgpu_vm_manager {
434 /* Handling of VMIDs */
435 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
436 unsigned int first_kfd_vmid;
437 bool concurrent_flush;
438
439 /* Handling of VM fences */
440 u64 fence_context;
441 unsigned seqno[AMDGPU_MAX_RINGS];
442
443 uint64_t max_pfn;
444 uint32_t num_level;
445 uint32_t block_size;
446 uint32_t fragment_size;
447 enum amdgpu_vm_level root_level;
448 /* vram base address for page table entry */
449 u64 vram_base_offset;
450 /* vm pte handling */
451 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
452 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS];
453 unsigned vm_pte_num_scheds;
454 struct amdgpu_ring *page_fault;
455
456 /* partial resident texture handling */
457 spinlock_t prt_lock;
458 atomic_t num_prt_users;
459
460 /* controls how VM page tables are updated for Graphics and Compute.
461 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
462 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
463 */
464 int vm_update_mode;
465
466 /* PASID to VM mapping, will be used in interrupt context to
467 * look up VM of a page fault
468 */
469 struct xarray pasids;
470 /* Global registration of recent page fault information */
471 struct amdgpu_vm_fault_info fault_info;
472 };
473
474 struct amdgpu_bo_va_mapping;
475
476 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
477 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
478 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
479
480 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
481 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
482
483 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
484 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
485
486 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
487 u32 pasid);
488
489 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
490 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id);
491 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
492 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
493 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
494 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
495 unsigned int num_fences);
496 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
497 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm);
498 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
499 struct ww_acquire_ctx *ticket,
500 int (*callback)(void *p, struct amdgpu_bo *bo),
501 void *param);
502 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
503 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
504 struct amdgpu_vm *vm, bool immediate);
505 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
506 struct amdgpu_vm *vm,
507 struct dma_fence **fence);
508 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
509 struct amdgpu_vm *vm,
510 struct ww_acquire_ctx *ticket);
511 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
512 struct amdgpu_vm *vm,
513 uint32_t flush_type,
514 uint32_t xcc_mask);
515 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
516 struct amdgpu_vm *vm, struct amdgpu_bo *bo);
517 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
518 bool immediate, bool unlocked, bool flush_tlb,
519 bool allow_override, struct amdgpu_sync *sync,
520 uint64_t start, uint64_t last, uint64_t flags,
521 uint64_t offset, uint64_t vram_base,
522 struct ttm_resource *res, dma_addr_t *pages_addr,
523 struct dma_fence **fence);
524 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
525 struct amdgpu_bo_va *bo_va,
526 bool clear);
527 bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
528 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
529 struct amdgpu_bo *bo, bool evicted);
530 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
531 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
532 struct amdgpu_bo *bo);
533 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
534 struct amdgpu_vm *vm,
535 struct amdgpu_bo *bo);
536 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
537 struct amdgpu_bo_va *bo_va,
538 uint64_t addr, uint64_t offset,
539 uint64_t size, uint64_t flags);
540 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
541 struct amdgpu_bo_va *bo_va,
542 uint64_t addr, uint64_t offset,
543 uint64_t size, uint64_t flags);
544 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
545 struct amdgpu_bo_va *bo_va,
546 uint64_t addr);
547 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
548 struct amdgpu_vm *vm,
549 uint64_t saddr, uint64_t size);
550 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
551 uint64_t addr);
552 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
553 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
554 struct amdgpu_bo_va *bo_va);
555 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
556 uint32_t fragment_size_default, unsigned max_level,
557 unsigned max_bits);
558 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
559 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
560 struct amdgpu_job *job);
561 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
562
563 struct amdgpu_task_info *
564 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid);
565
566 struct amdgpu_task_info *
567 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm);
568
569 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info);
570
571 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
572 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,
573 bool write_fault);
574
575 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
576
577 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
578 struct amdgpu_vm *vm);
579 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
580 struct amdgpu_mem_stats *stats);
581
582 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
583 struct amdgpu_bo_vm *vmbo, bool immediate);
584 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,
585 int level, bool immediate, struct amdgpu_bo_vm **vmbo,
586 int32_t xcp_id);
587 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm);
588
589 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params,
590 struct amdgpu_vm_bo_base *entry);
591 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
592 uint64_t start, uint64_t end,
593 uint64_t dst, uint64_t flags);
594 void amdgpu_vm_pt_free_work(struct work_struct *work);
595 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev,
596 struct amdgpu_vm_update_params *params);
597
598 #if defined(CONFIG_DEBUG_FS)
599 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
600 #endif
601
602 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm);
603
604 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo);
605
606 /**
607 * amdgpu_vm_tlb_seq - return tlb flush sequence number
608 * @vm: the amdgpu_vm structure to query
609 *
610 * Returns the tlb flush sequence number which indicates that the VM TLBs needs
611 * to be invalidated whenever the sequence number change.
612 */
amdgpu_vm_tlb_seq(struct amdgpu_vm * vm)613 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)
614 {
615 unsigned long flags;
616 spinlock_t *lock;
617
618 /*
619 * Workaround to stop racing between the fence signaling and handling
620 * the cb. The lock is static after initially setting it up, just make
621 * sure that the dma_fence structure isn't freed up.
622 */
623 rcu_read_lock();
624 lock = vm->last_tlb_flush->lock;
625 rcu_read_unlock();
626
627 spin_lock_irqsave(lock, flags);
628 spin_unlock_irqrestore(lock, flags);
629
630 return atomic64_read(&vm->tlb_seq);
631 }
632
633 /*
634 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
635 * happens while holding this lock anywhere to prevent deadlocks when
636 * an MMU notifier runs in reclaim-FS context.
637 */
amdgpu_vm_eviction_lock(struct amdgpu_vm * vm)638 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
639 {
640 mutex_lock(&vm->eviction_lock);
641 #ifdef notyet
642 vm->saved_flags = memalloc_noreclaim_save();
643 #endif
644 }
645
amdgpu_vm_eviction_trylock(struct amdgpu_vm * vm)646 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
647 {
648 if (mutex_trylock(&vm->eviction_lock)) {
649 #ifdef notyet
650 vm->saved_flags = memalloc_noreclaim_save();
651 #endif
652 return true;
653 }
654 return false;
655 }
656
amdgpu_vm_eviction_unlock(struct amdgpu_vm * vm)657 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
658 {
659 #ifdef notyet
660 memalloc_noreclaim_restore(vm->saved_flags);
661 #endif
662 mutex_unlock(&vm->eviction_lock);
663 }
664
665 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
666 unsigned int pasid,
667 uint64_t addr,
668 uint32_t status,
669 unsigned int vmhub);
670 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev,
671 struct amdgpu_vm *vm,
672 struct dma_fence **fence);
673
674 #endif
675