1 /* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
3 */
4 /*-
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include <dev/drm2/drmP.h>
36 #include <dev/drm2/drm.h>
37 #include <dev/drm2/drm_mm.h>
38 #include <dev/drm2/i915/i915_drm.h>
39 #include <dev/drm2/i915/i915_drv.h>
40 #include <dev/drm2/drm_pciids.h>
41 #include <dev/drm2/i915/intel_drv.h>
42
43 #include "fb_if.h"
44
45 int intel_iommu_enabled = 0;
46 TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
47 int intel_iommu_gfx_mapped = 0;
48 TUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped);
49
50 int i915_prefault_disable;
51 TUNABLE_INT("drm.i915.prefault_disable", &i915_prefault_disable);
52 int i915_semaphores = -1;
53 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
54 static int i915_try_reset = 1;
55 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
56 unsigned int i915_lvds_downclock = 0;
57 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
58 int i915_vbt_sdvo_panel_type = -1;
59 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
60 unsigned int i915_powersave = 1;
61 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
62 int i915_enable_fbc = 0;
63 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
64 int i915_enable_rc6 = 0;
65 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
66 int i915_lvds_channel_mode;
67 TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
68 int i915_panel_use_ssc = -1;
69 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
70 int i915_panel_ignore_lid = 0;
71 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
72 int i915_panel_invert_brightness;
73 TUNABLE_INT("drm.i915.panel_invert_brightness", &i915_panel_invert_brightness);
74 int i915_modeset = 1;
75 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
76 int i915_enable_ppgtt = -1;
77 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
78 int i915_enable_hangcheck = 1;
79 TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
80 static int i915_enable_unsupported = 0;
81 TUNABLE_INT("drm.i915.enable_unsupported", &i915_enable_unsupported);
82
83 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
84 static drm_pci_id_list_t i915_pciidlist[] = {
85 i915_PCI_IDS
86 };
87
88 #define INTEL_VGA_DEVICE(id, info_) { \
89 .device = id, \
90 .info = info_, \
91 }
92
93 static const struct intel_device_info intel_i830_info = {
94 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
95 .has_overlay = 1, .overlay_needs_physical = 1,
96 };
97
98 static const struct intel_device_info intel_845g_info = {
99 .gen = 2,
100 .has_overlay = 1, .overlay_needs_physical = 1,
101 };
102
103 static const struct intel_device_info intel_i85x_info = {
104 .gen = 2, .is_i85x = 1, .is_mobile = 1,
105 .cursor_needs_physical = 1,
106 .has_overlay = 1, .overlay_needs_physical = 1,
107 };
108
109 static const struct intel_device_info intel_i865g_info = {
110 .gen = 2,
111 .has_overlay = 1, .overlay_needs_physical = 1,
112 };
113
114 static const struct intel_device_info intel_i915g_info = {
115 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
116 .has_overlay = 1, .overlay_needs_physical = 1,
117 };
118 static const struct intel_device_info intel_i915gm_info = {
119 .gen = 3, .is_mobile = 1,
120 .cursor_needs_physical = 1,
121 .has_overlay = 1, .overlay_needs_physical = 1,
122 .supports_tv = 1,
123 };
124 static const struct intel_device_info intel_i945g_info = {
125 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
126 .has_overlay = 1, .overlay_needs_physical = 1,
127 };
128 static const struct intel_device_info intel_i945gm_info = {
129 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
130 .has_hotplug = 1, .cursor_needs_physical = 1,
131 .has_overlay = 1, .overlay_needs_physical = 1,
132 .supports_tv = 1,
133 };
134
135 static const struct intel_device_info intel_i965g_info = {
136 .gen = 4, .is_broadwater = 1,
137 .has_hotplug = 1,
138 .has_overlay = 1,
139 };
140
141 static const struct intel_device_info intel_i965gm_info = {
142 .gen = 4, .is_crestline = 1,
143 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
144 .has_overlay = 1,
145 .supports_tv = 1,
146 };
147
148 static const struct intel_device_info intel_g33_info = {
149 .gen = 3, .is_g33 = 1,
150 .need_gfx_hws = 1, .has_hotplug = 1,
151 .has_overlay = 1,
152 };
153
154 static const struct intel_device_info intel_g45_info = {
155 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
156 .has_pipe_cxsr = 1, .has_hotplug = 1,
157 .has_bsd_ring = 1,
158 };
159
160 static const struct intel_device_info intel_gm45_info = {
161 .gen = 4, .is_g4x = 1,
162 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
163 .has_pipe_cxsr = 1, .has_hotplug = 1,
164 .supports_tv = 1,
165 .has_bsd_ring = 1,
166 };
167
168 static const struct intel_device_info intel_pineview_info = {
169 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
170 .need_gfx_hws = 1, .has_hotplug = 1,
171 .has_overlay = 1,
172 };
173
174 static const struct intel_device_info intel_ironlake_d_info = {
175 .gen = 5,
176 .need_gfx_hws = 1, .has_hotplug = 1,
177 .has_bsd_ring = 1,
178 .has_pch_split = 1,
179 };
180
181 static const struct intel_device_info intel_ironlake_m_info = {
182 .gen = 5, .is_mobile = 1,
183 .need_gfx_hws = 1, .has_hotplug = 1,
184 .has_fbc = 0, /* disabled due to buggy hardware */
185 .has_bsd_ring = 1,
186 .has_pch_split = 1,
187 };
188
189 static const struct intel_device_info intel_sandybridge_d_info = {
190 .gen = 6,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .has_bsd_ring = 1,
193 .has_blt_ring = 1,
194 .has_llc = 1,
195 .has_pch_split = 1,
196 };
197
198 static const struct intel_device_info intel_sandybridge_m_info = {
199 .gen = 6, .is_mobile = 1,
200 .need_gfx_hws = 1, .has_hotplug = 1,
201 .has_fbc = 1,
202 .has_bsd_ring = 1,
203 .has_blt_ring = 1,
204 .has_llc = 1,
205 .has_pch_split = 1,
206 };
207
208 static const struct intel_device_info intel_ivybridge_d_info = {
209 .is_ivybridge = 1, .gen = 7,
210 .need_gfx_hws = 1, .has_hotplug = 1,
211 .has_bsd_ring = 1,
212 .has_blt_ring = 1,
213 .has_llc = 1,
214 .has_pch_split = 1,
215 };
216
217 static const struct intel_device_info intel_ivybridge_m_info = {
218 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
219 .need_gfx_hws = 1, .has_hotplug = 1,
220 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
221 .has_bsd_ring = 1,
222 .has_blt_ring = 1,
223 .has_llc = 1,
224 .has_pch_split = 1,
225 };
226
227 static const struct intel_device_info intel_valleyview_m_info = {
228 .gen = 7, .is_mobile = 1,
229 .need_gfx_hws = 1, .has_hotplug = 1,
230 .has_fbc = 0,
231 .has_bsd_ring = 1,
232 .has_blt_ring = 1,
233 .is_valleyview = 1,
234 .not_supported = 1,
235 };
236
237 static const struct intel_device_info intel_valleyview_d_info = {
238 .gen = 7,
239 .need_gfx_hws = 1, .has_hotplug = 1,
240 .has_fbc = 0,
241 .has_bsd_ring = 1,
242 .has_blt_ring = 1,
243 .is_valleyview = 1,
244 .not_supported = 1,
245 };
246
247 static const struct intel_device_info intel_haswell_d_info = {
248 .is_haswell = 1, .gen = 7,
249 .need_gfx_hws = 1, .has_hotplug = 1,
250 .has_bsd_ring = 1,
251 .has_blt_ring = 1,
252 .has_llc = 1,
253 .has_pch_split = 1,
254 .not_supported = 1,
255 };
256
257 static const struct intel_device_info intel_haswell_m_info = {
258 .is_haswell = 1, .gen = 7, .is_mobile = 1,
259 .need_gfx_hws = 1, .has_hotplug = 1,
260 .has_bsd_ring = 1,
261 .has_blt_ring = 1,
262 .has_llc = 1,
263 .has_pch_split = 1,
264 .not_supported = 1,
265 };
266
267 static const struct intel_gfx_device_id {
268 int device;
269 const struct intel_device_info *info;
270 } i915_infolist[] = { /* aka */
271 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
272 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
273 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
274 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
275 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
276 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
277 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
278 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
279 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
280 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
281 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
282 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
283 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
284 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
285 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
286 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
287 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
288 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
289 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
290 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
291 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
292 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
293 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
294 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
295 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
296 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
297 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
298 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
299 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
300 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
301 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
302 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
303 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
304 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
305 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
306 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
307 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
308 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
309 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
310 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
311 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
312 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
313 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
314 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
315 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
316 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
317 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
318 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
319 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
320 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
321 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
322 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
323 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
324 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
325 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
326 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
327 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
328 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
329 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
330 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
331 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
332 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
333 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
334 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
335 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
336 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
337 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
338 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
339 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
340 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
341 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
342 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
343 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
344 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
345 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
346 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
347 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
348 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
349 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
350 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
351 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
352 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
353 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
354 {0, 0}
355 };
356
357 #define PCI_VENDOR_INTEL 0x8086
358 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
359 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
360 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
361 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
362 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
363
intel_detect_pch(struct drm_device * dev)364 void intel_detect_pch(struct drm_device *dev)
365 {
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 device_t pch;
368 uint32_t id;
369
370 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
371 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
372 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
373 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
374 dev_priv->pch_type = PCH_IBX;
375 dev_priv->num_pch_pll = 2;
376 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
377 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
378 dev_priv->pch_type = PCH_CPT;
379 dev_priv->num_pch_pll = 2;
380 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
381 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
382 /* PantherPoint is CPT compatible */
383 dev_priv->pch_type = PCH_CPT;
384 dev_priv->num_pch_pll = 2;
385 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
386 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
387 dev_priv->pch_type = PCH_LPT;
388 dev_priv->num_pch_pll = 0;
389 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
390 } else
391 DRM_DEBUG_KMS("No PCH detected\n");
392 KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS,
393 ("num_pch_pll %d\n", dev_priv->num_pch_pll));
394 } else
395 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
396 }
397
i915_semaphore_is_enabled(struct drm_device * dev)398 bool i915_semaphore_is_enabled(struct drm_device *dev)
399 {
400 if (INTEL_INFO(dev)->gen < 6)
401 return 0;
402
403 if (i915_semaphores >= 0)
404 return i915_semaphores;
405
406 /* Enable semaphores on SNB when IO remapping is off */
407 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
408 return false;
409
410 return 1;
411 }
412
i915_drm_freeze(struct drm_device * dev)413 static int i915_drm_freeze(struct drm_device *dev)
414 {
415 struct drm_i915_private *dev_priv = dev->dev_private;
416
417 drm_kms_helper_poll_disable(dev);
418
419 #if 0
420 pci_save_state(dev->pdev);
421 #endif
422
423 /* If KMS is active, we do the leavevt stuff here */
424 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
425 int error = i915_gem_idle(dev);
426 if (error) {
427 device_printf(dev->dev,
428 "GEM idle failed, resume might fail\n");
429 return error;
430 }
431 drm_irq_uninstall(dev);
432 }
433
434 i915_save_state(dev);
435
436 intel_opregion_fini(dev);
437
438 /* Modeset on resume, not lid events */
439 dev_priv->modeset_on_lid = 0;
440
441 return 0;
442 }
443
i915_suspend(device_t kdev)444 static int i915_suspend(device_t kdev)
445 {
446 struct drm_device *dev;
447 int error;
448
449 dev = device_get_softc(kdev);
450 if (!dev || !dev->dev_private) {
451 DRM_ERROR("DRM not initialized, aborting suspend.\n");
452 return ENODEV;
453 }
454
455 DRM_DEBUG_KMS("starting suspend\n");
456 error = i915_drm_freeze(dev);
457 if (error)
458 return -error;
459
460 error = bus_generic_suspend(kdev);
461 DRM_DEBUG_KMS("finished suspend %d\n", error);
462 return (error);
463 }
464
i915_drm_thaw(struct drm_device * dev)465 static int i915_drm_thaw(struct drm_device *dev)
466 {
467 struct drm_i915_private *dev_priv = dev->dev_private;
468 int error = 0;
469
470 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
471 DRM_LOCK(dev);
472 i915_gem_restore_gtt_mappings(dev);
473 DRM_UNLOCK(dev);
474 }
475
476 i915_restore_state(dev);
477 intel_opregion_setup(dev);
478
479 /* KMS EnterVT equivalent */
480 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
481 if (HAS_PCH_SPLIT(dev))
482 ironlake_init_pch_refclk(dev);
483
484 DRM_LOCK(dev);
485 dev_priv->mm.suspended = 0;
486
487 error = i915_gem_init_hw(dev);
488 DRM_UNLOCK(dev);
489
490 intel_modeset_init_hw(dev);
491 sx_xlock(&dev->mode_config.mutex);
492 drm_mode_config_reset(dev);
493 sx_xunlock(&dev->mode_config.mutex);
494 drm_irq_install(dev);
495
496 sx_xlock(&dev->mode_config.mutex);
497 /* Resume the modeset for every activated CRTC */
498 drm_helper_resume_force_mode(dev);
499 sx_xunlock(&dev->mode_config.mutex);
500 }
501
502 intel_opregion_init(dev);
503
504 dev_priv->modeset_on_lid = 0;
505
506 return error;
507 }
508
i915_resume(device_t kdev)509 static int i915_resume(device_t kdev)
510 {
511 struct drm_device *dev;
512 int ret;
513
514 dev = device_get_softc(kdev);
515 DRM_DEBUG_KMS("starting resume\n");
516 #if 0
517 if (pci_enable_device(dev->pdev))
518 return -EIO;
519
520 pci_set_master(dev->pdev);
521 #endif
522
523 ret = i915_drm_thaw(dev);
524 if (ret)
525 return -ret;
526
527 drm_kms_helper_poll_enable(dev);
528 ret = bus_generic_resume(kdev);
529 DRM_DEBUG_KMS("finished resume %d\n", ret);
530 return (ret);
531 }
532
i8xx_do_reset(struct drm_device * dev)533 static int i8xx_do_reset(struct drm_device *dev)
534 {
535 struct drm_i915_private *dev_priv = dev->dev_private;
536 int onems;
537
538 if (IS_I85X(dev))
539 return -ENODEV;
540
541 onems = hz / 1000;
542 if (onems == 0)
543 onems = 1;
544
545 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
546 POSTING_READ(D_STATE);
547
548 if (IS_I830(dev) || IS_845G(dev)) {
549 I915_WRITE(DEBUG_RESET_I830,
550 DEBUG_RESET_DISPLAY |
551 DEBUG_RESET_RENDER |
552 DEBUG_RESET_FULL);
553 POSTING_READ(DEBUG_RESET_I830);
554 pause("i8xxrst1", onems);
555
556 I915_WRITE(DEBUG_RESET_I830, 0);
557 POSTING_READ(DEBUG_RESET_I830);
558 }
559
560 pause("i8xxrst2", onems);
561
562 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
563 POSTING_READ(D_STATE);
564
565 return 0;
566 }
567
i965_reset_complete(struct drm_device * dev)568 static int i965_reset_complete(struct drm_device *dev)
569 {
570 u8 gdrst;
571
572 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
573 return (gdrst & GRDOM_RESET_ENABLE) == 0;
574 }
575
i965_do_reset(struct drm_device * dev)576 static int i965_do_reset(struct drm_device *dev)
577 {
578 int ret;
579 u8 gdrst;
580
581 /*
582 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
583 * well as the reset bit (GR/bit 0). Setting the GR bit
584 * triggers the reset; when done, the hardware will clear it.
585 */
586 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
587 pci_write_config(dev->dev, I965_GDRST,
588 gdrst | GRDOM_RENDER |
589 GRDOM_RESET_ENABLE, 1);
590 ret = wait_for(i965_reset_complete(dev), 500);
591 if (ret)
592 return ret;
593
594 /* We can't reset render&media without also resetting display ... */
595 gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
596 pci_write_config(dev->dev, I965_GDRST,
597 gdrst | GRDOM_MEDIA |
598 GRDOM_RESET_ENABLE, 1);
599
600 return wait_for(i965_reset_complete(dev), 500);
601 }
602
ironlake_do_reset(struct drm_device * dev)603 static int ironlake_do_reset(struct drm_device *dev)
604 {
605 struct drm_i915_private *dev_priv = dev->dev_private;
606 u32 gdrst;
607 int ret;
608
609 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
610 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
611 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
612 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
613 if (ret)
614 return ret;
615
616 /* We can't reset render&media without also resetting display ... */
617 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
618 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
619 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
620 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
621 }
622
gen6_do_reset(struct drm_device * dev)623 static int gen6_do_reset(struct drm_device *dev)
624 {
625 struct drm_i915_private *dev_priv = dev->dev_private;
626 int ret;
627
628 /* Hold gt_lock across reset to prevent any register access
629 * with forcewake not set correctly
630 */
631 mtx_lock(&dev_priv->gt_lock);
632
633 /* Reset the chip */
634
635 /* GEN6_GDRST is not in the gt power well, no need to check
636 * for fifo space for the write or forcewake the chip for
637 * the read
638 */
639 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
640
641 /* Spin waiting for the device to ack the reset request */
642 ret = _intel_wait_for(dev,
643 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
644 500, 0, "915rst");
645
646 /* If reset with a user forcewake, try to restore, otherwise turn it off */
647 if (dev_priv->forcewake_count)
648 dev_priv->display.force_wake_get(dev_priv);
649 else
650 dev_priv->display.force_wake_put(dev_priv);
651
652 /* Restore fifo count */
653 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
654
655 mtx_unlock(&dev_priv->gt_lock);
656 return ret;
657 }
658
intel_gpu_reset(struct drm_device * dev)659 int intel_gpu_reset(struct drm_device *dev)
660 {
661 struct drm_i915_private *dev_priv = dev->dev_private;
662 int ret = -ENODEV;
663
664 switch (INTEL_INFO(dev)->gen) {
665 case 7:
666 case 6:
667 ret = gen6_do_reset(dev);
668 break;
669 case 5:
670 ret = ironlake_do_reset(dev);
671 break;
672 case 4:
673 ret = i965_do_reset(dev);
674 break;
675 case 2:
676 ret = i8xx_do_reset(dev);
677 break;
678 }
679
680 /* Also reset the gpu hangman. */
681 if (dev_priv->stop_rings) {
682 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
683 dev_priv->stop_rings = 0;
684 if (ret == -ENODEV) {
685 DRM_ERROR("Reset not implemented, but ignoring "
686 "error for simulated gpu hangs\n");
687 ret = 0;
688 }
689 }
690
691 return ret;
692 }
693
694 /**
695 * i915_reset - reset chip after a hang
696 * @dev: drm device to reset
697 *
698 * Reset the chip. Useful if a hang is detected. Returns zero on successful
699 * reset or otherwise an error code.
700 *
701 * Procedure is fairly simple:
702 * - reset the chip using the reset reg
703 * - re-init context state
704 * - re-init hardware status page
705 * - re-init ring buffer
706 * - re-init interrupt state
707 * - re-init display
708 */
i915_reset(struct drm_device * dev)709 int i915_reset(struct drm_device *dev)
710 {
711 drm_i915_private_t *dev_priv = dev->dev_private;
712 int ret;
713
714 if (!i915_try_reset)
715 return 0;
716
717 if (!sx_try_xlock(&dev->dev_struct_lock))
718 return (-EBUSY);
719
720 dev_priv->stop_rings = 0;
721
722 i915_gem_reset(dev);
723
724 ret = -ENODEV;
725 if (time_second - dev_priv->last_gpu_reset < 5)
726 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
727 else
728 ret = intel_gpu_reset(dev);
729
730 dev_priv->last_gpu_reset = time_second;
731 if (ret) {
732 DRM_ERROR("Failed to reset chip.\n");
733 DRM_UNLOCK(dev);
734 return ret;
735 }
736
737 /* Ok, now get things going again... */
738
739 /*
740 * Everything depends on having the GTT running, so we need to start
741 * there. Fortunately we don't need to do this unless we reset the
742 * chip at a PCI level.
743 *
744 * Next we need to restore the context, but we don't use those
745 * yet either...
746 *
747 * Ring buffer needs to be re-initialized in the KMS case, or if X
748 * was running at the time of the reset (i.e. we weren't VT
749 * switched away).
750 */
751 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
752 !dev_priv->mm.suspended) {
753 struct intel_ring_buffer *ring;
754 int i;
755
756 dev_priv->mm.suspended = 0;
757
758 i915_gem_init_swizzling(dev);
759
760 for_each_ring(ring, dev_priv, i)
761 ring->init(ring);
762
763 i915_gem_context_init(dev);
764 i915_gem_init_ppgtt(dev);
765
766 /*
767 * It would make sense to re-init all the other hw state, at
768 * least the rps/rc6/emon init done within modeset_init_hw. For
769 * some unknown reason, this blows up my ilk, so don't.
770 */
771
772 DRM_UNLOCK(dev);
773
774 if (drm_core_check_feature(dev, DRIVER_MODESET))
775 intel_modeset_init_hw(dev);
776
777 drm_irq_uninstall(dev);
778 drm_irq_install(dev);
779 } else {
780 DRM_UNLOCK(dev);
781 }
782
783 return 0;
784 }
785
786 const struct intel_device_info *
i915_get_device_id(int device)787 i915_get_device_id(int device)
788 {
789 const struct intel_gfx_device_id *did;
790
791 for (did = &i915_infolist[0]; did->device != 0; did++) {
792 if (did->device != device)
793 continue;
794 if (did->info->not_supported && !i915_enable_unsupported)
795 return (NULL);
796 return (did->info);
797 }
798 return (NULL);
799 }
800
i915_probe(device_t kdev)801 static int i915_probe(device_t kdev)
802 {
803 const struct intel_device_info *intel_info =
804 i915_get_device_id(pci_get_device(kdev));
805
806 if (intel_info == NULL)
807 return (ENXIO);
808
809 return -drm_probe_helper(kdev, i915_pciidlist);
810 }
811
i915_attach(device_t kdev)812 static int i915_attach(device_t kdev)
813 {
814
815 if (i915_modeset == 1)
816 i915_driver_info.driver_features |= DRIVER_MODESET;
817 return (-drm_attach_helper(kdev, i915_pciidlist, &i915_driver_info));
818 }
819
820 static struct fb_info *
i915_fb_helper_getinfo(device_t kdev)821 i915_fb_helper_getinfo(device_t kdev)
822 {
823 struct intel_fbdev *ifbdev;
824 drm_i915_private_t *dev_priv;
825 struct drm_device *dev;
826 struct fb_info *info;
827
828 dev = device_get_softc(kdev);
829 dev_priv = dev->dev_private;
830 ifbdev = dev_priv->fbdev;
831 if (ifbdev == NULL)
832 return (NULL);
833
834 info = ifbdev->helper.fbdev;
835
836 return (info);
837 }
838
839 static device_method_t i915_methods[] = {
840 /* Device interface */
841 DEVMETHOD(device_probe, i915_probe),
842 DEVMETHOD(device_attach, i915_attach),
843 DEVMETHOD(device_suspend, i915_suspend),
844 DEVMETHOD(device_resume, i915_resume),
845 DEVMETHOD(device_detach, drm_generic_detach),
846
847 /* Framebuffer service methods */
848 DEVMETHOD(fb_getinfo, i915_fb_helper_getinfo),
849
850 DEVMETHOD_END
851 };
852
853 static driver_t i915_driver = {
854 "drmn",
855 i915_methods,
856 sizeof(struct drm_device)
857 };
858
859 extern devclass_t drm_devclass;
860 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
861 SI_ORDER_ANY);
862 MODULE_DEPEND(i915kms, drmn, 1, 1, 1);
863 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
864 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
865 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
866 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
867
868 /* We give fast paths for the really cool registers */
869 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
870 (((dev_priv)->info->gen >= 6) && \
871 ((reg) < 0x40000) && \
872 ((reg) != FORCEWAKE)) && \
873 (!IS_VALLEYVIEW((dev_priv)->dev))
874
875 void
__gen6_gt_force_wake_get(struct drm_i915_private * dev_priv)876 __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
877 {
878 int count;
879
880 count = 0;
881 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
882 DELAY(10);
883
884 I915_WRITE_NOTRACE(FORCEWAKE, 1);
885 POSTING_READ(FORCEWAKE);
886
887 count = 0;
888 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
889 DELAY(10);
890 }
891
892 void
__gen6_gt_force_wake_mt_get(struct drm_i915_private * dev_priv)893 __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
894 {
895 int count;
896
897 count = 0;
898 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
899 DELAY(10);
900
901 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
902 POSTING_READ(FORCEWAKE_MT);
903
904 count = 0;
905 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
906 DELAY(10);
907 }
908
909 void
gen6_gt_force_wake_get(struct drm_i915_private * dev_priv)910 gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
911 {
912
913 mtx_lock(&dev_priv->gt_lock);
914 if (dev_priv->forcewake_count++ == 0)
915 dev_priv->display.force_wake_get(dev_priv);
916 mtx_unlock(&dev_priv->gt_lock);
917 }
918
919 static void
gen6_gt_check_fifodbg(struct drm_i915_private * dev_priv)920 gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
921 {
922 u32 gtfifodbg;
923
924 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
925 if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) {
926 printf("MMIO read or write has been dropped %x\n", gtfifodbg);
927 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
928 }
929 }
930
931 void
__gen6_gt_force_wake_put(struct drm_i915_private * dev_priv)932 __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
933 {
934
935 I915_WRITE_NOTRACE(FORCEWAKE, 0);
936 /* The below doubles as a POSTING_READ */
937 gen6_gt_check_fifodbg(dev_priv);
938 }
939
940 void
__gen6_gt_force_wake_mt_put(struct drm_i915_private * dev_priv)941 __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
942 {
943
944 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
945 /* The below doubles as a POSTING_READ */
946 gen6_gt_check_fifodbg(dev_priv);
947 }
948
949 void
gen6_gt_force_wake_put(struct drm_i915_private * dev_priv)950 gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
951 {
952
953 mtx_lock(&dev_priv->gt_lock);
954 if (--dev_priv->forcewake_count == 0)
955 dev_priv->display.force_wake_put(dev_priv);
956 mtx_unlock(&dev_priv->gt_lock);
957 }
958
959 int
__gen6_gt_wait_for_fifo(struct drm_i915_private * dev_priv)960 __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
961 {
962 int ret = 0;
963
964 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
965 int loop = 500;
966 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
967 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
968 DELAY(10);
969 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
970 }
971 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
972 printf("%s loop\n", __func__);
973 ++ret;
974 }
975 dev_priv->gt_fifo_count = fifo;
976 }
977 dev_priv->gt_fifo_count--;
978
979 return (ret);
980 }
981
vlv_force_wake_get(struct drm_i915_private * dev_priv)982 void vlv_force_wake_get(struct drm_i915_private *dev_priv)
983 {
984 int count;
985
986 count = 0;
987
988 /* Already awake? */
989 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
990 return;
991
992 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
993 POSTING_READ(FORCEWAKE_VLV);
994
995 count = 0;
996 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
997 DELAY(10);
998 }
999
vlv_force_wake_put(struct drm_i915_private * dev_priv)1000 void vlv_force_wake_put(struct drm_i915_private *dev_priv)
1001 {
1002 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
1003 /* FIXME: confirm VLV behavior with Punit folks */
1004 POSTING_READ(FORCEWAKE_VLV);
1005 }
1006
1007 #define __i915_read(x, y) \
1008 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1009 u##x val = 0; \
1010 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1011 mtx_lock(&dev_priv->gt_lock); \
1012 if (dev_priv->forcewake_count == 0) \
1013 dev_priv->display.force_wake_get(dev_priv); \
1014 val = DRM_READ##x(dev_priv->mmio_map, reg); \
1015 if (dev_priv->forcewake_count == 0) \
1016 dev_priv->display.force_wake_put(dev_priv); \
1017 mtx_unlock(&dev_priv->gt_lock); \
1018 } else { \
1019 val = DRM_READ##x(dev_priv->mmio_map, reg); \
1020 } \
1021 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1022 return val; \
1023 }
1024
1025 __i915_read(8, 8)
1026 __i915_read(16, 16)
1027 __i915_read(32, 32)
1028 __i915_read(64, 64)
1029 #undef __i915_read
1030
1031 #define __i915_write(x, y) \
1032 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1033 u32 __fifo_ret = 0; \
1034 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1035 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1036 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1037 } \
1038 DRM_WRITE##x(dev_priv->mmio_map, reg, val); \
1039 if (__predict_false(__fifo_ret)) { \
1040 gen6_gt_check_fifodbg(dev_priv); \
1041 } \
1042 }
1043 __i915_write(8, 8)
1044 __i915_write(16, 16)
1045 __i915_write(32, 32)
1046 __i915_write(64, 64)
1047 #undef __i915_write
1048