1 /* $NetBSD: i915_drv.c,v 1.48 2022/09/22 14:37:38 riastradh Exp $ */
2
3 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
4 */
5 /*
6 *
7 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * All Rights Reserved.
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the
12 * "Software"), to deal in the Software without restriction, including
13 * without limitation the rights to use, copy, modify, merge, publish,
14 * distribute, sub license, and/or sell copies of the Software, and to
15 * permit persons to whom the Software is furnished to do so, subject to
16 * the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 *
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: i915_drv.c,v 1.48 2022/09/22 14:37:38 riastradh Exp $");
34
35 #include <linux/acpi.h>
36 #include <linux/device.h>
37 #include <linux/oom.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/pm.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/pnp.h>
43 #include <linux/slab.h>
44 #include <linux/vga_switcheroo.h>
45 #include <linux/vt.h>
46 #include <acpi/video.h>
47
48 #include <drm/drm_atomic_helper.h>
49 #include <drm/drm_ioctl.h>
50 #include <drm/drm_irq.h>
51 #include <drm/drm_pci.h>
52 #include <drm/drm_probe_helper.h>
53 #include <drm/i915_drm.h>
54
55 #include "display/intel_acpi.h"
56 #include "display/intel_audio.h"
57 #include "display/intel_bw.h"
58 #include "display/intel_cdclk.h"
59 #include "display/intel_display_types.h"
60 #include "display/intel_dp.h"
61 #include "display/intel_fbdev.h"
62 #include "display/intel_hotplug.h"
63 #include "display/intel_overlay.h"
64 #include "display/intel_pipe_crc.h"
65 #include "display/intel_sprite.h"
66 #include "display/intel_vga.h"
67
68 #include "gem/i915_gem_context.h"
69 #include "gem/i915_gem_ioctls.h"
70 #include "gem/i915_gem_mman.h"
71 #include "gt/intel_gt.h"
72 #include "gt/intel_gt_pm.h"
73 #include "gt/intel_rc6.h"
74
75 #include "i915_debugfs.h"
76 #include "i915_drv.h"
77 #include "i915_irq.h"
78 #include "i915_memcpy.h"
79 #include "i915_perf.h"
80 #include "i915_query.h"
81 #include "i915_suspend.h"
82 #include "i915_switcheroo.h"
83 #include "i915_sysfs.h"
84 #include "i915_trace.h"
85 #include "i915_vgpu.h"
86 #include "intel_csr.h"
87 #include "intel_memory_region.h"
88 #include "intel_pm.h"
89
90 #ifdef __NetBSD__
91 #ifdef notyet
92 #if defined(__i386__)
93 #include "pnpbios.h"
94 #endif
95 #if NPNPBIOS > 0
96 #define CONFIG_PNP
97 #endif
98 #endif
99 #endif
100
101 #include <linux/nbsd-namespace.h>
102
103 static struct drm_driver driver;
104
105 struct vlv_s0ix_state {
106 /* GAM */
107 u32 wr_watermark;
108 u32 gfx_prio_ctrl;
109 u32 arb_mode;
110 u32 gfx_pend_tlb0;
111 u32 gfx_pend_tlb1;
112 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
113 u32 media_max_req_count;
114 u32 gfx_max_req_count;
115 u32 render_hwsp;
116 u32 ecochk;
117 u32 bsd_hwsp;
118 u32 blt_hwsp;
119 u32 tlb_rd_addr;
120
121 /* MBC */
122 u32 g3dctl;
123 u32 gsckgctl;
124 u32 mbctl;
125
126 /* GCP */
127 u32 ucgctl1;
128 u32 ucgctl3;
129 u32 rcgctl1;
130 u32 rcgctl2;
131 u32 rstctl;
132 u32 misccpctl;
133
134 /* GPM */
135 u32 gfxpause;
136 u32 rpdeuhwtc;
137 u32 rpdeuc;
138 u32 ecobus;
139 u32 pwrdwnupctl;
140 u32 rp_down_timeout;
141 u32 rp_deucsw;
142 u32 rcubmabdtmr;
143 u32 rcedata;
144 u32 spare2gh;
145
146 /* Display 1 CZ domain */
147 u32 gt_imr;
148 u32 gt_ier;
149 u32 pm_imr;
150 u32 pm_ier;
151 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
152
153 /* GT SA CZ domain */
154 u32 tilectl;
155 u32 gt_fifoctl;
156 u32 gtlc_wake_ctrl;
157 u32 gtlc_survive;
158 u32 pmwgicz;
159
160 /* Display 2 CZ domain */
161 u32 gu_ctl0;
162 u32 gu_ctl1;
163 u32 pcbr;
164 u32 clock_gate_dis2;
165 };
166
i915_get_bridge_dev(struct drm_i915_private * dev_priv)167 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
168 {
169 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
170
171 dev_priv->bridge_dev =
172 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
173 if (!dev_priv->bridge_dev) {
174 DRM_ERROR("bridge device not found\n");
175 return -1;
176 }
177 return 0;
178 }
179
180 /* Allocate space for the MCH regs if needed, return nonzero on error */
181 static int
intel_alloc_mchbar_resource(struct drm_i915_private * dev_priv)182 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
183 {
184 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
185 #ifdef CONFIG_PNP
186 u32 temp_lo, temp_hi = 0;
187 u64 mchbar_addr;
188 #endif
189 int ret;
190
191 #ifdef CONFIG_PNP
192 if (INTEL_GEN(dev_priv) >= 4)
193 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
194 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
195 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
196
197 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
198 if (mchbar_addr &&
199 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
200 return 0;
201 #endif
202
203 /* Get some space for it */
204 dev_priv->mch_res.name = "i915 MCHBAR";
205 dev_priv->mch_res.flags = IORESOURCE_MEM;
206 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
207 &dev_priv->mch_res,
208 MCHBAR_SIZE, MCHBAR_SIZE,
209 PCIBIOS_MIN_MEM,
210 0, pcibios_align_resource,
211 dev_priv->bridge_dev);
212 if (ret) {
213 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
214 dev_priv->mch_res.start = 0;
215 return ret;
216 }
217
218 if (INTEL_GEN(dev_priv) >= 4)
219 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
220 upper_32_bits(dev_priv->mch_res.start));
221
222 pci_write_config_dword(dev_priv->bridge_dev, reg,
223 lower_32_bits(dev_priv->mch_res.start));
224 return 0;
225 }
226
227 /* Setup MCHBAR if possible, return true if we should disable it again */
228 static void
intel_setup_mchbar(struct drm_i915_private * dev_priv)229 intel_setup_mchbar(struct drm_i915_private *dev_priv)
230 {
231 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
232 u32 temp;
233 bool enabled;
234
235 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
236 return;
237
238 dev_priv->mchbar_need_disable = false;
239
240 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
241 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
242 enabled = !!(temp & DEVEN_MCHBAR_EN);
243 } else {
244 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
245 enabled = temp & 1;
246 }
247
248 /* If it's already enabled, don't have to do anything */
249 if (enabled)
250 return;
251
252 if (intel_alloc_mchbar_resource(dev_priv))
253 return;
254
255 dev_priv->mchbar_need_disable = true;
256
257 /* Space is allocated or reserved, so enable it. */
258 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
259 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
260 temp | DEVEN_MCHBAR_EN);
261 } else {
262 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
263 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
264 }
265 }
266
267 static void
intel_teardown_mchbar(struct drm_i915_private * dev_priv)268 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
269 {
270 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
271
272 if (dev_priv->mchbar_need_disable) {
273 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
274 u32 deven_val;
275
276 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
277 &deven_val);
278 deven_val &= ~DEVEN_MCHBAR_EN;
279 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
280 deven_val);
281 } else {
282 u32 mchbar_val;
283
284 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
285 &mchbar_val);
286 mchbar_val &= ~1;
287 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
288 mchbar_val);
289 }
290 }
291
292 if (dev_priv->mch_res.start)
293 release_resource(&dev_priv->mch_res);
294 }
295
i915_driver_modeset_probe(struct drm_i915_private * i915)296 static int i915_driver_modeset_probe(struct drm_i915_private *i915)
297 {
298 int ret;
299
300 if (i915_inject_probe_failure(i915))
301 return -ENODEV;
302
303 if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
304 ret = drm_vblank_init(&i915->drm,
305 INTEL_NUM_PIPES(i915));
306 if (ret)
307 goto out;
308 }
309
310 intel_bios_init(i915);
311
312 ret = intel_vga_register(i915);
313 if (ret)
314 goto out;
315
316 #ifdef __NetBSD__
317 intel_register_dsm_handler(i915);
318 #else
319 intel_register_dsm_handler();
320 #endif
321
322 ret = i915_switcheroo_register(i915);
323 if (ret)
324 goto cleanup_vga_client;
325
326 intel_power_domains_init_hw(i915, false);
327
328 intel_csr_ucode_init(i915);
329
330 ret = intel_irq_install(i915);
331 if (ret)
332 goto cleanup_csr;
333
334 /* Important: The output setup functions called by modeset_init need
335 * working irqs for e.g. gmbus and dp aux transfers. */
336 ret = intel_modeset_init(i915);
337 if (ret)
338 goto cleanup_irq;
339
340 ret = i915_gem_init(i915);
341 if (ret)
342 goto cleanup_modeset;
343
344 intel_overlay_setup(i915);
345
346 if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
347 return 0;
348
349 ret = intel_fbdev_init(&i915->drm);
350 if (ret)
351 goto cleanup_gem;
352
353 /* Only enable hotplug handling once the fbdev is fully set up. */
354 intel_hpd_init(i915);
355
356 intel_init_ipc(i915);
357
358 return 0;
359
360 cleanup_gem:
361 i915_gem_suspend(i915);
362 i915_gem_driver_remove(i915);
363 i915_gem_driver_release(i915);
364 cleanup_modeset:
365 intel_modeset_driver_remove(i915);
366 cleanup_irq:
367 intel_irq_uninstall(i915);
368 cleanup_csr:
369 intel_csr_ucode_fini(i915);
370 intel_power_domains_driver_remove(i915);
371 i915_switcheroo_unregister(i915);
372 cleanup_vga_client:
373 intel_vga_unregister(i915);
374 out:
375 return ret;
376 }
377
i915_driver_modeset_remove(struct drm_i915_private * i915)378 static void i915_driver_modeset_remove(struct drm_i915_private *i915)
379 {
380 intel_modeset_driver_remove(i915);
381
382 intel_irq_uninstall(i915);
383
384 intel_bios_driver_remove(i915);
385
386 i915_switcheroo_unregister(i915);
387
388 intel_vga_unregister(i915);
389
390 intel_csr_ucode_fini(i915);
391 }
392
intel_init_dpio(struct drm_i915_private * dev_priv)393 static void intel_init_dpio(struct drm_i915_private *dev_priv)
394 {
395 /*
396 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
397 * CHV x1 PHY (DP/HDMI D)
398 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
399 */
400 if (IS_CHERRYVIEW(dev_priv)) {
401 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
402 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
403 } else if (IS_VALLEYVIEW(dev_priv)) {
404 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
405 }
406 }
407
i915_workqueues_init(struct drm_i915_private * dev_priv)408 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
409 {
410 /*
411 * The i915 workqueue is primarily used for batched retirement of
412 * requests (and thus managing bo) once the task has been completed
413 * by the GPU. i915_retire_requests() is called directly when we
414 * need high-priority retirement, such as waiting for an explicit
415 * bo.
416 *
417 * It is also used for periodic low-priority events, such as
418 * idle-timers and recording error state.
419 *
420 * All tasks on the workqueue are expected to acquire the dev mutex
421 * so there is no point in running more than one instance of the
422 * workqueue at any time. Use an ordered one.
423 */
424 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
425 if (dev_priv->wq == NULL)
426 goto out_err;
427
428 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
429 if (dev_priv->hotplug.dp_wq == NULL)
430 goto out_free_wq;
431
432 return 0;
433
434 out_free_wq:
435 destroy_workqueue(dev_priv->wq);
436 out_err:
437 DRM_ERROR("Failed to allocate workqueues.\n");
438
439 return -ENOMEM;
440 }
441
i915_workqueues_cleanup(struct drm_i915_private * dev_priv)442 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
443 {
444 destroy_workqueue(dev_priv->hotplug.dp_wq);
445 destroy_workqueue(dev_priv->wq);
446 }
447
448 /*
449 * We don't keep the workarounds for pre-production hardware, so we expect our
450 * driver to fail on these machines in one way or another. A little warning on
451 * dmesg may help both the user and the bug triagers.
452 *
453 * Our policy for removing pre-production workarounds is to keep the
454 * current gen workarounds as a guide to the bring-up of the next gen
455 * (workarounds have a habit of persisting!). Anything older than that
456 * should be removed along with the complications they introduce.
457 */
intel_detect_preproduction_hw(struct drm_i915_private * dev_priv)458 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
459 {
460 bool pre = false;
461
462 pre |= IS_HSW_EARLY_SDV(dev_priv);
463 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
464 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
465 pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
466
467 if (pre) {
468 DRM_ERROR("This is a pre-production stepping. "
469 "It may not be fully functional.\n");
470 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
471 }
472 }
473
vlv_alloc_s0ix_state(struct drm_i915_private * i915)474 static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
475 {
476 if (!IS_VALLEYVIEW(i915))
477 return 0;
478
479 /* we write all the values in the struct, so no need to zero it out */
480 i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
481 GFP_KERNEL);
482 if (!i915->vlv_s0ix_state)
483 return -ENOMEM;
484
485 return 0;
486 }
487
vlv_free_s0ix_state(struct drm_i915_private * i915)488 static void vlv_free_s0ix_state(struct drm_i915_private *i915)
489 {
490 if (!i915->vlv_s0ix_state)
491 return;
492
493 kfree(i915->vlv_s0ix_state);
494 i915->vlv_s0ix_state = NULL;
495 }
496
sanitize_gpu(struct drm_i915_private * i915)497 static void sanitize_gpu(struct drm_i915_private *i915)
498 {
499 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
500 __intel_gt_reset(&i915->gt, ALL_ENGINES);
501 }
502
503 /**
504 * i915_driver_early_probe - setup state not requiring device access
505 * @dev_priv: device private
506 *
507 * Initialize everything that is a "SW-only" state, that is state not
508 * requiring accessing the device or exposing the driver via kernel internal
509 * or userspace interfaces. Example steps belonging here: lock initialization,
510 * system memory allocation, setting up device specific attributes and
511 * function hooks not requiring accessing the device.
512 */
i915_driver_early_probe(struct drm_i915_private * dev_priv)513 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
514 {
515 int ret = 0;
516
517 if (i915_inject_probe_failure(dev_priv))
518 return -ENODEV;
519
520 intel_device_info_subplatform_init(dev_priv);
521
522 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
523 intel_uncore_init_early(&dev_priv->uncore, dev_priv);
524
525 spin_lock_init(&dev_priv->irq_lock);
526 spin_lock_init(&dev_priv->gpu_error.lock);
527 mutex_init(&dev_priv->backlight_lock);
528
529 mutex_init(&dev_priv->sb_lock);
530 pm_qos_add_request(&dev_priv->sb_qos,
531 PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
532
533 mutex_init(&dev_priv->av_mutex);
534 mutex_init(&dev_priv->wm.wm_mutex);
535 mutex_init(&dev_priv->pps_mutex);
536 mutex_init(&dev_priv->hdcp_comp_mutex);
537
538 i915_memcpy_init_early(dev_priv);
539 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
540
541 ret = i915_workqueues_init(dev_priv);
542 if (ret < 0)
543 return ret;
544
545 ret = vlv_alloc_s0ix_state(dev_priv);
546 if (ret < 0)
547 goto err_workqueues;
548
549 intel_wopcm_init_early(&dev_priv->wopcm);
550
551 intel_gt_init_early(&dev_priv->gt, dev_priv);
552
553 i915_gem_init_early(dev_priv);
554
555 /* This must be called before any calls to HAS_PCH_* */
556 intel_detect_pch(dev_priv);
557
558 intel_pm_setup(dev_priv);
559 intel_init_dpio(dev_priv);
560 ret = intel_power_domains_init(dev_priv);
561 if (ret < 0)
562 goto err_gem;
563 intel_irq_init(dev_priv);
564 intel_init_display_hooks(dev_priv);
565 intel_init_clock_gating_hooks(dev_priv);
566 intel_init_audio_hooks(dev_priv);
567 intel_display_crc_init(dev_priv);
568
569 intel_detect_preproduction_hw(dev_priv);
570
571 return 0;
572
573 err_gem:
574 i915_gem_cleanup_early(dev_priv);
575 intel_gt_driver_late_release(&dev_priv->gt);
576 vlv_free_s0ix_state(dev_priv);
577 err_workqueues:
578 i915_workqueues_cleanup(dev_priv);
579 mutex_destroy(&dev_priv->hdcp_comp_mutex);
580 mutex_destroy(&dev_priv->pps_mutex);
581 mutex_destroy(&dev_priv->wm.wm_mutex);
582 mutex_destroy(&dev_priv->av_mutex);
583 mutex_destroy(&dev_priv->sb_lock);
584 mutex_destroy(&dev_priv->backlight_lock);
585 spin_lock_destroy(&dev_priv->gpu_error.lock);
586 spin_lock_destroy(&dev_priv->irq_lock);
587 intel_uncore_fini_early(&dev_priv->uncore, dev_priv);
588 intel_uncore_mmio_debug_fini_early(&dev_priv->mmio_debug);
589 return ret;
590 }
591
592 /**
593 * i915_driver_late_release - cleanup the setup done in
594 * i915_driver_early_probe()
595 * @dev_priv: device private
596 */
i915_driver_late_release(struct drm_i915_private * dev_priv)597 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
598 {
599 intel_display_crc_fini(dev_priv);
600 intel_irq_fini(dev_priv);
601 intel_power_domains_cleanup(dev_priv);
602 i915_gem_cleanup_early(dev_priv);
603 intel_gt_driver_late_release(&dev_priv->gt);
604 vlv_free_s0ix_state(dev_priv);
605 i915_workqueues_cleanup(dev_priv);
606
607 pm_qos_remove_request(&dev_priv->sb_qos);
608 mutex_destroy(&dev_priv->hdcp_comp_mutex);
609 mutex_destroy(&dev_priv->pps_mutex);
610 mutex_destroy(&dev_priv->wm.wm_mutex);
611 mutex_destroy(&dev_priv->av_mutex);
612 mutex_destroy(&dev_priv->sb_lock);
613 mutex_destroy(&dev_priv->backlight_lock);
614 spin_lock_destroy(&dev_priv->gpu_error.lock);
615 spin_lock_destroy(&dev_priv->irq_lock);
616 intel_uncore_fini_early(&dev_priv->uncore, dev_priv);
617 intel_uncore_mmio_debug_fini_early(&dev_priv->mmio_debug);
618 }
619
620 /**
621 * i915_driver_mmio_probe - setup device MMIO
622 * @dev_priv: device private
623 *
624 * Setup minimal device state necessary for MMIO accesses later in the
625 * initialization sequence. The setup here should avoid any other device-wide
626 * side effects or exposing the driver via kernel internal or user space
627 * interfaces.
628 */
i915_driver_mmio_probe(struct drm_i915_private * dev_priv)629 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
630 {
631 int ret;
632
633 if (i915_inject_probe_failure(dev_priv))
634 return -ENODEV;
635
636 if (i915_get_bridge_dev(dev_priv))
637 return -EIO;
638
639 ret = intel_uncore_init_mmio(&dev_priv->uncore);
640 if (ret < 0)
641 goto err_bridge;
642
643 /* Try to make sure MCHBAR is enabled before poking at it */
644 intel_setup_mchbar(dev_priv);
645
646 intel_device_info_init_mmio(dev_priv);
647
648 intel_uncore_prune_mmio_domains(&dev_priv->uncore);
649
650 intel_uc_init_mmio(&dev_priv->gt.uc);
651
652 ret = intel_engines_init_mmio(&dev_priv->gt);
653 if (ret)
654 goto err_uncore;
655
656 /* As early as possible, scrub existing GPU state before clobbering */
657 sanitize_gpu(dev_priv);
658
659 return 0;
660
661 err_uncore:
662 intel_teardown_mchbar(dev_priv);
663 intel_uncore_fini_mmio(&dev_priv->uncore);
664 err_bridge:
665 pci_dev_put(dev_priv->bridge_dev);
666
667 return ret;
668 }
669
670 /**
671 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
672 * @dev_priv: device private
673 */
i915_driver_mmio_release(struct drm_i915_private * dev_priv)674 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
675 {
676 intel_teardown_mchbar(dev_priv);
677 intel_uncore_fini_mmio(&dev_priv->uncore);
678 pci_dev_put(dev_priv->bridge_dev);
679 }
680
intel_sanitize_options(struct drm_i915_private * dev_priv)681 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
682 {
683 intel_gvt_sanitize_options(dev_priv);
684 }
685
686 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
687
intel_dram_type_str(enum intel_dram_type type)688 static const char *intel_dram_type_str(enum intel_dram_type type)
689 {
690 static const char * const str[] = {
691 DRAM_TYPE_STR(UNKNOWN),
692 DRAM_TYPE_STR(DDR3),
693 DRAM_TYPE_STR(DDR4),
694 DRAM_TYPE_STR(LPDDR3),
695 DRAM_TYPE_STR(LPDDR4),
696 };
697
698 if (type >= ARRAY_SIZE(str))
699 type = INTEL_DRAM_UNKNOWN;
700
701 return str[type];
702 }
703
704 #undef DRAM_TYPE_STR
705
intel_dimm_num_devices(const struct dram_dimm_info * dimm)706 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
707 {
708 return dimm->ranks * 64 / (dimm->width ?: 1);
709 }
710
711 /* Returns total GB for the whole DIMM */
skl_get_dimm_size(u16 val)712 static int skl_get_dimm_size(u16 val)
713 {
714 return val & SKL_DRAM_SIZE_MASK;
715 }
716
skl_get_dimm_width(u16 val)717 static int skl_get_dimm_width(u16 val)
718 {
719 if (skl_get_dimm_size(val) == 0)
720 return 0;
721
722 switch (val & SKL_DRAM_WIDTH_MASK) {
723 case SKL_DRAM_WIDTH_X8:
724 case SKL_DRAM_WIDTH_X16:
725 case SKL_DRAM_WIDTH_X32:
726 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
727 return 8 << val;
728 default:
729 MISSING_CASE(val);
730 return 0;
731 }
732 }
733
skl_get_dimm_ranks(u16 val)734 static int skl_get_dimm_ranks(u16 val)
735 {
736 if (skl_get_dimm_size(val) == 0)
737 return 0;
738
739 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
740
741 return val + 1;
742 }
743
744 /* Returns total GB for the whole DIMM */
cnl_get_dimm_size(u16 val)745 static int cnl_get_dimm_size(u16 val)
746 {
747 return (val & CNL_DRAM_SIZE_MASK) / 2;
748 }
749
cnl_get_dimm_width(u16 val)750 static int cnl_get_dimm_width(u16 val)
751 {
752 if (cnl_get_dimm_size(val) == 0)
753 return 0;
754
755 switch (val & CNL_DRAM_WIDTH_MASK) {
756 case CNL_DRAM_WIDTH_X8:
757 case CNL_DRAM_WIDTH_X16:
758 case CNL_DRAM_WIDTH_X32:
759 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
760 return 8 << val;
761 default:
762 MISSING_CASE(val);
763 return 0;
764 }
765 }
766
cnl_get_dimm_ranks(u16 val)767 static int cnl_get_dimm_ranks(u16 val)
768 {
769 if (cnl_get_dimm_size(val) == 0)
770 return 0;
771
772 val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
773
774 return val + 1;
775 }
776
777 static bool
skl_is_16gb_dimm(const struct dram_dimm_info * dimm)778 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
779 {
780 /* Convert total GB to Gb per DRAM device */
781 return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
782 }
783
784 static void
skl_dram_get_dimm_info(struct drm_i915_private * dev_priv,struct dram_dimm_info * dimm,int channel,char dimm_name,u16 val)785 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
786 struct dram_dimm_info *dimm,
787 int channel, char dimm_name, u16 val)
788 {
789 if (INTEL_GEN(dev_priv) >= 10) {
790 dimm->size = cnl_get_dimm_size(val);
791 dimm->width = cnl_get_dimm_width(val);
792 dimm->ranks = cnl_get_dimm_ranks(val);
793 } else {
794 dimm->size = skl_get_dimm_size(val);
795 dimm->width = skl_get_dimm_width(val);
796 dimm->ranks = skl_get_dimm_ranks(val);
797 }
798
799 DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
800 channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
801 yesno(skl_is_16gb_dimm(dimm)));
802 }
803
804 static int
skl_dram_get_channel_info(struct drm_i915_private * dev_priv,struct dram_channel_info * ch,int channel,u32 val)805 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
806 struct dram_channel_info *ch,
807 int channel, u32 val)
808 {
809 skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
810 channel, 'L', val & 0xffff);
811 skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
812 channel, 'S', val >> 16);
813
814 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
815 DRM_DEBUG_KMS("CH%u not populated\n", channel);
816 return -EINVAL;
817 }
818
819 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
820 ch->ranks = 2;
821 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
822 ch->ranks = 2;
823 else
824 ch->ranks = 1;
825
826 ch->is_16gb_dimm =
827 skl_is_16gb_dimm(&ch->dimm_l) ||
828 skl_is_16gb_dimm(&ch->dimm_s);
829
830 DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
831 channel, ch->ranks, yesno(ch->is_16gb_dimm));
832
833 return 0;
834 }
835
836 static bool
intel_is_dram_symmetric(const struct dram_channel_info * ch0,const struct dram_channel_info * ch1)837 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
838 const struct dram_channel_info *ch1)
839 {
840 return !memcmp(ch0, ch1, sizeof(*ch0)) &&
841 (ch0->dimm_s.size == 0 ||
842 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
843 }
844
845 static int
skl_dram_get_channels_info(struct drm_i915_private * dev_priv)846 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
847 {
848 struct dram_info *dram_info = &dev_priv->dram_info;
849 struct dram_channel_info ch0 = {}, ch1 = {};
850 u32 val;
851 int ret;
852
853 val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
854 ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
855 if (ret == 0)
856 dram_info->num_channels++;
857
858 val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
859 ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
860 if (ret == 0)
861 dram_info->num_channels++;
862
863 if (dram_info->num_channels == 0) {
864 DRM_INFO("Number of memory channels is zero\n");
865 return -EINVAL;
866 }
867
868 /*
869 * If any of the channel is single rank channel, worst case output
870 * will be same as if single rank memory, so consider single rank
871 * memory.
872 */
873 if (ch0.ranks == 1 || ch1.ranks == 1)
874 dram_info->ranks = 1;
875 else
876 dram_info->ranks = max(ch0.ranks, ch1.ranks);
877
878 if (dram_info->ranks == 0) {
879 DRM_INFO("couldn't get memory rank information\n");
880 return -EINVAL;
881 }
882
883 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
884
885 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
886
887 DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
888 yesno(dram_info->symmetric_memory));
889 return 0;
890 }
891
892 static enum intel_dram_type
skl_get_dram_type(struct drm_i915_private * dev_priv)893 skl_get_dram_type(struct drm_i915_private *dev_priv)
894 {
895 u32 val;
896
897 val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
898
899 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
900 case SKL_DRAM_DDR_TYPE_DDR3:
901 return INTEL_DRAM_DDR3;
902 case SKL_DRAM_DDR_TYPE_DDR4:
903 return INTEL_DRAM_DDR4;
904 case SKL_DRAM_DDR_TYPE_LPDDR3:
905 return INTEL_DRAM_LPDDR3;
906 case SKL_DRAM_DDR_TYPE_LPDDR4:
907 return INTEL_DRAM_LPDDR4;
908 default:
909 MISSING_CASE(val);
910 return INTEL_DRAM_UNKNOWN;
911 }
912 }
913
914 static int
skl_get_dram_info(struct drm_i915_private * dev_priv)915 skl_get_dram_info(struct drm_i915_private *dev_priv)
916 {
917 struct dram_info *dram_info = &dev_priv->dram_info;
918 u32 mem_freq_khz, val;
919 int ret;
920
921 dram_info->type = skl_get_dram_type(dev_priv);
922 DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
923
924 ret = skl_dram_get_channels_info(dev_priv);
925 if (ret)
926 return ret;
927
928 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
929 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
930 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
931
932 dram_info->bandwidth_kbps = dram_info->num_channels *
933 mem_freq_khz * 8;
934
935 if (dram_info->bandwidth_kbps == 0) {
936 DRM_INFO("Couldn't get system memory bandwidth\n");
937 return -EINVAL;
938 }
939
940 dram_info->valid = true;
941 return 0;
942 }
943
944 /* Returns Gb per DRAM device */
bxt_get_dimm_size(u32 val)945 static int bxt_get_dimm_size(u32 val)
946 {
947 switch (val & BXT_DRAM_SIZE_MASK) {
948 case BXT_DRAM_SIZE_4GBIT:
949 return 4;
950 case BXT_DRAM_SIZE_6GBIT:
951 return 6;
952 case BXT_DRAM_SIZE_8GBIT:
953 return 8;
954 case BXT_DRAM_SIZE_12GBIT:
955 return 12;
956 case BXT_DRAM_SIZE_16GBIT:
957 return 16;
958 default:
959 MISSING_CASE(val);
960 return 0;
961 }
962 }
963
bxt_get_dimm_width(u32 val)964 static int bxt_get_dimm_width(u32 val)
965 {
966 if (!bxt_get_dimm_size(val))
967 return 0;
968
969 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
970
971 return 8 << val;
972 }
973
bxt_get_dimm_ranks(u32 val)974 static int bxt_get_dimm_ranks(u32 val)
975 {
976 if (!bxt_get_dimm_size(val))
977 return 0;
978
979 switch (val & BXT_DRAM_RANK_MASK) {
980 case BXT_DRAM_RANK_SINGLE:
981 return 1;
982 case BXT_DRAM_RANK_DUAL:
983 return 2;
984 default:
985 MISSING_CASE(val);
986 return 0;
987 }
988 }
989
bxt_get_dimm_type(u32 val)990 static enum intel_dram_type bxt_get_dimm_type(u32 val)
991 {
992 if (!bxt_get_dimm_size(val))
993 return INTEL_DRAM_UNKNOWN;
994
995 switch (val & BXT_DRAM_TYPE_MASK) {
996 case BXT_DRAM_TYPE_DDR3:
997 return INTEL_DRAM_DDR3;
998 case BXT_DRAM_TYPE_LPDDR3:
999 return INTEL_DRAM_LPDDR3;
1000 case BXT_DRAM_TYPE_DDR4:
1001 return INTEL_DRAM_DDR4;
1002 case BXT_DRAM_TYPE_LPDDR4:
1003 return INTEL_DRAM_LPDDR4;
1004 default:
1005 MISSING_CASE(val);
1006 return INTEL_DRAM_UNKNOWN;
1007 }
1008 }
1009
bxt_get_dimm_info(struct dram_dimm_info * dimm,u32 val)1010 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1011 u32 val)
1012 {
1013 dimm->width = bxt_get_dimm_width(val);
1014 dimm->ranks = bxt_get_dimm_ranks(val);
1015
1016 /*
1017 * Size in register is Gb per DRAM device. Convert to total
1018 * GB to match the way we report this for non-LP platforms.
1019 */
1020 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1021 }
1022
1023 static int
bxt_get_dram_info(struct drm_i915_private * dev_priv)1024 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1025 {
1026 struct dram_info *dram_info = &dev_priv->dram_info;
1027 u32 dram_channels;
1028 u32 mem_freq_khz, val;
1029 u8 num_active_channels;
1030 int i;
1031
1032 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1033 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1034 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1035
1036 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1037 num_active_channels = hweight32(dram_channels);
1038
1039 /* Each active bit represents 4-byte channel */
1040 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1041
1042 if (dram_info->bandwidth_kbps == 0) {
1043 DRM_INFO("Couldn't get system memory bandwidth\n");
1044 return -EINVAL;
1045 }
1046
1047 /*
1048 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1049 */
1050 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1051 struct dram_dimm_info dimm;
1052 enum intel_dram_type type;
1053
1054 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1055 if (val == 0xFFFFFFFF)
1056 continue;
1057
1058 dram_info->num_channels++;
1059
1060 bxt_get_dimm_info(&dimm, val);
1061 type = bxt_get_dimm_type(val);
1062
1063 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1064 dram_info->type != INTEL_DRAM_UNKNOWN &&
1065 dram_info->type != type);
1066
1067 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1068 i - BXT_D_CR_DRP0_DUNIT_START,
1069 dimm.size, dimm.width, dimm.ranks,
1070 intel_dram_type_str(type));
1071
1072 /*
1073 * If any of the channel is single rank channel,
1074 * worst case output will be same as if single rank
1075 * memory, so consider single rank memory.
1076 */
1077 if (dram_info->ranks == 0)
1078 dram_info->ranks = dimm.ranks;
1079 else if (dimm.ranks == 1)
1080 dram_info->ranks = 1;
1081
1082 if (type != INTEL_DRAM_UNKNOWN)
1083 dram_info->type = type;
1084 }
1085
1086 if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1087 dram_info->ranks == 0) {
1088 DRM_INFO("couldn't get memory information\n");
1089 return -EINVAL;
1090 }
1091
1092 dram_info->valid = true;
1093 return 0;
1094 }
1095
1096 static void
intel_get_dram_info(struct drm_i915_private * dev_priv)1097 intel_get_dram_info(struct drm_i915_private *dev_priv)
1098 {
1099 struct dram_info *dram_info = &dev_priv->dram_info;
1100 int ret;
1101
1102 /*
1103 * Assume 16Gb DIMMs are present until proven otherwise.
1104 * This is only used for the level 0 watermark latency
1105 * w/a which does not apply to bxt/glk.
1106 */
1107 dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1108
1109 if (INTEL_GEN(dev_priv) < 9 || !HAS_DISPLAY(dev_priv))
1110 return;
1111
1112 if (IS_GEN9_LP(dev_priv))
1113 ret = bxt_get_dram_info(dev_priv);
1114 else
1115 ret = skl_get_dram_info(dev_priv);
1116 if (ret)
1117 return;
1118
1119 DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1120 dram_info->bandwidth_kbps,
1121 dram_info->num_channels);
1122
1123 DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1124 dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1125 }
1126
gen9_edram_size_mb(struct drm_i915_private * dev_priv,u32 cap)1127 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1128 {
1129 static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1130 static const u8 sets[4] = { 1, 1, 2, 2 };
1131
1132 return EDRAM_NUM_BANKS(cap) *
1133 ways[EDRAM_WAYS_IDX(cap)] *
1134 sets[EDRAM_SETS_IDX(cap)];
1135 }
1136
edram_detect(struct drm_i915_private * dev_priv)1137 static void edram_detect(struct drm_i915_private *dev_priv)
1138 {
1139 u32 edram_cap = 0;
1140
1141 if (!(IS_HASWELL(dev_priv) ||
1142 IS_BROADWELL(dev_priv) ||
1143 INTEL_GEN(dev_priv) >= 9))
1144 return;
1145
1146 edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1147
1148 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1149
1150 if (!(edram_cap & EDRAM_ENABLED))
1151 return;
1152
1153 /*
1154 * The needed capability bits for size calculation are not there with
1155 * pre gen9 so return 128MB always.
1156 */
1157 if (INTEL_GEN(dev_priv) < 9)
1158 dev_priv->edram_size_mb = 128;
1159 else
1160 dev_priv->edram_size_mb =
1161 gen9_edram_size_mb(dev_priv, edram_cap);
1162
1163 dev_info(dev_priv->drm.dev,
1164 "Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1165 }
1166
1167 /**
1168 * i915_driver_hw_probe - setup state requiring device access
1169 * @dev_priv: device private
1170 *
1171 * Setup state that requires accessing the device, but doesn't require
1172 * exposing the driver via kernel internal or userspace interfaces.
1173 */
i915_driver_hw_probe(struct drm_i915_private * dev_priv)1174 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
1175 {
1176 struct pci_dev *pdev = dev_priv->drm.pdev;
1177 int ret;
1178
1179 if (i915_inject_probe_failure(dev_priv))
1180 return -ENODEV;
1181
1182 intel_device_info_runtime_init(dev_priv);
1183
1184 if (HAS_PPGTT(dev_priv)) {
1185 if (intel_vgpu_active(dev_priv) &&
1186 !intel_vgpu_has_full_ppgtt(dev_priv)) {
1187 i915_report_error(dev_priv,
1188 "incompatible vGPU found, support for isolated ppGTT required\n");
1189 return -ENXIO;
1190 }
1191 }
1192
1193 if (HAS_EXECLISTS(dev_priv)) {
1194 /*
1195 * Older GVT emulation depends upon intercepting CSB mmio,
1196 * which we no longer use, preferring to use the HWSP cache
1197 * instead.
1198 */
1199 if (intel_vgpu_active(dev_priv) &&
1200 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1201 i915_report_error(dev_priv,
1202 "old vGPU host found, support for HWSP emulation required\n");
1203 return -ENXIO;
1204 }
1205 }
1206
1207 intel_sanitize_options(dev_priv);
1208
1209 /* needs to be done before ggtt probe */
1210 edram_detect(dev_priv);
1211
1212 i915_perf_init(dev_priv);
1213
1214 ret = i915_ggtt_probe_hw(dev_priv);
1215 if (ret)
1216 goto err_perf;
1217
1218 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
1219 if (ret)
1220 goto err_ggtt;
1221
1222 ret = i915_ggtt_init_hw(dev_priv);
1223 if (ret)
1224 goto err_ggtt;
1225
1226 ret = intel_memory_regions_hw_probe(dev_priv);
1227 if (ret)
1228 goto err_ggtt;
1229
1230 intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
1231
1232 ret = i915_ggtt_enable_hw(dev_priv);
1233 if (ret) {
1234 DRM_ERROR("failed to enable GGTT\n");
1235 goto err_mem_regions;
1236 }
1237
1238 pci_set_master(pdev);
1239
1240 #ifndef __NetBSD__
1241 /*
1242 * We don't have a max segment size, so set it to the max so sg's
1243 * debugging layer doesn't complain
1244 */
1245 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1246 #endif
1247
1248 #ifndef __NetBSD__ /* Handled in intel_ggtt.c. */
1249 /* overlay on gen2 is broken and can't address above 1G */
1250 if (IS_GEN(dev_priv, 2)) {
1251 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1252 if (ret) {
1253 DRM_ERROR("failed to set DMA mask\n");
1254
1255 goto err_mem_regions;
1256 }
1257 }
1258
1259 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1260 * using 32bit addressing, overwriting memory if HWS is located
1261 * above 4GB.
1262 *
1263 * The documentation also mentions an issue with undefined
1264 * behaviour if any general state is accessed within a page above 4GB,
1265 * which also needs to be handled carefully.
1266 */
1267 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1268 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1269
1270 if (ret) {
1271 DRM_ERROR("failed to set DMA mask\n");
1272
1273 goto err_mem_regions;
1274 }
1275 }
1276 #endif
1277
1278 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1279 PM_QOS_DEFAULT_VALUE);
1280
1281 intel_gt_init_workarounds(dev_priv);
1282
1283 /* On the 945G/GM, the chipset reports the MSI capability on the
1284 * integrated graphics even though the support isn't actually there
1285 * according to the published specs. It doesn't appear to function
1286 * correctly in testing on 945G.
1287 * This may be a side effect of MSI having been made available for PEG
1288 * and the registers being closely associated.
1289 *
1290 * According to chipset errata, on the 965GM, MSI interrupts may
1291 * be lost or delayed, and was defeatured. MSI interrupts seem to
1292 * get lost on g4x as well, and interrupt delivery seems to stay
1293 * properly dead afterwards. So we'll just disable them for all
1294 * pre-gen5 chipsets.
1295 *
1296 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1297 * interrupts even when in MSI mode. This results in spurious
1298 * interrupt warnings if the legacy irq no. is shared with another
1299 * device. The kernel then disables that interrupt source and so
1300 * prevents the other device from working properly.
1301 */
1302 if (INTEL_GEN(dev_priv) >= 5) {
1303 if (pci_enable_msi(pdev) < 0)
1304 DRM_DEBUG_DRIVER("can't enable MSI");
1305 }
1306
1307 ret = intel_gvt_init(dev_priv);
1308 if (ret)
1309 goto err_msi;
1310
1311 intel_opregion_setup(dev_priv);
1312 /*
1313 * Fill the dram structure to get the system raw bandwidth and
1314 * dram info. This will be used for memory latency calculation.
1315 */
1316 intel_get_dram_info(dev_priv);
1317
1318 intel_bw_init_hw(dev_priv);
1319
1320 return 0;
1321
1322 err_msi:
1323 if (pdev->msi_enabled)
1324 pci_disable_msi(pdev);
1325 pm_qos_remove_request(&dev_priv->pm_qos);
1326 err_mem_regions:
1327 intel_memory_regions_driver_release(dev_priv);
1328 err_ggtt:
1329 i915_ggtt_driver_release(dev_priv);
1330 err_perf:
1331 i915_perf_fini(dev_priv);
1332 return ret;
1333 }
1334
1335 /**
1336 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1337 * @dev_priv: device private
1338 */
i915_driver_hw_remove(struct drm_i915_private * dev_priv)1339 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
1340 {
1341 struct pci_dev *pdev = dev_priv->drm.pdev;
1342
1343 i915_perf_fini(dev_priv);
1344
1345 if (pdev->msi_enabled)
1346 pci_disable_msi(pdev);
1347
1348 pm_qos_remove_request(&dev_priv->pm_qos);
1349 }
1350
1351 /**
1352 * i915_driver_register - register the driver with the rest of the system
1353 * @dev_priv: device private
1354 *
1355 * Perform any steps necessary to make the driver available via kernel
1356 * internal or userspace interfaces.
1357 */
i915_driver_register(struct drm_i915_private * dev_priv)1358 static void i915_driver_register(struct drm_i915_private *dev_priv)
1359 {
1360 struct drm_device *dev = &dev_priv->drm;
1361
1362 i915_gem_driver_register(dev_priv);
1363 i915_pmu_register(dev_priv);
1364
1365 /*
1366 * Notify a valid surface after modesetting,
1367 * when running inside a VM.
1368 */
1369 if (intel_vgpu_active(dev_priv))
1370 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1371
1372 /* Reveal our presence to userspace */
1373 if (drm_dev_register(dev, 0) == 0) {
1374 i915_debugfs_register(dev_priv);
1375 i915_setup_sysfs(dev_priv);
1376
1377 /* Depends on sysfs having been initialized */
1378 i915_perf_register(dev_priv);
1379 } else
1380 DRM_ERROR("Failed to register driver for userspace access!\n");
1381
1382 if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
1383 /* Must be done after probing outputs */
1384 intel_opregion_register(dev_priv);
1385 acpi_video_register();
1386 }
1387
1388 intel_gt_driver_register(&dev_priv->gt);
1389
1390 intel_audio_init(dev_priv);
1391
1392 /*
1393 * Some ports require correctly set-up hpd registers for detection to
1394 * work properly (leading to ghost connected connector status), e.g. VGA
1395 * on gm45. Hence we can only set up the initial fbdev config after hpd
1396 * irqs are fully enabled. We do it last so that the async config
1397 * cannot run before the connectors are registered.
1398 */
1399 intel_fbdev_initial_config_async(dev);
1400
1401 /*
1402 * We need to coordinate the hotplugs with the asynchronous fbdev
1403 * configuration, for which we use the fbdev->async_cookie.
1404 */
1405 if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv))
1406 drm_kms_helper_poll_init(dev);
1407
1408 intel_power_domains_enable(dev_priv);
1409 intel_runtime_pm_enable(&dev_priv->runtime_pm);
1410 }
1411
1412 /**
1413 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1414 * @dev_priv: device private
1415 */
i915_driver_unregister(struct drm_i915_private * dev_priv)1416 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1417 {
1418 intel_runtime_pm_disable(&dev_priv->runtime_pm);
1419 intel_power_domains_disable(dev_priv);
1420
1421 intel_fbdev_unregister(dev_priv);
1422 intel_audio_deinit(dev_priv);
1423
1424 /*
1425 * After flushing the fbdev (incl. a late async config which will
1426 * have delayed queuing of a hotplug event), then flush the hotplug
1427 * events.
1428 */
1429 drm_kms_helper_poll_fini(&dev_priv->drm);
1430
1431 intel_gt_driver_unregister(&dev_priv->gt);
1432 acpi_video_unregister();
1433 intel_opregion_unregister(dev_priv);
1434
1435 i915_perf_unregister(dev_priv);
1436 i915_pmu_unregister(dev_priv);
1437
1438 i915_teardown_sysfs(dev_priv);
1439 drm_dev_unplug(&dev_priv->drm);
1440
1441 i915_gem_driver_unregister(dev_priv);
1442 }
1443
i915_welcome_messages(struct drm_i915_private * dev_priv)1444 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1445 {
1446 if (drm_debug_enabled(DRM_UT_DRIVER)) {
1447 struct drm_printer p = drm_debug_printer("i915 device info:");
1448
1449 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1450 INTEL_DEVID(dev_priv),
1451 INTEL_REVID(dev_priv),
1452 intel_platform_name(INTEL_INFO(dev_priv)->platform),
1453 intel_subplatform(RUNTIME_INFO(dev_priv),
1454 INTEL_INFO(dev_priv)->platform),
1455 INTEL_GEN(dev_priv));
1456
1457 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
1458 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
1459 }
1460
1461 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1462 DRM_INFO("DRM_I915_DEBUG enabled\n");
1463 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1464 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1465 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1466 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1467 }
1468
1469 static struct drm_i915_private *
i915_driver_create(struct pci_dev * pdev,const struct pci_device_id * ent)1470 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1471 {
1472 const struct intel_device_info *match_info =
1473 (struct intel_device_info *)ent->driver_data;
1474 struct intel_device_info *device_info;
1475 struct drm_i915_private *i915;
1476 int err;
1477
1478 i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1479 if (!i915)
1480 return ERR_PTR(-ENOMEM);
1481
1482 err = drm_dev_init(&i915->drm, &driver, pci_dev_dev(pdev));
1483 if (err) {
1484 kfree(i915);
1485 return ERR_PTR(err);
1486 }
1487
1488 i915->drm.dev_private = i915;
1489
1490 i915->drm.pdev = pdev;
1491 pci_set_drvdata(pdev, i915);
1492
1493 /* Setup the write-once "constant" device info */
1494 device_info = mkwrite_device_info(i915);
1495 memcpy(device_info, match_info, sizeof(*device_info));
1496 RUNTIME_INFO(i915)->device_id = pdev->device;
1497
1498 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1499
1500 return i915;
1501 }
1502
i915_driver_destroy(struct drm_i915_private * i915)1503 static void i915_driver_destroy(struct drm_i915_private *i915)
1504 {
1505 struct pci_dev *pdev = i915->drm.pdev;
1506
1507 drm_dev_fini(&i915->drm);
1508 kfree(i915);
1509
1510 /* And make sure we never chase our dangling pointer from pci_dev */
1511 pci_set_drvdata(pdev, NULL);
1512 }
1513
1514 /**
1515 * i915_driver_probe - setup chip and create an initial config
1516 * @pdev: PCI device
1517 * @ent: matching PCI ID entry
1518 *
1519 * The driver probe routine has to do several things:
1520 * - drive output discovery via intel_modeset_init()
1521 * - initialize the memory manager
1522 * - allocate initial config memory
1523 * - setup the DRM framebuffer with the allocated memory
1524 */
i915_driver_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1525 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1526 {
1527 const struct intel_device_info *match_info =
1528 (struct intel_device_info *)ent->driver_data;
1529 struct drm_i915_private *dev_priv;
1530 int ret;
1531
1532 dev_priv = i915_driver_create(pdev, ent);
1533 if (IS_ERR(dev_priv))
1534 return PTR_ERR(dev_priv);
1535
1536 #ifdef __NetBSD__
1537 ret = drm_pci_attach(&dev_priv->drm, pdev);
1538 if (ret)
1539 goto out_destroy;
1540 #endif
1541
1542 /* Disable nuclear pageflip by default on pre-ILK */
1543 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1544 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1545
1546 /*
1547 * Check if we support fake LMEM -- for now we only unleash this for
1548 * the live selftests(test-and-exit).
1549 */
1550 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1551 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
1552 if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live < 0 &&
1553 i915_modparams.fake_lmem_start) {
1554 mkwrite_device_info(dev_priv)->memory_regions =
1555 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
1556 mkwrite_device_info(dev_priv)->is_dgfx = true;
1557 GEM_BUG_ON(!HAS_LMEM(dev_priv));
1558 GEM_BUG_ON(!IS_DGFX(dev_priv));
1559 }
1560 }
1561 #endif
1562
1563 #ifndef __NetBSD__ /* XXX done for us */
1564 ret = pci_enable_device(pdev);
1565 if (ret)
1566 goto out_fini;
1567 #endif
1568
1569 ret = i915_driver_early_probe(dev_priv);
1570 if (ret < 0)
1571 goto out_pci_disable;
1572
1573 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1574
1575 i915_detect_vgpu(dev_priv);
1576
1577 ret = i915_driver_mmio_probe(dev_priv);
1578 if (ret < 0)
1579 goto out_runtime_pm_put;
1580
1581 ret = i915_driver_hw_probe(dev_priv);
1582 if (ret < 0)
1583 goto out_cleanup_mmio;
1584
1585 ret = i915_driver_modeset_probe(dev_priv);
1586 if (ret < 0)
1587 goto out_cleanup_hw;
1588
1589 i915_driver_register(dev_priv);
1590
1591 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1592
1593 i915_welcome_messages(dev_priv);
1594
1595 return 0;
1596
1597 out_cleanup_hw:
1598 i915_driver_hw_remove(dev_priv);
1599 intel_memory_regions_driver_release(dev_priv);
1600 i915_ggtt_driver_release(dev_priv);
1601 out_cleanup_mmio:
1602 i915_driver_mmio_release(dev_priv);
1603 out_runtime_pm_put:
1604 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1605 i915_driver_late_release(dev_priv);
1606 out_pci_disable:
1607 #ifndef __NetBSD__
1608 pci_disable_device(pdev);
1609 out_fini:
1610 #endif
1611 i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret);
1612 #ifdef __NetBSD__
1613 drm_pci_detach(&dev_priv->drm);
1614 out_destroy:
1615 #endif
1616 i915_driver_destroy(dev_priv);
1617 return ret;
1618 }
1619
i915_driver_remove(struct drm_i915_private * i915)1620 void i915_driver_remove(struct drm_i915_private *i915)
1621 {
1622 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1623
1624 i915_driver_unregister(i915);
1625
1626 /*
1627 * After unregistering the device to prevent any new users, cancel
1628 * all in-flight requests so that we can quickly unbind the active
1629 * resources.
1630 */
1631 intel_gt_set_wedged(&i915->gt);
1632
1633 /* Flush any external code that still may be under the RCU lock */
1634 synchronize_rcu();
1635
1636 i915_gem_suspend(i915);
1637
1638 drm_atomic_helper_shutdown(&i915->drm);
1639
1640 intel_gvt_driver_remove(i915);
1641
1642 i915_driver_modeset_remove(i915);
1643
1644 i915_reset_error_state(i915);
1645 i915_gem_driver_remove(i915);
1646
1647 intel_power_domains_driver_remove(i915);
1648
1649 i915_driver_hw_remove(i915);
1650
1651 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1652 }
1653
i915_driver_release(struct drm_device * dev)1654 static void i915_driver_release(struct drm_device *dev)
1655 {
1656 struct drm_i915_private *dev_priv = to_i915(dev);
1657 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1658
1659 disable_rpm_wakeref_asserts(rpm);
1660
1661 i915_gem_driver_release(dev_priv);
1662
1663 intel_memory_regions_driver_release(dev_priv);
1664 i915_ggtt_driver_release(dev_priv);
1665
1666 i915_driver_mmio_release(dev_priv);
1667
1668 enable_rpm_wakeref_asserts(rpm);
1669 intel_runtime_pm_driver_release(rpm);
1670
1671 i915_driver_late_release(dev_priv);
1672 #ifdef __NetBSD__
1673 drm_pci_detach(dev);
1674 #endif
1675 i915_driver_destroy(dev_priv);
1676 }
1677
i915_driver_open(struct drm_device * dev,struct drm_file * file)1678 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1679 {
1680 struct drm_i915_private *i915 = to_i915(dev);
1681 int ret;
1682
1683 ret = i915_gem_open(i915, file);
1684 if (ret)
1685 return ret;
1686
1687 return 0;
1688 }
1689
1690 /**
1691 * i915_driver_lastclose - clean up after all DRM clients have exited
1692 * @dev: DRM device
1693 *
1694 * Take care of cleaning up after all DRM clients have exited. In the
1695 * mode setting case, we want to restore the kernel's initial mode (just
1696 * in case the last client left us in a bad state).
1697 *
1698 * Additionally, in the non-mode setting case, we'll tear down the GTT
1699 * and DMA structures, since the kernel won't be using them, and clea
1700 * up any GEM state.
1701 */
i915_driver_lastclose(struct drm_device * dev)1702 static void i915_driver_lastclose(struct drm_device *dev)
1703 {
1704 intel_fbdev_restore_mode(dev);
1705 #ifndef __NetBSD__ /* XXX vga */
1706 vga_switcheroo_process_delayed_switch();
1707 #endif
1708 }
1709
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)1710 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1711 {
1712 struct drm_i915_file_private *file_priv = file->driver_priv;
1713
1714 i915_gem_context_close(file);
1715 i915_gem_release(dev, file);
1716
1717 kfree_rcu(file_priv, rcu);
1718
1719 /* Catch up with all the deferred frees from "this" client */
1720 i915_gem_flush_free_objects(to_i915(dev));
1721 }
1722
intel_suspend_encoders(struct drm_i915_private * dev_priv)1723 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1724 {
1725 struct drm_device *dev = &dev_priv->drm;
1726 struct intel_encoder *encoder;
1727
1728 drm_modeset_lock_all(dev);
1729 for_each_intel_encoder(dev, encoder)
1730 if (encoder->suspend)
1731 encoder->suspend(encoder);
1732 drm_modeset_unlock_all(dev);
1733 }
1734
1735 #ifndef __NetBSD__ /* XXX vlv suspend/resume */
1736 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1737 bool rpm_resume);
1738 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1739 #endif
1740
suspend_to_idle(struct drm_i915_private * dev_priv)1741 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1742 {
1743 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1744 if (acpi_target_system_state() < ACPI_STATE_S3)
1745 return true;
1746 #endif
1747 return false;
1748 }
1749
i915_drm_prepare(struct drm_device * dev)1750 int i915_drm_prepare(struct drm_device *dev)
1751 {
1752 struct drm_i915_private *i915 = to_i915(dev);
1753
1754 /*
1755 * NB intel_display_suspend() may issue new requests after we've
1756 * ostensibly marked the GPU as ready-to-sleep here. We need to
1757 * split out that work and pull it forward so that after point,
1758 * the GPU is not woken again.
1759 */
1760 i915_gem_suspend(i915);
1761
1762 return 0;
1763 }
1764
i915_drm_suspend(struct drm_device * dev)1765 int i915_drm_suspend(struct drm_device *dev)
1766 {
1767 struct drm_i915_private *dev_priv = to_i915(dev);
1768 struct pci_dev *pdev = dev_priv->drm.pdev;
1769 pci_power_t opregion_target_state;
1770
1771 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1772
1773 /* We do a lot of poking in a lot of registers, make sure they work
1774 * properly. */
1775 intel_power_domains_disable(dev_priv);
1776
1777 drm_kms_helper_poll_disable(dev);
1778
1779 #ifdef __NetBSD__ /* pmf handles this for us. */
1780 __USE(pdev);
1781 #else
1782 pci_save_state(pdev);
1783 #endif
1784
1785 intel_display_suspend(dev);
1786
1787 intel_dp_mst_suspend(dev_priv);
1788
1789 intel_runtime_pm_disable_interrupts(dev_priv);
1790 intel_hpd_cancel_work(dev_priv);
1791
1792 intel_suspend_encoders(dev_priv);
1793
1794 intel_suspend_hw(dev_priv);
1795
1796 i915_gem_suspend_gtt_mappings(dev_priv);
1797
1798 i915_save_state(dev_priv);
1799
1800 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1801 intel_opregion_suspend(dev_priv, opregion_target_state);
1802
1803 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1804
1805 dev_priv->suspend_count++;
1806
1807 intel_csr_ucode_suspend(dev_priv);
1808
1809 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1810
1811 return 0;
1812 }
1813
1814 static enum i915_drm_suspend_mode
get_suspend_mode(struct drm_i915_private * dev_priv,bool hibernate)1815 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1816 {
1817 if (hibernate)
1818 return I915_DRM_SUSPEND_HIBERNATE;
1819
1820 if (suspend_to_idle(dev_priv))
1821 return I915_DRM_SUSPEND_IDLE;
1822
1823 return I915_DRM_SUSPEND_MEM;
1824 }
1825
i915_drm_suspend_late(struct drm_device * dev,bool hibernation)1826 int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1827 {
1828 struct drm_i915_private *dev_priv = to_i915(dev);
1829 struct pci_dev *pdev = dev_priv->drm.pdev;
1830 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1831 int ret = 0;
1832
1833 disable_rpm_wakeref_asserts(rpm);
1834
1835 i915_gem_suspend_late(dev_priv);
1836
1837 intel_uncore_suspend(&dev_priv->uncore);
1838
1839 intel_power_domains_suspend(dev_priv,
1840 get_suspend_mode(dev_priv, hibernation));
1841
1842 intel_display_power_suspend_late(dev_priv);
1843
1844 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1845 #ifdef __NetBSD__
1846 ret = 0;
1847 #else
1848 ret = vlv_suspend_complete(dev_priv);
1849 #endif
1850
1851 if (ret) {
1852 DRM_ERROR("Suspend complete failed: %d\n", ret);
1853 intel_power_domains_resume(dev_priv);
1854
1855 goto out;
1856 }
1857
1858 #ifdef __NetBSD__ /* pmf handles this for us. */
1859 __USE(pdev);
1860 #else
1861 pci_disable_device(pdev);
1862 /*
1863 * During hibernation on some platforms the BIOS may try to access
1864 * the device even though it's already in D3 and hang the machine. So
1865 * leave the device in D0 on those platforms and hope the BIOS will
1866 * power down the device properly. The issue was seen on multiple old
1867 * GENs with different BIOS vendors, so having an explicit blacklist
1868 * is inpractical; apply the workaround on everything pre GEN6. The
1869 * platforms where the issue was seen:
1870 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1871 * Fujitsu FSC S7110
1872 * Acer Aspire 1830T
1873 */
1874 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1875 pci_set_power_state(pdev, PCI_D3hot);
1876 #endif
1877
1878 out:
1879 enable_rpm_wakeref_asserts(rpm);
1880 if (!dev_priv->uncore.user_forcewake_count)
1881 intel_runtime_pm_driver_release(rpm);
1882
1883 return ret;
1884 }
1885
1886 #ifndef __NetBSD__ /* XXX vga switcheroo */
i915_suspend_switcheroo(struct drm_i915_private * i915,pm_message_t state)1887 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1888 {
1889 int error;
1890
1891 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1892 state.event != PM_EVENT_FREEZE))
1893 return -EINVAL;
1894
1895 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1896 return 0;
1897
1898 error = i915_drm_suspend(&i915->drm);
1899 if (error)
1900 return error;
1901
1902 return i915_drm_suspend_late(&i915->drm, false);
1903 }
1904 #endif
1905
i915_drm_resume(struct drm_device * dev)1906 int i915_drm_resume(struct drm_device *dev)
1907 {
1908 struct drm_i915_private *dev_priv = to_i915(dev);
1909 int ret;
1910
1911 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1912
1913 sanitize_gpu(dev_priv);
1914
1915 ret = i915_ggtt_enable_hw(dev_priv);
1916 if (ret)
1917 DRM_ERROR("failed to re-enable GGTT\n");
1918
1919 i915_gem_restore_gtt_mappings(dev_priv);
1920 i915_gem_restore_fences(&dev_priv->ggtt);
1921
1922 intel_csr_ucode_resume(dev_priv);
1923
1924 i915_restore_state(dev_priv);
1925 intel_pps_unlock_regs_wa(dev_priv);
1926
1927 intel_init_pch_refclk(dev_priv);
1928
1929 /*
1930 * Interrupts have to be enabled before any batches are run. If not the
1931 * GPU will hang. i915_gem_init_hw() will initiate batches to
1932 * update/restore the context.
1933 *
1934 * drm_mode_config_reset() needs AUX interrupts.
1935 *
1936 * Modeset enabling in intel_modeset_init_hw() also needs working
1937 * interrupts.
1938 */
1939 intel_runtime_pm_enable_interrupts(dev_priv);
1940
1941 drm_mode_config_reset(dev);
1942
1943 i915_gem_resume(dev_priv);
1944
1945 intel_modeset_init_hw(dev_priv);
1946 intel_init_clock_gating(dev_priv);
1947
1948 spin_lock_irq(&dev_priv->irq_lock);
1949 if (dev_priv->display.hpd_irq_setup)
1950 dev_priv->display.hpd_irq_setup(dev_priv);
1951 spin_unlock_irq(&dev_priv->irq_lock);
1952
1953 intel_dp_mst_resume(dev_priv);
1954
1955 intel_display_resume(dev);
1956
1957 drm_kms_helper_poll_enable(dev);
1958
1959 /*
1960 * ... but also need to make sure that hotplug processing
1961 * doesn't cause havoc. Like in the driver load code we don't
1962 * bother with the tiny race here where we might lose hotplug
1963 * notifications.
1964 * */
1965 intel_hpd_init(dev_priv);
1966
1967 intel_opregion_resume(dev_priv);
1968
1969 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1970
1971 intel_power_domains_enable(dev_priv);
1972
1973 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1974
1975 return 0;
1976 }
1977
i915_drm_resume_early(struct drm_device * dev)1978 int i915_drm_resume_early(struct drm_device *dev)
1979 {
1980 struct drm_i915_private *dev_priv = to_i915(dev);
1981 #ifndef __NetBSD__
1982 struct pci_dev *pdev = dev_priv->drm.pdev;
1983 #endif
1984 int ret = 0;
1985
1986 /*
1987 * We have a resume ordering issue with the snd-hda driver also
1988 * requiring our device to be power up. Due to the lack of a
1989 * parent/child relationship we currently solve this with an early
1990 * resume hook.
1991 *
1992 * FIXME: This should be solved with a special hdmi sink device or
1993 * similar so that power domains can be employed.
1994 */
1995
1996 /*
1997 * Note that we need to set the power state explicitly, since we
1998 * powered off the device during freeze and the PCI core won't power
1999 * it back up for us during thaw. Powering off the device during
2000 * freeze is not a hard requirement though, and during the
2001 * suspend/resume phases the PCI core makes sure we get here with the
2002 * device powered on. So in case we change our freeze logic and keep
2003 * the device powered we can also remove the following set power state
2004 * call.
2005 */
2006 #ifndef __NetBSD__ /* pmf handles this for us. */
2007 ret = pci_set_power_state(pdev, PCI_D0);
2008 if (ret) {
2009 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2010 return ret;
2011 }
2012
2013 /*
2014 * Note that pci_enable_device() first enables any parent bridge
2015 * device and only then sets the power state for this device. The
2016 * bridge enabling is a nop though, since bridge devices are resumed
2017 * first. The order of enabling power and enabling the device is
2018 * imposed by the PCI core as described above, so here we preserve the
2019 * same order for the freeze/thaw phases.
2020 *
2021 * TODO: eventually we should remove pci_disable_device() /
2022 * pci_enable_enable_device() from suspend/resume. Due to how they
2023 * depend on the device enable refcount we can't anyway depend on them
2024 * disabling/enabling the device.
2025 */
2026 if (pci_enable_device(pdev))
2027 return -EIO;
2028 #endif
2029
2030 /* XXX pmf probably handles this for us too. */
2031 pci_set_master(dev->pdev);
2032
2033 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2034
2035 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2036 #ifdef __NetBSD__ /* XXX vlv suspend/resume */
2037 ret = 0;
2038 #else
2039 ret = vlv_resume_prepare(dev_priv, false);
2040 #endif
2041 if (ret)
2042 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2043 ret);
2044
2045 intel_uncore_resume_early(&dev_priv->uncore);
2046
2047 intel_gt_check_and_clear_faults(&dev_priv->gt);
2048
2049 intel_display_power_resume_early(dev_priv);
2050
2051 intel_power_domains_resume(dev_priv);
2052
2053 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2054
2055 return ret;
2056 }
2057
2058 #ifndef __NetBSD__ /* XXX vga switcheroo */
i915_resume_switcheroo(struct drm_i915_private * i915)2059 int i915_resume_switcheroo(struct drm_i915_private *i915)
2060 {
2061 int ret;
2062
2063 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2064 return 0;
2065
2066 ret = i915_drm_resume_early(&i915->drm);
2067 if (ret)
2068 return ret;
2069
2070 return i915_drm_resume(&i915->drm);
2071 }
2072
i915_pm_prepare(struct device * kdev)2073 static int i915_pm_prepare(struct device *kdev)
2074 {
2075 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2076
2077 if (!i915) {
2078 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2079 return -ENODEV;
2080 }
2081
2082 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2083 return 0;
2084
2085 return i915_drm_prepare(&i915->drm);
2086 }
2087 #endif
2088
2089 #ifndef __NetBSD__
i915_pm_suspend(struct device * kdev)2090 static int i915_pm_suspend(struct device *kdev)
2091 {
2092 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2093
2094 if (!i915) {
2095 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2096 return -ENODEV;
2097 }
2098
2099 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2100 return 0;
2101
2102 return i915_drm_suspend(&i915->drm);
2103 }
2104
i915_pm_suspend_late(struct device * kdev)2105 static int i915_pm_suspend_late(struct device *kdev)
2106 {
2107 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2108
2109 /*
2110 * We have a suspend ordering issue with the snd-hda driver also
2111 * requiring our device to be power up. Due to the lack of a
2112 * parent/child relationship we currently solve this with an late
2113 * suspend hook.
2114 *
2115 * FIXME: This should be solved with a special hdmi sink device or
2116 * similar so that power domains can be employed.
2117 */
2118 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2119 return 0;
2120
2121 return i915_drm_suspend_late(&i915->drm, false);
2122 }
2123
i915_pm_poweroff_late(struct device * kdev)2124 static int i915_pm_poweroff_late(struct device *kdev)
2125 {
2126 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2127
2128 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2129 return 0;
2130
2131 return i915_drm_suspend_late(&i915->drm, true);
2132 }
2133
i915_pm_resume_early(struct device * kdev)2134 static int i915_pm_resume_early(struct device *kdev)
2135 {
2136 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2137
2138 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2139 return 0;
2140
2141 return i915_drm_resume_early(&i915->drm);
2142 }
2143
i915_pm_resume(struct device * kdev)2144 static int i915_pm_resume(struct device *kdev)
2145 {
2146 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2147
2148 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
2149 return 0;
2150
2151 return i915_drm_resume(&i915->drm);
2152 }
2153
2154 /* freeze: before creating the hibernation_image */
i915_pm_freeze(struct device * kdev)2155 static int i915_pm_freeze(struct device *kdev)
2156 {
2157 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2158 int ret;
2159
2160 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2161 ret = i915_drm_suspend(&i915->drm);
2162 if (ret)
2163 return ret;
2164 }
2165
2166 ret = i915_gem_freeze(i915);
2167 if (ret)
2168 return ret;
2169
2170 return 0;
2171 }
2172
i915_pm_freeze_late(struct device * kdev)2173 static int i915_pm_freeze_late(struct device *kdev)
2174 {
2175 struct drm_i915_private *i915 = kdev_to_i915(kdev);
2176 int ret;
2177
2178 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
2179 ret = i915_drm_suspend_late(&i915->drm, true);
2180 if (ret)
2181 return ret;
2182 }
2183
2184 ret = i915_gem_freeze_late(i915);
2185 if (ret)
2186 return ret;
2187
2188 return 0;
2189 }
2190
2191 /* thaw: called after creating the hibernation image, but before turning off. */
i915_pm_thaw_early(struct device * kdev)2192 static int i915_pm_thaw_early(struct device *kdev)
2193 {
2194 return i915_pm_resume_early(kdev);
2195 }
2196
i915_pm_thaw(struct device * kdev)2197 static int i915_pm_thaw(struct device *kdev)
2198 {
2199 return i915_pm_resume(kdev);
2200 }
2201
2202 /* restore: called after loading the hibernation image. */
i915_pm_restore_early(struct device * kdev)2203 static int i915_pm_restore_early(struct device *kdev)
2204 {
2205 return i915_pm_resume_early(kdev);
2206 }
2207
i915_pm_restore(struct device * kdev)2208 static int i915_pm_restore(struct device *kdev)
2209 {
2210 return i915_pm_resume(kdev);
2211 }
2212
2213 /*
2214 * Save all Gunit registers that may be lost after a D3 and a subsequent
2215 * S0i[R123] transition. The list of registers needing a save/restore is
2216 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2217 * registers in the following way:
2218 * - Driver: saved/restored by the driver
2219 * - Punit : saved/restored by the Punit firmware
2220 * - No, w/o marking: no need to save/restore, since the register is R/O or
2221 * used internally by the HW in a way that doesn't depend
2222 * keeping the content across a suspend/resume.
2223 * - Debug : used for debugging
2224 *
2225 * We save/restore all registers marked with 'Driver', with the following
2226 * exceptions:
2227 * - Registers out of use, including also registers marked with 'Debug'.
2228 * These have no effect on the driver's operation, so we don't save/restore
2229 * them to reduce the overhead.
2230 * - Registers that are fully setup by an initialization function called from
2231 * the resume path. For example many clock gating and RPS/RC6 registers.
2232 * - Registers that provide the right functionality with their reset defaults.
2233 *
2234 * TODO: Except for registers that based on the above 3 criteria can be safely
2235 * ignored, we save/restore all others, practically treating the HW context as
2236 * a black-box for the driver. Further investigation is needed to reduce the
2237 * saved/restored registers even further, by following the same 3 criteria.
2238 */
vlv_save_gunit_s0ix_state(struct drm_i915_private * dev_priv)2239 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2240 {
2241 struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2242 int i;
2243
2244 if (!s)
2245 return;
2246
2247 /* GAM 0x4000-0x4770 */
2248 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2249 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2250 s->arb_mode = I915_READ(ARB_MODE);
2251 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2252 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2253
2254 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2255 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2256
2257 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2258 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2259
2260 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2261 s->ecochk = I915_READ(GAM_ECOCHK);
2262 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2263 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2264
2265 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2266
2267 /* MBC 0x9024-0x91D0, 0x8500 */
2268 s->g3dctl = I915_READ(VLV_G3DCTL);
2269 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2270 s->mbctl = I915_READ(GEN6_MBCTL);
2271
2272 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2273 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2274 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2275 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2276 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2277 s->rstctl = I915_READ(GEN6_RSTCTL);
2278 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2279
2280 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2281 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2282 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2283 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2284 s->ecobus = I915_READ(ECOBUS);
2285 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2286 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2287 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2288 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2289 s->rcedata = I915_READ(VLV_RCEDATA);
2290 s->spare2gh = I915_READ(VLV_SPAREG2H);
2291
2292 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2293 s->gt_imr = I915_READ(GTIMR);
2294 s->gt_ier = I915_READ(GTIER);
2295 s->pm_imr = I915_READ(GEN6_PMIMR);
2296 s->pm_ier = I915_READ(GEN6_PMIER);
2297
2298 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2299 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2300
2301 /* GT SA CZ domain, 0x100000-0x138124 */
2302 s->tilectl = I915_READ(TILECTL);
2303 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2304 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2305 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2306 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2307
2308 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2309 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2310 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2311 s->pcbr = I915_READ(VLV_PCBR);
2312 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2313
2314 /*
2315 * Not saving any of:
2316 * DFT, 0x9800-0x9EC0
2317 * SARB, 0xB000-0xB1FC
2318 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2319 * PCI CFG
2320 */
2321 }
2322
vlv_restore_gunit_s0ix_state(struct drm_i915_private * dev_priv)2323 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2324 {
2325 struct vlv_s0ix_state *s = dev_priv->vlv_s0ix_state;
2326 u32 val;
2327 int i;
2328
2329 if (!s)
2330 return;
2331
2332 /* GAM 0x4000-0x4770 */
2333 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2334 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2335 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2336 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2337 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2338
2339 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2340 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2341
2342 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2343 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2344
2345 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2346 I915_WRITE(GAM_ECOCHK, s->ecochk);
2347 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2348 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2349
2350 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2351
2352 /* MBC 0x9024-0x91D0, 0x8500 */
2353 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2354 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2355 I915_WRITE(GEN6_MBCTL, s->mbctl);
2356
2357 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2358 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2359 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2360 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2361 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2362 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2363 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2364
2365 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2366 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2367 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2368 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2369 I915_WRITE(ECOBUS, s->ecobus);
2370 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2371 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2372 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2373 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2374 I915_WRITE(VLV_RCEDATA, s->rcedata);
2375 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2376
2377 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2378 I915_WRITE(GTIMR, s->gt_imr);
2379 I915_WRITE(GTIER, s->gt_ier);
2380 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2381 I915_WRITE(GEN6_PMIER, s->pm_ier);
2382
2383 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2384 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2385
2386 /* GT SA CZ domain, 0x100000-0x138124 */
2387 I915_WRITE(TILECTL, s->tilectl);
2388 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2389 /*
2390 * Preserve the GT allow wake and GFX force clock bit, they are not
2391 * be restored, as they are used to control the s0ix suspend/resume
2392 * sequence by the caller.
2393 */
2394 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2395 val &= VLV_GTLC_ALLOWWAKEREQ;
2396 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2397 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2398
2399 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2400 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2401 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2402 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2403
2404 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2405
2406 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2407 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2408 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2409 I915_WRITE(VLV_PCBR, s->pcbr);
2410 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2411 }
2412
vlv_wait_for_pw_status(struct drm_i915_private * i915,u32 mask,u32 val)2413 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
2414 u32 mask, u32 val)
2415 {
2416 i915_reg_t reg = VLV_GTLC_PW_STATUS;
2417 u32 reg_value;
2418 int ret;
2419
2420 /* The HW does not like us polling for PW_STATUS frequently, so
2421 * use the sleeping loop rather than risk the busy spin within
2422 * intel_wait_for_register().
2423 *
2424 * Transitioning between RC6 states should be at most 2ms (see
2425 * valleyview_enable_rps) so use a 3ms timeout.
2426 */
2427 ret = wait_for(((reg_value =
2428 intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
2429 == val, 3);
2430
2431 /* just trace the final value */
2432 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2433
2434 return ret;
2435 }
2436 #endif
2437
vlv_force_gfx_clock(struct drm_i915_private * dev_priv,bool force_on)2438 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2439 {
2440 u32 val;
2441 int err;
2442
2443 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2444 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2445 if (force_on)
2446 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2447 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2448
2449 if (!force_on)
2450 return 0;
2451
2452 err = intel_wait_for_register(&dev_priv->uncore,
2453 VLV_GTLC_SURVIVABILITY_REG,
2454 VLV_GFX_CLK_STATUS_BIT,
2455 VLV_GFX_CLK_STATUS_BIT,
2456 20);
2457 if (err)
2458 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2459 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2460
2461 return err;
2462 }
2463
2464 #ifndef __NetBSD__ /* XXX vlv suspend/resume */
vlv_allow_gt_wake(struct drm_i915_private * dev_priv,bool allow)2465 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2466 {
2467 u32 mask;
2468 u32 val;
2469 int err;
2470
2471 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2472 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2473 if (allow)
2474 val |= VLV_GTLC_ALLOWWAKEREQ;
2475 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2476 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2477
2478 mask = VLV_GTLC_ALLOWWAKEACK;
2479 val = allow ? mask : 0;
2480
2481 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2482 if (err)
2483 DRM_ERROR("timeout disabling GT waking\n");
2484
2485 return err;
2486 }
2487
vlv_wait_for_gt_wells(struct drm_i915_private * dev_priv,bool wait_for_on)2488 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2489 bool wait_for_on)
2490 {
2491 u32 mask;
2492 u32 val;
2493
2494 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2495 val = wait_for_on ? mask : 0;
2496
2497 /*
2498 * RC6 transitioning can be delayed up to 2 msec (see
2499 * valleyview_enable_rps), use 3 msec for safety.
2500 *
2501 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2502 * reset and we are trying to force the machine to sleep.
2503 */
2504 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2505 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2506 onoff(wait_for_on));
2507 }
2508
vlv_check_no_gt_access(struct drm_i915_private * dev_priv)2509 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2510 {
2511 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2512 return;
2513
2514 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2515 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2516 }
2517
vlv_suspend_complete(struct drm_i915_private * dev_priv)2518 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2519 {
2520 u32 mask;
2521 int err;
2522
2523 /*
2524 * Bspec defines the following GT well on flags as debug only, so
2525 * don't treat them as hard failures.
2526 */
2527 vlv_wait_for_gt_wells(dev_priv, false);
2528
2529 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2530 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2531
2532 vlv_check_no_gt_access(dev_priv);
2533
2534 err = vlv_force_gfx_clock(dev_priv, true);
2535 if (err)
2536 goto err1;
2537
2538 err = vlv_allow_gt_wake(dev_priv, false);
2539 if (err)
2540 goto err2;
2541
2542 vlv_save_gunit_s0ix_state(dev_priv);
2543
2544 err = vlv_force_gfx_clock(dev_priv, false);
2545 if (err)
2546 goto err2;
2547
2548 return 0;
2549
2550 err2:
2551 /* For safety always re-enable waking and disable gfx clock forcing */
2552 vlv_allow_gt_wake(dev_priv, true);
2553 err1:
2554 vlv_force_gfx_clock(dev_priv, false);
2555
2556 return err;
2557 }
2558
vlv_resume_prepare(struct drm_i915_private * dev_priv,bool rpm_resume)2559 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2560 bool rpm_resume)
2561 {
2562 int err;
2563 int ret;
2564
2565 /*
2566 * If any of the steps fail just try to continue, that's the best we
2567 * can do at this point. Return the first error code (which will also
2568 * leave RPM permanently disabled).
2569 */
2570 ret = vlv_force_gfx_clock(dev_priv, true);
2571
2572 vlv_restore_gunit_s0ix_state(dev_priv);
2573
2574 err = vlv_allow_gt_wake(dev_priv, true);
2575 if (!ret)
2576 ret = err;
2577
2578 err = vlv_force_gfx_clock(dev_priv, false);
2579 if (!ret)
2580 ret = err;
2581
2582 vlv_check_no_gt_access(dev_priv);
2583
2584 if (rpm_resume)
2585 intel_init_clock_gating(dev_priv);
2586
2587 return ret;
2588 }
2589 #endif
2590
2591 #ifndef __NetBSD__ /* XXX runtime pm */
intel_runtime_suspend(struct device * kdev)2592 static int intel_runtime_suspend(struct device *kdev)
2593 {
2594 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2595 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2596 int ret = 0;
2597
2598 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2599 return -ENODEV;
2600
2601 DRM_DEBUG_KMS("Suspending device\n");
2602
2603 disable_rpm_wakeref_asserts(rpm);
2604
2605 /*
2606 * We are safe here against re-faults, since the fault handler takes
2607 * an RPM reference.
2608 */
2609 i915_gem_runtime_suspend(dev_priv);
2610
2611 intel_gt_runtime_suspend(&dev_priv->gt);
2612
2613 intel_runtime_pm_disable_interrupts(dev_priv);
2614
2615 intel_uncore_suspend(&dev_priv->uncore);
2616
2617 intel_display_power_suspend(dev_priv);
2618
2619 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2620 #ifndef __NetBSD__ /* XXX vlv suspend/resume */
2621 ret = vlv_suspend_complete(dev_priv);
2622 #endif
2623
2624 if (ret) {
2625 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2626 intel_uncore_runtime_resume(&dev_priv->uncore);
2627
2628 intel_runtime_pm_enable_interrupts(dev_priv);
2629
2630 intel_gt_runtime_resume(&dev_priv->gt);
2631
2632 i915_gem_restore_fences(&dev_priv->ggtt);
2633
2634 enable_rpm_wakeref_asserts(rpm);
2635
2636 return ret;
2637 }
2638
2639 enable_rpm_wakeref_asserts(rpm);
2640 intel_runtime_pm_driver_release(rpm);
2641
2642 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2643 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2644
2645 rpm->suspended = true;
2646
2647 /*
2648 * FIXME: We really should find a document that references the arguments
2649 * used below!
2650 */
2651 if (IS_BROADWELL(dev_priv)) {
2652 /*
2653 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2654 * being detected, and the call we do at intel_runtime_resume()
2655 * won't be able to restore them. Since PCI_D3hot matches the
2656 * actual specification and appears to be working, use it.
2657 */
2658 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2659 } else {
2660 /*
2661 * current versions of firmware which depend on this opregion
2662 * notification have repurposed the D1 definition to mean
2663 * "runtime suspended" vs. what you would normally expect (D3)
2664 * to distinguish it from notifications that might be sent via
2665 * the suspend path.
2666 */
2667 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2668 }
2669
2670 assert_forcewakes_inactive(&dev_priv->uncore);
2671
2672 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2673 intel_hpd_poll_init(dev_priv);
2674
2675 DRM_DEBUG_KMS("Device suspended\n");
2676 return 0;
2677 }
2678
intel_runtime_resume(struct device * kdev)2679 static int intel_runtime_resume(struct device *kdev)
2680 {
2681 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
2682 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2683 int ret = 0;
2684
2685 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2686 return -ENODEV;
2687
2688 DRM_DEBUG_KMS("Resuming device\n");
2689
2690 WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));
2691 disable_rpm_wakeref_asserts(rpm);
2692
2693 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2694 rpm->suspended = false;
2695 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2696 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2697
2698 intel_display_power_resume(dev_priv);
2699
2700 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2701 ret = vlv_resume_prepare(dev_priv, true);
2702
2703 intel_uncore_runtime_resume(&dev_priv->uncore);
2704
2705 intel_runtime_pm_enable_interrupts(dev_priv);
2706
2707 /*
2708 * No point of rolling back things in case of an error, as the best
2709 * we can do is to hope that things will still work (and disable RPM).
2710 */
2711 intel_gt_runtime_resume(&dev_priv->gt);
2712 i915_gem_restore_fences(&dev_priv->ggtt);
2713
2714 /*
2715 * On VLV/CHV display interrupts are part of the display
2716 * power well, so hpd is reinitialized from there. For
2717 * everyone else do it here.
2718 */
2719 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2720 intel_hpd_init(dev_priv);
2721
2722 intel_enable_ipc(dev_priv);
2723
2724 enable_rpm_wakeref_asserts(rpm);
2725
2726 if (ret)
2727 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2728 else
2729 DRM_DEBUG_KMS("Device resumed\n");
2730
2731 return ret;
2732 }
2733 #endif
2734
2735 #ifndef __NetBSD__
2736 const struct dev_pm_ops i915_pm_ops = {
2737 /*
2738 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2739 * PMSG_RESUME]
2740 */
2741 .prepare = i915_pm_prepare,
2742 .suspend = i915_pm_suspend,
2743 .suspend_late = i915_pm_suspend_late,
2744 .resume_early = i915_pm_resume_early,
2745 .resume = i915_pm_resume,
2746
2747 /*
2748 * S4 event handlers
2749 * @freeze, @freeze_late : called (1) before creating the
2750 * hibernation image [PMSG_FREEZE] and
2751 * (2) after rebooting, before restoring
2752 * the image [PMSG_QUIESCE]
2753 * @thaw, @thaw_early : called (1) after creating the hibernation
2754 * image, before writing it [PMSG_THAW]
2755 * and (2) after failing to create or
2756 * restore the image [PMSG_RECOVER]
2757 * @poweroff, @poweroff_late: called after writing the hibernation
2758 * image, before rebooting [PMSG_HIBERNATE]
2759 * @restore, @restore_early : called after rebooting and restoring the
2760 * hibernation image [PMSG_RESTORE]
2761 */
2762 .freeze = i915_pm_freeze,
2763 .freeze_late = i915_pm_freeze_late,
2764 .thaw_early = i915_pm_thaw_early,
2765 .thaw = i915_pm_thaw,
2766 .poweroff = i915_pm_suspend,
2767 .poweroff_late = i915_pm_poweroff_late,
2768 .restore_early = i915_pm_restore_early,
2769 .restore = i915_pm_restore,
2770
2771 /* S0ix (via runtime suspend) event handlers */
2772 .runtime_suspend = intel_runtime_suspend,
2773 .runtime_resume = intel_runtime_resume,
2774 };
2775
2776 static const struct file_operations i915_driver_fops = {
2777 .owner = THIS_MODULE,
2778 .open = drm_open,
2779 .release = drm_release,
2780 .unlocked_ioctl = drm_ioctl,
2781 .mmap = i915_gem_mmap,
2782 .poll = drm_poll,
2783 .read = drm_read,
2784 .compat_ioctl = i915_compat_ioctl,
2785 .llseek = noop_llseek,
2786 };
2787 #endif /* defined(__NetBSD__) */
2788
2789 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)2790 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2791 struct drm_file *file)
2792 {
2793 return -ENODEV;
2794 }
2795
2796 static const struct drm_ioctl_desc i915_ioctls[] = {
2797 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2798 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2799 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2800 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2801 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2802 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2803 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
2804 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2805 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2806 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2807 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2808 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2809 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2810 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2811 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2812 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2813 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2814 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2815 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2816 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
2817 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2818 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2819 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
2820 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2821 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2822 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
2823 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2824 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2825 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2826 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2827 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2828 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2829 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
2830 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2831 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2832 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2833 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2834 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2835 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2836 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2837 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2838 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2839 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2840 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2841 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
2842 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2843 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2844 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2845 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2846 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2847 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2848 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2849 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2850 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
2851 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
2852 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
2853 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
2854 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
2855 };
2856
2857 static struct drm_driver driver = {
2858 /* Don't use MTRRs here; the Xserver or userspace app should
2859 * deal with them for Intel hardware.
2860 */
2861 .driver_features =
2862 DRIVER_GEM |
2863 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2864 .release = i915_driver_release,
2865 .open = i915_driver_open,
2866 .lastclose = i915_driver_lastclose,
2867 .postclose = i915_driver_postclose,
2868
2869 .gem_close_object = i915_gem_close_object,
2870 .gem_free_object_unlocked = i915_gem_free_object,
2871 #ifdef __NetBSD__
2872 .request_irq = drm_pci_request_irq,
2873 .free_irq = drm_pci_free_irq,
2874
2875 .mmap_object = &i915_gem_mmap_object,
2876 .gem_uvm_ops = &i915_gem_uvm_ops,
2877 #endif
2878
2879
2880 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2881 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2882 .gem_prime_export = i915_gem_prime_export,
2883 .gem_prime_import = i915_gem_prime_import,
2884
2885 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
2886 .get_scanout_position = i915_get_crtc_scanoutpos,
2887
2888 .dumb_create = i915_gem_dumb_create,
2889 .dumb_map_offset = i915_gem_dumb_mmap_offset,
2890
2891 .ioctls = i915_ioctls,
2892 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2893 #ifdef __NetBSD__
2894 .fops = NULL,
2895 #else
2896 .fops = &i915_driver_fops,
2897 #endif
2898 .name = DRIVER_NAME,
2899 .desc = DRIVER_DESC,
2900 .date = DRIVER_DATE,
2901 .major = DRIVER_MAJOR,
2902 .minor = DRIVER_MINOR,
2903 .patchlevel = DRIVER_PATCHLEVEL,
2904 };
2905