1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD: stable/12/sys/x86/x86/identcpu.c 369007 2021-01-13 01:15:45Z kib $");
43
44 #include "opt_cpu.h"
45
46 #include <sys/param.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
55
56 #include <machine/asmacros.h>
57 #include <machine/clock.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
63 #include <machine/specialreg.h>
64
65 #include <amd64/vmm/intel/vmx_controls.h>
66 #include <x86/isa/icu.h>
67 #include <x86/vmware.h>
68
69 #ifdef __i386__
70 #define IDENTBLUE_CYRIX486 0
71 #define IDENTBLUE_IBMCPU 1
72 #define IDENTBLUE_CYRIXM2 2
73
74 static void identifycyrix(void);
75 static void print_transmeta_info(void);
76 #endif
77 static u_int find_cpu_vendor_id(void);
78 static void print_AMD_info(void);
79 static void print_INTEL_info(void);
80 static void print_INTEL_TLB(u_int data);
81 static void print_hypervisor_info(void);
82 static void print_svm_info(void);
83 static void print_via_padlock_info(void);
84 static void print_vmx_info(void);
85
86 #ifdef __i386__
87 int cpu; /* Are we 386, 386sx, 486, etc? */
88 int cpu_class;
89 #endif
90 u_int cpu_feature; /* Feature flags */
91 u_int cpu_feature2; /* Feature flags */
92 u_int amd_feature; /* AMD feature flags */
93 u_int amd_feature2; /* AMD feature flags */
94 u_int amd_rascap; /* AMD RAS capabilities */
95 u_int amd_pminfo; /* AMD advanced power management info */
96 u_int amd_extended_feature_extensions;
97 u_int via_feature_rng; /* VIA RNG features */
98 u_int via_feature_xcrypt; /* VIA ACE features */
99 u_int cpu_high; /* Highest arg to CPUID */
100 u_int cpu_exthigh; /* Highest arg to extended CPUID */
101 u_int cpu_id; /* Stepping ID */
102 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
103 u_int cpu_procinfo2; /* Multicore info */
104 char cpu_vendor[20]; /* CPU Origin code */
105 u_int cpu_vendor_id; /* CPU vendor ID */
106 u_int cpu_fxsr; /* SSE enabled */
107 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
108 u_int cpu_clflush_line_size = 32;
109 u_int cpu_stdext_feature; /* %ebx */
110 u_int cpu_stdext_feature2; /* %ecx */
111 u_int cpu_stdext_feature3; /* %edx */
112 uint64_t cpu_ia32_arch_caps;
113 u_int cpu_max_ext_state_size;
114 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
115 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
116 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
117 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
118 char machine[] = MACHINE;
119
120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
121 &via_feature_rng, 0,
122 "VIA RNG feature available in CPU");
123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
124 &via_feature_xcrypt, 0,
125 "VIA xcrypt feature available in CPU");
126
127 #ifdef __amd64__
128 #ifdef SCTL_MASK32
129 extern int adaptive_machine_arch;
130 #endif
131
132 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
134 {
135 #ifdef SCTL_MASK32
136 static const char machine32[] = "i386";
137 #endif
138 int error;
139
140 #ifdef SCTL_MASK32
141 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
142 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
143 else
144 #endif
145 error = SYSCTL_OUT(req, machine, sizeof(machine));
146 return (error);
147
148 }
149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
150 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
151 #else
152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
153 machine, 0, "Machine class");
154 #endif
155
156 static char cpu_model[128];
157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
158 cpu_model, 0, "Machine model");
159
160 static int hw_clockrate;
161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
162 &hw_clockrate, 0, "CPU instruction clock rate");
163
164 u_int hv_high;
165 char hv_vendor[16];
166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
167 0, "Hypervisor vendor");
168
169 static eventhandler_tag tsc_post_tag;
170
171 static char cpu_brand[48];
172
173 #ifdef __i386__
174 #define MAX_BRAND_INDEX 8
175
176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
177 NULL, /* No brand */
178 "Intel Celeron",
179 "Intel Pentium III",
180 "Intel Pentium III Xeon",
181 NULL,
182 NULL,
183 NULL,
184 NULL,
185 "Intel Pentium 4"
186 };
187
188 static struct {
189 char *cpu_name;
190 int cpu_class;
191 } cpus[] = {
192 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
193 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
194 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
195 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
196 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
197 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
198 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
199 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
200 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
201 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
202 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
203 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
204 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
205 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
206 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
207 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
208 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
209 };
210 #endif
211
212 static struct {
213 char *vendor;
214 u_int vendor_id;
215 } cpu_vendors[] = {
216 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
217 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
218 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
219 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
220 #ifdef __i386__
221 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
222 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
223 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
224 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
225 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
226 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
227 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
228 #if 0
229 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
230 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
231 #endif
232 #endif
233 };
234
235 void
printcpuinfo(void)236 printcpuinfo(void)
237 {
238 u_int regs[4], i;
239 char *brand;
240
241 printf("CPU: ");
242 #ifdef __i386__
243 cpu_class = cpus[cpu].cpu_class;
244 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
245 #else
246 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
247 #endif
248
249 /* Check for extended CPUID information and a processor name. */
250 if (cpu_exthigh >= 0x80000004) {
251 brand = cpu_brand;
252 for (i = 0x80000002; i < 0x80000005; i++) {
253 do_cpuid(i, regs);
254 memcpy(brand, regs, sizeof(regs));
255 brand += sizeof(regs);
256 }
257 }
258
259 switch (cpu_vendor_id) {
260 case CPU_VENDOR_INTEL:
261 #ifdef __i386__
262 if ((cpu_id & 0xf00) > 0x300) {
263 u_int brand_index;
264
265 cpu_model[0] = '\0';
266
267 switch (cpu_id & 0x3000) {
268 case 0x1000:
269 strcpy(cpu_model, "Overdrive ");
270 break;
271 case 0x2000:
272 strcpy(cpu_model, "Dual ");
273 break;
274 }
275
276 switch (cpu_id & 0xf00) {
277 case 0x400:
278 strcat(cpu_model, "i486 ");
279 /* Check the particular flavor of 486 */
280 switch (cpu_id & 0xf0) {
281 case 0x00:
282 case 0x10:
283 strcat(cpu_model, "DX");
284 break;
285 case 0x20:
286 strcat(cpu_model, "SX");
287 break;
288 case 0x30:
289 strcat(cpu_model, "DX2");
290 break;
291 case 0x40:
292 strcat(cpu_model, "SL");
293 break;
294 case 0x50:
295 strcat(cpu_model, "SX2");
296 break;
297 case 0x70:
298 strcat(cpu_model,
299 "DX2 Write-Back Enhanced");
300 break;
301 case 0x80:
302 strcat(cpu_model, "DX4");
303 break;
304 }
305 break;
306 case 0x500:
307 /* Check the particular flavor of 586 */
308 strcat(cpu_model, "Pentium");
309 switch (cpu_id & 0xf0) {
310 case 0x00:
311 strcat(cpu_model, " A-step");
312 break;
313 case 0x10:
314 strcat(cpu_model, "/P5");
315 break;
316 case 0x20:
317 strcat(cpu_model, "/P54C");
318 break;
319 case 0x30:
320 strcat(cpu_model, "/P24T");
321 break;
322 case 0x40:
323 strcat(cpu_model, "/P55C");
324 break;
325 case 0x70:
326 strcat(cpu_model, "/P54C");
327 break;
328 case 0x80:
329 strcat(cpu_model, "/P55C (quarter-micron)");
330 break;
331 default:
332 /* nothing */
333 break;
334 }
335 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
336 /*
337 * XXX - If/when Intel fixes the bug, this
338 * should also check the version of the
339 * CPU, not just that it's a Pentium.
340 */
341 has_f00f_bug = 1;
342 #endif
343 break;
344 case 0x600:
345 /* Check the particular flavor of 686 */
346 switch (cpu_id & 0xf0) {
347 case 0x00:
348 strcat(cpu_model, "Pentium Pro A-step");
349 break;
350 case 0x10:
351 strcat(cpu_model, "Pentium Pro");
352 break;
353 case 0x30:
354 case 0x50:
355 case 0x60:
356 strcat(cpu_model,
357 "Pentium II/Pentium II Xeon/Celeron");
358 cpu = CPU_PII;
359 break;
360 case 0x70:
361 case 0x80:
362 case 0xa0:
363 case 0xb0:
364 strcat(cpu_model,
365 "Pentium III/Pentium III Xeon/Celeron");
366 cpu = CPU_PIII;
367 break;
368 default:
369 strcat(cpu_model, "Unknown 80686");
370 break;
371 }
372 break;
373 case 0xf00:
374 strcat(cpu_model, "Pentium 4");
375 cpu = CPU_P4;
376 break;
377 default:
378 strcat(cpu_model, "unknown");
379 break;
380 }
381
382 /*
383 * If we didn't get a brand name from the extended
384 * CPUID, try to look it up in the brand table.
385 */
386 if (cpu_high > 0 && *cpu_brand == '\0') {
387 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
388 if (brand_index <= MAX_BRAND_INDEX &&
389 cpu_brandtable[brand_index] != NULL)
390 strcpy(cpu_brand,
391 cpu_brandtable[brand_index]);
392 }
393 }
394 #else
395 /* Please make up your mind folks! */
396 strcat(cpu_model, "EM64T");
397 #endif
398 break;
399 case CPU_VENDOR_AMD:
400 /*
401 * Values taken from AMD Processor Recognition
402 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
403 * (also describes ``Features'' encodings.
404 */
405 strcpy(cpu_model, "AMD ");
406 #ifdef __i386__
407 switch (cpu_id & 0xFF0) {
408 case 0x410:
409 strcat(cpu_model, "Standard Am486DX");
410 break;
411 case 0x430:
412 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
413 break;
414 case 0x470:
415 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
416 break;
417 case 0x480:
418 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
419 break;
420 case 0x490:
421 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
422 break;
423 case 0x4E0:
424 strcat(cpu_model, "Am5x86 Write-Through");
425 break;
426 case 0x4F0:
427 strcat(cpu_model, "Am5x86 Write-Back");
428 break;
429 case 0x500:
430 strcat(cpu_model, "K5 model 0");
431 break;
432 case 0x510:
433 strcat(cpu_model, "K5 model 1");
434 break;
435 case 0x520:
436 strcat(cpu_model, "K5 PR166 (model 2)");
437 break;
438 case 0x530:
439 strcat(cpu_model, "K5 PR200 (model 3)");
440 break;
441 case 0x560:
442 strcat(cpu_model, "K6");
443 break;
444 case 0x570:
445 strcat(cpu_model, "K6 266 (model 1)");
446 break;
447 case 0x580:
448 strcat(cpu_model, "K6-2");
449 break;
450 case 0x590:
451 strcat(cpu_model, "K6-III");
452 break;
453 case 0x5a0:
454 strcat(cpu_model, "Geode LX");
455 break;
456 default:
457 strcat(cpu_model, "Unknown");
458 break;
459 }
460 #else
461 if ((cpu_id & 0xf00) == 0xf00)
462 strcat(cpu_model, "AMD64 Processor");
463 else
464 strcat(cpu_model, "Unknown");
465 #endif
466 break;
467 #ifdef __i386__
468 case CPU_VENDOR_CYRIX:
469 strcpy(cpu_model, "Cyrix ");
470 switch (cpu_id & 0xff0) {
471 case 0x440:
472 strcat(cpu_model, "MediaGX");
473 break;
474 case 0x520:
475 strcat(cpu_model, "6x86");
476 break;
477 case 0x540:
478 cpu_class = CPUCLASS_586;
479 strcat(cpu_model, "GXm");
480 break;
481 case 0x600:
482 strcat(cpu_model, "6x86MX");
483 break;
484 default:
485 /*
486 * Even though CPU supports the cpuid
487 * instruction, it can be disabled.
488 * Therefore, this routine supports all Cyrix
489 * CPUs.
490 */
491 switch (cyrix_did & 0xf0) {
492 case 0x00:
493 switch (cyrix_did & 0x0f) {
494 case 0x00:
495 strcat(cpu_model, "486SLC");
496 break;
497 case 0x01:
498 strcat(cpu_model, "486DLC");
499 break;
500 case 0x02:
501 strcat(cpu_model, "486SLC2");
502 break;
503 case 0x03:
504 strcat(cpu_model, "486DLC2");
505 break;
506 case 0x04:
507 strcat(cpu_model, "486SRx");
508 break;
509 case 0x05:
510 strcat(cpu_model, "486DRx");
511 break;
512 case 0x06:
513 strcat(cpu_model, "486SRx2");
514 break;
515 case 0x07:
516 strcat(cpu_model, "486DRx2");
517 break;
518 case 0x08:
519 strcat(cpu_model, "486SRu");
520 break;
521 case 0x09:
522 strcat(cpu_model, "486DRu");
523 break;
524 case 0x0a:
525 strcat(cpu_model, "486SRu2");
526 break;
527 case 0x0b:
528 strcat(cpu_model, "486DRu2");
529 break;
530 default:
531 strcat(cpu_model, "Unknown");
532 break;
533 }
534 break;
535 case 0x10:
536 switch (cyrix_did & 0x0f) {
537 case 0x00:
538 strcat(cpu_model, "486S");
539 break;
540 case 0x01:
541 strcat(cpu_model, "486S2");
542 break;
543 case 0x02:
544 strcat(cpu_model, "486Se");
545 break;
546 case 0x03:
547 strcat(cpu_model, "486S2e");
548 break;
549 case 0x0a:
550 strcat(cpu_model, "486DX");
551 break;
552 case 0x0b:
553 strcat(cpu_model, "486DX2");
554 break;
555 case 0x0f:
556 strcat(cpu_model, "486DX4");
557 break;
558 default:
559 strcat(cpu_model, "Unknown");
560 break;
561 }
562 break;
563 case 0x20:
564 if ((cyrix_did & 0x0f) < 8)
565 strcat(cpu_model, "6x86"); /* Where did you get it? */
566 else
567 strcat(cpu_model, "5x86");
568 break;
569 case 0x30:
570 strcat(cpu_model, "6x86");
571 break;
572 case 0x40:
573 if ((cyrix_did & 0xf000) == 0x3000) {
574 cpu_class = CPUCLASS_586;
575 strcat(cpu_model, "GXm");
576 } else
577 strcat(cpu_model, "MediaGX");
578 break;
579 case 0x50:
580 strcat(cpu_model, "6x86MX");
581 break;
582 case 0xf0:
583 switch (cyrix_did & 0x0f) {
584 case 0x0d:
585 strcat(cpu_model, "Overdrive CPU");
586 break;
587 case 0x0e:
588 strcpy(cpu_model, "Texas Instruments 486SXL");
589 break;
590 case 0x0f:
591 strcat(cpu_model, "486SLC/DLC");
592 break;
593 default:
594 strcat(cpu_model, "Unknown");
595 break;
596 }
597 break;
598 default:
599 strcat(cpu_model, "Unknown");
600 break;
601 }
602 break;
603 }
604 break;
605 case CPU_VENDOR_RISE:
606 strcpy(cpu_model, "Rise ");
607 switch (cpu_id & 0xff0) {
608 case 0x500: /* 6401 and 6441 (Kirin) */
609 case 0x520: /* 6510 (Lynx) */
610 strcat(cpu_model, "mP6");
611 break;
612 default:
613 strcat(cpu_model, "Unknown");
614 }
615 break;
616 #endif
617 case CPU_VENDOR_CENTAUR:
618 #ifdef __i386__
619 switch (cpu_id & 0xff0) {
620 case 0x540:
621 strcpy(cpu_model, "IDT WinChip C6");
622 break;
623 case 0x580:
624 strcpy(cpu_model, "IDT WinChip 2");
625 break;
626 case 0x590:
627 strcpy(cpu_model, "IDT WinChip 3");
628 break;
629 case 0x660:
630 strcpy(cpu_model, "VIA C3 Samuel");
631 break;
632 case 0x670:
633 if (cpu_id & 0x8)
634 strcpy(cpu_model, "VIA C3 Ezra");
635 else
636 strcpy(cpu_model, "VIA C3 Samuel 2");
637 break;
638 case 0x680:
639 strcpy(cpu_model, "VIA C3 Ezra-T");
640 break;
641 case 0x690:
642 strcpy(cpu_model, "VIA C3 Nehemiah");
643 break;
644 case 0x6a0:
645 case 0x6d0:
646 strcpy(cpu_model, "VIA C7 Esther");
647 break;
648 case 0x6f0:
649 strcpy(cpu_model, "VIA Nano");
650 break;
651 default:
652 strcpy(cpu_model, "VIA/IDT Unknown");
653 }
654 #else
655 strcpy(cpu_model, "VIA ");
656 if ((cpu_id & 0xff0) == 0x6f0)
657 strcat(cpu_model, "Nano Processor");
658 else
659 strcat(cpu_model, "Unknown");
660 #endif
661 break;
662 #ifdef __i386__
663 case CPU_VENDOR_IBM:
664 strcpy(cpu_model, "Blue Lightning CPU");
665 break;
666 case CPU_VENDOR_NSC:
667 switch (cpu_id & 0xff0) {
668 case 0x540:
669 strcpy(cpu_model, "Geode SC1100");
670 cpu = CPU_GEODE1100;
671 break;
672 default:
673 strcpy(cpu_model, "Geode/NSC unknown");
674 break;
675 }
676 break;
677 #endif
678 case CPU_VENDOR_HYGON:
679 strcpy(cpu_model, "Hygon ");
680 #ifdef __i386__
681 strcat(cpu_model, "Unknown");
682 #else
683 if ((cpu_id & 0xf00) == 0xf00)
684 strcat(cpu_model, "AMD64 Processor");
685 else
686 strcat(cpu_model, "Unknown");
687 #endif
688 break;
689
690 default:
691 strcat(cpu_model, "Unknown");
692 break;
693 }
694
695 /*
696 * Replace cpu_model with cpu_brand minus leading spaces if
697 * we have one.
698 */
699 brand = cpu_brand;
700 while (*brand == ' ')
701 ++brand;
702 if (*brand != '\0')
703 strcpy(cpu_model, brand);
704
705 printf("%s (", cpu_model);
706 if (tsc_freq != 0) {
707 hw_clockrate = (tsc_freq + 5000) / 1000000;
708 printf("%jd.%02d-MHz ",
709 (intmax_t)(tsc_freq + 4999) / 1000000,
710 (u_int)((tsc_freq + 4999) / 10000) % 100);
711 }
712 #ifdef __i386__
713 switch(cpu_class) {
714 case CPUCLASS_286:
715 printf("286");
716 break;
717 case CPUCLASS_386:
718 printf("386");
719 break;
720 #if defined(I486_CPU)
721 case CPUCLASS_486:
722 printf("486");
723 break;
724 #endif
725 #if defined(I586_CPU)
726 case CPUCLASS_586:
727 printf("586");
728 break;
729 #endif
730 #if defined(I686_CPU)
731 case CPUCLASS_686:
732 printf("686");
733 break;
734 #endif
735 default:
736 printf("Unknown"); /* will panic below... */
737 }
738 #else
739 printf("K8");
740 #endif
741 printf("-class CPU)\n");
742 if (*cpu_vendor)
743 printf(" Origin=\"%s\"", cpu_vendor);
744 if (cpu_id)
745 printf(" Id=0x%x", cpu_id);
746
747 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
748 cpu_vendor_id == CPU_VENDOR_AMD ||
749 cpu_vendor_id == CPU_VENDOR_HYGON ||
750 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
751 #ifdef __i386__
752 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
753 cpu_vendor_id == CPU_VENDOR_RISE ||
754 cpu_vendor_id == CPU_VENDOR_NSC ||
755 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
756 #endif
757 0) {
758 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
759 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
760 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
761 #ifdef __i386__
762 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
763 printf("\n DIR=0x%04x", cyrix_did);
764 #endif
765
766 /*
767 * AMD CPUID Specification
768 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
769 *
770 * Intel Processor Identification and CPUID Instruction
771 * http://www.intel.com/assets/pdf/appnote/241618.pdf
772 */
773 if (cpu_high > 0) {
774
775 /*
776 * Here we should probably set up flags indicating
777 * whether or not various features are available.
778 * The interesting ones are probably VME, PSE, PAE,
779 * and PGE. The code already assumes without bothering
780 * to check that all CPUs >= Pentium have a TSC and
781 * MSRs.
782 */
783 printf("\n Features=0x%b", cpu_feature,
784 "\020"
785 "\001FPU" /* Integral FPU */
786 "\002VME" /* Extended VM86 mode support */
787 "\003DE" /* Debugging Extensions (CR4.DE) */
788 "\004PSE" /* 4MByte page tables */
789 "\005TSC" /* Timestamp counter */
790 "\006MSR" /* Machine specific registers */
791 "\007PAE" /* Physical address extension */
792 "\010MCE" /* Machine Check support */
793 "\011CX8" /* CMPEXCH8 instruction */
794 "\012APIC" /* SMP local APIC */
795 "\013oldMTRR" /* Previous implementation of MTRR */
796 "\014SEP" /* Fast System Call */
797 "\015MTRR" /* Memory Type Range Registers */
798 "\016PGE" /* PG_G (global bit) support */
799 "\017MCA" /* Machine Check Architecture */
800 "\020CMOV" /* CMOV instruction */
801 "\021PAT" /* Page attributes table */
802 "\022PSE36" /* 36 bit address space support */
803 "\023PN" /* Processor Serial number */
804 "\024CLFLUSH" /* Has the CLFLUSH instruction */
805 "\025<b20>"
806 "\026DTS" /* Debug Trace Store */
807 "\027ACPI" /* ACPI support */
808 "\030MMX" /* MMX instructions */
809 "\031FXSR" /* FXSAVE/FXRSTOR */
810 "\032SSE" /* Streaming SIMD Extensions */
811 "\033SSE2" /* Streaming SIMD Extensions #2 */
812 "\034SS" /* Self snoop */
813 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
814 "\036TM" /* Thermal Monitor clock slowdown */
815 "\037IA64" /* CPU can execute IA64 instructions */
816 "\040PBE" /* Pending Break Enable */
817 );
818
819 if (cpu_feature2 != 0) {
820 printf("\n Features2=0x%b", cpu_feature2,
821 "\020"
822 "\001SSE3" /* SSE3 */
823 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
824 "\003DTES64" /* 64-bit Debug Trace */
825 "\004MON" /* MONITOR/MWAIT Instructions */
826 "\005DS_CPL" /* CPL Qualified Debug Store */
827 "\006VMX" /* Virtual Machine Extensions */
828 "\007SMX" /* Safer Mode Extensions */
829 "\010EST" /* Enhanced SpeedStep */
830 "\011TM2" /* Thermal Monitor 2 */
831 "\012SSSE3" /* SSSE3 */
832 "\013CNXT-ID" /* L1 context ID available */
833 "\014SDBG" /* IA32 silicon debug */
834 "\015FMA" /* Fused Multiply Add */
835 "\016CX16" /* CMPXCHG16B Instruction */
836 "\017xTPR" /* Send Task Priority Messages*/
837 "\020PDCM" /* Perf/Debug Capability MSR */
838 "\021<b16>"
839 "\022PCID" /* Process-context Identifiers*/
840 "\023DCA" /* Direct Cache Access */
841 "\024SSE4.1" /* SSE 4.1 */
842 "\025SSE4.2" /* SSE 4.2 */
843 "\026x2APIC" /* xAPIC Extensions */
844 "\027MOVBE" /* MOVBE Instruction */
845 "\030POPCNT" /* POPCNT Instruction */
846 "\031TSCDLT" /* TSC-Deadline Timer */
847 "\032AESNI" /* AES Crypto */
848 "\033XSAVE" /* XSAVE/XRSTOR States */
849 "\034OSXSAVE" /* OS-Enabled State Management*/
850 "\035AVX" /* Advanced Vector Extensions */
851 "\036F16C" /* Half-precision conversions */
852 "\037RDRAND" /* RDRAND Instruction */
853 "\040HV" /* Hypervisor */
854 );
855 }
856
857 if (amd_feature != 0) {
858 printf("\n AMD Features=0x%b", amd_feature,
859 "\020" /* in hex */
860 "\001<s0>" /* Same */
861 "\002<s1>" /* Same */
862 "\003<s2>" /* Same */
863 "\004<s3>" /* Same */
864 "\005<s4>" /* Same */
865 "\006<s5>" /* Same */
866 "\007<s6>" /* Same */
867 "\010<s7>" /* Same */
868 "\011<s8>" /* Same */
869 "\012<s9>" /* Same */
870 "\013<b10>" /* Undefined */
871 "\014SYSCALL" /* Have SYSCALL/SYSRET */
872 "\015<s12>" /* Same */
873 "\016<s13>" /* Same */
874 "\017<s14>" /* Same */
875 "\020<s15>" /* Same */
876 "\021<s16>" /* Same */
877 "\022<s17>" /* Same */
878 "\023<b18>" /* Reserved, unknown */
879 "\024MP" /* Multiprocessor Capable */
880 "\025NX" /* Has EFER.NXE, NX */
881 "\026<b21>" /* Undefined */
882 "\027MMX+" /* AMD MMX Extensions */
883 "\030<s23>" /* Same */
884 "\031<s24>" /* Same */
885 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
886 "\033Page1GB" /* 1-GB large page support */
887 "\034RDTSCP" /* RDTSCP */
888 "\035<b28>" /* Undefined */
889 "\036LM" /* 64 bit long mode */
890 "\0373DNow!+" /* AMD 3DNow! Extensions */
891 "\0403DNow!" /* AMD 3DNow! */
892 );
893 }
894
895 if (amd_feature2 != 0) {
896 printf("\n AMD Features2=0x%b", amd_feature2,
897 "\020"
898 "\001LAHF" /* LAHF/SAHF in long mode */
899 "\002CMP" /* CMP legacy */
900 "\003SVM" /* Secure Virtual Mode */
901 "\004ExtAPIC" /* Extended APIC register */
902 "\005CR8" /* CR8 in legacy mode */
903 "\006ABM" /* LZCNT instruction */
904 "\007SSE4A" /* SSE4A */
905 "\010MAS" /* Misaligned SSE mode */
906 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
907 "\012OSVW" /* OS visible workaround */
908 "\013IBS" /* Instruction based sampling */
909 "\014XOP" /* XOP extended instructions */
910 "\015SKINIT" /* SKINIT/STGI */
911 "\016WDT" /* Watchdog timer */
912 "\017<b14>"
913 "\020LWP" /* Lightweight Profiling */
914 "\021FMA4" /* 4-operand FMA instructions */
915 "\022TCE" /* Translation Cache Extension */
916 "\023<b18>"
917 "\024NodeId" /* NodeId MSR support */
918 "\025<b20>"
919 "\026TBM" /* Trailing Bit Manipulation */
920 "\027Topology" /* Topology Extensions */
921 "\030PCXC" /* Core perf count */
922 "\031PNXC" /* NB perf count */
923 "\032<b25>"
924 "\033DBE" /* Data Breakpoint extension */
925 "\034PTSC" /* Performance TSC */
926 "\035PL2I" /* L2I perf count */
927 "\036MWAITX" /* MONITORX/MWAITX instructions */
928 "\037<b30>"
929 "\040<b31>"
930 );
931 }
932
933 if (cpu_stdext_feature != 0) {
934 printf("\n Structured Extended Features=0x%b",
935 cpu_stdext_feature,
936 "\020"
937 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
938 "\001FSGSBASE"
939 "\002TSCADJ"
940 "\003SGX"
941 /* Bit Manipulation Instructions */
942 "\004BMI1"
943 /* Hardware Lock Elision */
944 "\005HLE"
945 /* Advanced Vector Instructions 2 */
946 "\006AVX2"
947 /* FDP_EXCPTN_ONLY */
948 "\007FDPEXC"
949 /* Supervisor Mode Execution Prot. */
950 "\010SMEP"
951 /* Bit Manipulation Instructions */
952 "\011BMI2"
953 "\012ERMS"
954 /* Invalidate Processor Context ID */
955 "\013INVPCID"
956 /* Restricted Transactional Memory */
957 "\014RTM"
958 "\015PQM"
959 "\016NFPUSG"
960 /* Intel Memory Protection Extensions */
961 "\017MPX"
962 "\020PQE"
963 /* AVX512 Foundation */
964 "\021AVX512F"
965 "\022AVX512DQ"
966 /* Enhanced NRBG */
967 "\023RDSEED"
968 /* ADCX + ADOX */
969 "\024ADX"
970 /* Supervisor Mode Access Prevention */
971 "\025SMAP"
972 "\026AVX512IFMA"
973 "\027PCOMMIT"
974 "\030CLFLUSHOPT"
975 "\031CLWB"
976 "\032PROCTRACE"
977 "\033AVX512PF"
978 "\034AVX512ER"
979 "\035AVX512CD"
980 "\036SHA"
981 "\037AVX512BW"
982 "\040AVX512VL"
983 );
984 }
985
986 if (cpu_stdext_feature2 != 0) {
987 printf("\n Structured Extended Features2=0x%b",
988 cpu_stdext_feature2,
989 "\020"
990 "\001PREFETCHWT1"
991 "\002AVX512VBMI"
992 "\003UMIP"
993 "\004PKU"
994 "\005OSPKE"
995 "\006WAITPKG"
996 "\007AVX512VBMI2"
997 "\011GFNI"
998 "\012VAES"
999 "\013VPCLMULQDQ"
1000 "\014AVX512VNNI"
1001 "\015AVX512BITALG"
1002 "\016AVX512VPOPCNTDQ"
1003 "\027RDPID"
1004 "\032CLDEMOTE"
1005 "\034MOVDIRI"
1006 "\035MOVDIRI64B"
1007 "\036ENQCMD"
1008 "\037SGXLC"
1009 );
1010 }
1011
1012 if (cpu_stdext_feature3 != 0) {
1013 printf("\n Structured Extended Features3=0x%b",
1014 cpu_stdext_feature3,
1015 "\020"
1016 "\003AVX512_4VNNIW"
1017 "\004AVX512_4FMAPS"
1018 "\011AVX512VP2INTERSECT"
1019 "\012MCUOPT"
1020 "\013MD_CLEAR"
1021 "\016TSXFA"
1022 "\023PCONFIG"
1023 "\033IBPB"
1024 "\034STIBP"
1025 "\035L1DFL"
1026 "\036ARCH_CAP"
1027 "\037CORE_CAP"
1028 "\040SSBD"
1029 );
1030 }
1031
1032 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1033 cpuid_count(0xd, 0x1, regs);
1034 if (regs[0] != 0) {
1035 printf("\n XSAVE Features=0x%b",
1036 regs[0],
1037 "\020"
1038 "\001XSAVEOPT"
1039 "\002XSAVEC"
1040 "\003XINUSE"
1041 "\004XSAVES");
1042 }
1043 }
1044
1045 if (cpu_ia32_arch_caps != 0) {
1046 printf("\n IA32_ARCH_CAPS=0x%b",
1047 (u_int)cpu_ia32_arch_caps,
1048 "\020"
1049 "\001RDCL_NO"
1050 "\002IBRS_ALL"
1051 "\003RSBA"
1052 "\004SKIP_L1DFL_VME"
1053 "\005SSB_NO"
1054 "\005MDS_NO"
1055 "\010TSX_CTRL"
1056 "\011TAA_NO"
1057 );
1058 }
1059
1060 if (amd_extended_feature_extensions != 0) {
1061 printf("\n "
1062 "AMD Extended Feature Extensions ID EBX="
1063 "0x%b", amd_extended_feature_extensions,
1064 "\020"
1065 "\001CLZERO"
1066 "\002IRPerf"
1067 "\003XSaveErPtr");
1068 }
1069
1070 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1071 print_via_padlock_info();
1072
1073 if (cpu_feature2 & CPUID2_VMX)
1074 print_vmx_info();
1075
1076 if (amd_feature2 & AMDID2_SVM)
1077 print_svm_info();
1078
1079 if ((cpu_feature & CPUID_HTT) &&
1080 (cpu_vendor_id == CPU_VENDOR_AMD ||
1081 cpu_vendor_id == CPU_VENDOR_HYGON))
1082 cpu_feature &= ~CPUID_HTT;
1083
1084 /*
1085 * If this CPU supports P-state invariant TSC then
1086 * mention the capability.
1087 */
1088 if (tsc_is_invariant) {
1089 printf("\n TSC: P-state invariant");
1090 if (tsc_perf_stat)
1091 printf(", performance statistics");
1092 }
1093 }
1094 #ifdef __i386__
1095 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1096 printf(" DIR=0x%04x", cyrix_did);
1097 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1098 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1099 #ifndef CYRIX_CACHE_REALLY_WORKS
1100 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1101 printf("\n CPU cache: write-through mode");
1102 #endif
1103 #endif
1104 }
1105
1106 /* Avoid ugly blank lines: only print newline when we have to. */
1107 if (*cpu_vendor || cpu_id)
1108 printf("\n");
1109
1110 if (bootverbose) {
1111 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1112 cpu_vendor_id == CPU_VENDOR_HYGON)
1113 print_AMD_info();
1114 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1115 print_INTEL_info();
1116 #ifdef __i386__
1117 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1118 print_transmeta_info();
1119 #endif
1120 }
1121
1122 print_hypervisor_info();
1123 }
1124
1125 #ifdef __i386__
1126 void
panicifcpuunsupported(void)1127 panicifcpuunsupported(void)
1128 {
1129
1130 #if !defined(lint)
1131 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1132 #error This kernel is not configured for one of the supported CPUs
1133 #endif
1134 #else /* lint */
1135 #endif /* lint */
1136 /*
1137 * Now that we have told the user what they have,
1138 * let them know if that machine type isn't configured.
1139 */
1140 switch (cpu_class) {
1141 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1142 case CPUCLASS_386:
1143 #if !defined(I486_CPU)
1144 case CPUCLASS_486:
1145 #endif
1146 #if !defined(I586_CPU)
1147 case CPUCLASS_586:
1148 #endif
1149 #if !defined(I686_CPU)
1150 case CPUCLASS_686:
1151 #endif
1152 panic("CPU class not configured");
1153 default:
1154 break;
1155 }
1156 }
1157
1158 static volatile u_int trap_by_rdmsr;
1159
1160 /*
1161 * Special exception 6 handler.
1162 * The rdmsr instruction generates invalid opcodes fault on 486-class
1163 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1164 * function identblue() when this handler is called. Stacked eip should
1165 * be advanced.
1166 */
1167 inthand_t bluetrap6;
1168 #ifdef __GNUCLIKE_ASM
1169 __asm
1170 (" \n\
1171 .text \n\
1172 .p2align 2,0x90 \n\
1173 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1174 " __XSTRING(CNAME(bluetrap6)) ": \n\
1175 ss \n\
1176 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1177 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1178 iret \n\
1179 ");
1180 #endif
1181
1182 /*
1183 * Special exception 13 handler.
1184 * Accessing non-existent MSR generates general protection fault.
1185 */
1186 inthand_t bluetrap13;
1187 #ifdef __GNUCLIKE_ASM
1188 __asm
1189 (" \n\
1190 .text \n\
1191 .p2align 2,0x90 \n\
1192 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1193 " __XSTRING(CNAME(bluetrap13)) ": \n\
1194 ss \n\
1195 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1196 popl %eax /* discard error code */ \n\
1197 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1198 iret \n\
1199 ");
1200 #endif
1201
1202 /*
1203 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1204 * support cpuid instruction. This function should be called after
1205 * loading interrupt descriptor table register.
1206 *
1207 * I don't like this method that handles fault, but I couldn't get
1208 * information for any other methods. Does blue giant know?
1209 */
1210 static int
identblue(void)1211 identblue(void)
1212 {
1213
1214 trap_by_rdmsr = 0;
1215
1216 /*
1217 * Cyrix 486-class CPU does not support rdmsr instruction.
1218 * The rdmsr instruction generates invalid opcode fault, and exception
1219 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1220 * bluetrap6() set the magic number to trap_by_rdmsr.
1221 */
1222 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1223 GSEL(GCODE_SEL, SEL_KPL));
1224
1225 /*
1226 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1227 * In this case, rdmsr generates general protection fault, and
1228 * exception will be trapped by bluetrap13().
1229 */
1230 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1231 GSEL(GCODE_SEL, SEL_KPL));
1232
1233 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1234
1235 if (trap_by_rdmsr == 0xa8c1d)
1236 return IDENTBLUE_CYRIX486;
1237 else if (trap_by_rdmsr == 0xa89c4)
1238 return IDENTBLUE_CYRIXM2;
1239 return IDENTBLUE_IBMCPU;
1240 }
1241
1242
1243 /*
1244 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1245 *
1246 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1247 * +-------+-------+---------------+
1248 * | SID | RID | Device ID |
1249 * | (DIR 1) | (DIR 0) |
1250 * +-------+-------+---------------+
1251 */
1252 static void
identifycyrix(void)1253 identifycyrix(void)
1254 {
1255 register_t saveintr;
1256 int ccr2_test = 0, dir_test = 0;
1257 u_char ccr2, ccr3;
1258
1259 saveintr = intr_disable();
1260
1261 ccr2 = read_cyrix_reg(CCR2);
1262 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1263 read_cyrix_reg(CCR2);
1264 if (read_cyrix_reg(CCR2) != ccr2)
1265 ccr2_test = 1;
1266 write_cyrix_reg(CCR2, ccr2);
1267
1268 ccr3 = read_cyrix_reg(CCR3);
1269 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1270 read_cyrix_reg(CCR3);
1271 if (read_cyrix_reg(CCR3) != ccr3)
1272 dir_test = 1; /* CPU supports DIRs. */
1273 write_cyrix_reg(CCR3, ccr3);
1274
1275 if (dir_test) {
1276 /* Device ID registers are available. */
1277 cyrix_did = read_cyrix_reg(DIR1) << 8;
1278 cyrix_did += read_cyrix_reg(DIR0);
1279 } else if (ccr2_test)
1280 cyrix_did = 0x0010; /* 486S A-step */
1281 else
1282 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1283
1284 intr_restore(saveintr);
1285 }
1286 #endif
1287
1288 /* Update TSC freq with the value indicated by the caller. */
1289 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1290 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1291 {
1292
1293 /* If there was an error during the transition, don't do anything. */
1294 if (status != 0)
1295 return;
1296
1297 /* Total setting for this level gives the new frequency in MHz. */
1298 hw_clockrate = level->total_set.freq;
1299 }
1300
1301 static void
hook_tsc_freq(void * arg __unused)1302 hook_tsc_freq(void *arg __unused)
1303 {
1304
1305 if (tsc_is_invariant)
1306 return;
1307
1308 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1309 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1310 }
1311
1312 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1313
1314 static const char *const vm_bnames[] = {
1315 "QEMU", /* QEMU */
1316 "Plex86", /* Plex86 */
1317 "Bochs", /* Bochs */
1318 "Xen", /* Xen */
1319 "BHYVE", /* bhyve */
1320 "Seabios", /* KVM */
1321 NULL
1322 };
1323
1324 static const char *const vm_pnames[] = {
1325 "VMware Virtual Platform", /* VMWare VM */
1326 "Virtual Machine", /* Microsoft VirtualPC */
1327 "VirtualBox", /* Sun xVM VirtualBox */
1328 "Parallels Virtual Platform", /* Parallels VM */
1329 "KVM", /* KVM */
1330 NULL
1331 };
1332
1333 void
identify_hypervisor(void)1334 identify_hypervisor(void)
1335 {
1336 u_int regs[4];
1337 char *p;
1338 int i;
1339
1340 /*
1341 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1342 * http://lkml.org/lkml/2008/10/1/246
1343 *
1344 * KB1009458: Mechanisms to determine if software is running in
1345 * a VMware virtual machine
1346 * http://kb.vmware.com/kb/1009458
1347 */
1348 if (cpu_feature2 & CPUID2_HV) {
1349 vm_guest = VM_GUEST_VM;
1350 do_cpuid(0x40000000, regs);
1351
1352 /*
1353 * KVM from Linux kernels prior to commit
1354 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1355 * to 0 rather than a valid hv_high value. Check for
1356 * the KVM signature bytes and fixup %eax to the
1357 * highest supported leaf in that case.
1358 */
1359 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1360 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1361 regs[0] = 0x40000001;
1362
1363 if (regs[0] >= 0x40000000) {
1364 hv_high = regs[0];
1365 ((u_int *)&hv_vendor)[0] = regs[1];
1366 ((u_int *)&hv_vendor)[1] = regs[2];
1367 ((u_int *)&hv_vendor)[2] = regs[3];
1368 hv_vendor[12] = '\0';
1369 if (strcmp(hv_vendor, "VMwareVMware") == 0)
1370 vm_guest = VM_GUEST_VMWARE;
1371 else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1372 vm_guest = VM_GUEST_HV;
1373 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1374 vm_guest = VM_GUEST_KVM;
1375 else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1376 vm_guest = VM_GUEST_BHYVE;
1377 }
1378 return;
1379 }
1380
1381 /*
1382 * Examine SMBIOS strings for older hypervisors.
1383 */
1384 p = kern_getenv("smbios.system.serial");
1385 if (p != NULL) {
1386 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1387 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1388 if (regs[1] == VMW_HVMAGIC) {
1389 vm_guest = VM_GUEST_VMWARE;
1390 freeenv(p);
1391 return;
1392 }
1393 }
1394 freeenv(p);
1395 }
1396
1397 /*
1398 * XXX: Some of these entries may not be needed since they were
1399 * added to FreeBSD before the checks above.
1400 */
1401 p = kern_getenv("smbios.bios.vendor");
1402 if (p != NULL) {
1403 for (i = 0; vm_bnames[i] != NULL; i++)
1404 if (strcmp(p, vm_bnames[i]) == 0) {
1405 vm_guest = VM_GUEST_VM;
1406 freeenv(p);
1407 return;
1408 }
1409 freeenv(p);
1410 }
1411 p = kern_getenv("smbios.system.product");
1412 if (p != NULL) {
1413 for (i = 0; vm_pnames[i] != NULL; i++)
1414 if (strcmp(p, vm_pnames[i]) == 0) {
1415 vm_guest = VM_GUEST_VM;
1416 freeenv(p);
1417 return;
1418 }
1419 freeenv(p);
1420 }
1421 }
1422
1423 bool
fix_cpuid(void)1424 fix_cpuid(void)
1425 {
1426 uint64_t msr;
1427
1428 /*
1429 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1430 * get the largest standard CPUID function number again if it is set
1431 * from BIOS. It is necessary for probing correct CPU topology later
1432 * and for the correct operation of the AVX-aware userspace.
1433 */
1434 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1435 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1436 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1437 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1438 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1439 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1440 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1441 msr &= ~IA32_MISC_EN_LIMCPUID;
1442 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1443 return (true);
1444 }
1445 }
1446
1447 /*
1448 * Re-enable AMD Topology Extension that could be disabled by BIOS
1449 * on some notebook processors. Without the extension it's really
1450 * hard to determine the correct CPU cache topology.
1451 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1452 * Models 60h-6Fh Processors, Publication # 50742.
1453 */
1454 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1455 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1456 msr = rdmsr(MSR_EXTFEATURES);
1457 if ((msr & ((uint64_t)1 << 54)) == 0) {
1458 msr |= (uint64_t)1 << 54;
1459 wrmsr(MSR_EXTFEATURES, msr);
1460 return (true);
1461 }
1462 }
1463 return (false);
1464 }
1465
1466 void
identify_cpu1(void)1467 identify_cpu1(void)
1468 {
1469 u_int regs[4];
1470
1471 do_cpuid(0, regs);
1472 cpu_high = regs[0];
1473 ((u_int *)&cpu_vendor)[0] = regs[1];
1474 ((u_int *)&cpu_vendor)[1] = regs[3];
1475 ((u_int *)&cpu_vendor)[2] = regs[2];
1476 cpu_vendor[12] = '\0';
1477
1478 do_cpuid(1, regs);
1479 cpu_id = regs[0];
1480 cpu_procinfo = regs[1];
1481 cpu_feature = regs[3];
1482 cpu_feature2 = regs[2];
1483 }
1484
1485 void
identify_cpu2(void)1486 identify_cpu2(void)
1487 {
1488 u_int regs[4], cpu_stdext_disable;
1489
1490 if (cpu_high >= 7) {
1491 cpuid_count(7, 0, regs);
1492 cpu_stdext_feature = regs[1];
1493
1494 /*
1495 * Some hypervisors failed to filter out unsupported
1496 * extended features. Allow to disable the
1497 * extensions, activation of which requires setting a
1498 * bit in CR4, and which VM monitors do not support.
1499 */
1500 cpu_stdext_disable = 0;
1501 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1502 cpu_stdext_feature &= ~cpu_stdext_disable;
1503
1504 cpu_stdext_feature2 = regs[2];
1505 cpu_stdext_feature3 = regs[3];
1506
1507 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1508 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1509 }
1510 }
1511
1512 void
identify_cpu_fixup_bsp(void)1513 identify_cpu_fixup_bsp(void)
1514 {
1515 u_int regs[4];
1516
1517 cpu_vendor_id = find_cpu_vendor_id();
1518
1519 if (fix_cpuid()) {
1520 do_cpuid(0, regs);
1521 cpu_high = regs[0];
1522 }
1523 }
1524
1525 /*
1526 * Final stage of CPU identification.
1527 */
1528 void
finishidentcpu(void)1529 finishidentcpu(void)
1530 {
1531 u_int regs[4];
1532 #ifdef __i386__
1533 u_char ccr3;
1534 #endif
1535
1536 identify_cpu_fixup_bsp();
1537
1538 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1539 do_cpuid(5, regs);
1540 cpu_mon_mwait_flags = regs[2];
1541 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1542 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1543 }
1544
1545 identify_cpu2();
1546
1547 #ifdef __i386__
1548 if (cpu_high > 0 &&
1549 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1550 cpu_vendor_id == CPU_VENDOR_AMD ||
1551 cpu_vendor_id == CPU_VENDOR_HYGON ||
1552 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1553 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1554 cpu_vendor_id == CPU_VENDOR_NSC)) {
1555 do_cpuid(0x80000000, regs);
1556 if (regs[0] >= 0x80000000)
1557 cpu_exthigh = regs[0];
1558 }
1559 #else
1560 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1561 cpu_vendor_id == CPU_VENDOR_AMD ||
1562 cpu_vendor_id == CPU_VENDOR_HYGON ||
1563 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1564 do_cpuid(0x80000000, regs);
1565 cpu_exthigh = regs[0];
1566 }
1567 #endif
1568 if (cpu_exthigh >= 0x80000001) {
1569 do_cpuid(0x80000001, regs);
1570 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1571 amd_feature2 = regs[2];
1572 }
1573 if (cpu_exthigh >= 0x80000007) {
1574 do_cpuid(0x80000007, regs);
1575 amd_rascap = regs[1];
1576 amd_pminfo = regs[3];
1577 }
1578 if (cpu_exthigh >= 0x80000008) {
1579 do_cpuid(0x80000008, regs);
1580 cpu_maxphyaddr = regs[0] & 0xff;
1581 amd_extended_feature_extensions = regs[1];
1582 cpu_procinfo2 = regs[2];
1583 } else {
1584 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1585 }
1586
1587 #ifdef __i386__
1588 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1589 if (cpu == CPU_486) {
1590 /*
1591 * These conditions are equivalent to:
1592 * - CPU does not support cpuid instruction.
1593 * - Cyrix/IBM CPU is detected.
1594 */
1595 if (identblue() == IDENTBLUE_IBMCPU) {
1596 strcpy(cpu_vendor, "IBM");
1597 cpu_vendor_id = CPU_VENDOR_IBM;
1598 cpu = CPU_BLUE;
1599 return;
1600 }
1601 }
1602 switch (cpu_id & 0xf00) {
1603 case 0x600:
1604 /*
1605 * Cyrix's datasheet does not describe DIRs.
1606 * Therefor, I assume it does not have them
1607 * and use the result of the cpuid instruction.
1608 * XXX they seem to have it for now at least. -Peter
1609 */
1610 identifycyrix();
1611 cpu = CPU_M2;
1612 break;
1613 default:
1614 identifycyrix();
1615 /*
1616 * This routine contains a trick.
1617 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1618 */
1619 switch (cyrix_did & 0x00f0) {
1620 case 0x00:
1621 case 0xf0:
1622 cpu = CPU_486DLC;
1623 break;
1624 case 0x10:
1625 cpu = CPU_CY486DX;
1626 break;
1627 case 0x20:
1628 if ((cyrix_did & 0x000f) < 8)
1629 cpu = CPU_M1;
1630 else
1631 cpu = CPU_M1SC;
1632 break;
1633 case 0x30:
1634 cpu = CPU_M1;
1635 break;
1636 case 0x40:
1637 /* MediaGX CPU */
1638 cpu = CPU_M1SC;
1639 break;
1640 default:
1641 /* M2 and later CPUs are treated as M2. */
1642 cpu = CPU_M2;
1643
1644 /*
1645 * enable cpuid instruction.
1646 */
1647 ccr3 = read_cyrix_reg(CCR3);
1648 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1649 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1650 write_cyrix_reg(CCR3, ccr3);
1651
1652 do_cpuid(0, regs);
1653 cpu_high = regs[0]; /* eax */
1654 do_cpuid(1, regs);
1655 cpu_id = regs[0]; /* eax */
1656 cpu_feature = regs[3]; /* edx */
1657 break;
1658 }
1659 }
1660 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1661 /*
1662 * There are BlueLightning CPUs that do not change
1663 * undefined flags by dividing 5 by 2. In this case,
1664 * the CPU identification routine in locore.s leaves
1665 * cpu_vendor null string and puts CPU_486 into the
1666 * cpu.
1667 */
1668 if (identblue() == IDENTBLUE_IBMCPU) {
1669 strcpy(cpu_vendor, "IBM");
1670 cpu_vendor_id = CPU_VENDOR_IBM;
1671 cpu = CPU_BLUE;
1672 return;
1673 }
1674 }
1675 #endif
1676 }
1677
1678 int
pti_get_default(void)1679 pti_get_default(void)
1680 {
1681
1682 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1683 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1684 return (0);
1685 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1686 return (0);
1687 return (1);
1688 }
1689
1690 static u_int
find_cpu_vendor_id(void)1691 find_cpu_vendor_id(void)
1692 {
1693 int i;
1694
1695 for (i = 0; i < nitems(cpu_vendors); i++)
1696 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1697 return (cpu_vendors[i].vendor_id);
1698 return (0);
1699 }
1700
1701 static void
print_AMD_assoc(int i)1702 print_AMD_assoc(int i)
1703 {
1704 if (i == 255)
1705 printf(", fully associative\n");
1706 else
1707 printf(", %d-way associative\n", i);
1708 }
1709
1710 static void
print_AMD_l2_assoc(int i)1711 print_AMD_l2_assoc(int i)
1712 {
1713 switch (i & 0x0f) {
1714 case 0: printf(", disabled/not present\n"); break;
1715 case 1: printf(", direct mapped\n"); break;
1716 case 2: printf(", 2-way associative\n"); break;
1717 case 4: printf(", 4-way associative\n"); break;
1718 case 6: printf(", 8-way associative\n"); break;
1719 case 8: printf(", 16-way associative\n"); break;
1720 case 15: printf(", fully associative\n"); break;
1721 default: printf(", reserved configuration\n"); break;
1722 }
1723 }
1724
1725 static void
print_AMD_info(void)1726 print_AMD_info(void)
1727 {
1728 #ifdef __i386__
1729 uint64_t amd_whcr;
1730 #endif
1731 u_int regs[4];
1732
1733 if (cpu_exthigh >= 0x80000005) {
1734 do_cpuid(0x80000005, regs);
1735 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1736 print_AMD_assoc(regs[0] >> 24);
1737
1738 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1739 print_AMD_assoc((regs[0] >> 8) & 0xff);
1740
1741 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1742 print_AMD_assoc(regs[1] >> 24);
1743
1744 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1745 print_AMD_assoc((regs[1] >> 8) & 0xff);
1746
1747 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1748 printf(", %d bytes/line", regs[2] & 0xff);
1749 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1750 print_AMD_assoc((regs[2] >> 16) & 0xff);
1751
1752 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1753 printf(", %d bytes/line", regs[3] & 0xff);
1754 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1755 print_AMD_assoc((regs[3] >> 16) & 0xff);
1756 }
1757
1758 if (cpu_exthigh >= 0x80000006) {
1759 do_cpuid(0x80000006, regs);
1760 if ((regs[0] >> 16) != 0) {
1761 printf("L2 2MB data TLB: %d entries",
1762 (regs[0] >> 16) & 0xfff);
1763 print_AMD_l2_assoc(regs[0] >> 28);
1764 printf("L2 2MB instruction TLB: %d entries",
1765 regs[0] & 0xfff);
1766 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1767 } else {
1768 printf("L2 2MB unified TLB: %d entries",
1769 regs[0] & 0xfff);
1770 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1771 }
1772 if ((regs[1] >> 16) != 0) {
1773 printf("L2 4KB data TLB: %d entries",
1774 (regs[1] >> 16) & 0xfff);
1775 print_AMD_l2_assoc(regs[1] >> 28);
1776
1777 printf("L2 4KB instruction TLB: %d entries",
1778 (regs[1] >> 16) & 0xfff);
1779 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1780 } else {
1781 printf("L2 4KB unified TLB: %d entries",
1782 (regs[1] >> 16) & 0xfff);
1783 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1784 }
1785 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1786 printf(", %d bytes/line", regs[2] & 0xff);
1787 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1788 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1789 }
1790
1791 #ifdef __i386__
1792 if (((cpu_id & 0xf00) == 0x500)
1793 && (((cpu_id & 0x0f0) > 0x80)
1794 || (((cpu_id & 0x0f0) == 0x80)
1795 && (cpu_id & 0x00f) > 0x07))) {
1796 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1797 amd_whcr = rdmsr(0xc0000082);
1798 if (!(amd_whcr & (0x3ff << 22))) {
1799 printf("Write Allocate Disable\n");
1800 } else {
1801 printf("Write Allocate Enable Limit: %dM bytes\n",
1802 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1803 printf("Write Allocate 15-16M bytes: %s\n",
1804 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1805 }
1806 } else if (((cpu_id & 0xf00) == 0x500)
1807 && ((cpu_id & 0x0f0) > 0x50)) {
1808 /* K6, K6-2(old core) */
1809 amd_whcr = rdmsr(0xc0000082);
1810 if (!(amd_whcr & (0x7f << 1))) {
1811 printf("Write Allocate Disable\n");
1812 } else {
1813 printf("Write Allocate Enable Limit: %dM bytes\n",
1814 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1815 printf("Write Allocate 15-16M bytes: %s\n",
1816 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1817 printf("Hardware Write Allocate Control: %s\n",
1818 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1819 }
1820 }
1821 #endif
1822 /*
1823 * Opteron Rev E shows a bug as in very rare occasions a read memory
1824 * barrier is not performed as expected if it is followed by a
1825 * non-atomic read-modify-write instruction.
1826 * As long as that bug pops up very rarely (intensive machine usage
1827 * on other operating systems generally generates one unexplainable
1828 * crash any 2 months) and as long as a model specific fix would be
1829 * impractical at this stage, print out a warning string if the broken
1830 * model and family are identified.
1831 */
1832 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1833 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1834 printf("WARNING: This architecture revision has known SMP "
1835 "hardware bugs which may cause random instability\n");
1836 }
1837
1838 static void
print_INTEL_info(void)1839 print_INTEL_info(void)
1840 {
1841 u_int regs[4];
1842 u_int rounds, regnum;
1843 u_int nwaycode, nway;
1844
1845 if (cpu_high >= 2) {
1846 rounds = 0;
1847 do {
1848 do_cpuid(0x2, regs);
1849 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1850 break; /* we have a buggy CPU */
1851
1852 for (regnum = 0; regnum <= 3; ++regnum) {
1853 if (regs[regnum] & (1<<31))
1854 continue;
1855 if (regnum != 0)
1856 print_INTEL_TLB(regs[regnum] & 0xff);
1857 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1858 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1859 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1860 }
1861 } while (--rounds > 0);
1862 }
1863
1864 if (cpu_exthigh >= 0x80000006) {
1865 do_cpuid(0x80000006, regs);
1866 nwaycode = (regs[2] >> 12) & 0x0f;
1867 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1868 nway = 1 << (nwaycode / 2);
1869 else
1870 nway = 0;
1871 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1872 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1873 }
1874 }
1875
1876 static void
print_INTEL_TLB(u_int data)1877 print_INTEL_TLB(u_int data)
1878 {
1879 switch (data) {
1880 case 0x0:
1881 case 0x40:
1882 default:
1883 break;
1884 case 0x1:
1885 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1886 break;
1887 case 0x2:
1888 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1889 break;
1890 case 0x3:
1891 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1892 break;
1893 case 0x4:
1894 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1895 break;
1896 case 0x6:
1897 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1898 break;
1899 case 0x8:
1900 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1901 break;
1902 case 0x9:
1903 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1904 break;
1905 case 0xa:
1906 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1907 break;
1908 case 0xb:
1909 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1910 break;
1911 case 0xc:
1912 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1913 break;
1914 case 0xd:
1915 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1916 break;
1917 case 0xe:
1918 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1919 break;
1920 case 0x1d:
1921 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1922 break;
1923 case 0x21:
1924 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1925 break;
1926 case 0x22:
1927 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1928 break;
1929 case 0x23:
1930 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1931 break;
1932 case 0x24:
1933 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1934 break;
1935 case 0x25:
1936 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1937 break;
1938 case 0x29:
1939 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1940 break;
1941 case 0x2c:
1942 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1943 break;
1944 case 0x30:
1945 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1946 break;
1947 case 0x39: /* De-listed in SDM rev. 54 */
1948 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1949 break;
1950 case 0x3b: /* De-listed in SDM rev. 54 */
1951 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1952 break;
1953 case 0x3c: /* De-listed in SDM rev. 54 */
1954 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1955 break;
1956 case 0x41:
1957 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1958 break;
1959 case 0x42:
1960 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1961 break;
1962 case 0x43:
1963 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1964 break;
1965 case 0x44:
1966 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1967 break;
1968 case 0x45:
1969 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1970 break;
1971 case 0x46:
1972 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1973 break;
1974 case 0x47:
1975 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1976 break;
1977 case 0x48:
1978 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1979 break;
1980 case 0x49:
1981 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1982 CPUID_TO_MODEL(cpu_id) == 0x6)
1983 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1984 else
1985 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1986 break;
1987 case 0x4a:
1988 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1989 break;
1990 case 0x4b:
1991 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1992 break;
1993 case 0x4c:
1994 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1995 break;
1996 case 0x4d:
1997 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1998 break;
1999 case 0x4e:
2000 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2001 break;
2002 case 0x4f:
2003 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2004 break;
2005 case 0x50:
2006 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2007 break;
2008 case 0x51:
2009 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2010 break;
2011 case 0x52:
2012 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2013 break;
2014 case 0x55:
2015 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2016 break;
2017 case 0x56:
2018 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2019 break;
2020 case 0x57:
2021 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2022 break;
2023 case 0x59:
2024 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2025 break;
2026 case 0x5a:
2027 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2028 break;
2029 case 0x5b:
2030 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2031 break;
2032 case 0x5c:
2033 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2034 break;
2035 case 0x5d:
2036 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2037 break;
2038 case 0x60:
2039 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2040 break;
2041 case 0x61:
2042 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2043 break;
2044 case 0x63:
2045 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2046 break;
2047 case 0x64:
2048 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2049 break;
2050 case 0x66:
2051 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2052 break;
2053 case 0x67:
2054 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2055 break;
2056 case 0x68:
2057 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2058 break;
2059 case 0x6a:
2060 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2061 break;
2062 case 0x6b:
2063 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2064 break;
2065 case 0x6c:
2066 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2067 break;
2068 case 0x6d:
2069 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2070 break;
2071 case 0x70:
2072 printf("Trace cache: 12K-uops, 8-way set associative\n");
2073 break;
2074 case 0x71:
2075 printf("Trace cache: 16K-uops, 8-way set associative\n");
2076 break;
2077 case 0x72:
2078 printf("Trace cache: 32K-uops, 8-way set associative\n");
2079 break;
2080 case 0x76:
2081 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2082 break;
2083 case 0x78:
2084 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2085 break;
2086 case 0x79:
2087 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2088 break;
2089 case 0x7a:
2090 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2091 break;
2092 case 0x7b:
2093 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2094 break;
2095 case 0x7c:
2096 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2097 break;
2098 case 0x7d:
2099 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2100 break;
2101 case 0x7f:
2102 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2103 break;
2104 case 0x80:
2105 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2106 break;
2107 case 0x82:
2108 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2109 break;
2110 case 0x83:
2111 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2112 break;
2113 case 0x84:
2114 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2115 break;
2116 case 0x85:
2117 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2118 break;
2119 case 0x86:
2120 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2121 break;
2122 case 0x87:
2123 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2124 break;
2125 case 0xa0:
2126 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2127 break;
2128 case 0xb0:
2129 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2130 break;
2131 case 0xb1:
2132 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2133 break;
2134 case 0xb2:
2135 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2136 break;
2137 case 0xb3:
2138 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2139 break;
2140 case 0xb4:
2141 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2142 break;
2143 case 0xb5:
2144 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2145 break;
2146 case 0xb6:
2147 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2148 break;
2149 case 0xba:
2150 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2151 break;
2152 case 0xc0:
2153 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2154 break;
2155 case 0xc1:
2156 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2157 break;
2158 case 0xc2:
2159 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2160 break;
2161 case 0xc3:
2162 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2163 break;
2164 case 0xc4:
2165 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2166 break;
2167 case 0xca:
2168 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2169 break;
2170 case 0xd0:
2171 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2172 break;
2173 case 0xd1:
2174 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2175 break;
2176 case 0xd2:
2177 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2178 break;
2179 case 0xd6:
2180 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2181 break;
2182 case 0xd7:
2183 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2184 break;
2185 case 0xd8:
2186 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2187 break;
2188 case 0xdc:
2189 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2190 break;
2191 case 0xdd:
2192 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2193 break;
2194 case 0xde:
2195 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2196 break;
2197 case 0xe2:
2198 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2199 break;
2200 case 0xe3:
2201 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2202 break;
2203 case 0xe4:
2204 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2205 break;
2206 case 0xea:
2207 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2208 break;
2209 case 0xeb:
2210 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2211 break;
2212 case 0xec:
2213 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2214 break;
2215 case 0xf0:
2216 printf("64-Byte prefetching\n");
2217 break;
2218 case 0xf1:
2219 printf("128-Byte prefetching\n");
2220 break;
2221 }
2222 }
2223
2224 static void
print_svm_info(void)2225 print_svm_info(void)
2226 {
2227 u_int features, regs[4];
2228 uint64_t msr;
2229 int comma;
2230
2231 printf("\n SVM: ");
2232 do_cpuid(0x8000000A, regs);
2233 features = regs[3];
2234
2235 msr = rdmsr(MSR_VM_CR);
2236 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2237 printf("(disabled in BIOS) ");
2238
2239 if (!bootverbose) {
2240 comma = 0;
2241 if (features & (1 << 0)) {
2242 printf("%sNP", comma ? "," : "");
2243 comma = 1;
2244 }
2245 if (features & (1 << 3)) {
2246 printf("%sNRIP", comma ? "," : "");
2247 comma = 1;
2248 }
2249 if (features & (1 << 5)) {
2250 printf("%sVClean", comma ? "," : "");
2251 comma = 1;
2252 }
2253 if (features & (1 << 6)) {
2254 printf("%sAFlush", comma ? "," : "");
2255 comma = 1;
2256 }
2257 if (features & (1 << 7)) {
2258 printf("%sDAssist", comma ? "," : "");
2259 comma = 1;
2260 }
2261 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2262 return;
2263 }
2264
2265 printf("Features=0x%b", features,
2266 "\020"
2267 "\001NP" /* Nested paging */
2268 "\002LbrVirt" /* LBR virtualization */
2269 "\003SVML" /* SVM lock */
2270 "\004NRIPS" /* NRIP save */
2271 "\005TscRateMsr" /* MSR based TSC rate control */
2272 "\006VmcbClean" /* VMCB clean bits */
2273 "\007FlushByAsid" /* Flush by ASID */
2274 "\010DecodeAssist" /* Decode assist */
2275 "\011<b8>"
2276 "\012<b9>"
2277 "\013PauseFilter" /* PAUSE intercept filter */
2278 "\014EncryptedMcodePatch"
2279 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2280 "\016AVIC" /* virtual interrupt controller */
2281 "\017<b14>"
2282 "\020V_VMSAVE_VMLOAD"
2283 "\021vGIF"
2284 "\022<b17>"
2285 "\023<b18>"
2286 "\024<b19>"
2287 "\025GuesSpecCtl" /* Guest Spec_ctl */
2288 "\026<b21>"
2289 "\027<b22>"
2290 "\030<b23>"
2291 "\031<b24>"
2292 "\032<b25>"
2293 "\033<b26>"
2294 "\034<b27>"
2295 "\035<b28>"
2296 "\036<b29>"
2297 "\037<b30>"
2298 "\040<b31>"
2299 );
2300 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2301 }
2302
2303 #ifdef __i386__
2304 static void
print_transmeta_info(void)2305 print_transmeta_info(void)
2306 {
2307 u_int regs[4], nreg = 0;
2308
2309 do_cpuid(0x80860000, regs);
2310 nreg = regs[0];
2311 if (nreg >= 0x80860001) {
2312 do_cpuid(0x80860001, regs);
2313 printf(" Processor revision %u.%u.%u.%u\n",
2314 (regs[1] >> 24) & 0xff,
2315 (regs[1] >> 16) & 0xff,
2316 (regs[1] >> 8) & 0xff,
2317 regs[1] & 0xff);
2318 }
2319 if (nreg >= 0x80860002) {
2320 do_cpuid(0x80860002, regs);
2321 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2322 (regs[1] >> 24) & 0xff,
2323 (regs[1] >> 16) & 0xff,
2324 (regs[1] >> 8) & 0xff,
2325 regs[1] & 0xff,
2326 regs[2]);
2327 }
2328 if (nreg >= 0x80860006) {
2329 char info[65];
2330 do_cpuid(0x80860003, (u_int*) &info[0]);
2331 do_cpuid(0x80860004, (u_int*) &info[16]);
2332 do_cpuid(0x80860005, (u_int*) &info[32]);
2333 do_cpuid(0x80860006, (u_int*) &info[48]);
2334 info[64] = 0;
2335 printf(" %s\n", info);
2336 }
2337 }
2338 #endif
2339
2340 static void
print_via_padlock_info(void)2341 print_via_padlock_info(void)
2342 {
2343 u_int regs[4];
2344
2345 do_cpuid(0xc0000001, regs);
2346 printf("\n VIA Padlock Features=0x%b", regs[3],
2347 "\020"
2348 "\003RNG" /* RNG */
2349 "\007AES" /* ACE */
2350 "\011AES-CTR" /* ACE2 */
2351 "\013SHA1,SHA256" /* PHE */
2352 "\015RSA" /* PMM */
2353 );
2354 }
2355
2356 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2357 vmx_settable(uint64_t basic, int msr, int true_msr)
2358 {
2359 uint64_t val;
2360
2361 if (basic & (1ULL << 55))
2362 val = rdmsr(true_msr);
2363 else
2364 val = rdmsr(msr);
2365
2366 /* Just report the controls that can be set to 1. */
2367 return (val >> 32);
2368 }
2369
2370 static void
print_vmx_info(void)2371 print_vmx_info(void)
2372 {
2373 uint64_t basic, msr;
2374 uint32_t entry, exit, mask, pin, proc, proc2;
2375 int comma;
2376
2377 printf("\n VT-x: ");
2378 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2379 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2380 printf("(disabled in BIOS) ");
2381 basic = rdmsr(MSR_VMX_BASIC);
2382 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2383 MSR_VMX_TRUE_PINBASED_CTLS);
2384 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2385 MSR_VMX_TRUE_PROCBASED_CTLS);
2386 if (proc & PROCBASED_SECONDARY_CONTROLS)
2387 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2388 MSR_VMX_PROCBASED_CTLS2);
2389 else
2390 proc2 = 0;
2391 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2392 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2393
2394 if (!bootverbose) {
2395 comma = 0;
2396 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2397 entry & VM_ENTRY_LOAD_PAT) {
2398 printf("%sPAT", comma ? "," : "");
2399 comma = 1;
2400 }
2401 if (proc & PROCBASED_HLT_EXITING) {
2402 printf("%sHLT", comma ? "," : "");
2403 comma = 1;
2404 }
2405 if (proc & PROCBASED_MTF) {
2406 printf("%sMTF", comma ? "," : "");
2407 comma = 1;
2408 }
2409 if (proc & PROCBASED_PAUSE_EXITING) {
2410 printf("%sPAUSE", comma ? "," : "");
2411 comma = 1;
2412 }
2413 if (proc2 & PROCBASED2_ENABLE_EPT) {
2414 printf("%sEPT", comma ? "," : "");
2415 comma = 1;
2416 }
2417 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2418 printf("%sUG", comma ? "," : "");
2419 comma = 1;
2420 }
2421 if (proc2 & PROCBASED2_ENABLE_VPID) {
2422 printf("%sVPID", comma ? "," : "");
2423 comma = 1;
2424 }
2425 if (proc & PROCBASED_USE_TPR_SHADOW &&
2426 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2427 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2428 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2429 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2430 printf("%sVID", comma ? "," : "");
2431 comma = 1;
2432 if (pin & PINBASED_POSTED_INTERRUPT)
2433 printf(",PostIntr");
2434 }
2435 return;
2436 }
2437
2438 mask = basic >> 32;
2439 printf("Basic Features=0x%b", mask,
2440 "\020"
2441 "\02132PA" /* 32-bit physical addresses */
2442 "\022SMM" /* SMM dual-monitor */
2443 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2444 "\030TRUE" /* TRUE_CTLS MSRs */
2445 );
2446 printf("\n Pin-Based Controls=0x%b", pin,
2447 "\020"
2448 "\001ExtINT" /* External-interrupt exiting */
2449 "\004NMI" /* NMI exiting */
2450 "\006VNMI" /* Virtual NMIs */
2451 "\007PreTmr" /* Activate VMX-preemption timer */
2452 "\010PostIntr" /* Process posted interrupts */
2453 );
2454 printf("\n Primary Processor Controls=0x%b", proc,
2455 "\020"
2456 "\003INTWIN" /* Interrupt-window exiting */
2457 "\004TSCOff" /* Use TSC offsetting */
2458 "\010HLT" /* HLT exiting */
2459 "\012INVLPG" /* INVLPG exiting */
2460 "\013MWAIT" /* MWAIT exiting */
2461 "\014RDPMC" /* RDPMC exiting */
2462 "\015RDTSC" /* RDTSC exiting */
2463 "\020CR3-LD" /* CR3-load exiting */
2464 "\021CR3-ST" /* CR3-store exiting */
2465 "\024CR8-LD" /* CR8-load exiting */
2466 "\025CR8-ST" /* CR8-store exiting */
2467 "\026TPR" /* Use TPR shadow */
2468 "\027NMIWIN" /* NMI-window exiting */
2469 "\030MOV-DR" /* MOV-DR exiting */
2470 "\031IO" /* Unconditional I/O exiting */
2471 "\032IOmap" /* Use I/O bitmaps */
2472 "\034MTF" /* Monitor trap flag */
2473 "\035MSRmap" /* Use MSR bitmaps */
2474 "\036MONITOR" /* MONITOR exiting */
2475 "\037PAUSE" /* PAUSE exiting */
2476 );
2477 if (proc & PROCBASED_SECONDARY_CONTROLS)
2478 printf("\n Secondary Processor Controls=0x%b", proc2,
2479 "\020"
2480 "\001APIC" /* Virtualize APIC accesses */
2481 "\002EPT" /* Enable EPT */
2482 "\003DT" /* Descriptor-table exiting */
2483 "\004RDTSCP" /* Enable RDTSCP */
2484 "\005x2APIC" /* Virtualize x2APIC mode */
2485 "\006VPID" /* Enable VPID */
2486 "\007WBINVD" /* WBINVD exiting */
2487 "\010UG" /* Unrestricted guest */
2488 "\011APIC-reg" /* APIC-register virtualization */
2489 "\012VID" /* Virtual-interrupt delivery */
2490 "\013PAUSE-loop" /* PAUSE-loop exiting */
2491 "\014RDRAND" /* RDRAND exiting */
2492 "\015INVPCID" /* Enable INVPCID */
2493 "\016VMFUNC" /* Enable VM functions */
2494 "\017VMCS" /* VMCS shadowing */
2495 "\020EPT#VE" /* EPT-violation #VE */
2496 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2497 );
2498 printf("\n Exit Controls=0x%b", mask,
2499 "\020"
2500 "\003DR" /* Save debug controls */
2501 /* Ignore Host address-space size */
2502 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2503 "\020AckInt" /* Acknowledge interrupt on exit */
2504 "\023PAT-SV" /* Save MSR_PAT */
2505 "\024PAT-LD" /* Load MSR_PAT */
2506 "\025EFER-SV" /* Save MSR_EFER */
2507 "\026EFER-LD" /* Load MSR_EFER */
2508 "\027PTMR-SV" /* Save VMX-preemption timer value */
2509 );
2510 printf("\n Entry Controls=0x%b", mask,
2511 "\020"
2512 "\003DR" /* Save debug controls */
2513 /* Ignore IA-32e mode guest */
2514 /* Ignore Entry to SMM */
2515 /* Ignore Deactivate dual-monitor treatment */
2516 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2517 "\017PAT" /* Load MSR_PAT */
2518 "\020EFER" /* Load MSR_EFER */
2519 );
2520 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2521 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2522 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2523 mask = msr;
2524 printf("\n EPT Features=0x%b", mask,
2525 "\020"
2526 "\001XO" /* Execute-only translations */
2527 "\007PW4" /* Page-walk length of 4 */
2528 "\011UC" /* EPT paging-structure mem can be UC */
2529 "\017WB" /* EPT paging-structure mem can be WB */
2530 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2531 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2532 "\025INVEPT" /* INVEPT is supported */
2533 "\026AD" /* Accessed and dirty flags for EPT */
2534 "\032single" /* INVEPT single-context type */
2535 "\033all" /* INVEPT all-context type */
2536 );
2537 mask = msr >> 32;
2538 printf("\n VPID Features=0x%b", mask,
2539 "\020"
2540 "\001INVVPID" /* INVVPID is supported */
2541 "\011individual" /* INVVPID individual-address type */
2542 "\012single" /* INVVPID single-context type */
2543 "\013all" /* INVVPID all-context type */
2544 /* INVVPID single-context-retaining-globals type */
2545 "\014single-globals"
2546 );
2547 }
2548 }
2549
2550 static void
print_hypervisor_info(void)2551 print_hypervisor_info(void)
2552 {
2553
2554 if (*hv_vendor)
2555 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2556 }
2557