1 /******************************************************************************* 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /*$FreeBSD: if_em_hw.h,v 1.13 2004/02/10 21:31:09 pdeuskar Exp $*/ 35 /* $OpenBSD: if_em_hw.h,v 1.5 2004/04/18 04:15:00 henric Exp $ */ 36 /* if_em_hw.h 37 * Structures, enums, and macros for the MAC 38 */ 39 40 #ifndef _EM_HW_H_ 41 #define _EM_HW_H_ 42 43 #define NO_VERSION_CONTROL 44 45 #include <dev/pci/if_em_osdep.h> 46 47 #ifndef NO_VERSION_CONTROL 48 #ident "@(#)$RCSfile: if_em_hw.h,v $$Revision: 1.5 $$Date: 2004/04/18 04:15:00 $" 49 #endif 50 51 /* Forward declarations of structures used by the shared code */ 52 struct em_hw; 53 struct em_hw_stats; 54 55 /* Enumerated types specific to the e1000 hardware */ 56 /* Media Access Controlers */ 57 typedef enum { 58 em_undefined = 0, 59 em_82542_rev2_0, 60 em_82542_rev2_1, 61 em_82543, 62 em_82544, 63 em_82540, 64 em_82545, 65 em_82545_rev_3, 66 em_82546, 67 em_82546_rev_3, 68 em_82541, 69 em_82541_rev_2, 70 em_82547, 71 em_82547_rev_2, 72 em_num_macs 73 } em_mac_type; 74 75 typedef enum { 76 em_eeprom_uninitialized = 0, 77 em_eeprom_spi, 78 em_eeprom_microwire, 79 em_num_eeprom_types 80 } em_eeprom_type; 81 82 /* Media Types */ 83 typedef enum { 84 em_media_type_copper = 0, 85 em_media_type_fiber = 1, 86 em_media_type_internal_serdes = 2, 87 em_num_media_types 88 } em_media_type; 89 90 typedef enum { 91 em_10_half = 0, 92 em_10_full = 1, 93 em_100_half = 2, 94 em_100_full = 3 95 } em_speed_duplex_type; 96 97 /* Flow Control Settings */ 98 typedef enum { 99 em_fc_none = 0, 100 em_fc_rx_pause = 1, 101 em_fc_tx_pause = 2, 102 em_fc_full = 3, 103 em_fc_default = 0xFF 104 } em_fc_type; 105 106 /* PCI bus types */ 107 typedef enum { 108 em_bus_type_unknown = 0, 109 em_bus_type_pci, 110 em_bus_type_pcix, 111 em_bus_type_reserved 112 } em_bus_type; 113 114 /* PCI bus speeds */ 115 typedef enum { 116 em_bus_speed_unknown = 0, 117 em_bus_speed_33, 118 em_bus_speed_66, 119 em_bus_speed_100, 120 em_bus_speed_120, 121 em_bus_speed_133, 122 em_bus_speed_reserved 123 } em_bus_speed; 124 125 /* PCI bus widths */ 126 typedef enum { 127 em_bus_width_unknown = 0, 128 em_bus_width_32, 129 em_bus_width_64, 130 em_bus_width_reserved 131 } em_bus_width; 132 133 /* PHY status info structure and supporting enums */ 134 typedef enum { 135 em_cable_length_50 = 0, 136 em_cable_length_50_80, 137 em_cable_length_80_110, 138 em_cable_length_110_140, 139 em_cable_length_140, 140 em_cable_length_undefined = 0xFF 141 } em_cable_length; 142 143 typedef enum { 144 em_igp_cable_length_10 = 10, 145 em_igp_cable_length_20 = 20, 146 em_igp_cable_length_30 = 30, 147 em_igp_cable_length_40 = 40, 148 em_igp_cable_length_50 = 50, 149 em_igp_cable_length_60 = 60, 150 em_igp_cable_length_70 = 70, 151 em_igp_cable_length_80 = 80, 152 em_igp_cable_length_90 = 90, 153 em_igp_cable_length_100 = 100, 154 em_igp_cable_length_110 = 110, 155 em_igp_cable_length_120 = 120, 156 em_igp_cable_length_130 = 130, 157 em_igp_cable_length_140 = 140, 158 em_igp_cable_length_150 = 150, 159 em_igp_cable_length_160 = 160, 160 em_igp_cable_length_170 = 170, 161 em_igp_cable_length_180 = 180 162 } em_igp_cable_length; 163 164 typedef enum { 165 em_10bt_ext_dist_enable_normal = 0, 166 em_10bt_ext_dist_enable_lower, 167 em_10bt_ext_dist_enable_undefined = 0xFF 168 } em_10bt_ext_dist_enable; 169 170 typedef enum { 171 em_rev_polarity_normal = 0, 172 em_rev_polarity_reversed, 173 em_rev_polarity_undefined = 0xFF 174 } em_rev_polarity; 175 176 typedef enum { 177 em_downshift_normal = 0, 178 em_downshift_activated, 179 em_downshift_undefined = 0xFF 180 } em_downshift; 181 182 typedef enum { 183 em_polarity_reversal_enabled = 0, 184 em_polarity_reversal_disabled, 185 em_polarity_reversal_undefined = 0xFF 186 } em_polarity_reversal; 187 188 typedef enum { 189 em_auto_x_mode_manual_mdi = 0, 190 em_auto_x_mode_manual_mdix, 191 em_auto_x_mode_auto1, 192 em_auto_x_mode_auto2, 193 em_auto_x_mode_undefined = 0xFF 194 } em_auto_x_mode; 195 196 typedef enum { 197 em_1000t_rx_status_not_ok = 0, 198 em_1000t_rx_status_ok, 199 em_1000t_rx_status_undefined = 0xFF 200 } em_1000t_rx_status; 201 202 typedef enum { 203 em_phy_m88 = 0, 204 em_phy_igp, 205 em_phy_undefined = 0xFF 206 } em_phy_type; 207 208 typedef enum { 209 em_ms_hw_default = 0, 210 em_ms_force_master, 211 em_ms_force_slave, 212 em_ms_auto 213 } em_ms_type; 214 215 typedef enum { 216 em_ffe_config_enabled = 0, 217 em_ffe_config_active, 218 em_ffe_config_blocked 219 } em_ffe_config; 220 221 typedef enum { 222 em_dsp_config_disabled = 0, 223 em_dsp_config_enabled, 224 em_dsp_config_activated, 225 em_dsp_config_undefined = 0xFF 226 } em_dsp_config; 227 228 struct em_phy_info { 229 em_cable_length cable_length; 230 em_10bt_ext_dist_enable extended_10bt_distance; 231 em_rev_polarity cable_polarity; 232 em_downshift downshift; 233 em_polarity_reversal polarity_correction; 234 em_auto_x_mode mdix_mode; 235 em_1000t_rx_status local_rx; 236 em_1000t_rx_status remote_rx; 237 }; 238 239 struct em_phy_stats { 240 uint32_t idle_errors; 241 uint32_t receive_errors; 242 }; 243 244 struct em_eeprom_info { 245 em_eeprom_type type; 246 uint16_t word_size; 247 uint16_t opcode_bits; 248 uint16_t address_bits; 249 uint16_t delay_usec; 250 uint16_t page_size; 251 }; 252 253 254 255 /* Error Codes */ 256 #define E1000_SUCCESS 0 257 #define E1000_ERR_EEPROM 1 258 #define E1000_ERR_PHY 2 259 #define E1000_ERR_CONFIG 3 260 #define E1000_ERR_PARAM 4 261 #define E1000_ERR_MAC_TYPE 5 262 #define E1000_ERR_PHY_TYPE 6 263 264 /* Function prototypes */ 265 /* Initialization */ 266 int32_t em_reset_hw(struct em_hw *hw); 267 int32_t em_init_hw(struct em_hw *hw); 268 int32_t em_set_mac_type(struct em_hw *hw); 269 void em_set_media_type(struct em_hw *hw); 270 271 /* Link Configuration */ 272 int32_t em_setup_link(struct em_hw *hw); 273 int32_t em_phy_setup_autoneg(struct em_hw *hw); 274 void em_config_collision_dist(struct em_hw *hw); 275 int32_t em_config_fc_after_link_up(struct em_hw *hw); 276 int32_t em_check_for_link(struct em_hw *hw); 277 int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex); 278 int32_t em_wait_autoneg(struct em_hw *hw); 279 int32_t em_force_mac_fc(struct em_hw *hw); 280 281 /* PHY */ 282 int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 283 int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data); 284 void em_phy_hw_reset(struct em_hw *hw); 285 int32_t em_phy_reset(struct em_hw *hw); 286 int32_t em_detect_gig_phy(struct em_hw *hw); 287 int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info); 288 int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info); 289 int32_t em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info); 290 int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length); 291 int32_t em_check_polarity(struct em_hw *hw, uint16_t *polarity); 292 int32_t em_check_downshift(struct em_hw *hw); 293 int32_t em_validate_mdi_setting(struct em_hw *hw); 294 295 /* EEPROM Functions */ 296 void em_init_eeprom_params(struct em_hw *hw); 297 int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 298 int32_t em_validate_eeprom_checksum(struct em_hw *hw); 299 int32_t em_update_eeprom_checksum(struct em_hw *hw); 300 int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 301 int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num); 302 int32_t em_read_mac_addr(struct em_hw * hw); 303 304 /* Filters (multicast, vlan, receive) */ 305 void em_init_rx_addrs(struct em_hw *hw); 306 void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count); 307 uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr); 308 void em_mta_set(struct em_hw *hw, uint32_t hash_value); 309 void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index); 310 void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value); 311 void em_clear_vfta(struct em_hw *hw); 312 313 /* LED functions */ 314 int32_t em_setup_led(struct em_hw *hw); 315 int32_t em_cleanup_led(struct em_hw *hw); 316 int32_t em_led_on(struct em_hw *hw); 317 int32_t em_led_off(struct em_hw *hw); 318 319 /* Adaptive IFS Functions */ 320 321 /* Everything else */ 322 void em_clear_hw_cntrs(struct em_hw *hw); 323 void em_reset_adaptive(struct em_hw *hw); 324 void em_update_adaptive(struct em_hw *hw); 325 void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr); 326 void em_get_bus_info(struct em_hw *hw); 327 void em_pci_set_mwi(struct em_hw *hw); 328 void em_pci_clear_mwi(struct em_hw *hw); 329 void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value); 330 void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value); 331 /* Port I/O is only supported on 82544 and newer */ 332 #ifdef __FreeBSD__ 333 uint32_t em_io_read(struct em_hw *hw, unsigned long port); 334 #endif /* __FreeBSD__ */ 335 uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset); 336 #ifdef __FreeBSD__ 337 void em_io_write(struct em_hw *hw, unsigned long port, uint32_t value); 338 #endif /* __FreeBSD__ */ 339 void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value); 340 int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up); 341 int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active); 342 343 #define E1000_READ_REG_IO(a, reg) \ 344 em_read_reg_io((a), E1000_##reg) 345 #define E1000_WRITE_REG_IO(a, reg, val) \ 346 em_write_reg_io((a), E1000_##reg, val) 347 348 /* PCI Device IDs */ 349 #define E1000_DEV_ID_82542 0x1000 350 #define E1000_DEV_ID_82543GC_FIBER 0x1001 351 #define E1000_DEV_ID_82543GC_COPPER 0x1004 352 #define E1000_DEV_ID_82544EI_COPPER 0x1008 353 #define E1000_DEV_ID_82544EI_FIBER 0x1009 354 #define E1000_DEV_ID_82544GC_COPPER 0x100C 355 #define E1000_DEV_ID_82544GC_LOM 0x100D 356 #define E1000_DEV_ID_82540EM 0x100E 357 #define E1000_DEV_ID_82540EM_LOM 0x1015 358 #define E1000_DEV_ID_82540EP_LOM 0x1016 359 #define E1000_DEV_ID_82540EP 0x1017 360 #define E1000_DEV_ID_82540EP_LP 0x101E 361 #define E1000_DEV_ID_82545EM_COPPER 0x100F 362 #define E1000_DEV_ID_82545EM_FIBER 0x1011 363 #define E1000_DEV_ID_82545GM_COPPER 0x1026 364 #define E1000_DEV_ID_82545GM_FIBER 0x1027 365 #define E1000_DEV_ID_82545GM_SERDES 0x1028 366 #define E1000_DEV_ID_82546EB_COPPER 0x1010 367 #define E1000_DEV_ID_82546EB_FIBER 0x1012 368 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 369 #define E1000_DEV_ID_82541EI 0x1013 370 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 371 #define E1000_DEV_ID_82541ER 0x1078 372 #define E1000_DEV_ID_82547GI 0x1075 373 #define E1000_DEV_ID_82541GI 0x1076 374 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 375 #define E1000_DEV_ID_82546GB_COPPER 0x1079 376 #define E1000_DEV_ID_82546GB_FIBER 0x107A 377 #define E1000_DEV_ID_82546GB_SERDES 0x107B 378 #define E1000_DEV_ID_82547EI 0x1019 379 380 #define NODE_ADDRESS_SIZE 6 381 #define ETH_LENGTH_OF_ADDRESS 6 382 383 /* MAC decode size is 128K - This is the size of BAR0 */ 384 #define MAC_DECODE_SIZE (128 * 1024) 385 386 #define E1000_82542_2_0_REV_ID 2 387 #define E1000_82542_2_1_REV_ID 3 388 389 #define SPEED_10 10 390 #define SPEED_100 100 391 #define SPEED_1000 1000 392 #define HALF_DUPLEX 1 393 #define FULL_DUPLEX 2 394 395 /* The sizes (in bytes) of an ethernet packet */ 396 #define ENET_HEADER_SIZE 14 397 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ 398 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 399 #define ETHERNET_FCS_SIZE 4 400 #define MAXIMUM_ETHERNET_PACKET_SIZE \ 401 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 402 #define MINIMUM_ETHERNET_PACKET_SIZE \ 403 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 404 #define CRC_LENGTH ETHERNET_FCS_SIZE 405 #define MAX_JUMBO_FRAME_SIZE 0x3F00 406 407 408 /* 802.1q VLAN Packet Sizes */ 409 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 410 411 /* Ethertype field values */ 412 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 413 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 414 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 415 416 /* Packet Header defines */ 417 #define IP_PROTOCOL_TCP 6 418 #define IP_PROTOCOL_UDP 0x11 419 420 /* This defines the bits that are set in the Interrupt Mask 421 * Set/Read Register. Each bit is documented below: 422 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 423 * o RXSEQ = Receive Sequence Error 424 */ 425 #define POLL_IMS_ENABLE_MASK ( \ 426 E1000_IMS_RXDMT0 | \ 427 E1000_IMS_RXSEQ) 428 429 /* This defines the bits that are set in the Interrupt Mask 430 * Set/Read Register. Each bit is documented below: 431 * o RXT0 = Receiver Timer Interrupt (ring 0) 432 * o TXDW = Transmit Descriptor Written Back 433 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 434 * o RXSEQ = Receive Sequence Error 435 * o LSC = Link Status Change 436 */ 437 #define IMS_ENABLE_MASK ( \ 438 E1000_IMS_RXT0 | \ 439 E1000_IMS_TXDW | \ 440 E1000_IMS_RXDMT0 | \ 441 E1000_IMS_RXSEQ | \ 442 E1000_IMS_LSC) 443 444 /* Number of high/low register pairs in the RAR. The RAR (Receive Address 445 * Registers) holds the directed and multicast addresses that we monitor. We 446 * reserve one of these spots for our directed address, allowing us room for 447 * E1000_RAR_ENTRIES - 1 multicast addresses. 448 */ 449 #define E1000_RAR_ENTRIES 15 450 451 #define MIN_NUMBER_OF_DESCRIPTORS 8 452 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 453 454 /* Receive Descriptor */ 455 struct em_rx_desc { 456 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 457 uint16_t length; /* Length of data DMAed into data buffer */ 458 uint16_t csum; /* Packet checksum */ 459 uint8_t status; /* Descriptor status */ 460 uint8_t errors; /* Descriptor Errors */ 461 uint16_t special; 462 }; 463 464 /* Receive Decriptor bit definitions */ 465 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 466 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 467 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 468 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 469 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 470 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 471 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 472 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 473 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 474 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 475 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 476 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 477 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 478 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 479 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 480 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 481 #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ 482 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 483 #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ 484 485 /* mask to determine if packets should be dropped due to frame errors */ 486 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 487 E1000_RXD_ERR_CE | \ 488 E1000_RXD_ERR_SE | \ 489 E1000_RXD_ERR_SEQ | \ 490 E1000_RXD_ERR_CXE | \ 491 E1000_RXD_ERR_RXE) 492 493 /* Transmit Descriptor */ 494 struct em_tx_desc { 495 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 496 union { 497 uint32_t data; 498 struct { 499 uint16_t length; /* Data buffer length */ 500 uint8_t cso; /* Checksum offset */ 501 uint8_t cmd; /* Descriptor control */ 502 } flags; 503 } lower; 504 union { 505 uint32_t data; 506 struct { 507 uint8_t status; /* Descriptor status */ 508 uint8_t css; /* Checksum start */ 509 uint16_t special; 510 } fields; 511 } upper; 512 }; 513 514 /* Transmit Descriptor bit definitions */ 515 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 516 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 517 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 518 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 519 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 520 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 521 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 522 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 523 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 524 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 525 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 526 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 527 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 528 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 529 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 530 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 531 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 532 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 533 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 534 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 535 536 /* Offload Context Descriptor */ 537 struct em_context_desc { 538 union { 539 uint32_t ip_config; 540 struct { 541 uint8_t ipcss; /* IP checksum start */ 542 uint8_t ipcso; /* IP checksum offset */ 543 uint16_t ipcse; /* IP checksum end */ 544 } ip_fields; 545 } lower_setup; 546 union { 547 uint32_t tcp_config; 548 struct { 549 uint8_t tucss; /* TCP checksum start */ 550 uint8_t tucso; /* TCP checksum offset */ 551 uint16_t tucse; /* TCP checksum end */ 552 } tcp_fields; 553 } upper_setup; 554 uint32_t cmd_and_length; /* */ 555 union { 556 uint32_t data; 557 struct { 558 uint8_t status; /* Descriptor status */ 559 uint8_t hdr_len; /* Header length */ 560 uint16_t mss; /* Maximum segment size */ 561 } fields; 562 } tcp_seg_setup; 563 }; 564 565 /* Offload data descriptor */ 566 struct em_data_desc { 567 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 568 union { 569 uint32_t data; 570 struct { 571 uint16_t length; /* Data buffer length */ 572 uint8_t typ_len_ext; /* */ 573 uint8_t cmd; /* */ 574 } flags; 575 } lower; 576 union { 577 uint32_t data; 578 struct { 579 uint8_t status; /* Descriptor status */ 580 uint8_t popts; /* Packet Options */ 581 uint16_t special; /* */ 582 } fields; 583 } upper; 584 }; 585 586 /* Filters */ 587 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 588 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 589 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 590 591 592 /* Receive Address Register */ 593 struct em_rar { 594 volatile uint32_t low; /* receive address low */ 595 volatile uint32_t high; /* receive address high */ 596 }; 597 598 /* Number of entries in the Multicast Table Array (MTA). */ 599 #define E1000_NUM_MTA_REGISTERS 128 600 601 /* IPv4 Address Table Entry */ 602 struct em_ipv4_at_entry { 603 volatile uint32_t ipv4_addr; /* IP Address (RW) */ 604 volatile uint32_t reserved; 605 }; 606 607 /* Four wakeup IP addresses are supported */ 608 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 609 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 610 #define E1000_IP6AT_SIZE 1 611 612 /* IPv6 Address Table Entry */ 613 struct em_ipv6_at_entry { 614 volatile uint8_t ipv6_addr[16]; 615 }; 616 617 /* Flexible Filter Length Table Entry */ 618 struct em_fflt_entry { 619 volatile uint32_t length; /* Flexible Filter Length (RW) */ 620 volatile uint32_t reserved; 621 }; 622 623 /* Flexible Filter Mask Table Entry */ 624 struct em_ffmt_entry { 625 volatile uint32_t mask; /* Flexible Filter Mask (RW) */ 626 volatile uint32_t reserved; 627 }; 628 629 /* Flexible Filter Value Table Entry */ 630 struct em_ffvt_entry { 631 volatile uint32_t value; /* Flexible Filter Value (RW) */ 632 volatile uint32_t reserved; 633 }; 634 635 /* Four Flexible Filters are supported */ 636 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 637 638 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 639 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 640 641 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 642 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 643 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 644 645 /* Register Set. (82543, 82544) 646 * 647 * Registers are defined to be 32 bits and should be accessed as 32 bit values. 648 * These registers are physically located on the NIC, but are mapped into the 649 * host memory address space. 650 * 651 * RW - register is both readable and writable 652 * RO - register is read only 653 * WO - register is write only 654 * R/clr - register is read only and is cleared when read 655 * A - register array 656 */ 657 #define E1000_CTRL 0x00000 /* Device Control - RW */ 658 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 659 #define E1000_STATUS 0x00008 /* Device Status - RO */ 660 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 661 #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 662 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 663 #define E1000_FLA 0x0001C /* Flash Access - RW */ 664 #define E1000_MDIC 0x00020 /* MDI Control - RW */ 665 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 666 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 667 #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 668 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 669 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 670 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 671 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 672 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 673 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 674 #define E1000_RCTL 0x00100 /* RX Control - RW */ 675 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 676 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 677 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 678 #define E1000_TCTL 0x00400 /* TX Control - RW */ 679 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 680 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 681 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 682 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 683 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 684 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 685 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 686 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 687 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 688 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 689 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 690 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 691 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 692 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 693 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 694 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 695 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 696 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 697 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 698 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 699 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 700 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 701 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 702 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 703 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 704 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 705 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 706 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 707 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 708 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 709 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 710 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 711 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 712 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 713 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 714 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 715 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 716 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 717 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 718 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 719 #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 720 #define E1000_DC 0x04030 /* Defer Count - R/clr */ 721 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 722 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 723 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 724 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 725 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 726 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 727 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 728 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 729 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 730 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 731 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 732 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 733 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 734 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 735 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 736 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 737 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 738 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 739 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 740 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 741 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 742 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 743 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 744 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 745 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 746 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 747 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 748 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 749 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 750 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 751 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 752 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 753 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 754 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 755 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 756 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 757 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 758 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 759 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 760 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 761 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 762 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 763 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 764 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 765 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 766 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 767 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 768 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 769 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 770 #define E1000_RA 0x05400 /* Receive Address - RW Array */ 771 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 772 #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 773 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 774 #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 775 #define E1000_MANC 0x05820 /* Management Control - RW */ 776 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 777 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 778 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 779 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 780 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 781 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 782 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 783 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 784 785 /* Register Set (82542) 786 * 787 * Some of the 82542 registers are located at different offsets than they are 788 * in more current versions of the 8254x. Despite the difference in location, 789 * the registers function in the same manner. 790 */ 791 #define E1000_82542_CTRL E1000_CTRL 792 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP 793 #define E1000_82542_STATUS E1000_STATUS 794 #define E1000_82542_EECD E1000_EECD 795 #define E1000_82542_EERD E1000_EERD 796 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT 797 #define E1000_82542_FLA E1000_FLA 798 #define E1000_82542_MDIC E1000_MDIC 799 #define E1000_82542_FCAL E1000_FCAL 800 #define E1000_82542_FCAH E1000_FCAH 801 #define E1000_82542_FCT E1000_FCT 802 #define E1000_82542_VET E1000_VET 803 #define E1000_82542_RA 0x00040 804 #define E1000_82542_ICR E1000_ICR 805 #define E1000_82542_ITR E1000_ITR 806 #define E1000_82542_ICS E1000_ICS 807 #define E1000_82542_IMS E1000_IMS 808 #define E1000_82542_IMC E1000_IMC 809 #define E1000_82542_RCTL E1000_RCTL 810 #define E1000_82542_RDTR 0x00108 811 #define E1000_82542_RDBAL 0x00110 812 #define E1000_82542_RDBAH 0x00114 813 #define E1000_82542_RDLEN 0x00118 814 #define E1000_82542_RDH 0x00120 815 #define E1000_82542_RDT 0x00128 816 #define E1000_82542_FCRTH 0x00160 817 #define E1000_82542_FCRTL 0x00168 818 #define E1000_82542_FCTTV E1000_FCTTV 819 #define E1000_82542_TXCW E1000_TXCW 820 #define E1000_82542_RXCW E1000_RXCW 821 #define E1000_82542_MTA 0x00200 822 #define E1000_82542_TCTL E1000_TCTL 823 #define E1000_82542_TIPG E1000_TIPG 824 #define E1000_82542_TDBAL 0x00420 825 #define E1000_82542_TDBAH 0x00424 826 #define E1000_82542_TDLEN 0x00428 827 #define E1000_82542_TDH 0x00430 828 #define E1000_82542_TDT 0x00438 829 #define E1000_82542_TIDV 0x00440 830 #define E1000_82542_TBT E1000_TBT 831 #define E1000_82542_AIT E1000_AIT 832 #define E1000_82542_VFTA 0x00600 833 #define E1000_82542_LEDCTL E1000_LEDCTL 834 #define E1000_82542_PBA E1000_PBA 835 #define E1000_82542_RXDCTL E1000_RXDCTL 836 #define E1000_82542_RADV E1000_RADV 837 #define E1000_82542_RSRPD E1000_RSRPD 838 #define E1000_82542_TXDMAC E1000_TXDMAC 839 #define E1000_82542_TDFHS E1000_TDFHS 840 #define E1000_82542_TDFTS E1000_TDFTS 841 #define E1000_82542_TDFPC E1000_TDFPC 842 #define E1000_82542_TXDCTL E1000_TXDCTL 843 #define E1000_82542_TADV E1000_TADV 844 #define E1000_82542_TSPMT E1000_TSPMT 845 #define E1000_82542_CRCERRS E1000_CRCERRS 846 #define E1000_82542_ALGNERRC E1000_ALGNERRC 847 #define E1000_82542_SYMERRS E1000_SYMERRS 848 #define E1000_82542_RXERRC E1000_RXERRC 849 #define E1000_82542_MPC E1000_MPC 850 #define E1000_82542_SCC E1000_SCC 851 #define E1000_82542_ECOL E1000_ECOL 852 #define E1000_82542_MCC E1000_MCC 853 #define E1000_82542_LATECOL E1000_LATECOL 854 #define E1000_82542_COLC E1000_COLC 855 #define E1000_82542_DC E1000_DC 856 #define E1000_82542_TNCRS E1000_TNCRS 857 #define E1000_82542_SEC E1000_SEC 858 #define E1000_82542_CEXTERR E1000_CEXTERR 859 #define E1000_82542_RLEC E1000_RLEC 860 #define E1000_82542_XONRXC E1000_XONRXC 861 #define E1000_82542_XONTXC E1000_XONTXC 862 #define E1000_82542_XOFFRXC E1000_XOFFRXC 863 #define E1000_82542_XOFFTXC E1000_XOFFTXC 864 #define E1000_82542_FCRUC E1000_FCRUC 865 #define E1000_82542_PRC64 E1000_PRC64 866 #define E1000_82542_PRC127 E1000_PRC127 867 #define E1000_82542_PRC255 E1000_PRC255 868 #define E1000_82542_PRC511 E1000_PRC511 869 #define E1000_82542_PRC1023 E1000_PRC1023 870 #define E1000_82542_PRC1522 E1000_PRC1522 871 #define E1000_82542_GPRC E1000_GPRC 872 #define E1000_82542_BPRC E1000_BPRC 873 #define E1000_82542_MPRC E1000_MPRC 874 #define E1000_82542_GPTC E1000_GPTC 875 #define E1000_82542_GORCL E1000_GORCL 876 #define E1000_82542_GORCH E1000_GORCH 877 #define E1000_82542_GOTCL E1000_GOTCL 878 #define E1000_82542_GOTCH E1000_GOTCH 879 #define E1000_82542_RNBC E1000_RNBC 880 #define E1000_82542_RUC E1000_RUC 881 #define E1000_82542_RFC E1000_RFC 882 #define E1000_82542_ROC E1000_ROC 883 #define E1000_82542_RJC E1000_RJC 884 #define E1000_82542_MGTPRC E1000_MGTPRC 885 #define E1000_82542_MGTPDC E1000_MGTPDC 886 #define E1000_82542_MGTPTC E1000_MGTPTC 887 #define E1000_82542_TORL E1000_TORL 888 #define E1000_82542_TORH E1000_TORH 889 #define E1000_82542_TOTL E1000_TOTL 890 #define E1000_82542_TOTH E1000_TOTH 891 #define E1000_82542_TPR E1000_TPR 892 #define E1000_82542_TPT E1000_TPT 893 #define E1000_82542_PTC64 E1000_PTC64 894 #define E1000_82542_PTC127 E1000_PTC127 895 #define E1000_82542_PTC255 E1000_PTC255 896 #define E1000_82542_PTC511 E1000_PTC511 897 #define E1000_82542_PTC1023 E1000_PTC1023 898 #define E1000_82542_PTC1522 E1000_PTC1522 899 #define E1000_82542_MPTC E1000_MPTC 900 #define E1000_82542_BPTC E1000_BPTC 901 #define E1000_82542_TSCTC E1000_TSCTC 902 #define E1000_82542_TSCTFC E1000_TSCTFC 903 #define E1000_82542_RXCSUM E1000_RXCSUM 904 #define E1000_82542_WUC E1000_WUC 905 #define E1000_82542_WUFC E1000_WUFC 906 #define E1000_82542_WUS E1000_WUS 907 #define E1000_82542_MANC E1000_MANC 908 #define E1000_82542_IPAV E1000_IPAV 909 #define E1000_82542_IP4AT E1000_IP4AT 910 #define E1000_82542_IP6AT E1000_IP6AT 911 #define E1000_82542_WUPL E1000_WUPL 912 #define E1000_82542_WUPM E1000_WUPM 913 #define E1000_82542_FFLT E1000_FFLT 914 #define E1000_82542_TDFH 0x08010 915 #define E1000_82542_TDFT 0x08018 916 #define E1000_82542_FFMT E1000_FFMT 917 #define E1000_82542_FFVT E1000_FFVT 918 919 /* Statistics counters collected by the MAC */ 920 struct em_hw_stats { 921 uint64_t crcerrs; 922 uint64_t algnerrc; 923 uint64_t symerrs; 924 uint64_t rxerrc; 925 uint64_t mpc; 926 uint64_t scc; 927 uint64_t ecol; 928 uint64_t mcc; 929 uint64_t latecol; 930 uint64_t colc; 931 uint64_t dc; 932 uint64_t tncrs; 933 uint64_t sec; 934 uint64_t cexterr; 935 uint64_t rlec; 936 uint64_t xonrxc; 937 uint64_t xontxc; 938 uint64_t xoffrxc; 939 uint64_t xofftxc; 940 uint64_t fcruc; 941 uint64_t prc64; 942 uint64_t prc127; 943 uint64_t prc255; 944 uint64_t prc511; 945 uint64_t prc1023; 946 uint64_t prc1522; 947 uint64_t gprc; 948 uint64_t bprc; 949 uint64_t mprc; 950 uint64_t gptc; 951 uint64_t gorcl; 952 uint64_t gorch; 953 uint64_t gotcl; 954 uint64_t gotch; 955 uint64_t rnbc; 956 uint64_t ruc; 957 uint64_t rfc; 958 uint64_t roc; 959 uint64_t rjc; 960 uint64_t mgprc; 961 uint64_t mgpdc; 962 uint64_t mgptc; 963 uint64_t torl; 964 uint64_t torh; 965 uint64_t totl; 966 uint64_t toth; 967 uint64_t tpr; 968 uint64_t tpt; 969 uint64_t ptc64; 970 uint64_t ptc127; 971 uint64_t ptc255; 972 uint64_t ptc511; 973 uint64_t ptc1023; 974 uint64_t ptc1522; 975 uint64_t mptc; 976 uint64_t bptc; 977 uint64_t tsctc; 978 uint64_t tsctfc; 979 }; 980 981 /* Structure containing variables used by the shared code (em_hw.c) */ 982 struct em_hw { 983 uint8_t *hw_addr; 984 em_mac_type mac_type; 985 em_phy_type phy_type; 986 uint32_t phy_init_script; 987 em_media_type media_type; 988 void *back; 989 em_fc_type fc; 990 em_bus_speed bus_speed; 991 em_bus_width bus_width; 992 em_bus_type bus_type; 993 struct em_eeprom_info eeprom; 994 em_ms_type master_slave; 995 em_ms_type original_master_slave; 996 em_ffe_config ffe_config_state; 997 unsigned long io_base; 998 uint32_t phy_id; 999 uint32_t phy_revision; 1000 uint32_t phy_addr; 1001 uint32_t original_fc; 1002 uint32_t txcw; 1003 uint32_t autoneg_failed; 1004 uint32_t max_frame_size; 1005 uint32_t min_frame_size; 1006 uint32_t mc_filter_type; 1007 uint32_t num_mc_addrs; 1008 uint32_t collision_delta; 1009 uint32_t tx_packet_delta; 1010 uint32_t ledctl_default; 1011 uint32_t ledctl_mode1; 1012 uint32_t ledctl_mode2; 1013 uint16_t phy_spd_default; 1014 uint16_t autoneg_advertised; 1015 uint16_t pci_cmd_word; 1016 uint16_t fc_high_water; 1017 uint16_t fc_low_water; 1018 uint16_t fc_pause_time; 1019 uint16_t current_ifs_val; 1020 uint16_t ifs_min_val; 1021 uint16_t ifs_max_val; 1022 uint16_t ifs_step_size; 1023 uint16_t ifs_ratio; 1024 uint16_t device_id; 1025 uint16_t vendor_id; 1026 uint16_t subsystem_id; 1027 uint16_t subsystem_vendor_id; 1028 uint8_t revision_id; 1029 uint8_t autoneg; 1030 uint8_t mdix; 1031 uint8_t forced_speed_duplex; 1032 uint8_t wait_autoneg_complete; 1033 uint8_t dma_fairness; 1034 uint8_t mac_addr[NODE_ADDRESS_SIZE]; 1035 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; 1036 boolean_t disable_polarity_correction; 1037 boolean_t speed_downgraded; 1038 em_dsp_config dsp_config_state; 1039 boolean_t get_link_status; 1040 boolean_t serdes_link_down; 1041 boolean_t tbi_compatibility_en; 1042 boolean_t tbi_compatibility_on; 1043 boolean_t phy_reset_disable; 1044 boolean_t fc_send_xon; 1045 boolean_t fc_strict_ieee; 1046 boolean_t report_tx_early; 1047 boolean_t adaptive_ifs; 1048 boolean_t ifs_params_forced; 1049 boolean_t in_ifs_mode; 1050 }; 1051 1052 1053 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1054 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1055 1056 /* Register Bit Masks */ 1057 /* Device Control */ 1058 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1059 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1060 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1061 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1062 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1063 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1064 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 1065 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 1066 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 1067 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 1068 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 1069 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 1070 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 1071 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1072 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1073 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1074 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1075 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1076 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1077 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 1078 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 1079 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 1080 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 1081 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 1082 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 1083 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 1084 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 1085 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1086 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1087 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1088 1089 /* Device Status */ 1090 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1091 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1092 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1093 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1094 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1095 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1096 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 1097 #define E1000_STATUS_SPEED_MASK 0x000000C0 1098 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1099 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1100 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1101 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1102 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1103 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1104 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1105 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 1106 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 1107 1108 /* Constants used to intrepret the masked PCI-X bus speed. */ 1109 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 1110 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 1111 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 1112 1113 /* EEPROM/Flash Control */ 1114 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 1115 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 1116 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 1117 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 1118 #define E1000_EECD_FWE_MASK 0x00000030 1119 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1120 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1121 #define E1000_EECD_FWE_SHIFT 4 1122 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 1123 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 1124 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1125 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 1126 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1127 * (0-small, 1-large) */ 1128 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1129 #ifndef E1000_EEPROM_GRANT_ATTEMPTS 1130 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1131 #endif 1132 1133 /* EEPROM Read */ 1134 #define E1000_EERD_START 0x00000001 /* Start Read */ 1135 #define E1000_EERD_DONE 0x00000010 /* Read Done */ 1136 #define E1000_EERD_ADDR_SHIFT 8 1137 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 1138 #define E1000_EERD_DATA_SHIFT 16 1139 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 1140 1141 /* SPI EEPROM Status Register */ 1142 #define EEPROM_STATUS_RDY_SPI 0x01 1143 #define EEPROM_STATUS_WEN_SPI 0x02 1144 #define EEPROM_STATUS_BP0_SPI 0x04 1145 #define EEPROM_STATUS_BP1_SPI 0x08 1146 #define EEPROM_STATUS_WPEN_SPI 0x80 1147 1148 /* Extended Device Control */ 1149 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 1150 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 1151 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 1152 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 1153 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1154 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 1155 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 1156 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 1157 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 1158 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 1159 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 1160 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 1161 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 1162 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 1163 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 1164 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 1165 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 1166 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1167 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 1168 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 1169 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 1170 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 1171 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 1172 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1173 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1174 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1175 1176 /* MDI Control */ 1177 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1178 #define E1000_MDIC_REG_MASK 0x001F0000 1179 #define E1000_MDIC_REG_SHIFT 16 1180 #define E1000_MDIC_PHY_MASK 0x03E00000 1181 #define E1000_MDIC_PHY_SHIFT 21 1182 #define E1000_MDIC_OP_WRITE 0x04000000 1183 #define E1000_MDIC_OP_READ 0x08000000 1184 #define E1000_MDIC_READY 0x10000000 1185 #define E1000_MDIC_INT_EN 0x20000000 1186 #define E1000_MDIC_ERROR 0x40000000 1187 1188 /* LED Control */ 1189 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1190 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 1191 #define E1000_LEDCTL_LED0_IVRT 0x00000040 1192 #define E1000_LEDCTL_LED0_BLINK 0x00000080 1193 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 1194 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 1195 #define E1000_LEDCTL_LED1_IVRT 0x00004000 1196 #define E1000_LEDCTL_LED1_BLINK 0x00008000 1197 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 1198 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 1199 #define E1000_LEDCTL_LED2_IVRT 0x00400000 1200 #define E1000_LEDCTL_LED2_BLINK 0x00800000 1201 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 1202 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 1203 #define E1000_LEDCTL_LED3_IVRT 0x40000000 1204 #define E1000_LEDCTL_LED3_BLINK 0x80000000 1205 1206 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 1207 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 1208 #define E1000_LEDCTL_MODE_LINK_UP 0x2 1209 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 1210 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 1211 #define E1000_LEDCTL_MODE_LINK_10 0x5 1212 #define E1000_LEDCTL_MODE_LINK_100 0x6 1213 #define E1000_LEDCTL_MODE_LINK_1000 0x7 1214 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 1215 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 1216 #define E1000_LEDCTL_MODE_COLLISION 0xA 1217 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 1218 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 1219 #define E1000_LEDCTL_MODE_PAUSED 0xD 1220 #define E1000_LEDCTL_MODE_LED_ON 0xE 1221 #define E1000_LEDCTL_MODE_LED_OFF 0xF 1222 1223 /* Receive Address */ 1224 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1225 1226 /* Interrupt Cause Read */ 1227 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1228 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1229 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1230 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1231 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1232 #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1233 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1234 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1235 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1236 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1237 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1238 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1239 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1240 #define E1000_ICR_TXD_LOW 0x00008000 1241 #define E1000_ICR_SRPD 0x00010000 1242 1243 /* Interrupt Cause Set */ 1244 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1245 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1246 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1247 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1248 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1249 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1250 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1251 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1252 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1253 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1254 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1255 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1256 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1257 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1258 #define E1000_ICS_SRPD E1000_ICR_SRPD 1259 1260 /* Interrupt Mask Set */ 1261 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1262 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1263 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1264 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1265 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1266 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1267 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1268 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1269 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1270 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1271 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1272 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1273 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1274 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1275 #define E1000_IMS_SRPD E1000_ICR_SRPD 1276 1277 /* Interrupt Mask Clear */ 1278 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1279 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1280 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1281 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1282 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1283 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1284 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1285 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1286 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1287 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1288 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1289 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1290 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1291 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1292 #define E1000_IMC_SRPD E1000_ICR_SRPD 1293 1294 /* Receive Control */ 1295 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 1296 #define E1000_RCTL_EN 0x00000002 /* enable */ 1297 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1298 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1299 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1300 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1301 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1302 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1303 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1304 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1305 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1306 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1307 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1308 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1309 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1310 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1311 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1312 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1313 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1314 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1315 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1316 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1317 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1318 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1319 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1320 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1321 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1322 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1323 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1324 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1325 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1326 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1327 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1328 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1329 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1330 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1331 1332 /* Receive Descriptor */ 1333 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1334 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 1335 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 1336 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 1337 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 1338 1339 /* Flow Control */ 1340 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1341 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1342 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1343 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1344 1345 /* Receive Descriptor Control */ 1346 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1347 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1348 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 1349 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1350 1351 /* Transmit Descriptor Control */ 1352 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */ 1353 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */ 1354 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */ 1355 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1356 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1357 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1358 1359 /* Transmit Configuration Word */ 1360 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1361 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1362 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1363 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1364 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1365 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1366 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1367 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1368 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1369 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1370 1371 /* Receive Configuration Word */ 1372 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1373 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1374 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1375 #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1376 #define E1000_RXCW_C 0x20000000 /* Receive config */ 1377 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1378 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1379 1380 /* Transmit Control */ 1381 #define E1000_TCTL_RST 0x00000001 /* software reset */ 1382 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 1383 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 1384 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 1385 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 1386 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 1387 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 1388 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1389 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1390 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1391 1392 /* Receive Checksum Control */ 1393 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1394 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1395 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1396 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1397 1398 /* Definitions for power management and wakeup registers */ 1399 /* Wake Up Control */ 1400 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 1401 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 1402 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 1403 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 1404 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 1405 1406 /* Wake Up Filter Control */ 1407 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 1408 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 1409 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 1410 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 1411 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 1412 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1413 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1414 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1415 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 1416 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 1417 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 1418 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 1419 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 1420 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 1421 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1422 1423 /* Wake Up Status */ 1424 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 1425 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 1426 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 1427 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 1428 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 1429 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 1430 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 1431 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 1432 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 1433 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 1434 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 1435 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 1436 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1437 1438 /* Management Control */ 1439 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 1440 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 1441 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 1442 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 1443 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 1444 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 1445 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 1446 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 1447 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 1448 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 1449 * Filtering */ 1450 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 1451 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 1452 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 1453 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 1454 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 1455 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 1456 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 1457 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 1458 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 1459 1460 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 1461 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 1462 1463 /* Wake Up Packet Length */ 1464 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 1465 1466 #define E1000_MDALIGN 4096 1467 1468 /* EEPROM Commands - Microwire */ 1469 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 1470 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 1471 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 1472 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 1473 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 1474 1475 /* EEPROM Commands - SPI */ 1476 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1477 #define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */ 1478 #define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */ 1479 #define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */ 1480 #define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */ 1481 #define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */ 1482 #define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */ 1483 #define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */ 1484 1485 /* EEPROM Size definitions */ 1486 #define EEPROM_SIZE_16KB 0x1800 1487 #define EEPROM_SIZE_8KB 0x1400 1488 #define EEPROM_SIZE_4KB 0x1000 1489 #define EEPROM_SIZE_2KB 0x0C00 1490 #define EEPROM_SIZE_1KB 0x0800 1491 #define EEPROM_SIZE_512B 0x0400 1492 #define EEPROM_SIZE_128B 0x0000 1493 #define EEPROM_SIZE_MASK 0x1C00 1494 1495 /* EEPROM Word Offsets */ 1496 #define EEPROM_COMPAT 0x0003 1497 #define EEPROM_ID_LED_SETTINGS 0x0004 1498 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 1499 #define EEPROM_INIT_CONTROL1_REG 0x000A 1500 #define EEPROM_INIT_CONTROL2_REG 0x000F 1501 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 1502 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 1503 #define EEPROM_CFG 0x0012 1504 #define EEPROM_FLASH_VERSION 0x0032 1505 #define EEPROM_CHECKSUM_REG 0x003F 1506 1507 /* Word definitions for ID LED Settings */ 1508 #define ID_LED_RESERVED_0000 0x0000 1509 #define ID_LED_RESERVED_FFFF 0xFFFF 1510 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1511 (ID_LED_OFF1_OFF2 << 8) | \ 1512 (ID_LED_DEF1_DEF2 << 4) | \ 1513 (ID_LED_DEF1_DEF2)) 1514 #define ID_LED_DEF1_DEF2 0x1 1515 #define ID_LED_DEF1_ON2 0x2 1516 #define ID_LED_DEF1_OFF2 0x3 1517 #define ID_LED_ON1_DEF2 0x4 1518 #define ID_LED_ON1_ON2 0x5 1519 #define ID_LED_ON1_OFF2 0x6 1520 #define ID_LED_OFF1_DEF2 0x7 1521 #define ID_LED_OFF1_ON2 0x8 1522 #define ID_LED_OFF1_OFF2 0x9 1523 1524 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1525 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1526 #define IGP_LED3_MODE 0x07000000 1527 1528 1529 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ 1530 #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F 1531 1532 /* Mask bits for fields in Word 0x0a of the EEPROM */ 1533 #define EEPROM_WORD0A_ILOS 0x0010 1534 #define EEPROM_WORD0A_SWDPIO 0x01E0 1535 #define EEPROM_WORD0A_LRST 0x0200 1536 #define EEPROM_WORD0A_FD 0x0400 1537 #define EEPROM_WORD0A_66MHZ 0x0800 1538 1539 /* Mask bits for fields in Word 0x0f of the EEPROM */ 1540 #define EEPROM_WORD0F_PAUSE_MASK 0x3000 1541 #define EEPROM_WORD0F_PAUSE 0x1000 1542 #define EEPROM_WORD0F_ASM_DIR 0x2000 1543 #define EEPROM_WORD0F_ANE 0x0800 1544 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 1545 1546 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 1547 #define EEPROM_SUM 0xBABA 1548 1549 /* EEPROM Map defines (WORD OFFSETS)*/ 1550 #define EEPROM_NODE_ADDRESS_BYTE_0 0 1551 #define EEPROM_PBA_BYTE_1 8 1552 1553 #define EEPROM_RESERVED_WORD 0xFFFF 1554 1555 /* EEPROM Map Sizes (Byte Counts) */ 1556 #define PBA_SIZE 4 1557 1558 /* Collision related configuration parameters */ 1559 #define E1000_COLLISION_THRESHOLD 16 1560 #define E1000_CT_SHIFT 4 1561 #define E1000_COLLISION_DISTANCE 64 1562 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 1563 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 1564 #define E1000_COLD_SHIFT 12 1565 1566 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 1567 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 1568 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 1569 1570 /* Default values for the transmit IPG register */ 1571 #define DEFAULT_82542_TIPG_IPGT 10 1572 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 1573 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 1574 1575 #define E1000_TIPG_IPGT_MASK 0x000003FF 1576 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 1577 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 1578 1579 #define DEFAULT_82542_TIPG_IPGR1 2 1580 #define DEFAULT_82543_TIPG_IPGR1 8 1581 #define E1000_TIPG_IPGR1_SHIFT 10 1582 1583 #define DEFAULT_82542_TIPG_IPGR2 10 1584 #define DEFAULT_82543_TIPG_IPGR2 6 1585 #define E1000_TIPG_IPGR2_SHIFT 20 1586 1587 #define E1000_TXDMAC_DPP 0x00000001 1588 1589 /* Adaptive IFS defines */ 1590 #define TX_THRESHOLD_START 8 1591 #define TX_THRESHOLD_INCREMENT 10 1592 #define TX_THRESHOLD_DECREMENT 1 1593 #define TX_THRESHOLD_STOP 190 1594 #define TX_THRESHOLD_DISABLE 0 1595 #define TX_THRESHOLD_TIMER_MS 10000 1596 #define MIN_NUM_XMITS 1000 1597 #define IFS_MAX 80 1598 #define IFS_STEP 10 1599 #define IFS_MIN 40 1600 #define IFS_RATIO 4 1601 1602 /* PBA constants */ 1603 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 1604 #define E1000_PBA_22K 0x0016 1605 #define E1000_PBA_24K 0x0018 1606 #define E1000_PBA_30K 0x001E 1607 #define E1000_PBA_40K 0x0028 1608 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 1609 1610 /* Flow Control Constants */ 1611 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 1612 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 1613 #define FLOW_CONTROL_TYPE 0x8808 1614 1615 /* The historical defaults for the flow control values are given below. */ 1616 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 1617 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 1618 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 1619 1620 /* PCIX Config space */ 1621 #define PCIX_COMMAND_REGISTER 0xE6 1622 #define PCIX_STATUS_REGISTER_LO 0xE8 1623 #define PCIX_STATUS_REGISTER_HI 0xEA 1624 1625 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1626 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1627 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1628 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1629 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1630 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1631 1632 1633 /* Number of bits required to shift right the "pause" bits from the 1634 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. 1635 */ 1636 #define PAUSE_SHIFT 5 1637 1638 /* Number of bits required to shift left the "SWDPIO" bits from the 1639 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register. 1640 */ 1641 #define SWDPIO_SHIFT 17 1642 1643 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the 1644 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register. 1645 */ 1646 #define SWDPIO__EXT_SHIFT 4 1647 1648 /* Number of bits required to shift left the "ILOS" bit from the EEPROM 1649 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register. 1650 */ 1651 #define ILOS_SHIFT 3 1652 1653 1654 #define RECEIVE_BUFFER_ALIGN_SIZE (256) 1655 1656 /* Number of milliseconds we wait for auto-negotiation to complete */ 1657 #define LINK_UP_TIMEOUT 500 1658 1659 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 1660 1661 /* The carrier extension symbol, as received by the NIC. */ 1662 #define CARRIER_EXTENSION 0x0F 1663 1664 /* TBI_ACCEPT macro definition: 1665 * 1666 * This macro requires: 1667 * adapter = a pointer to struct em_hw 1668 * status = the 8 bit status field of the RX descriptor with EOP set 1669 * error = the 8 bit error field of the RX descriptor with EOP set 1670 * length = the sum of all the length fields of the RX descriptors that 1671 * make up the current frame 1672 * last_byte = the last byte of the frame DMAed by the hardware 1673 * max_frame_length = the maximum frame length we want to accept. 1674 * min_frame_length = the minimum frame length we want to accept. 1675 * 1676 * This macro is a conditional that should be used in the interrupt 1677 * handler's Rx processing routine when RxErrors have been detected. 1678 * 1679 * Typical use: 1680 * ... 1681 * if (TBI_ACCEPT) { 1682 * accept_frame = TRUE; 1683 * em_tbi_adjust_stats(sc, MacAddress); 1684 * frame_length--; 1685 * } else { 1686 * accept_frame = FALSE; 1687 * } 1688 * ... 1689 */ 1690 1691 #define TBI_ACCEPT(sc, status, errors, length, last_byte) \ 1692 ((sc)->tbi_compatibility_on && \ 1693 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ 1694 ((last_byte) == CARRIER_EXTENSION) && \ 1695 (((status) & E1000_RXD_STAT_VP) ? \ 1696 (((length) > ((sc)->min_frame_size - VLAN_TAG_SIZE)) && \ 1697 ((length) <= ((sc)->max_frame_size + 1))) : \ 1698 (((length) > (sc)->min_frame_size) && \ 1699 ((length) <= ((sc)->max_frame_size + VLAN_TAG_SIZE + 1))))) 1700 1701 1702 /* Structures, enums, and macros for the PHY */ 1703 1704 /* Bit definitions for the Management Data IO (MDIO) and Management Data 1705 * Clock (MDC) pins in the Device Control Register. 1706 */ 1707 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 1708 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 1709 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 1710 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 1711 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 1712 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 1713 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 1714 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 1715 1716 /* PHY 1000 MII Register/Bit Definitions */ 1717 /* PHY Registers defined by IEEE */ 1718 #define PHY_CTRL 0x00 /* Control Register */ 1719 #define PHY_STATUS 0x01 /* Status Regiser */ 1720 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1721 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1722 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1723 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1724 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1725 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 1726 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1727 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1728 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1729 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1730 1731 /* M88E1000 Specific Registers */ 1732 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 1733 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 1734 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 1735 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 1736 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 1737 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1738 1739 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1740 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 1741 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 1742 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1743 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1744 1745 #define IGP01E1000_IEEE_REGS_PAGE 0x0000 1746 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 1747 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 1748 1749 /* IGP01E1000 Specific Registers */ 1750 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 1751 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 1752 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 1753 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 1754 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 1755 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 1756 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 1757 1758 /* IGP01E1000 AGC Registers - stores the cable length values*/ 1759 #define IGP01E1000_PHY_AGC_A 0x1172 1760 #define IGP01E1000_PHY_AGC_B 0x1272 1761 #define IGP01E1000_PHY_AGC_C 0x1472 1762 #define IGP01E1000_PHY_AGC_D 0x1872 1763 1764 /* IGP01E1000 DSP Reset Register */ 1765 #define IGP01E1000_PHY_DSP_RESET 0x1F33 1766 #define IGP01E1000_PHY_DSP_SET 0x1F71 1767 #define IGP01E1000_PHY_DSP_FFE 0x1F35 1768 1769 #define IGP01E1000_PHY_CHANNEL_NUM 4 1770 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 1771 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 1772 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 1773 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 1774 1775 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 1776 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 1777 1778 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 1779 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 1780 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 1781 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 1782 1783 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A 1784 /* IGP01E1000 PCS Initialization register - stores the polarity status when 1785 * speed = 1000 Mbps. */ 1786 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 1787 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 1788 1789 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 1790 1791 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1792 #define MAX_PHY_MULTI_PAGE_REG 0xF /*Registers that are equal on all pages*/ 1793 /* PHY Control Register */ 1794 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1795 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 1796 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 1797 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 1798 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 1799 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 1800 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 1801 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1802 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 1803 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 1804 1805 /* PHY Status Register */ 1806 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 1807 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 1808 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 1809 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 1810 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 1811 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 1812 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 1813 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 1814 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 1815 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 1816 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 1817 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 1818 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 1819 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 1820 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 1821 1822 /* Autoneg Advertisement Register */ 1823 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 1824 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 1825 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 1826 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 1827 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 1828 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 1829 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 1830 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 1831 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 1832 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1833 1834 /* Link Partner Ability Register (Base Page) */ 1835 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 1836 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 1837 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 1838 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 1839 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 1840 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 1841 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 1842 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 1843 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 1844 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 1845 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1846 1847 /* Autoneg Expansion Register */ 1848 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 1849 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 1850 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 1851 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 1852 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 1853 1854 /* Next Page TX Register */ 1855 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 1856 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 1857 * of different NP 1858 */ 1859 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 1860 * 0 = cannot comply with msg 1861 */ 1862 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 1863 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 1864 * 0 = sending last NP 1865 */ 1866 1867 /* Link Partner Next Page Register */ 1868 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 1869 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 1870 * of different NP 1871 */ 1872 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 1873 * 0 = cannot comply with msg 1874 */ 1875 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 1876 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 1877 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 1878 * 0 = sending last NP 1879 */ 1880 1881 /* 1000BASE-T Control Register */ 1882 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1883 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1884 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1885 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 1886 /* 0=DTE device */ 1887 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 1888 /* 0=Configure PHY as Slave */ 1889 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 1890 /* 0=Automatic Master/Slave config */ 1891 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1892 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1893 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1894 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1895 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1896 1897 /* 1000BASE-T Status Register */ 1898 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 1899 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 1900 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1901 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1902 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1903 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1904 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 1905 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1906 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 1907 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 1908 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1909 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 1910 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 1911 1912 /* Extended Status Register */ 1913 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 1914 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 1915 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 1916 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 1917 1918 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 1919 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 1920 1921 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 1922 /* (0=enable, 1=disable) */ 1923 1924 /* M88E1000 PHY Specific Control Register */ 1925 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 1926 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 1927 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 1928 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 1929 * 0=CLK125 toggling 1930 */ 1931 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 1932 /* Manual MDI configuration */ 1933 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1934 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 1935 * 100BASE-TX/10BASE-T: 1936 * MDI Mode 1937 */ 1938 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 1939 * all speeds. 1940 */ 1941 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 1942 /* 1=Enable Extended 10BASE-T distance 1943 * (Lower 10BASE-T RX Threshold) 1944 * 0=Normal 10BASE-T RX Threshold */ 1945 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 1946 /* 1=5-Bit interface in 100BASE-TX 1947 * 0=MII interface in 100BASE-TX */ 1948 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 1949 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 1950 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 1951 1952 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 1953 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 1954 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 1955 1956 /* M88E1000 PHY Specific Status Register */ 1957 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 1958 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1959 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1960 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1961 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 1962 * 3=110-140M;4=>140M */ 1963 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1964 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1965 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 1966 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1967 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1968 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 1969 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1970 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1971 1972 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 1973 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 1974 #define M88E1000_PSSR_MDIX_SHIFT 6 1975 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1976 1977 /* M88E1000 Extended PHY Specific Control Register */ 1978 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 1979 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 1980 * Will assert lost lock and bring 1981 * link down if idle not seen 1982 * within 1ms in 1000BASE-T 1983 */ 1984 /* Number of times we will attempt to autonegotiate before downshifting if we 1985 * are the master */ 1986 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1987 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1988 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 1989 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 1990 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 1991 /* Number of times we will attempt to autonegotiate before downshifting if we 1992 * are the slave */ 1993 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1994 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 1995 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1996 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 1997 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 1998 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 1999 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2000 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2001 2002 /* IGP01E1000 Specific Port Config Register - R/W */ 2003 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 2004 #define IGP01E1000_PSCFR_PRE_EN 0x0020 2005 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 2006 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 2007 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 2008 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 2009 2010 /* IGP01E1000 Specific Port Status Register - R/O */ 2011 #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 2012 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 2013 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C 2014 #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 2015 #define IGP01E1000_PSSR_LINK_UP 0x0400 2016 #define IGP01E1000_PSSR_MDIX 0x0800 2017 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 2018 #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 2019 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 2020 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 2021 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 2022 #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 2023 2024 /* IGP01E1000 Specific Port Control Register - R/W */ 2025 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0001 2026 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 2027 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 2028 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 2029 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 2030 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 2031 2032 /* IGP01E1000 Specific Port Link Health Register */ 2033 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 2034 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 2035 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 2036 #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 2037 #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ 2038 #define IGP01E1000_PLHR_DATA_ERR_0 0x0100 2039 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0010 2040 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0008 2041 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0004 2042 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0002 2043 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0001 2044 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0000 2045 2046 /* IGP01E1000 Channel Quality Register */ 2047 #define IGP01E1000_MSE_CHANNEL_D 0x000F 2048 #define IGP01E1000_MSE_CHANNEL_C 0x00F0 2049 #define IGP01E1000_MSE_CHANNEL_B 0x0F00 2050 #define IGP01E1000_MSE_CHANNEL_A 0xF000 2051 2052 /* IGP01E1000 DSP reset macros */ 2053 #define DSP_RESET_ENABLE 0x0 2054 #define DSP_RESET_DISABLE 0x2 2055 #define E1000_MAX_DSP_RESETS 10 2056 2057 /* IGP01E1000 AGC Registers */ 2058 2059 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 2060 2061 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ 2062 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 2063 2064 /* The precision of the length is +/- 10 meters */ 2065 #define IGP01E1000_AGC_RANGE 10 2066 2067 /* IGP01E1000 PCS Initialization register */ 2068 /* bits 3:6 in the PCS registers stores the channels polarity */ 2069 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 2070 2071 /* IGP01E1000 GMII FIFO Register */ 2072 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 2073 * on Link-Up */ 2074 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 2075 2076 /* IGP01E1000 Analog Register */ 2077 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 2078 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 2079 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC 2080 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE 2081 2082 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 2083 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 2084 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 2085 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 2086 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 2087 2088 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 2089 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 2090 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 2091 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 2092 2093 /* Bit definitions for valid PHY IDs. */ 2094 #define M88E1000_E_PHY_ID 0x01410C50 2095 #define M88E1000_I_PHY_ID 0x01410C30 2096 #define M88E1011_I_PHY_ID 0x01410C20 2097 #define IGP01E1000_I_PHY_ID 0x02A80380 2098 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 2099 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 2100 #define M88E1011_I_REV_4 0x04 2101 2102 /* Miscellaneous PHY bit definitions. */ 2103 #define PHY_PREAMBLE 0xFFFFFFFF 2104 #define PHY_SOF 0x01 2105 #define PHY_OP_READ 0x02 2106 #define PHY_OP_WRITE 0x01 2107 #define PHY_TURNAROUND 0x02 2108 #define PHY_PREAMBLE_SIZE 32 2109 #define MII_CR_SPEED_1000 0x0040 2110 #define MII_CR_SPEED_100 0x2000 2111 #define MII_CR_SPEED_10 0x0000 2112 #define E1000_PHY_ADDRESS 0x01 2113 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 2114 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 2115 #define PHY_REVISION_MASK 0xFFFFFFF0 2116 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 2117 #define REG4_SPEED_MASK 0x01E0 2118 #define REG9_SPEED_MASK 0x0300 2119 #define ADVERTISE_10_HALF 0x0001 2120 #define ADVERTISE_10_FULL 0x0002 2121 #define ADVERTISE_100_HALF 0x0004 2122 #define ADVERTISE_100_FULL 0x0008 2123 #define ADVERTISE_1000_HALF 0x0010 2124 #define ADVERTISE_1000_FULL 0x0020 2125 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 2126 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ 2127 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ 2128 2129 #endif /* _EM_HW_H_ */ 2130