1 /*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 * Copyright (c) 2016, Hiroki Mori
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_ddb.h"
30
31 #include <sys/param.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/socket.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/cons.h>
38 #include <sys/kdb.h>
39 #include <sys/reboot.h>
40
41 #include <vm/vm.h>
42 #include <vm/vm_page.h>
43
44 #include <net/ethernet.h>
45
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
53
54 #include <mips/atheros/ar531x/ar5315reg.h>
55 #include <mips/atheros/ar531x/ar5315_chip.h>
56 #include <mips/atheros/ar531x/ar5315_cpudef.h>
57
58 /* XXX these shouldn't be in here - this file is a per-chip file */
59 /* XXX these should be in the top-level ar5315 type, not ar5315 -chip */
60 uint32_t u_ar531x_cpu_freq;
61 uint32_t u_ar531x_ahb_freq;
62 uint32_t u_ar531x_ddr_freq;
63
64 uint32_t u_ar531x_uart_addr;
65
66 uint32_t u_ar531x_gpio_di;
67 uint32_t u_ar531x_gpio_do;
68 uint32_t u_ar531x_gpio_cr;
69 uint32_t u_ar531x_gpio_pins;
70
71 uint32_t u_ar531x_wdog_ctl;
72 uint32_t u_ar531x_wdog_timer;
73
74 static void
ar5315_chip_detect_mem_size(void)75 ar5315_chip_detect_mem_size(void)
76 {
77 uint32_t memsize = 0;
78 uint32_t memcfg, cw, rw, dw;
79
80 /*
81 * Determine the memory size. We query the board info.
82 */
83 memcfg = ATH_READ_REG(AR5315_SDRAMCTL_BASE + AR5315_SDRAMCTL_MEM_CFG);
84 cw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_COL_WIDTH);
85 cw += 1;
86 rw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_ROW_WIDTH);
87 rw += 1;
88
89 /* XXX: according to redboot, this could be wrong if DDR SDRAM */
90 dw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_DATA_WIDTH);
91 dw += 1;
92 dw *= 8; /* bits */
93
94 /* not too sure about this math, but it _seems_ to add up */
95 memsize = (1 << cw) * (1 << rw) * dw;
96 #if 0
97 printf("SDRAM_MEM_CFG =%x, cw=%d rw=%d dw=%d xmemsize=%d\n", memcfg,
98 cw, rw, dw, memsize);
99 #endif
100 realmem = memsize;
101 }
102
103 static void
ar5315_chip_detect_sys_frequency(void)104 ar5315_chip_detect_sys_frequency(void)
105 {
106 uint32_t freq_ref, freq_pll;
107 static const uint8_t pll_divide_table[] = {
108 2, 3, 4, 6, 3,
109 /*
110 * these entries are bogus, but it avoids a possible
111 * bad table dereference
112 */
113 1, 1, 1
114 };
115 static const uint8_t pre_divide_table[] = {
116 1, 2, 4, 5
117 };
118
119 const uint32_t pllc = ATH_READ_REG(AR5315_SYSREG_BASE +
120 AR5315_SYSREG_PLLC_CTL);
121
122 const uint32_t refdiv = pre_divide_table[AR5315_PLLC_REF_DIV(pllc)];
123 const uint32_t fbdiv = AR5315_PLLC_FB_DIV(pllc);
124 const uint32_t div2 = (AR5315_PLLC_DIV_2(pllc) + 1) * 2; /* results in 2 or 4 */
125
126 freq_ref = 40000000;
127
128 /* 40MHz reference clk, reference and feedback dividers */
129 freq_pll = (freq_ref / refdiv) * div2 * fbdiv;
130
131 const uint32_t pllout[4] = {
132 /* CLKM select */
133 [0] = freq_pll / pll_divide_table[AR5315_PLLC_CLKM(pllc)],
134 [1] = freq_pll / pll_divide_table[AR5315_PLLC_CLKM(pllc)],
135
136 /* CLKC select */
137 [2] = freq_pll / pll_divide_table[AR5315_PLLC_CLKC(pllc)],
138
139 /* ref_clk select */
140 [3] = freq_ref, /* use original reference clock */
141 };
142
143 const uint32_t amba_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE +
144 AR5315_SYSREG_AMBACLK);
145 uint32_t ambadiv = AR5315_CLOCKCTL_DIV(amba_clkctl);
146 ambadiv = ambadiv ? (ambadiv * 2) : 1;
147 u_ar531x_ahb_freq = pllout[AR5315_CLOCKCTL_SELECT(amba_clkctl)] / ambadiv;
148
149 const uint32_t cpu_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE +
150 AR5315_SYSREG_CPUCLK);
151 uint32_t cpudiv = AR5315_CLOCKCTL_DIV(cpu_clkctl);
152 cpudiv = cpudiv ? (cpudiv * 2) : 1;
153 u_ar531x_cpu_freq = pllout[AR5315_CLOCKCTL_SELECT(cpu_clkctl)] / cpudiv;
154
155 u_ar531x_ddr_freq = 0;
156 }
157
158 /*
159 * This does not lock the CPU whilst doing the work!
160 */
161 static void
ar5315_chip_device_reset(void)162 ar5315_chip_device_reset(void)
163 {
164 ATH_WRITE_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_COLDRESET,
165 AR5315_COLD_AHB | AR5315_COLD_APB | AR5315_COLD_CPU);
166 }
167
168 static void
ar5315_chip_device_start(void)169 ar5315_chip_device_start(void)
170 {
171 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR0,
172 AR5315_AHB_ERROR_DET);
173 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR1);
174 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_WDOG_CTL,
175 AR5315_WDOG_CTL_IGNORE);
176
177 // set Ethernet AHB master arbitration control
178 // Maybe RedBoot was enabled. But to make sure.
179 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL,
180 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL) |
181 AR5315_ARB_ENET);
182
183 // set Ethernet controller byteswap control
184 /*
185 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN,
186 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN) |
187 AR5315_ENDIAN_ENET);
188 */
189 /* Disable interrupts for all gpio pins. */
190 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_GPIO_INT, 0);
191
192 printf("AHB Master Arbitration Control %08x\n",
193 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL));
194 printf("Byteswap Control %08x\n",
195 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN));
196 }
197
198 static int
ar5315_chip_device_stopped(uint32_t mask)199 ar5315_chip_device_stopped(uint32_t mask)
200 {
201 uint32_t reg;
202
203 reg = ATH_READ_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_COLDRESET);
204 return ((reg & mask) == mask);
205 }
206
207 static void
ar5315_chip_set_mii_speed(uint32_t unit,uint32_t speed)208 ar5315_chip_set_mii_speed(uint32_t unit, uint32_t speed)
209 {
210 }
211
212 /* Speed is either 10, 100 or 1000 */
213 static void
ar5315_chip_set_pll_ge(int unit,int speed)214 ar5315_chip_set_pll_ge(int unit, int speed)
215 {
216 }
217
218 static void
ar5315_chip_ddr_flush_ge(int unit)219 ar5315_chip_ddr_flush_ge(int unit)
220 {
221 }
222
223 static void
ar5315_chip_soc_init(void)224 ar5315_chip_soc_init(void)
225 {
226 u_ar531x_uart_addr = MIPS_PHYS_TO_KSEG1(AR5315_UART_BASE);
227
228 u_ar531x_gpio_di = AR5315_SYSREG_GPIO_DI;
229 u_ar531x_gpio_do = AR5315_SYSREG_GPIO_DO;
230 u_ar531x_gpio_cr = AR5315_SYSREG_GPIO_CR;
231 u_ar531x_gpio_pins = AR5315_GPIO_PINS;
232
233 u_ar531x_wdog_ctl = AR5315_SYSREG_WDOG_CTL;
234 u_ar531x_wdog_timer = AR5315_SYSREG_WDOG_TIMER;
235 }
236
237 static uint32_t
ar5315_chip_get_eth_pll(unsigned int mac,int speed)238 ar5315_chip_get_eth_pll(unsigned int mac, int speed)
239 {
240 return 0;
241 }
242
243 struct ar5315_cpu_def ar5315_chip_def = {
244 &ar5315_chip_detect_mem_size,
245 &ar5315_chip_detect_sys_frequency,
246 &ar5315_chip_device_reset,
247 &ar5315_chip_device_start,
248 &ar5315_chip_device_stopped,
249 &ar5315_chip_set_pll_ge,
250 &ar5315_chip_set_mii_speed,
251 &ar5315_chip_ddr_flush_ge,
252 &ar5315_chip_get_eth_pll,
253 &ar5315_chip_soc_init,
254 };
255