1 /*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39
40 /* $FreeBSD: src/sys/dev/oce/oce_if.h,v 1.6 2013/07/07 00:30:13 svnexp Exp $ */
41
42 #include <sys/param.h>
43 #include <sys/endian.h>
44 #include <sys/module.h>
45 #include <sys/kernel.h>
46 #include <sys/bus.h>
47 #include <sys/malloc.h> /* for M_NOWAIT */
48 #include <sys/mbuf.h>
49 #include <sys/rman.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/queue.h>
53 #include <sys/taskqueue.h>
54 #include <sys/lock.h>
55 #include <sys/sysctl.h>
56 #include <sys/random.h>
57 #include <sys/firmware.h>
58 #include <sys/systm.h>
59 #include <sys/caps.h>
60 #include <sys/proc.h>
61
62 #include <bus/pci/pcireg.h>
63 #include <bus/pci/pcivar.h>
64
65 #include <net/bpf.h>
66 #include <net/ethernet.h>
67 #include <net/if.h>
68 #include <net/if_types.h>
69 #include <net/if_media.h>
70 #include <net/ifq_var.h>
71 #include <net/vlan/if_vlan_ether.h>
72 #include <net/vlan/if_vlan_var.h>
73 #include <net/if_dl.h>
74
75 #include <netinet/in.h>
76 #include <netinet/in_systm.h>
77 #include <netinet/in_var.h>
78 #include <netinet/if_ether.h>
79 #include <netinet/ip.h>
80 #include <netinet/ip6.h>
81 #include <netinet6/in6_var.h>
82 #include <netinet6/ip6_mroute.h>
83
84 #include <netinet/udp.h>
85 #include <netinet/tcp.h>
86 #if 0 /* XXX swildner: LRO */
87 #include <netinet/tcp_lro.h>
88 #endif
89
90 #include "oce_hw.h"
91
92 #define COMPONENT_REVISION "4.6.95.0"
93
94 /* OCE devices supported by this driver */
95 #define PCI_VENDOR_EMULEX 0x10df /* Emulex */
96 #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
97 #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
98 #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
99 #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
100 #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */
101 #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */
102
103 #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \
104 (sc->flags & OCE_FLAGS_BE2))? 1:0)
105 #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3)
106 #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2)
107 #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
108 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
109 #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
110
111 #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \
112 (sc->function_mode & FNM_UMC_MODE) || \
113 (sc->function_mode & FNM_VNIC_MODE))
114 #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40
115 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
116
117
118 /* proportion Service Level Interface queues */
119 #define OCE_MAX_UNITS 2
120 #define OCE_MAX_PPORT OCE_MAX_UNITS
121 #define OCE_MAX_VPORT OCE_MAX_UNITS
122
123 #define OCE_NCPUS ncpus
124
125 /* This should be powers of 2. Like 2,4,8 & 16 */
126 #define OCE_MAX_RSS 8
127 #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/
128 #if 0 /* XXX swildner: RSS */
129 #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
130 #else
131 #define is_rss_enabled(sc) 0
132 #endif
133
134 #define OCE_MIN_RQ 1
135 #define OCE_MIN_WQ 1
136
137 #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */
138 #define OCE_MAX_WQ 8
139
140 #define OCE_MAX_EQ 32
141 #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
142 #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */
143
144 #define OCE_DEFAULT_WQ_EQD 16
145 #define OCE_MAX_PACKET_Q 16
146 #define OCE_RQ_BUF_SIZE 2048
147 #define OCE_LSO_MAX_SIZE (64 * 1024)
148 #define LONG_TIMEOUT 30
149 #define OCE_MAX_JUMBO_FRAME_SIZE 9018
150 #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
151 ETHER_VLAN_ENCAP_LEN - \
152 ETHER_HDR_LEN)
153
154 #define OCE_MAX_TX_ELEMENTS 29
155 #define OCE_MAX_TX_DESC 1024
156 #define OCE_MAX_TX_SIZE 65535
157 #define OCE_MAX_RX_SIZE 4096
158 #define OCE_MAX_RQ_POSTS 255
159 #define OCE_DEFAULT_PROMISCUOUS 0
160
161
162 #define RSS_ENABLE_IPV4 0x1
163 #define RSS_ENABLE_TCP_IPV4 0x2
164 #define RSS_ENABLE_IPV6 0x4
165 #define RSS_ENABLE_TCP_IPV6 0x8
166
167 #define INDIRECTION_TABLE_ENTRIES 128
168
169 /* flow control definitions */
170 #define OCE_FC_NONE 0x00000000
171 #define OCE_FC_TX 0x00000001
172 #define OCE_FC_RX 0x00000002
173 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
174
175
176 /* Interface capabilities to give device when creating interface */
177 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
178 MBX_RX_IFACE_FLAGS_UNTAGGED | \
179 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
180 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
181 MBX_RX_IFACE_FLAGS_RSS | \
182 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
183
184 /* Interface capabilities to enable by default (others set dynamically) */
185 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
186 MBX_RX_IFACE_FLAGS_UNTAGGED | \
187 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
188
189 #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP)
190 #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
191 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
192 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
193 #define OCE_IF_HWASSIST_NONE 0
194 #define OCE_IF_CAPABILITIES_NONE 0
195
196
197 #define ETH_ADDR_LEN 6
198 #define MAX_VLANFILTER_SIZE 64
199 #define MAX_VLANS 4096
200
201 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
202 #define BSWAP_8(x) ((x) & 0xff)
203 #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
204 #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \
205 BSWAP_16((x) >> 16))
206 #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \
207 BSWAP_32((x) >> 32))
208
209 #define for_all_wq_queues(sc, wq, i) \
210 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
211 #define for_all_rq_queues(sc, rq, i) \
212 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
213 #define for_all_rss_queues(sc, rq, i) \
214 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
215 i++, rq = sc->rq[i + 1])
216 #define for_all_evnt_queues(sc, eq, i) \
217 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
218 #define for_all_cq_queues(sc, cq, i) \
219 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
220
221
222 /* Flash specific */
223 #define IOCTL_COOKIE "SERVERENGINES CORP"
224 #define MAX_FLASH_COMP 32
225
226 #define IMG_ISCSI 160
227 #define IMG_REDBOOT 224
228 #define IMG_BIOS 34
229 #define IMG_PXEBIOS 32
230 #define IMG_FCOEBIOS 33
231 #define IMG_ISCSI_BAK 176
232 #define IMG_FCOE 162
233 #define IMG_FCOE_BAK 178
234 #define IMG_NCSI 16
235 #define IMG_PHY 192
236 #define FLASHROM_OPER_FLASH 1
237 #define FLASHROM_OPER_SAVE 2
238 #define FLASHROM_OPER_REPORT 4
239 #define FLASHROM_OPER_FLASH_PHY 9
240 #define FLASHROM_OPER_SAVE_PHY 10
241 #define TN_8022 13
242
243 enum {
244 PHY_TYPE_CX4_10GB = 0,
245 PHY_TYPE_XFP_10GB,
246 PHY_TYPE_SFP_1GB,
247 PHY_TYPE_SFP_PLUS_10GB,
248 PHY_TYPE_KR_10GB,
249 PHY_TYPE_KX4_10GB,
250 PHY_TYPE_BASET_10GB,
251 PHY_TYPE_BASET_1GB,
252 PHY_TYPE_BASEX_1GB,
253 PHY_TYPE_SGMII,
254 PHY_TYPE_DISABLED = 255
255 };
256
257 /**
258 * @brief Define and hold all necessary info for a single interrupt
259 */
260 #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */
261 #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */
262
263 typedef struct oce_intr_info {
264 void *tag; /* cookie returned by bus_setup_intr */
265 struct resource *intr_res; /* PCI resource container */
266 int irq_rr; /* resource id for the interrupt */
267 int irq_type; /* interrupt type */
268 struct oce_softc *sc; /* pointer to the parent soft c */
269 struct oce_eq *eq; /* pointer to the connected EQ */
270 struct taskqueue *tq; /* Associated task queue */
271 struct task task; /* task queue task */
272 char task_name[32]; /* task name */
273 int vector; /* interrupt vector number */
274 } OCE_INTR_INFO, *POCE_INTR_INFO;
275
276
277 /* Ring related */
278 #define GET_Q_NEXT(_START, _STEP, _END) \
279 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
280 : (((_START) + (_STEP)) - (_END)))
281
282 #define DBUF_PA(obj) ((obj)->addr)
283 #define DBUF_VA(obj) ((obj)->ptr)
284 #define DBUF_TAG(obj) ((obj)->tag)
285 #define DBUF_MAP(obj) ((obj)->map)
286 #define DBUF_SYNC(obj, flags) \
287 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
288
289 #define RING_NUM_PENDING(ring) ring->num_used
290 #define RING_FULL(ring) (ring->num_used == ring->num_items)
291 #define RING_EMPTY(ring) (ring->num_used == 0)
292 #define RING_NUM_FREE(ring) \
293 (uint32_t)(ring->num_items - ring->num_used)
294 #define RING_GET(ring, n) \
295 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
296 #define RING_PUT(ring, n) \
297 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
298
299 #define RING_GET_CONSUMER_ITEM_VA(ring, type) \
300 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
301 #define RING_GET_CONSUMER_ITEM_PA(ring, type) \
302 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
303 #define RING_GET_PRODUCER_ITEM_VA(ring, type) \
304 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
305 #define RING_GET_PRODUCER_ITEM_PA(ring, type) \
306 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
307
308 #define OCE_DMAPTR(o, c) ((c *)(o)->ptr)
309
310 struct oce_packet_desc {
311 struct mbuf *mbuf;
312 bus_dmamap_t map;
313 int nsegs;
314 uint32_t wqe_idx;
315 };
316
317 typedef struct oce_dma_mem {
318 bus_dma_tag_t tag;
319 bus_dmamap_t map;
320 void *ptr;
321 bus_addr_t paddr;
322 } OCE_DMA_MEM, *POCE_DMA_MEM;
323
324 typedef struct oce_ring_buffer_s {
325 uint16_t cidx; /* Get ptr */
326 uint16_t pidx; /* Put Ptr */
327 size_t item_size;
328 size_t num_items;
329 uint32_t num_used;
330 OCE_DMA_MEM dma;
331 } oce_ring_buffer_t;
332
333 /* Stats */
334 #define OCE_UNICAST_PACKET 0
335 #define OCE_MULTICAST_PACKET 1
336 #define OCE_BROADCAST_PACKET 2
337 #define OCE_RSVD_PACKET 3
338
339 struct oce_rx_stats {
340 /* Total Receive Stats*/
341 uint64_t t_rx_pkts;
342 uint64_t t_rx_bytes;
343 uint32_t t_rx_frags;
344 uint32_t t_rx_mcast_pkts;
345 uint32_t t_rx_ucast_pkts;
346 uint32_t t_rxcp_errs;
347 };
348 struct oce_tx_stats {
349 /*Total Transmit Stats */
350 uint64_t t_tx_pkts;
351 uint64_t t_tx_bytes;
352 uint32_t t_tx_reqs;
353 uint32_t t_tx_stops;
354 uint32_t t_tx_wrbs;
355 uint32_t t_tx_compl;
356 uint32_t t_ipv6_ext_hdr_tx_drop;
357 };
358
359 struct oce_be_stats {
360 uint8_t be_on_die_temperature;
361 uint32_t be_tx_events;
362 uint32_t eth_red_drops;
363 uint32_t rx_drops_no_pbuf;
364 uint32_t rx_drops_no_txpb;
365 uint32_t rx_drops_no_erx_descr;
366 uint32_t rx_drops_no_tpre_descr;
367 uint32_t rx_drops_too_many_frags;
368 uint32_t rx_drops_invalid_ring;
369 uint32_t forwarded_packets;
370 uint32_t rx_drops_mtu;
371 uint32_t rx_crc_errors;
372 uint32_t rx_alignment_symbol_errors;
373 uint32_t rx_pause_frames;
374 uint32_t rx_priority_pause_frames;
375 uint32_t rx_control_frames;
376 uint32_t rx_in_range_errors;
377 uint32_t rx_out_range_errors;
378 uint32_t rx_frame_too_long;
379 uint32_t rx_address_match_errors;
380 uint32_t rx_dropped_too_small;
381 uint32_t rx_dropped_too_short;
382 uint32_t rx_dropped_header_too_small;
383 uint32_t rx_dropped_tcp_length;
384 uint32_t rx_dropped_runt;
385 uint32_t rx_ip_checksum_errs;
386 uint32_t rx_tcp_checksum_errs;
387 uint32_t rx_udp_checksum_errs;
388 uint32_t rx_switched_unicast_packets;
389 uint32_t rx_switched_multicast_packets;
390 uint32_t rx_switched_broadcast_packets;
391 uint32_t tx_pauseframes;
392 uint32_t tx_priority_pauseframes;
393 uint32_t tx_controlframes;
394 uint32_t rxpp_fifo_overflow_drop;
395 uint32_t rx_input_fifo_overflow_drop;
396 uint32_t pmem_fifo_overflow_drop;
397 uint32_t jabber_events;
398 };
399
400 struct oce_xe201_stats {
401 uint64_t tx_pkts;
402 uint64_t tx_unicast_pkts;
403 uint64_t tx_multicast_pkts;
404 uint64_t tx_broadcast_pkts;
405 uint64_t tx_bytes;
406 uint64_t tx_unicast_bytes;
407 uint64_t tx_multicast_bytes;
408 uint64_t tx_broadcast_bytes;
409 uint64_t tx_discards;
410 uint64_t tx_errors;
411 uint64_t tx_pause_frames;
412 uint64_t tx_pause_on_frames;
413 uint64_t tx_pause_off_frames;
414 uint64_t tx_internal_mac_errors;
415 uint64_t tx_control_frames;
416 uint64_t tx_pkts_64_bytes;
417 uint64_t tx_pkts_65_to_127_bytes;
418 uint64_t tx_pkts_128_to_255_bytes;
419 uint64_t tx_pkts_256_to_511_bytes;
420 uint64_t tx_pkts_512_to_1023_bytes;
421 uint64_t tx_pkts_1024_to_1518_bytes;
422 uint64_t tx_pkts_1519_to_2047_bytes;
423 uint64_t tx_pkts_2048_to_4095_bytes;
424 uint64_t tx_pkts_4096_to_8191_bytes;
425 uint64_t tx_pkts_8192_to_9216_bytes;
426 uint64_t tx_lso_pkts;
427 uint64_t rx_pkts;
428 uint64_t rx_unicast_pkts;
429 uint64_t rx_multicast_pkts;
430 uint64_t rx_broadcast_pkts;
431 uint64_t rx_bytes;
432 uint64_t rx_unicast_bytes;
433 uint64_t rx_multicast_bytes;
434 uint64_t rx_broadcast_bytes;
435 uint32_t rx_unknown_protos;
436 uint64_t rx_discards;
437 uint64_t rx_errors;
438 uint64_t rx_crc_errors;
439 uint64_t rx_alignment_errors;
440 uint64_t rx_symbol_errors;
441 uint64_t rx_pause_frames;
442 uint64_t rx_pause_on_frames;
443 uint64_t rx_pause_off_frames;
444 uint64_t rx_frames_too_long;
445 uint64_t rx_internal_mac_errors;
446 uint32_t rx_undersize_pkts;
447 uint32_t rx_oversize_pkts;
448 uint32_t rx_fragment_pkts;
449 uint32_t rx_jabbers;
450 uint64_t rx_control_frames;
451 uint64_t rx_control_frames_unknown_opcode;
452 uint32_t rx_in_range_errors;
453 uint32_t rx_out_of_range_errors;
454 uint32_t rx_address_match_errors;
455 uint32_t rx_vlan_mismatch_errors;
456 uint32_t rx_dropped_too_small;
457 uint32_t rx_dropped_too_short;
458 uint32_t rx_dropped_header_too_small;
459 uint32_t rx_dropped_invalid_tcp_length;
460 uint32_t rx_dropped_runt;
461 uint32_t rx_ip_checksum_errors;
462 uint32_t rx_tcp_checksum_errors;
463 uint32_t rx_udp_checksum_errors;
464 uint32_t rx_non_rss_pkts;
465 uint64_t rx_ipv4_pkts;
466 uint64_t rx_ipv6_pkts;
467 uint64_t rx_ipv4_bytes;
468 uint64_t rx_ipv6_bytes;
469 uint64_t rx_nic_pkts;
470 uint64_t rx_tcp_pkts;
471 uint64_t rx_iscsi_pkts;
472 uint64_t rx_management_pkts;
473 uint64_t rx_switched_unicast_pkts;
474 uint64_t rx_switched_multicast_pkts;
475 uint64_t rx_switched_broadcast_pkts;
476 uint64_t num_forwards;
477 uint32_t rx_fifo_overflow;
478 uint32_t rx_input_fifo_overflow;
479 uint64_t rx_drops_too_many_frags;
480 uint32_t rx_drops_invalid_queue;
481 uint64_t rx_drops_mtu;
482 uint64_t rx_pkts_64_bytes;
483 uint64_t rx_pkts_65_to_127_bytes;
484 uint64_t rx_pkts_128_to_255_bytes;
485 uint64_t rx_pkts_256_to_511_bytes;
486 uint64_t rx_pkts_512_to_1023_bytes;
487 uint64_t rx_pkts_1024_to_1518_bytes;
488 uint64_t rx_pkts_1519_to_2047_bytes;
489 uint64_t rx_pkts_2048_to_4095_bytes;
490 uint64_t rx_pkts_4096_to_8191_bytes;
491 uint64_t rx_pkts_8192_to_9216_bytes;
492 };
493
494 struct oce_drv_stats {
495 struct oce_rx_stats rx;
496 struct oce_tx_stats tx;
497 union {
498 struct oce_be_stats be;
499 struct oce_xe201_stats xe201;
500 } u0;
501 };
502
503 #define INTR_RATE_HWM 15000
504 #define INTR_RATE_LWM 10000
505
506 #define OCE_MAX_EQD 128u
507 #define OCE_MIN_EQD 50u
508
509 struct oce_set_eqd {
510 uint32_t eq_id;
511 uint32_t phase;
512 uint32_t delay_multiplier;
513 };
514
515 struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
516 boolean_t enable;
517 uint32_t min_eqd; /* in usecs */
518 uint32_t max_eqd; /* in usecs */
519 uint32_t cur_eqd; /* in usecs */
520 uint32_t et_eqd; /* configured value when aic is off */
521 uint64_t ticks;
522 uint64_t intr_prev;
523 };
524
525 #define MAX_LOCK_DESC_LEN 32
526 struct oce_lock {
527 struct lock lock;
528 char name[MAX_LOCK_DESC_LEN+1];
529 };
530 #define OCE_LOCK struct oce_lock
531
532 #define LOCK_CREATE(ocelock, desc) { \
533 strncpy((ocelock)->name, (desc), MAX_LOCK_DESC_LEN); \
534 (ocelock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
535 lockinit(&(ocelock)->lock, (ocelock)->name, 0, LK_CANRECURSE); \
536 }
537 #define LOCK_DESTROY(ocelock) \
538 /* if (mtx_initialized(&(lock)->mutex)) */ \
539 lockuninit(&(ocelock)->lock)
540 #define LOCK(ocelock) lockmgr(&(ocelock)->lock, LK_EXCLUSIVE)
541 #define LOCKED(ocelock) lockowned(&(ocelock)->lock)
542 #define UNLOCK(ocelock) lockmgr(&(ocelock)->lock, LK_RELEASE)
543
544 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000)
545 #define MBX_READY_TIMEOUT (1 * 1000 * 1000)
546 #define DEFAULT_DRAIN_TIME 200
547 #define MBX_TIMEOUT_SEC 5
548 #define STAT_TIMEOUT 2000000
549
550 /* size of the packet descriptor array in a transmit queue */
551 #define OCE_TX_RING_SIZE 2048
552 #define OCE_RX_RING_SIZE 1024
553 #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2)
554 #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE)
555
556 struct oce_dev;
557
558 enum eq_len {
559 EQ_LEN_256 = 256,
560 EQ_LEN_512 = 512,
561 EQ_LEN_1024 = 1024,
562 EQ_LEN_2048 = 2048,
563 EQ_LEN_4096 = 4096
564 };
565
566 enum eqe_size {
567 EQE_SIZE_4 = 4,
568 EQE_SIZE_16 = 16
569 };
570
571 enum qtype {
572 QTYPE_EQ,
573 QTYPE_MQ,
574 QTYPE_WQ,
575 QTYPE_RQ,
576 QTYPE_CQ,
577 QTYPE_RSS
578 };
579
580 typedef enum qstate_e {
581 QDELETED = 0x0,
582 QCREATED = 0x1
583 } qstate_t;
584
585 struct eq_config {
586 enum eq_len q_len;
587 enum eqe_size item_size;
588 uint32_t q_vector_num;
589 uint8_t min_eqd;
590 uint8_t max_eqd;
591 uint8_t cur_eqd;
592 uint8_t pad;
593 };
594
595 struct oce_eq {
596 uint32_t eq_id;
597 void *parent;
598 void *cb_context;
599 oce_ring_buffer_t *ring;
600 uint32_t ref_count;
601 qstate_t qstate;
602 struct oce_cq *cq[OCE_MAX_CQ_EQ];
603 int cq_valid;
604 struct eq_config eq_cfg;
605 int vector;
606 uint64_t intr;
607 };
608
609 enum cq_len {
610 CQ_LEN_256 = 256,
611 CQ_LEN_512 = 512,
612 CQ_LEN_1024 = 1024
613 };
614
615 struct cq_config {
616 enum cq_len q_len;
617 uint32_t item_size;
618 boolean_t is_eventable;
619 boolean_t sol_eventable;
620 boolean_t nodelay;
621 uint16_t dma_coalescing;
622 };
623
624 typedef uint16_t(*cq_handler_t) (void *arg1);
625
626 struct oce_cq {
627 uint32_t cq_id;
628 void *parent;
629 struct oce_eq *eq;
630 cq_handler_t cq_handler;
631 void *cb_arg;
632 oce_ring_buffer_t *ring;
633 qstate_t qstate;
634 struct cq_config cq_cfg;
635 uint32_t ref_count;
636 };
637
638
639 struct mq_config {
640 uint32_t eqd;
641 uint8_t q_len;
642 uint8_t pad[3];
643 };
644
645
646 struct oce_mq {
647 void *parent;
648 oce_ring_buffer_t *ring;
649 uint32_t mq_id;
650 struct oce_cq *cq;
651 struct oce_cq *async_cq;
652 uint32_t mq_free;
653 qstate_t qstate;
654 struct mq_config cfg;
655 };
656
657 struct oce_mbx_ctx {
658 struct oce_mbx *mbx;
659 void (*cb) (void *ctx);
660 void *cb_ctx;
661 };
662
663 struct wq_config {
664 uint8_t wq_type;
665 uint16_t buf_size;
666 uint8_t pad[1];
667 uint32_t q_len;
668 uint16_t pd_id;
669 uint16_t pci_fn_num;
670 uint32_t eqd; /* interrupt delay */
671 uint32_t nbufs;
672 uint32_t nhdl;
673 };
674
675 struct oce_tx_queue_stats {
676 uint64_t tx_pkts;
677 uint64_t tx_bytes;
678 uint32_t tx_reqs;
679 uint32_t tx_stops; /* number of times TX Q was stopped */
680 uint32_t tx_wrbs;
681 uint32_t tx_compl;
682 uint32_t tx_rate;
683 uint32_t ipv6_ext_hdr_tx_drop;
684 };
685
686 struct oce_wq {
687 OCE_LOCK tx_lock;
688 void *parent;
689 oce_ring_buffer_t *ring;
690 struct oce_cq *cq;
691 bus_dma_tag_t tag;
692 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
693 uint32_t pkt_desc_tail;
694 uint32_t pkt_desc_head;
695 uint32_t wqm_used;
696 boolean_t resched;
697 uint32_t wq_free;
698 uint32_t tx_deferd;
699 uint32_t pkt_drops;
700 qstate_t qstate;
701 uint16_t wq_id;
702 struct wq_config cfg;
703 int queue_index;
704 struct oce_tx_queue_stats tx_stats;
705 struct buf_ring *br;
706 struct task txtask;
707 uint32_t db_offset;
708 };
709
710 struct rq_config {
711 uint32_t q_len;
712 uint32_t frag_size;
713 uint32_t mtu;
714 uint32_t if_id;
715 uint32_t is_rss_queue;
716 uint32_t eqd;
717 uint32_t nbufs;
718 };
719
720 struct oce_rx_queue_stats {
721 uint32_t rx_post_fail;
722 uint32_t rx_ucast_pkts;
723 uint32_t rx_compl;
724 uint64_t rx_bytes;
725 uint64_t rx_bytes_prev;
726 uint64_t rx_pkts;
727 uint32_t rx_rate;
728 uint32_t rx_mcast_pkts;
729 uint32_t rxcp_err;
730 uint32_t rx_frags;
731 uint32_t prev_rx_frags;
732 uint32_t rx_fps;
733 };
734
735
736 struct oce_rq {
737 struct rq_config cfg;
738 uint32_t rq_id;
739 int queue_index;
740 uint32_t rss_cpuid;
741 void *parent;
742 oce_ring_buffer_t *ring;
743 struct oce_cq *cq;
744 void *pad1;
745 bus_dma_tag_t tag;
746 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
747 uint32_t packets_in;
748 uint32_t packets_out;
749 uint32_t pending;
750 #ifdef notdef
751 struct mbuf *head;
752 struct mbuf *tail;
753 int fragsleft;
754 #endif
755 qstate_t qstate;
756 OCE_LOCK rx_lock;
757 struct oce_rx_queue_stats rx_stats;
758 #if 0 /* XXX swildner: LRO */
759 struct lro_ctrl lro;
760 int lro_pkts_queued;
761 #endif
762
763 };
764
765 struct link_status {
766 uint8_t physical_port;
767 uint8_t mac_duplex;
768 uint8_t mac_speed;
769 uint8_t mac_fault;
770 uint8_t mgmt_mac_duplex;
771 uint8_t mgmt_mac_speed;
772 uint16_t qos_link_speed;
773 uint32_t logical_link_status;
774 };
775
776
777
778 #define OCE_FLAGS_PCIX 0x00000001
779 #define OCE_FLAGS_PCIE 0x00000002
780 #define OCE_FLAGS_MSI_CAPABLE 0x00000004
781 #define OCE_FLAGS_MSIX_CAPABLE 0x00000008
782 #define OCE_FLAGS_USING_MSI 0x00000010
783 #define OCE_FLAGS_USING_MSIX 0x00000020
784 #define OCE_FLAGS_FUNCRESET_RQD 0x00000040
785 #define OCE_FLAGS_VIRTUAL_PORT 0x00000080
786 #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100
787 #define OCE_FLAGS_BE3 0x00000200
788 #define OCE_FLAGS_XE201 0x00000400
789 #define OCE_FLAGS_BE2 0x00000800
790 #define OCE_FLAGS_SH 0x00001000
791
792 #define OCE_DEV_BE2_CFG_BAR 1
793 #define OCE_DEV_CFG_BAR 0
794 #define OCE_PCI_CSR_BAR 2
795 #define OCE_PCI_DB_BAR 4
796
797 typedef struct oce_softc {
798 device_t dev;
799 OCE_LOCK dev_lock;
800
801 uint32_t flags;
802
803 uint32_t pcie_link_speed;
804 uint32_t pcie_link_width;
805
806 uint8_t fn; /* PCI function number */
807
808 struct resource *devcfg_res;
809 bus_space_tag_t devcfg_btag;
810 bus_space_handle_t devcfg_bhandle;
811 void *devcfg_vhandle;
812
813 struct resource *csr_res;
814 bus_space_tag_t csr_btag;
815 bus_space_handle_t csr_bhandle;
816 void *csr_vhandle;
817
818 struct resource *db_res;
819 bus_space_tag_t db_btag;
820 bus_space_handle_t db_bhandle;
821 void *db_vhandle;
822
823 OCE_INTR_INFO intrs[OCE_MAX_EQ];
824 int intr_count;
825
826 struct ifnet *ifp;
827
828 struct ifmedia media;
829 uint8_t link_status;
830 uint8_t link_speed;
831 uint8_t duplex;
832 uint32_t qos_link_speed;
833 uint32_t speed;
834
835 char fw_version[32];
836 struct mac_address_format macaddr;
837
838 OCE_DMA_MEM bsmbx;
839 OCE_LOCK bmbx_lock;
840
841 uint32_t config_number;
842 uint32_t asic_revision;
843 uint32_t port_id;
844 uint32_t function_mode;
845 uint32_t function_caps;
846 uint32_t max_tx_rings;
847 uint32_t max_rx_rings;
848
849 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */
850 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */
851 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */
852 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */
853 struct oce_mq *mq; /* Mailbox queue */
854
855 uint32_t neqs;
856 uint32_t ncqs;
857 uint32_t nrqs;
858 uint32_t nwqs;
859 uint32_t nrssqs;
860
861 uint32_t tx_ring_size;
862 uint32_t rx_ring_size;
863 uint32_t rq_frag_size;
864
865 uint32_t if_id; /* interface ID */
866 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
867 uint32_t pmac_id; /* PMAC id */
868
869 uint32_t if_cap_flags;
870
871 uint32_t flow_control;
872 uint32_t promisc;
873
874 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
875
876 /*Vlan Filtering related */
877 eventhandler_tag vlan_attach;
878 eventhandler_tag vlan_detach;
879 uint16_t vlans_added;
880 uint8_t vlan_tag[MAX_VLANS];
881 /*stats */
882 OCE_DMA_MEM stats_mem;
883 struct oce_drv_stats oce_stats_info;
884 struct callout timer;
885 int8_t be3_native;
886 uint16_t qnq_debug_event;
887 uint16_t qnqid;
888 uint16_t pvid;
889
890 } OCE_SOFTC, *POCE_SOFTC;
891
892
893
894 /**************************************************
895 * BUS memory read/write macros
896 * BE3: accesses three BAR spaces (CFG, CSR, DB)
897 * Lancer: accesses one BAR space (CFG)
898 **************************************************/
899 #define OCE_READ_CSR_MPU(sc, space, o) \
900 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
901 (sc)->space##_bhandle,o)) \
902 : (bus_space_read_4((sc)->devcfg_btag, \
903 (sc)->devcfg_bhandle,o)))
904 #define OCE_READ_REG32(sc, space, o) \
905 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
906 (sc)->space##_bhandle,o)) \
907 : (bus_space_read_4((sc)->devcfg_btag, \
908 (sc)->devcfg_bhandle,o)))
909 #define OCE_READ_REG16(sc, space, o) \
910 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
911 (sc)->space##_bhandle,o)) \
912 : (bus_space_read_2((sc)->devcfg_btag, \
913 (sc)->devcfg_bhandle,o)))
914 #define OCE_READ_REG8(sc, space, o) \
915 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
916 (sc)->space##_bhandle,o)) \
917 : (bus_space_read_1((sc)->devcfg_btag, \
918 (sc)->devcfg_bhandle,o)))
919
920 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
921 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
922 (sc)->space##_bhandle,o,v)) \
923 : (bus_space_write_4((sc)->devcfg_btag, \
924 (sc)->devcfg_bhandle,o,v)))
925 #define OCE_WRITE_REG32(sc, space, o, v) \
926 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
927 (sc)->space##_bhandle,o,v)) \
928 : (bus_space_write_4((sc)->devcfg_btag, \
929 (sc)->devcfg_bhandle,o,v)))
930 #define OCE_WRITE_REG16(sc, space, o, v) \
931 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
932 (sc)->space##_bhandle,o,v)) \
933 : (bus_space_write_2((sc)->devcfg_btag, \
934 (sc)->devcfg_bhandle,o,v)))
935 #define OCE_WRITE_REG8(sc, space, o, v) \
936 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
937 (sc)->space##_bhandle,o,v)) \
938 : (bus_space_write_1((sc)->devcfg_btag, \
939 (sc)->devcfg_bhandle,o,v)))
940
941
942 /***********************************************************
943 * DMA memory functions
944 ***********************************************************/
945 #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f)
946 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
947 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
948 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
949 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
950 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
951 uint32_t q_len, uint32_t num_entries);
952 /************************************************************
953 * oce_hw_xxx functions
954 ************************************************************/
955 int oce_clear_rx_buf(struct oce_rq *rq);
956 int oce_hw_pci_alloc(POCE_SOFTC sc);
957 int oce_hw_init(POCE_SOFTC sc);
958 int oce_hw_start(POCE_SOFTC sc);
959 int oce_create_nw_interface(POCE_SOFTC sc);
960 int oce_pci_soft_reset(POCE_SOFTC sc);
961 int oce_hw_update_multicast(POCE_SOFTC sc);
962 void oce_delete_nw_interface(POCE_SOFTC sc);
963 void oce_hw_shutdown(POCE_SOFTC sc);
964 void oce_hw_intr_enable(POCE_SOFTC sc);
965 void oce_hw_intr_disable(POCE_SOFTC sc);
966 void oce_hw_pci_free(POCE_SOFTC sc);
967
968 /***********************************************************
969 * oce_queue_xxx functions
970 ***********************************************************/
971 int oce_queue_init_all(POCE_SOFTC sc);
972 int oce_start_rq(struct oce_rq *rq);
973 int oce_start_wq(struct oce_wq *wq);
974 int oce_start_mq(struct oce_mq *mq);
975 int oce_start_rx(POCE_SOFTC sc);
976 void oce_arm_eq(POCE_SOFTC sc,
977 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
978 void oce_queue_release_all(POCE_SOFTC sc);
979 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
980 void oce_drain_eq(struct oce_eq *eq);
981 void oce_drain_mq_cq(void *arg);
982 void oce_drain_rq_cq(struct oce_rq *rq);
983 void oce_drain_wq_cq(struct oce_wq *wq);
984
985 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
986
987 /***********************************************************
988 * cleanup functions
989 ***********************************************************/
990 void oce_stop_rx(POCE_SOFTC sc);
991 void oce_intr_free(POCE_SOFTC sc);
992 void oce_free_posted_rxbuf(struct oce_rq *rq);
993 #if defined(INET6) || defined(INET)
994 void oce_free_lro(POCE_SOFTC sc);
995 #endif
996
997
998 /************************************************************
999 * Mailbox functions
1000 ************************************************************/
1001 int oce_fw_clean(POCE_SOFTC sc);
1002 int oce_reset_fun(POCE_SOFTC sc);
1003 int oce_mbox_init(POCE_SOFTC sc);
1004 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
1005 int oce_get_fw_version(POCE_SOFTC sc);
1006 int oce_first_mcc_cmd(POCE_SOFTC sc);
1007
1008 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1009 uint8_t type, struct mac_address_format *mac);
1010 int oce_get_fw_config(POCE_SOFTC sc);
1011 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1012 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1013 int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1014 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1015 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1016 uint32_t untagged, uint32_t enable_promisc);
1017 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1018 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1019 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable);
1020 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1021 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1022 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1023 int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1024 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1025 uint32_t reset_stats);
1026 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1027 uint32_t req_size, uint32_t reset_stats);
1028 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1029 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1030 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1031 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1032 uint32_t if_id, uint32_t *pmac_id);
1033 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1034 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1035 uint64_t pattern);
1036
1037 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1038 uint8_t loopback_type, uint8_t enable);
1039
1040 int oce_mbox_check_native_mode(POCE_SOFTC sc);
1041 int oce_mbox_post(POCE_SOFTC sc,
1042 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1043 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1044 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1045 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1046 uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1047 uint32_t *written_data, uint32_t *additional_status);
1048
1049 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1050 uint32_t offset, uint32_t optype);
1051 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1052 int oce_mbox_create_rq(struct oce_rq *rq);
1053 int oce_mbox_create_wq(struct oce_wq *wq);
1054 int oce_mbox_create_eq(struct oce_eq *eq);
1055 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1056 uint32_t is_eventable);
1057 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1058 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1059 int num);
1060 int oce_get_profile_config(POCE_SOFTC sc);
1061 int oce_get_func_config(POCE_SOFTC sc);
1062 void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1063 uint8_t dom,
1064 uint8_t port,
1065 uint8_t subsys,
1066 uint8_t opcode,
1067 uint32_t timeout, uint32_t pyld_len,
1068 uint8_t version);
1069
1070
1071 uint16_t oce_mq_handler(void *arg);
1072
1073 /************************************************************
1074 * Transmit functions
1075 ************************************************************/
1076 uint16_t oce_wq_handler(void *arg);
1077 void oce_start_locked(struct ifnet *ifp);
1078 void oce_start(struct ifnet *ifp, struct ifaltq_subque *ifsq);
1079 void oce_tx_task(void *arg, int npending);
1080
1081 /************************************************************
1082 * Receive functions
1083 ************************************************************/
1084 int oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1085 uint16_t oce_rq_handler(void *arg);
1086
1087
1088 /* Sysctl functions */
1089 void oce_add_sysctls(POCE_SOFTC sc);
1090 void oce_refresh_queue_stats(POCE_SOFTC sc);
1091 int oce_refresh_nic_stats(POCE_SOFTC sc);
1092 int oce_stats_init(POCE_SOFTC sc);
1093 void oce_stats_free(POCE_SOFTC sc);
1094
1095 /* Capabilities */
1096 #define OCE_MODCAP_RSS 1
1097 #define OCE_MAX_RSP_HANDLED 64
1098 extern uint32_t oce_max_rsp_handled; /* max responses */
1099
1100 #define OCE_MAC_LOOPBACK 0x0
1101 #define OCE_PHY_LOOPBACK 0x1
1102 #define OCE_ONE_PORT_EXT_LOOPBACK 0x2
1103 #define OCE_NO_LOOPBACK 0xff
1104
1105 #define atomic_inc_32(x) atomic_add_32(x, 1)
1106 #define atomic_dec_32(x) atomic_subtract_32(x, 1)
1107
1108 #define LE_64(x) htole64(x)
1109 #define LE_32(x) htole32(x)
1110 #define LE_16(x) htole16(x)
1111 #define HOST_64(x) le64toh(x)
1112 #define HOST_32(x) le32toh(x)
1113 #define HOST_16(x) le16toh(x)
1114 #define DW_SWAP(x, l)
1115 #define IS_ALIGNED(x,a) ((x % a) == 0)
1116 #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32))
1117 #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff));
1118
1119 #define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0)
1120 #define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0)
1121 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0)
1122
1123 #define OCE_LOG2(x) (oce_highbit(x))
oce_highbit(uint32_t x)1124 static inline uint32_t oce_highbit(uint32_t x)
1125 {
1126 int i;
1127 int c;
1128 int b;
1129
1130 c = 0;
1131 b = 0;
1132
1133 for (i = 0; i < 32; i++) {
1134 if ((1 << i) & x) {
1135 c++;
1136 b = i;
1137 }
1138 }
1139
1140 if (c == 1)
1141 return b;
1142
1143 return 0;
1144 }
1145
MPU_EP_SEMAPHORE(POCE_SOFTC sc)1146 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1147 {
1148 if (IS_BE(sc))
1149 return MPU_EP_SEMAPHORE_BE3;
1150 else if (IS_SH(sc))
1151 return MPU_EP_SEMAPHORE_SH;
1152 else
1153 return MPU_EP_SEMAPHORE_XE201;
1154 }
1155
1156 #define TRANSCEIVER_DATA_NUM_ELE 64
1157 #define TRANSCEIVER_DATA_SIZE 256
1158 #define TRANSCEIVER_A0_SIZE 128
1159 #define TRANSCEIVER_A2_SIZE 128
1160 #define PAGE_NUM_A0 0xa0
1161 #define PAGE_NUM_A2 0xa2
1162 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1163 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1164