1 /*-
2 * Copyright (c) 2011 Chelsio Communications, Inc.
3 * All rights reserved.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 *
29 */
30
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
33
34 #include <sys/kernel.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/types.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
41 #include <sys/sx.h>
42 #include <sys/vmem.h>
43 #include <vm/uma.h>
44
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47 #include <machine/bus.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <net/ethernet.h>
51 #include <net/if.h>
52 #include <net/if_var.h>
53 #include <net/if_media.h>
54 #include <netinet/in.h>
55 #include <netinet/tcp_lro.h>
56
57 #include "offload.h"
58 #include "t4_ioctl.h"
59 #include "common/t4_msg.h"
60 #include "firmware/t4fw_interface.h"
61
62 #define KTR_CXGBE KTR_SPARE3
63 MALLOC_DECLARE(M_CXGBE);
64 #define CXGBE_UNIMPLEMENTED(s) \
65 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
66
67 #if defined(__i386__) || defined(__amd64__)
68 static __inline void
prefetch(void * x)69 prefetch(void *x)
70 {
71 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
72 }
73 #else
74 #define prefetch(x) __builtin_prefetch(x)
75 #endif
76
77 #ifndef SYSCTL_ADD_UQUAD
78 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
79 #define sysctl_handle_64 sysctl_handle_quad
80 #define CTLTYPE_U64 CTLTYPE_QUAD
81 #endif
82
83 SYSCTL_DECL(_hw_cxgbe);
84
85 struct adapter;
86 typedef struct adapter adapter_t;
87
88 enum {
89 /*
90 * All ingress queues use this entry size. Note that the firmware event
91 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
92 * be at least 64.
93 */
94 IQ_ESIZE = 64,
95
96 /* Default queue sizes for all kinds of ingress queues */
97 FW_IQ_QSIZE = 256,
98 RX_IQ_QSIZE = 1024,
99
100 /* All egress queues use this entry size */
101 EQ_ESIZE = 64,
102
103 /* Default queue sizes for all kinds of egress queues */
104 CTRL_EQ_QSIZE = 1024,
105 TX_EQ_QSIZE = 1024,
106
107 #if MJUMPAGESIZE != MCLBYTES
108 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
109 #else
110 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
111 #endif
112 CL_METADATA_SIZE = CACHE_LINE_SIZE,
113
114 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
115 TX_SGL_SEGS = 39,
116 TX_SGL_SEGS_TSO = 38,
117 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */
118 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
119 };
120
121 enum {
122 /* adapter intr_type */
123 INTR_INTX = (1 << 0),
124 INTR_MSI = (1 << 1),
125 INTR_MSIX = (1 << 2)
126 };
127
128 enum {
129 XGMAC_MTU = (1 << 0),
130 XGMAC_PROMISC = (1 << 1),
131 XGMAC_ALLMULTI = (1 << 2),
132 XGMAC_VLANEX = (1 << 3),
133 XGMAC_UCADDR = (1 << 4),
134 XGMAC_MCADDRS = (1 << 5),
135
136 XGMAC_ALL = 0xffff
137 };
138
139 enum {
140 /* flags understood by begin_synchronized_op */
141 HOLD_LOCK = (1 << 0),
142 SLEEP_OK = (1 << 1),
143 INTR_OK = (1 << 2),
144
145 /* flags understood by end_synchronized_op */
146 LOCK_HELD = HOLD_LOCK,
147 };
148
149 enum {
150 /* adapter flags */
151 FULL_INIT_DONE = (1 << 0),
152 FW_OK = (1 << 1),
153 CHK_MBOX_ACCESS = (1 << 2),
154 MASTER_PF = (1 << 3),
155 ADAP_SYSCTL_CTX = (1 << 4),
156 ADAP_ERR = (1 << 5),
157 BUF_PACKING_OK = (1 << 6),
158 IS_VF = (1 << 7),
159
160 CXGBE_BUSY = (1 << 9),
161
162 /* port flags */
163 HAS_TRACEQ = (1 << 3),
164 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
165
166 /* VI flags */
167 DOOMED = (1 << 0),
168 VI_INIT_DONE = (1 << 1),
169 VI_SYSCTL_CTX = (1 << 2),
170
171 /* adapter debug_flags */
172 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
173 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
174 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
175 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
176 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
177 };
178
179 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
180 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
181 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
182 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
183 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
184
185 struct vi_info {
186 device_t dev;
187 struct port_info *pi;
188
189 struct ifnet *ifp;
190
191 unsigned long flags;
192 int if_flags;
193
194 uint16_t *rss, *nm_rss;
195 uint16_t viid; /* opaque VI identifier */
196 uint16_t smt_idx;
197 uint16_t vin;
198 uint8_t vfvld;
199 int16_t xact_addr_filt;/* index of exact MAC address filter */
200 uint16_t rss_size; /* size of VI's RSS table slice */
201 uint16_t rss_base; /* start of VI's RSS table slice */
202
203 int nintr;
204 int first_intr;
205
206 /* These need to be int as they are used in sysctl */
207 int ntxq; /* # of tx queues */
208 int first_txq; /* index of first tx queue */
209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
210 int nrxq; /* # of rx queues */
211 int first_rxq; /* index of first rx queue */
212 int nofldtxq; /* # of offload tx queues */
213 int first_ofld_txq; /* index of first offload tx queue */
214 int nofldrxq; /* # of offload rx queues */
215 int first_ofld_rxq; /* index of first offload rx queue */
216 int nnmtxq;
217 int first_nm_txq;
218 int nnmrxq;
219 int first_nm_rxq;
220 int tmr_idx;
221 int ofld_tmr_idx;
222 int pktc_idx;
223 int ofld_pktc_idx;
224 int qsize_rxq;
225 int qsize_txq;
226
227 struct timeval last_refreshed;
228 struct fw_vi_stats_vf stats;
229
230 struct callout tick;
231 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
232
233 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
234 };
235
236 struct tx_ch_rl_params {
237 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
238 uint32_t maxrate;
239 };
240
241 enum {
242 CLRL_USER = (1 << 0), /* allocated manually. */
243 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */
244 CLRL_ASYNC = (1 << 2), /* async hw update requested. */
245 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */
246 };
247
248 struct tx_cl_rl_params {
249 int refcount;
250 uint8_t flags;
251 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
252 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
253 enum fw_sched_params_mode mode; /* aggr or per-flow */
254 uint32_t maxrate;
255 uint16_t pktsize;
256 uint16_t burstsize;
257 };
258
259 /* Tx scheduler parameters for a channel/port */
260 struct tx_sched_params {
261 /* Channel Rate Limiter */
262 struct tx_ch_rl_params ch_rl;
263
264 /* Class WRR */
265 /* XXX */
266
267 /* Class Rate Limiter (including the default pktsize and burstsize). */
268 int pktsize;
269 int burstsize;
270 struct tx_cl_rl_params cl_rl[];
271 };
272
273 struct port_info {
274 device_t dev;
275 struct adapter *adapter;
276
277 struct vi_info *vi;
278 int nvi;
279 int up_vis;
280 int uld_vis;
281
282 struct tx_sched_params *sched_params;
283
284 struct mtx pi_lock;
285 char lockname[16];
286 unsigned long flags;
287
288 uint8_t lport; /* associated offload logical port */
289 int8_t mdio_addr;
290 uint8_t port_type;
291 uint8_t mod_type;
292 uint8_t port_id;
293 uint8_t tx_chan;
294 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
295 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
296
297 struct link_config link_cfg;
298 struct ifmedia media;
299
300 struct timeval last_refreshed;
301 struct port_stats stats;
302 u_int tnl_cong_drops;
303 u_int tx_parse_error;
304 u_long tx_tls_records;
305 u_long tx_tls_octets;
306 u_long rx_tls_records;
307 u_long rx_tls_octets;
308
309 struct callout tick;
310 };
311
312 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
313
314 /* Where the cluster came from, how it has been carved up. */
315 struct cluster_layout {
316 int8_t zidx;
317 int8_t hwidx;
318 uint16_t region1; /* mbufs laid out within this region */
319 /* region2 is the DMA region */
320 uint16_t region3; /* cluster_metadata within this region */
321 };
322
323 struct cluster_metadata {
324 u_int refcount;
325 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
326 };
327
328 struct fl_sdesc {
329 caddr_t cl;
330 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
331 struct cluster_layout cll;
332 };
333
334 struct tx_desc {
335 __be64 flit[8];
336 };
337
338 struct tx_sdesc {
339 struct mbuf *m; /* m_nextpkt linked chain of frames */
340 uint8_t desc_used; /* # of hardware descriptors used by the WR */
341 };
342
343
344 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
345 struct iq_desc {
346 struct rss_header rss;
347 uint8_t cpl[IQ_PAD];
348 struct rsp_ctrl rsp;
349 };
350 #undef IQ_PAD
351 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
352
353 enum {
354 /* iq flags */
355 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
356 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
357 /* 1 << 2 Used to be IQ_INTR */
358 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
359 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
360
361 /* iq state */
362 IQS_DISABLED = 0,
363 IQS_BUSY = 1,
364 IQS_IDLE = 2,
365
366 /* netmap related flags */
367 NM_OFF = 0,
368 NM_ON = 1,
369 NM_BUSY = 2,
370 };
371
372 enum {
373 CPL_COOKIE_RESERVED = 0,
374 CPL_COOKIE_FILTER,
375 CPL_COOKIE_DDP0,
376 CPL_COOKIE_DDP1,
377 CPL_COOKIE_TOM,
378 CPL_COOKIE_HASHFILTER,
379 CPL_COOKIE_ETHOFLD,
380 CPL_COOKIE_AVAILABLE3,
381
382 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
383 };
384
385 struct sge_iq;
386 struct rss_header;
387 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
388 struct mbuf *);
389 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
390 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
391
392 /*
393 * Ingress Queue: T4 is producer, driver is consumer.
394 */
395 struct sge_iq {
396 uint32_t flags;
397 volatile int state;
398 struct adapter *adapter;
399 struct iq_desc *desc; /* KVA of descriptor ring */
400 int8_t intr_pktc_idx; /* packet count threshold index */
401 uint8_t gen; /* generation bit */
402 uint8_t intr_params; /* interrupt holdoff parameters */
403 uint8_t intr_next; /* XXX: holdoff for next interrupt */
404 uint16_t qsize; /* size (# of entries) of the queue */
405 uint16_t sidx; /* index of the entry with the status page */
406 uint16_t cidx; /* consumer index */
407 uint16_t cntxt_id; /* SGE context id for the iq */
408 uint16_t abs_id; /* absolute SGE id for the iq */
409
410 STAILQ_ENTRY(sge_iq) link;
411
412 bus_dma_tag_t desc_tag;
413 bus_dmamap_t desc_map;
414 bus_addr_t ba; /* bus address of descriptor ring */
415 };
416
417 enum {
418 EQ_CTRL = 1,
419 EQ_ETH = 2,
420 EQ_OFLD = 3,
421
422 /* eq flags */
423 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
424 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
425 EQ_ENABLED = (1 << 3), /* open for business */
426 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
427 };
428
429 /* Listed in order of preference. Update t4_sysctls too if you change these */
430 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
431
432 /*
433 * Egress Queue: driver is producer, T4 is consumer.
434 *
435 * Note: A free list is an egress queue (driver produces the buffers and T4
436 * consumes them) but it's special enough to have its own struct (see sge_fl).
437 */
438 struct sge_eq {
439 unsigned int flags; /* MUST be first */
440 unsigned int cntxt_id; /* SGE context id for the eq */
441 unsigned int abs_id; /* absolute SGE id for the eq */
442 struct mtx eq_lock;
443
444 struct tx_desc *desc; /* KVA of descriptor ring */
445 uint8_t doorbells;
446 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
447 u_int udb_qid; /* relative qid within the doorbell page */
448 uint16_t sidx; /* index of the entry with the status page */
449 uint16_t cidx; /* consumer idx (desc idx) */
450 uint16_t pidx; /* producer idx (desc idx) */
451 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
452 uint16_t dbidx; /* pidx of the most recent doorbell */
453 uint16_t iqid; /* iq that gets egr_update for the eq */
454 uint8_t tx_chan; /* tx channel used by the eq */
455 volatile u_int equiq; /* EQUIQ outstanding */
456
457 bus_dma_tag_t desc_tag;
458 bus_dmamap_t desc_map;
459 bus_addr_t ba; /* bus address of descriptor ring */
460 char lockname[16];
461 };
462
463 struct sw_zone_info {
464 uma_zone_t zone; /* zone that this cluster comes from */
465 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
466 int type; /* EXT_xxx type of the cluster */
467 int8_t head_hwidx;
468 int8_t tail_hwidx;
469 };
470
471 struct hw_buf_info {
472 int8_t zidx; /* backpointer to zone; -ve means unused */
473 int8_t next; /* next hwidx for this zone; -1 means no more */
474 int size;
475 };
476
477 enum {
478 NUM_MEMWIN = 3,
479
480 MEMWIN0_APERTURE = 2048,
481 MEMWIN0_BASE = 0x1b800,
482
483 MEMWIN1_APERTURE = 32768,
484 MEMWIN1_BASE = 0x28000,
485
486 MEMWIN2_APERTURE_T4 = 65536,
487 MEMWIN2_BASE_T4 = 0x30000,
488
489 MEMWIN2_APERTURE_T5 = 128 * 1024,
490 MEMWIN2_BASE_T5 = 0x60000,
491 };
492
493 struct memwin {
494 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
495 uint32_t mw_base; /* constant after setup_memwin */
496 uint32_t mw_aperture; /* ditto */
497 uint32_t mw_curpos; /* protected by mw_lock */
498 };
499
500 enum {
501 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
502 FL_DOOMED = (1 << 1), /* about to be destroyed */
503 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
504 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
505 };
506
507 #define FL_RUNNING_LOW(fl) \
508 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
509 #define FL_NOT_RUNNING_LOW(fl) \
510 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
511
512 struct sge_fl {
513 struct mtx fl_lock;
514 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
515 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
516 struct cluster_layout cll_def; /* default refill zone, layout */
517 uint16_t lowat; /* # of buffers <= this means fl needs help */
518 int flags;
519 uint16_t buf_boundary;
520
521 /* The 16b idx all deal with hw descriptors */
522 uint16_t dbidx; /* hw pidx after last doorbell */
523 uint16_t sidx; /* index of status page */
524 volatile uint16_t hw_cidx;
525
526 /* The 32b idx are all buffer idx, not hardware descriptor idx */
527 uint32_t cidx; /* consumer index */
528 uint32_t pidx; /* producer index */
529
530 uint32_t dbval;
531 u_int rx_offset; /* offset in fl buf (when buffer packing) */
532 volatile uint32_t *udb;
533
534 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
535 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
536 uint64_t cl_allocated; /* # of clusters allocated */
537 uint64_t cl_recycled; /* # of clusters recycled */
538 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
539
540 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
541 struct mbuf *m0;
542 struct mbuf **pnext;
543 u_int remaining;
544
545 uint16_t qsize; /* # of hw descriptors (status page included) */
546 uint16_t cntxt_id; /* SGE context id for the freelist */
547 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
548 bus_dma_tag_t desc_tag;
549 bus_dmamap_t desc_map;
550 char lockname[16];
551 bus_addr_t ba; /* bus address of descriptor ring */
552 struct cluster_layout cll_alt; /* alternate refill zone, layout */
553 };
554
555 struct mp_ring;
556
557 /* txq: SGE egress queue + what's needed for Ethernet NIC */
558 struct sge_txq {
559 struct sge_eq eq; /* MUST be first */
560
561 struct ifnet *ifp; /* the interface this txq belongs to */
562 struct mp_ring *r; /* tx software ring */
563 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
564 struct sglist *gl;
565 __be32 cpl_ctrl0; /* for convenience */
566 int tc_idx; /* traffic class */
567
568 struct task tx_reclaim_task;
569 /* stats for common events first */
570
571 uint64_t txcsum; /* # of times hardware assisted with checksum */
572 uint64_t tso_wrs; /* # of TSO work requests */
573 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
574 uint64_t imm_wrs; /* # of work requests with immediate data */
575 uint64_t sgl_wrs; /* # of work requests with direct SGL */
576 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
577 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
578 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
579 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
580 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
581
582 /* stats for not-that-common events */
583 } __aligned(CACHE_LINE_SIZE);
584
585 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
586 struct sge_rxq {
587 struct sge_iq iq; /* MUST be first */
588 struct sge_fl fl; /* MUST follow iq */
589
590 struct ifnet *ifp; /* the interface this rxq belongs to */
591 #if defined(INET) || defined(INET6)
592 struct lro_ctrl lro; /* LRO state */
593 #endif
594
595 /* stats for common events first */
596
597 uint64_t rxcsum; /* # of times hardware assisted with checksum */
598 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
599
600 /* stats for not-that-common events */
601
602 } __aligned(CACHE_LINE_SIZE);
603
604 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)605 iq_to_rxq(struct sge_iq *iq)
606 {
607
608 return (__containerof(iq, struct sge_rxq, iq));
609 }
610
611
612 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
613 struct sge_ofld_rxq {
614 struct sge_iq iq; /* MUST be first */
615 struct sge_fl fl; /* MUST follow iq */
616 } __aligned(CACHE_LINE_SIZE);
617
618 static inline struct sge_ofld_rxq *
iq_to_ofld_rxq(struct sge_iq * iq)619 iq_to_ofld_rxq(struct sge_iq *iq)
620 {
621
622 return (__containerof(iq, struct sge_ofld_rxq, iq));
623 }
624
625 struct wrqe {
626 STAILQ_ENTRY(wrqe) link;
627 struct sge_wrq *wrq;
628 int wr_len;
629 char wr[] __aligned(16);
630 };
631
632 struct wrq_cookie {
633 TAILQ_ENTRY(wrq_cookie) link;
634 int ndesc;
635 int pidx;
636 };
637
638 /*
639 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
640 * and offload tx queues are of this type.
641 */
642 struct sge_wrq {
643 struct sge_eq eq; /* MUST be first */
644
645 struct adapter *adapter;
646 struct task wrq_tx_task;
647
648 /* Tx desc reserved but WR not "committed" yet. */
649 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
650
651 /* List of WRs ready to go out as soon as descriptors are available. */
652 STAILQ_HEAD(, wrqe) wr_list;
653 u_int nwr_pending;
654 u_int ndesc_needed;
655
656 /* stats for common events first */
657
658 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
659 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
660 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
661
662 /* stats for not-that-common events */
663
664 /*
665 * Scratch space for work requests that wrap around after reaching the
666 * status page, and some information about the last WR that used it.
667 */
668 uint16_t ss_pidx;
669 uint16_t ss_len;
670 uint8_t ss[SGE_MAX_WR_LEN];
671
672 } __aligned(CACHE_LINE_SIZE);
673
674
675 struct sge_nm_rxq {
676 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
677 struct vi_info *vi;
678
679 struct iq_desc *iq_desc;
680 uint16_t iq_abs_id;
681 uint16_t iq_cntxt_id;
682 uint16_t iq_cidx;
683 uint16_t iq_sidx;
684 uint8_t iq_gen;
685
686 __be64 *fl_desc;
687 uint16_t fl_cntxt_id;
688 uint32_t fl_cidx;
689 uint32_t fl_pidx;
690 uint32_t fl_sidx;
691 uint32_t fl_db_val;
692 u_int fl_hwidx:4;
693
694 u_int nid; /* netmap ring # for this queue */
695
696 /* infrequently used items after this */
697
698 bus_dma_tag_t iq_desc_tag;
699 bus_dmamap_t iq_desc_map;
700 bus_addr_t iq_ba;
701 int intr_idx;
702
703 bus_dma_tag_t fl_desc_tag;
704 bus_dmamap_t fl_desc_map;
705 bus_addr_t fl_ba;
706 } __aligned(CACHE_LINE_SIZE);
707
708 struct sge_nm_txq {
709 struct tx_desc *desc;
710 uint16_t cidx;
711 uint16_t pidx;
712 uint16_t sidx;
713 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
714 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
715 uint16_t dbidx; /* pidx of the most recent doorbell */
716 uint8_t doorbells;
717 volatile uint32_t *udb;
718 u_int udb_qid;
719 u_int cntxt_id;
720 __be32 cpl_ctrl0; /* for convenience */
721 u_int nid; /* netmap ring # for this queue */
722
723 /* infrequently used items after this */
724
725 bus_dma_tag_t desc_tag;
726 bus_dmamap_t desc_map;
727 bus_addr_t ba;
728 int iqidx;
729 } __aligned(CACHE_LINE_SIZE);
730
731 struct sge {
732 int nrxq; /* total # of Ethernet rx queues */
733 int ntxq; /* total # of Ethernet tx queues */
734 int nofldrxq; /* total # of TOE rx queues */
735 int nofldtxq; /* total # of TOE tx queues */
736 int nnmrxq; /* total # of netmap rx queues */
737 int nnmtxq; /* total # of netmap tx queues */
738 int niq; /* total # of ingress queues */
739 int neq; /* total # of egress queues */
740
741 struct sge_iq fwq; /* Firmware event queue */
742 struct sge_wrq *ctrlq; /* Control queues */
743 struct sge_txq *txq; /* NIC tx queues */
744 struct sge_rxq *rxq; /* NIC rx queues */
745 struct sge_wrq *ofld_txq; /* TOE tx queues */
746 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
747 struct sge_nm_txq *nm_txq; /* netmap tx queues */
748 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
749
750 uint16_t iq_start; /* first cntxt_id */
751 uint16_t iq_base; /* first abs_id */
752 int eq_start; /* first cntxt_id */
753 int eq_base; /* first abs_id */
754 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
755 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
756
757 int8_t safe_hwidx1; /* may not have room for metadata */
758 int8_t safe_hwidx2; /* with room for metadata and maybe more */
759 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
760 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
761 };
762
763 struct devnames {
764 const char *nexus_name;
765 const char *ifnet_name;
766 const char *vi_ifnet_name;
767 const char *pf03_drv_name;
768 const char *vf_nexus_name;
769 const char *vf_ifnet_name;
770 };
771
772 struct clip_entry;
773
774 struct adapter {
775 SLIST_ENTRY(adapter) link;
776 device_t dev;
777 struct cdev *cdev;
778 const struct devnames *names;
779
780 /* PCIe register resources */
781 int regs_rid;
782 struct resource *regs_res;
783 int msix_rid;
784 struct resource *msix_res;
785 bus_space_handle_t bh;
786 bus_space_tag_t bt;
787 bus_size_t mmio_len;
788 int udbs_rid;
789 struct resource *udbs_res;
790 volatile uint8_t *udbs_base;
791
792 unsigned int pf;
793 unsigned int mbox;
794 unsigned int vpd_busy;
795 unsigned int vpd_flag;
796
797 /* Interrupt information */
798 int intr_type;
799 int intr_count;
800 struct irq {
801 struct resource *res;
802 int rid;
803 void *tag;
804 struct sge_rxq *rxq;
805 struct sge_nm_rxq *nm_rxq;
806 } __aligned(CACHE_LINE_SIZE) *irq;
807 int sge_gts_reg;
808 int sge_kdoorbell_reg;
809
810 bus_dma_tag_t dmat; /* Parent DMA tag */
811
812 struct sge sge;
813 int lro_timeout;
814 int sc_do_rxcopy;
815
816 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
817 struct port_info *port[MAX_NPORTS];
818 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
819
820 struct mtx clip_table_lock;
821 TAILQ_HEAD(, clip_entry) clip_table;
822 int clip_gen;
823
824 void *tom_softc; /* (struct tom_data *) */
825 struct tom_tunables tt;
826 struct t4_offload_policy *policy;
827 struct rwlock policy_lock;
828
829 void *iwarp_softc; /* (struct c4iw_dev *) */
830 struct iw_tunables iwt;
831 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
832 void *ccr_softc; /* (struct ccr_softc *) */
833 struct l2t_data *l2t; /* L2 table */
834 struct smt_data *smt; /* Source MAC Table */
835 struct tid_info tids;
836 vmem_t *key_map;
837
838 uint8_t doorbells;
839 int offload_map; /* ports with IFCAP_TOE enabled */
840 int active_ulds; /* ULDs activated on this adapter */
841 int flags;
842 int debug_flags;
843
844 char ifp_lockname[16];
845 struct mtx ifp_lock;
846 struct ifnet *ifp; /* tracer ifp */
847 struct ifmedia media;
848 int traceq; /* iq used by all tracers, -1 if none */
849 int tracer_valid; /* bitmap of valid tracers */
850 int tracer_enabled; /* bitmap of enabled tracers */
851
852 char fw_version[16];
853 char tp_version[16];
854 char er_version[16];
855 char bs_version[16];
856 char cfg_file[32];
857 u_int cfcsum;
858 struct adapter_params params;
859 const struct chip_params *chip_params;
860 struct t4_virt_res vres;
861
862 uint16_t nbmcaps;
863 uint16_t linkcaps;
864 uint16_t switchcaps;
865 uint16_t niccaps;
866 uint16_t toecaps;
867 uint16_t rdmacaps;
868 uint16_t cryptocaps;
869 uint16_t iscsicaps;
870 uint16_t fcoecaps;
871
872 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
873
874 struct mtx sc_lock;
875 char lockname[16];
876
877 /* Starving free lists */
878 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
879 TAILQ_HEAD(, sge_fl) sfl;
880 struct callout sfl_callout;
881
882 struct mtx reg_lock; /* for indirect register access */
883
884 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
885
886 struct mtx tc_lock;
887 struct task tc_task;
888
889 const char *last_op;
890 const void *last_op_thr;
891 int last_op_flags;
892
893 int swintr;
894 };
895
896 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
897 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
898 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
899 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
900
901 #define ASSERT_SYNCHRONIZED_OP(sc) \
902 KASSERT(IS_BUSY(sc) && \
903 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
904 ("%s: operation not synchronized.", __func__))
905
906 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
907 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
908 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
909 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
910
911 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
912 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
913 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
914 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
915 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
916
917 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
918 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
919 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
920 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
921
922 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
923 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
924 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
925 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
926 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
927
928 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
929 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
930 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
931 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
932 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
933
934 #define for_each_txq(vi, iter, q) \
935 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
936 iter < vi->ntxq; ++iter, ++q)
937 #define for_each_rxq(vi, iter, q) \
938 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
939 iter < vi->nrxq; ++iter, ++q)
940 #define for_each_ofld_txq(vi, iter, q) \
941 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
942 iter < vi->nofldtxq; ++iter, ++q)
943 #define for_each_ofld_rxq(vi, iter, q) \
944 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
945 iter < vi->nofldrxq; ++iter, ++q)
946 #define for_each_nm_txq(vi, iter, q) \
947 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
948 iter < vi->nnmtxq; ++iter, ++q)
949 #define for_each_nm_rxq(vi, iter, q) \
950 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
951 iter < vi->nnmrxq; ++iter, ++q)
952 #define for_each_vi(_pi, _iter, _vi) \
953 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
954 ++(_iter), ++(_vi))
955
956 #define IDXINCR(idx, incr, wrap) do { \
957 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
958 } while (0)
959 #define IDXDIFF(head, tail, wrap) \
960 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
961
962 /* One for errors, one for firmware events */
963 #define T4_EXTRA_INTR 2
964
965 /* One for firmware events */
966 #define T4VF_EXTRA_INTR 1
967
968 static inline int
forwarding_intr_to_fwq(struct adapter * sc)969 forwarding_intr_to_fwq(struct adapter *sc)
970 {
971
972 return (sc->intr_count == 1);
973 }
974
975 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)976 t4_read_reg(struct adapter *sc, uint32_t reg)
977 {
978
979 return bus_space_read_4(sc->bt, sc->bh, reg);
980 }
981
982 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)983 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
984 {
985
986 bus_space_write_4(sc->bt, sc->bh, reg, val);
987 }
988
989 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)990 t4_read_reg64(struct adapter *sc, uint32_t reg)
991 {
992
993 #ifdef __LP64__
994 return bus_space_read_8(sc->bt, sc->bh, reg);
995 #else
996 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
997 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
998
999 #endif
1000 }
1001
1002 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)1003 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1004 {
1005
1006 #ifdef __LP64__
1007 bus_space_write_8(sc->bt, sc->bh, reg, val);
1008 #else
1009 bus_space_write_4(sc->bt, sc->bh, reg, val);
1010 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1011 #endif
1012 }
1013
1014 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)1015 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1016 {
1017
1018 *val = pci_read_config(sc->dev, reg, 1);
1019 }
1020
1021 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)1022 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1023 {
1024
1025 pci_write_config(sc->dev, reg, val, 1);
1026 }
1027
1028 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)1029 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1030 {
1031
1032 *val = pci_read_config(sc->dev, reg, 2);
1033 }
1034
1035 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)1036 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1037 {
1038
1039 pci_write_config(sc->dev, reg, val, 2);
1040 }
1041
1042 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)1043 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1044 {
1045
1046 *val = pci_read_config(sc->dev, reg, 4);
1047 }
1048
1049 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)1050 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1051 {
1052
1053 pci_write_config(sc->dev, reg, val, 4);
1054 }
1055
1056 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)1057 adap2pinfo(struct adapter *sc, int idx)
1058 {
1059
1060 return (sc->port[idx]);
1061 }
1062
1063 static inline void
t4_os_set_hw_addr(struct port_info * pi,uint8_t hw_addr[])1064 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1065 {
1066
1067 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1068 }
1069
1070 static inline int
tx_resume_threshold(struct sge_eq * eq)1071 tx_resume_threshold(struct sge_eq *eq)
1072 {
1073
1074 /* not quite the same as qsize / 4, but this will do. */
1075 return (eq->sidx / 4);
1076 }
1077
1078 static inline int
t4_use_ldst(struct adapter * sc)1079 t4_use_ldst(struct adapter *sc)
1080 {
1081
1082 #ifdef notyet
1083 return (sc->flags & FW_OK || !sc->use_bd);
1084 #else
1085 return (0);
1086 #endif
1087 }
1088
1089 static inline void
CH_DUMP_MBOX(struct adapter * sc,int mbox,const int reg,const char * msg,const __be64 * const p,const bool err)1090 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1091 const char *msg, const __be64 *const p, const bool err)
1092 {
1093
1094 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1095 return;
1096 if (p != NULL) {
1097 log(err ? LOG_ERR : LOG_DEBUG,
1098 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1099 "%016llx %016llx %016llx %016llx\n",
1100 device_get_nameunit(sc->dev), mbox, msg,
1101 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1102 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1103 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1104 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1105 } else {
1106 log(err ? LOG_ERR : LOG_DEBUG,
1107 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1108 "%016llx %016llx %016llx %016llx\n",
1109 device_get_nameunit(sc->dev), mbox, msg,
1110 (long long)t4_read_reg64(sc, reg),
1111 (long long)t4_read_reg64(sc, reg + 8),
1112 (long long)t4_read_reg64(sc, reg + 16),
1113 (long long)t4_read_reg64(sc, reg + 24),
1114 (long long)t4_read_reg64(sc, reg + 32),
1115 (long long)t4_read_reg64(sc, reg + 40),
1116 (long long)t4_read_reg64(sc, reg + 48),
1117 (long long)t4_read_reg64(sc, reg + 56));
1118 }
1119 }
1120
1121 /* t4_main.c */
1122 extern int t4_ntxq;
1123 extern int t4_nrxq;
1124 extern int t4_intr_types;
1125 extern int t4_tmr_idx;
1126 extern int t4_pktc_idx;
1127 extern unsigned int t4_qsize_rxq;
1128 extern unsigned int t4_qsize_txq;
1129 extern device_method_t cxgbe_methods[];
1130
1131 int t4_os_find_pci_capability(struct adapter *, int);
1132 int t4_os_pci_save_state(struct adapter *);
1133 int t4_os_pci_restore_state(struct adapter *);
1134 void t4_os_portmod_changed(struct port_info *);
1135 void t4_os_link_changed(struct port_info *);
1136 void t4_iterate(void (*)(struct adapter *, void *), void *);
1137 void t4_init_devnames(struct adapter *);
1138 void t4_add_adapter(struct adapter *);
1139 void t4_aes_getdeckey(void *, const void *, unsigned int);
1140 int t4_detach_common(device_t);
1141 int t4_map_bars_0_and_4(struct adapter *);
1142 int t4_map_bar_2(struct adapter *);
1143 int t4_setup_intr_handlers(struct adapter *);
1144 void t4_sysctls(struct adapter *);
1145 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1146 void doom_vi(struct adapter *, struct vi_info *);
1147 void end_synchronized_op(struct adapter *, int);
1148 int update_mac_settings(struct ifnet *, int);
1149 int adapter_full_init(struct adapter *);
1150 int adapter_full_uninit(struct adapter *);
1151 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1152 int vi_full_init(struct vi_info *);
1153 int vi_full_uninit(struct vi_info *);
1154 void vi_sysctls(struct vi_info *);
1155 void vi_tick(void *);
1156 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1157 int alloc_atid_tab(struct tid_info *, int);
1158 void free_atid_tab(struct tid_info *);
1159 int alloc_atid(struct adapter *, void *);
1160 void *lookup_atid(struct adapter *, int);
1161 void free_atid(struct adapter *, int);
1162 void release_tid(struct adapter *, int, struct sge_wrq *);
1163 int cxgbe_media_change(struct ifnet *);
1164 void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
1165 bool t4_os_dump_cimla(struct adapter *, int, bool);
1166 void t4_os_dump_devlog(struct adapter *);
1167
1168 #ifdef DEV_NETMAP
1169 /* t4_netmap.c */
1170 struct sge_nm_rxq;
1171 void cxgbe_nm_attach(struct vi_info *);
1172 void cxgbe_nm_detach(struct vi_info *);
1173 void service_nm_rxq(struct sge_nm_rxq *);
1174 #endif
1175
1176 /* t4_sge.c */
1177 void t4_sge_modload(void);
1178 void t4_sge_modunload(void);
1179 uint64_t t4_sge_extfree_refs(void);
1180 void t4_tweak_chip_settings(struct adapter *);
1181 int t4_read_chip_settings(struct adapter *);
1182 int t4_create_dma_tag(struct adapter *);
1183 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1184 struct sysctl_oid_list *);
1185 int t4_destroy_dma_tag(struct adapter *);
1186 int t4_setup_adapter_queues(struct adapter *);
1187 int t4_teardown_adapter_queues(struct adapter *);
1188 int t4_setup_vi_queues(struct vi_info *);
1189 int t4_teardown_vi_queues(struct vi_info *);
1190 void t4_intr_all(void *);
1191 void t4_intr(void *);
1192 #ifdef DEV_NETMAP
1193 void t4_nm_intr(void *);
1194 void t4_vi_intr(void *);
1195 #endif
1196 void t4_intr_err(void *);
1197 void t4_intr_evt(void *);
1198 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1199 void t4_update_fl_bufsize(struct ifnet *);
1200 int parse_pkt(struct adapter *, struct mbuf **);
1201 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1202 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1203 int tnl_cong(struct port_info *, int);
1204 void t4_register_an_handler(an_handler_t);
1205 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1206 void t4_register_cpl_handler(int, cpl_handler_t);
1207 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1208
1209 /* t4_tracer.c */
1210 struct t4_tracer;
1211 void t4_tracer_modload(void);
1212 void t4_tracer_modunload(void);
1213 void t4_tracer_port_detach(struct adapter *);
1214 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1215 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1216 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1217 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1218
1219 /* t4_sched.c */
1220 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1221 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1222 int t4_init_tx_sched(struct adapter *);
1223 int t4_free_tx_sched(struct adapter *);
1224 void t4_update_tx_sched(struct adapter *);
1225 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1226 void t4_release_cl_rl(struct adapter *, int, int);
1227 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1228 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1229
1230 /* t4_filter.c */
1231 int get_filter_mode(struct adapter *, uint32_t *);
1232 int set_filter_mode(struct adapter *, uint32_t);
1233 int get_filter(struct adapter *, struct t4_filter *);
1234 int set_filter(struct adapter *, struct t4_filter *);
1235 int del_filter(struct adapter *, struct t4_filter *);
1236 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1237 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1238 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1239 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1240 void free_hftid_hash(struct tid_info *);
1241
1242 static inline struct wrqe *
alloc_wrqe(int wr_len,struct sge_wrq * wrq)1243 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1244 {
1245 int len = offsetof(struct wrqe, wr) + wr_len;
1246 struct wrqe *wr;
1247
1248 wr = malloc(len, M_CXGBE, M_NOWAIT);
1249 if (__predict_false(wr == NULL))
1250 return (NULL);
1251 wr->wr_len = wr_len;
1252 wr->wrq = wrq;
1253 return (wr);
1254 }
1255
1256 static inline void *
wrtod(struct wrqe * wr)1257 wrtod(struct wrqe *wr)
1258 {
1259 return (&wr->wr[0]);
1260 }
1261
1262 static inline void
free_wrqe(struct wrqe * wr)1263 free_wrqe(struct wrqe *wr)
1264 {
1265 free(wr, M_CXGBE);
1266 }
1267
1268 static inline void
t4_wrq_tx(struct adapter * sc,struct wrqe * wr)1269 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1270 {
1271 struct sge_wrq *wrq = wr->wrq;
1272
1273 TXQ_LOCK(wrq);
1274 t4_wrq_tx_locked(sc, wrq, wr);
1275 TXQ_UNLOCK(wrq);
1276 }
1277
1278 static inline int
read_via_memwin(struct adapter * sc,int idx,uint32_t addr,uint32_t * val,int len)1279 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1280 int len)
1281 {
1282
1283 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1284 }
1285
1286 static inline int
write_via_memwin(struct adapter * sc,int idx,uint32_t addr,const uint32_t * val,int len)1287 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1288 const uint32_t *val, int len)
1289 {
1290
1291 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1292 }
1293 #endif
1294