1 /*-
2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/12/sys/dev/mlx5/mlx5_en/mlx5_en_main.c 371834 2022-04-02 13:44:35Z gbe $
26 */
27
28 #include "en.h"
29
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
32
33 #ifndef ETH_DRIVER_VERSION
34 #define ETH_DRIVER_VERSION "3.6.0"
35 #endif
36 #define DRIVER_RELDATE "December 2020"
37
38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
39 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
40
41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
42
43 struct mlx5e_channel_param {
44 struct mlx5e_rq_param rq;
45 struct mlx5e_sq_param sq;
46 struct mlx5e_cq_param rx_cq;
47 struct mlx5e_cq_param tx_cq;
48 };
49
50 struct media {
51 u32 subtype;
52 u64 baudrate;
53 };
54
55 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
56
57 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
58 .subtype = IFM_1000_CX_SGMII,
59 .baudrate = IF_Mbps(1000ULL),
60 },
61 [MLX5E_1000BASE_KX][MLX5E_KX] = {
62 .subtype = IFM_1000_KX,
63 .baudrate = IF_Mbps(1000ULL),
64 },
65 [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
66 .subtype = IFM_10G_CX4,
67 .baudrate = IF_Gbps(10ULL),
68 },
69 [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
70 .subtype = IFM_10G_KX4,
71 .baudrate = IF_Gbps(10ULL),
72 },
73 [MLX5E_10GBASE_KR][MLX5E_KR] = {
74 .subtype = IFM_10G_KR,
75 .baudrate = IF_Gbps(10ULL),
76 },
77 [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
78 .subtype = IFM_20G_KR2,
79 .baudrate = IF_Gbps(20ULL),
80 },
81 [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
82 .subtype = IFM_40G_CR4,
83 .baudrate = IF_Gbps(40ULL),
84 },
85 [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
86 .subtype = IFM_40G_KR4,
87 .baudrate = IF_Gbps(40ULL),
88 },
89 [MLX5E_56GBASE_R4][MLX5E_R] = {
90 .subtype = IFM_56G_R4,
91 .baudrate = IF_Gbps(56ULL),
92 },
93 [MLX5E_10GBASE_CR][MLX5E_CR1] = {
94 .subtype = IFM_10G_CR1,
95 .baudrate = IF_Gbps(10ULL),
96 },
97 [MLX5E_10GBASE_SR][MLX5E_SR] = {
98 .subtype = IFM_10G_SR,
99 .baudrate = IF_Gbps(10ULL),
100 },
101 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
102 .subtype = IFM_10G_ER,
103 .baudrate = IF_Gbps(10ULL),
104 },
105 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
106 .subtype = IFM_10G_LR,
107 .baudrate = IF_Gbps(10ULL),
108 },
109 [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
110 .subtype = IFM_40G_SR4,
111 .baudrate = IF_Gbps(40ULL),
112 },
113 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
114 .subtype = IFM_40G_LR4,
115 .baudrate = IF_Gbps(40ULL),
116 },
117 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
118 .subtype = IFM_40G_ER4,
119 .baudrate = IF_Gbps(40ULL),
120 },
121 [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
122 .subtype = IFM_100G_CR4,
123 .baudrate = IF_Gbps(100ULL),
124 },
125 [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
126 .subtype = IFM_100G_SR4,
127 .baudrate = IF_Gbps(100ULL),
128 },
129 [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
130 .subtype = IFM_100G_KR4,
131 .baudrate = IF_Gbps(100ULL),
132 },
133 [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
134 .subtype = IFM_100G_LR4,
135 .baudrate = IF_Gbps(100ULL),
136 },
137 [MLX5E_100BASE_TX][MLX5E_TX] = {
138 .subtype = IFM_100_TX,
139 .baudrate = IF_Mbps(100ULL),
140 },
141 [MLX5E_1000BASE_T][MLX5E_T] = {
142 .subtype = IFM_1000_T,
143 .baudrate = IF_Mbps(1000ULL),
144 },
145 [MLX5E_10GBASE_T][MLX5E_T] = {
146 .subtype = IFM_10G_T,
147 .baudrate = IF_Gbps(10ULL),
148 },
149 [MLX5E_25GBASE_CR][MLX5E_CR] = {
150 .subtype = IFM_25G_CR,
151 .baudrate = IF_Gbps(25ULL),
152 },
153 [MLX5E_25GBASE_KR][MLX5E_KR] = {
154 .subtype = IFM_25G_KR,
155 .baudrate = IF_Gbps(25ULL),
156 },
157 [MLX5E_25GBASE_SR][MLX5E_SR] = {
158 .subtype = IFM_25G_SR,
159 .baudrate = IF_Gbps(25ULL),
160 },
161 [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
162 .subtype = IFM_50G_CR2,
163 .baudrate = IF_Gbps(50ULL),
164 },
165 [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
166 .subtype = IFM_50G_KR2,
167 .baudrate = IF_Gbps(50ULL),
168 },
169 [MLX5E_50GBASE_KR4][MLX5E_KR4] = {
170 .subtype = IFM_50G_KR4,
171 .baudrate = IF_Gbps(50ULL),
172 },
173 };
174
175 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
176 [MLX5E_SGMII_100M][MLX5E_SGMII] = {
177 .subtype = IFM_100_SGMII,
178 .baudrate = IF_Mbps(100),
179 },
180 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
181 .subtype = IFM_1000_KX,
182 .baudrate = IF_Mbps(1000),
183 },
184 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
185 .subtype = IFM_1000_CX_SGMII,
186 .baudrate = IF_Mbps(1000),
187 },
188 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
189 .subtype = IFM_1000_CX,
190 .baudrate = IF_Mbps(1000),
191 },
192 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
193 .subtype = IFM_1000_LX,
194 .baudrate = IF_Mbps(1000),
195 },
196 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
197 .subtype = IFM_1000_SX,
198 .baudrate = IF_Mbps(1000),
199 },
200 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
201 .subtype = IFM_1000_T,
202 .baudrate = IF_Mbps(1000),
203 },
204 [MLX5E_5GBASE_R][MLX5E_T] = {
205 .subtype = IFM_5000_T,
206 .baudrate = IF_Mbps(5000),
207 },
208 [MLX5E_5GBASE_R][MLX5E_KR] = {
209 .subtype = IFM_5000_KR,
210 .baudrate = IF_Mbps(5000),
211 },
212 [MLX5E_5GBASE_R][MLX5E_KR1] = {
213 .subtype = IFM_5000_KR1,
214 .baudrate = IF_Mbps(5000),
215 },
216 [MLX5E_5GBASE_R][MLX5E_KR_S] = {
217 .subtype = IFM_5000_KR_S,
218 .baudrate = IF_Mbps(5000),
219 },
220 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
221 .subtype = IFM_10G_ER,
222 .baudrate = IF_Gbps(10ULL),
223 },
224 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
225 .subtype = IFM_10G_KR,
226 .baudrate = IF_Gbps(10ULL),
227 },
228 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
229 .subtype = IFM_10G_LR,
230 .baudrate = IF_Gbps(10ULL),
231 },
232 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
233 .subtype = IFM_10G_SR,
234 .baudrate = IF_Gbps(10ULL),
235 },
236 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
237 .subtype = IFM_10G_T,
238 .baudrate = IF_Gbps(10ULL),
239 },
240 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
241 .subtype = IFM_10G_AOC,
242 .baudrate = IF_Gbps(10ULL),
243 },
244 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
245 .subtype = IFM_10G_CR1,
246 .baudrate = IF_Gbps(10ULL),
247 },
248 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
249 .subtype = IFM_40G_CR4,
250 .baudrate = IF_Gbps(40ULL),
251 },
252 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
253 .subtype = IFM_40G_KR4,
254 .baudrate = IF_Gbps(40ULL),
255 },
256 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
257 .subtype = IFM_40G_LR4,
258 .baudrate = IF_Gbps(40ULL),
259 },
260 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
261 .subtype = IFM_40G_SR4,
262 .baudrate = IF_Gbps(40ULL),
263 },
264 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
265 .subtype = IFM_40G_ER4,
266 .baudrate = IF_Gbps(40ULL),
267 },
268
269 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
270 .subtype = IFM_25G_CR,
271 .baudrate = IF_Gbps(25ULL),
272 },
273 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
274 .subtype = IFM_25G_KR,
275 .baudrate = IF_Gbps(25ULL),
276 },
277 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
278 .subtype = IFM_25G_SR,
279 .baudrate = IF_Gbps(25ULL),
280 },
281 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
282 .subtype = IFM_25G_ACC,
283 .baudrate = IF_Gbps(25ULL),
284 },
285 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
286 .subtype = IFM_25G_AOC,
287 .baudrate = IF_Gbps(25ULL),
288 },
289 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
290 .subtype = IFM_25G_CR1,
291 .baudrate = IF_Gbps(25ULL),
292 },
293 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
294 .subtype = IFM_25G_CR_S,
295 .baudrate = IF_Gbps(25ULL),
296 },
297 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
298 .subtype = IFM_5000_KR1,
299 .baudrate = IF_Gbps(25ULL),
300 },
301 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
302 .subtype = IFM_25G_KR_S,
303 .baudrate = IF_Gbps(25ULL),
304 },
305 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
306 .subtype = IFM_25G_LR,
307 .baudrate = IF_Gbps(25ULL),
308 },
309 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
310 .subtype = IFM_25G_T,
311 .baudrate = IF_Gbps(25ULL),
312 },
313 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
314 .subtype = IFM_50G_CR2,
315 .baudrate = IF_Gbps(50ULL),
316 },
317 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
318 .subtype = IFM_50G_KR2,
319 .baudrate = IF_Gbps(50ULL),
320 },
321 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR4] = {
322 .subtype = IFM_50G_KR4,
323 .baudrate = IF_Gbps(50ULL),
324 },
325 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
326 .subtype = IFM_50G_SR2,
327 .baudrate = IF_Gbps(50ULL),
328 },
329 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
330 .subtype = IFM_50G_LR2,
331 .baudrate = IF_Gbps(50ULL),
332 },
333 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
334 .subtype = IFM_50G_LR,
335 .baudrate = IF_Gbps(50ULL),
336 },
337 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
338 .subtype = IFM_50G_SR,
339 .baudrate = IF_Gbps(50ULL),
340 },
341 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
342 .subtype = IFM_50G_CP,
343 .baudrate = IF_Gbps(50ULL),
344 },
345 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
346 .subtype = IFM_50G_FR,
347 .baudrate = IF_Gbps(50ULL),
348 },
349 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
350 .subtype = IFM_50G_KR_PAM4,
351 .baudrate = IF_Gbps(50ULL),
352 },
353 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
354 .subtype = IFM_100G_CR4,
355 .baudrate = IF_Gbps(100ULL),
356 },
357 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
358 .subtype = IFM_100G_KR4,
359 .baudrate = IF_Gbps(100ULL),
360 },
361 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
362 .subtype = IFM_100G_LR4,
363 .baudrate = IF_Gbps(100ULL),
364 },
365 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
366 .subtype = IFM_100G_SR4,
367 .baudrate = IF_Gbps(100ULL),
368 },
369 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
370 .subtype = IFM_100G_SR2,
371 .baudrate = IF_Gbps(100ULL),
372 },
373 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
374 .subtype = IFM_100G_CP2,
375 .baudrate = IF_Gbps(100ULL),
376 },
377 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
378 .subtype = IFM_100G_KR2_PAM4,
379 .baudrate = IF_Gbps(100ULL),
380 },
381 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
382 .subtype = IFM_200G_DR4,
383 .baudrate = IF_Gbps(200ULL),
384 },
385 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
386 .subtype = IFM_200G_LR4,
387 .baudrate = IF_Gbps(200ULL),
388 },
389 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
390 .subtype = IFM_200G_SR4,
391 .baudrate = IF_Gbps(200ULL),
392 },
393 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
394 .subtype = IFM_200G_FR4,
395 .baudrate = IF_Gbps(200ULL),
396 },
397 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
398 .subtype = IFM_200G_CR4_PAM4,
399 .baudrate = IF_Gbps(200ULL),
400 },
401 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
402 .subtype = IFM_200G_KR4_PAM4,
403 .baudrate = IF_Gbps(200ULL),
404 },
405 };
406
407 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
408
409 static void
mlx5e_update_carrier(struct mlx5e_priv * priv)410 mlx5e_update_carrier(struct mlx5e_priv *priv)
411 {
412 struct mlx5_core_dev *mdev = priv->mdev;
413 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
414 u32 eth_proto_oper;
415 int error;
416 u8 port_state;
417 u8 is_er_type;
418 u8 i, j;
419 bool ext;
420 struct media media_entry = {};
421
422 port_state = mlx5_query_vport_state(mdev,
423 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
424
425 if (port_state == VPORT_STATE_UP) {
426 priv->media_status_last |= IFM_ACTIVE;
427 } else {
428 priv->media_status_last &= ~IFM_ACTIVE;
429 priv->media_active_last = IFM_ETHER;
430 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
431 return;
432 }
433
434 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
435 MLX5_PTYS_EN, 1);
436 if (error) {
437 priv->media_active_last = IFM_ETHER;
438 priv->ifp->if_baudrate = 1;
439 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
440 error);
441 return;
442 }
443
444 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
445 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
446 eth_proto_oper);
447
448 i = ilog2(eth_proto_oper);
449
450 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
451 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
452 mlx5e_mode_table[i][j];
453 if (media_entry.baudrate != 0)
454 break;
455 }
456
457 if (media_entry.subtype == 0) {
458 mlx5_en_err(priv->ifp,
459 "Could not find operational media subtype\n");
460 return;
461 }
462
463 switch (media_entry.subtype) {
464 case IFM_10G_ER:
465 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
466 if (error != 0) {
467 mlx5_en_err(priv->ifp,
468 "query port pddr failed: %d\n", error);
469 }
470 if (error != 0 || is_er_type == 0)
471 media_entry.subtype = IFM_10G_LR;
472 break;
473 case IFM_40G_LR4:
474 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
475 if (error != 0) {
476 mlx5_en_err(priv->ifp,
477 "query port pddr failed: %d\n", error);
478 }
479 if (error == 0 && is_er_type != 0)
480 media_entry.subtype = IFM_40G_ER4;
481 break;
482 }
483 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
484 priv->ifp->if_baudrate = media_entry.baudrate;
485
486 if_link_state_change(priv->ifp, LINK_STATE_UP);
487 }
488
489 static void
mlx5e_media_status(struct ifnet * dev,struct ifmediareq * ifmr)490 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
491 {
492 struct mlx5e_priv *priv = dev->if_softc;
493
494 ifmr->ifm_status = priv->media_status_last;
495 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last |
496 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
497 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
498
499 }
500
501 static u32
mlx5e_find_link_mode(u32 subtype,bool ext)502 mlx5e_find_link_mode(u32 subtype, bool ext)
503 {
504 u32 i;
505 u32 j;
506 u32 link_mode = 0;
507 u32 speeds_num = 0;
508 struct media media_entry = {};
509
510 switch (subtype) {
511 case IFM_10G_LR:
512 subtype = IFM_10G_ER;
513 break;
514 case IFM_40G_ER4:
515 subtype = IFM_40G_LR4;
516 break;
517 }
518
519 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
520 MLX5E_LINK_SPEEDS_NUMBER;
521
522 for (i = 0; i != speeds_num; i++) {
523 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
524 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
525 mlx5e_mode_table[i][j];
526 if (media_entry.baudrate == 0)
527 continue;
528 if (media_entry.subtype == subtype) {
529 link_mode |= MLX5E_PROT_MASK(i);
530 }
531 }
532 }
533
534 return (link_mode);
535 }
536
537 static int
mlx5e_set_port_pause_and_pfc(struct mlx5e_priv * priv)538 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
539 {
540 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
541 priv->params.rx_pauseframe_control,
542 priv->params.tx_pauseframe_control,
543 priv->params.rx_priority_flow_control,
544 priv->params.tx_priority_flow_control));
545 }
546
547 static int
mlx5e_set_port_pfc(struct mlx5e_priv * priv)548 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
549 {
550 int error;
551
552 if (priv->gone != 0) {
553 error = -ENXIO;
554 } else if (priv->params.rx_pauseframe_control ||
555 priv->params.tx_pauseframe_control) {
556 mlx5_en_err(priv->ifp,
557 "Global pauseframes must be disabled before enabling PFC.\n");
558 error = -EINVAL;
559 } else {
560 error = mlx5e_set_port_pause_and_pfc(priv);
561 }
562 return (error);
563 }
564
565 static int
mlx5e_media_change(struct ifnet * dev)566 mlx5e_media_change(struct ifnet *dev)
567 {
568 struct mlx5e_priv *priv = dev->if_softc;
569 struct mlx5_core_dev *mdev = priv->mdev;
570 u32 eth_proto_cap;
571 u32 link_mode;
572 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
573 int was_opened;
574 int locked;
575 int error;
576 bool ext;
577
578 locked = PRIV_LOCKED(priv);
579 if (!locked)
580 PRIV_LOCK(priv);
581
582 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
583 error = EINVAL;
584 goto done;
585 }
586
587 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
588 MLX5_PTYS_EN, 1);
589 if (error != 0) {
590 mlx5_en_err(dev, "Query port media capability failed\n");
591 goto done;
592 }
593
594 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
595 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
596
597 /* query supported capabilities */
598 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
599 eth_proto_capability);
600
601 /* check for autoselect */
602 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
603 link_mode = eth_proto_cap;
604 if (link_mode == 0) {
605 mlx5_en_err(dev, "Port media capability is zero\n");
606 error = EINVAL;
607 goto done;
608 }
609 } else {
610 link_mode = link_mode & eth_proto_cap;
611 if (link_mode == 0) {
612 mlx5_en_err(dev, "Not supported link mode requested\n");
613 error = EINVAL;
614 goto done;
615 }
616 }
617 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
618 /* check if PFC is enabled */
619 if (priv->params.rx_priority_flow_control ||
620 priv->params.tx_priority_flow_control) {
621 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
622 error = EINVAL;
623 goto done;
624 }
625 }
626 /* update pauseframe control bits */
627 priv->params.rx_pauseframe_control =
628 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
629 priv->params.tx_pauseframe_control =
630 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
631
632 /* check if device is opened */
633 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
634
635 /* reconfigure the hardware */
636 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
637 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
638 error = -mlx5e_set_port_pause_and_pfc(priv);
639 if (was_opened)
640 mlx5_set_port_status(mdev, MLX5_PORT_UP);
641
642 done:
643 if (!locked)
644 PRIV_UNLOCK(priv);
645 return (error);
646 }
647
648 static void
mlx5e_update_carrier_work(struct work_struct * work)649 mlx5e_update_carrier_work(struct work_struct *work)
650 {
651 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
652 update_carrier_work);
653
654 PRIV_LOCK(priv);
655 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
656 mlx5e_update_carrier(priv);
657 PRIV_UNLOCK(priv);
658 }
659
660 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \
661 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
662
663 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \
664 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
665
666 static void
mlx5e_update_pcie_counters(struct mlx5e_priv * priv)667 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
668 {
669 struct mlx5_core_dev *mdev = priv->mdev;
670 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
671 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
672 void *out;
673 void *in;
674 int err;
675
676 /* allocate firmware request structures */
677 in = mlx5_vzalloc(sz);
678 out = mlx5_vzalloc(sz);
679 if (in == NULL || out == NULL)
680 goto free_out;
681
682 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
683 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
684 if (err != 0)
685 goto free_out;
686
687 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
688 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
689
690 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
691 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
692 if (err != 0)
693 goto free_out;
694
695 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
696
697 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
698 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
699 if (err != 0)
700 goto free_out;
701
702 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
703
704 free_out:
705 /* free firmware request structures */
706 kvfree(in);
707 kvfree(out);
708 }
709
710 /*
711 * This function reads the physical port counters from the firmware
712 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
713 * macros. The output is converted from big-endian 64-bit values into
714 * host endian ones and stored in the "priv->stats.pport" structure.
715 */
716 static void
mlx5e_update_pport_counters(struct mlx5e_priv * priv)717 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
718 {
719 struct mlx5_core_dev *mdev = priv->mdev;
720 struct mlx5e_pport_stats *s = &priv->stats.pport;
721 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
722 u32 *in;
723 u32 *out;
724 const u64 *ptr;
725 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
726 unsigned x;
727 unsigned y;
728 unsigned z;
729
730 /* allocate firmware request structures */
731 in = mlx5_vzalloc(sz);
732 out = mlx5_vzalloc(sz);
733 if (in == NULL || out == NULL)
734 goto free_out;
735
736 /*
737 * Get pointer to the 64-bit counter set which is located at a
738 * fixed offset in the output firmware request structure:
739 */
740 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
741
742 MLX5_SET(ppcnt_reg, in, local_port, 1);
743
744 /* read IEEE802_3 counter group using predefined counter layout */
745 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
746 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
747 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
748 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
749 s->arg[y] = be64toh(ptr[x]);
750
751 /* read RFC2819 counter group using predefined counter layout */
752 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
753 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
754 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
755 s->arg[y] = be64toh(ptr[x]);
756
757 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
758 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
759 s_debug->arg[y] = be64toh(ptr[x]);
760
761 /* read RFC2863 counter group using predefined counter layout */
762 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
763 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
764 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
765 s_debug->arg[y] = be64toh(ptr[x]);
766
767 /* read physical layer stats counter group using predefined counter layout */
768 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
769 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
770 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
771 s_debug->arg[y] = be64toh(ptr[x]);
772
773 /* read Extended Ethernet counter group using predefined counter layout */
774 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
775 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
776 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
777 s_debug->arg[y] = be64toh(ptr[x]);
778
779 /* read Extended Statistical Group */
780 if (MLX5_CAP_GEN(mdev, pcam_reg) &&
781 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
782 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
783 /* read Extended Statistical counter group using predefined counter layout */
784 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
785 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
786
787 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
788 s_debug->arg[y] = be64toh(ptr[x]);
789 }
790
791 /* read PCIE counters */
792 mlx5e_update_pcie_counters(priv);
793
794 /* read per-priority counters */
795 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
796
797 /* iterate all the priorities */
798 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
799 MLX5_SET(ppcnt_reg, in, prio_tc, z);
800 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
801
802 /* read per priority stats counter group using predefined counter layout */
803 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
804 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
805 s->arg[y] = be64toh(ptr[x]);
806 }
807
808 free_out:
809 /* free firmware request structures */
810 kvfree(in);
811 kvfree(out);
812 }
813
814 static void
mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv * priv)815 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
816 {
817 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
818 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
819
820 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
821 return;
822
823 MLX5_SET(query_vnic_env_in, in, opcode,
824 MLX5_CMD_OP_QUERY_VNIC_ENV);
825 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
826 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
827
828 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
829 return;
830
831 priv->stats.vport.rx_steer_missed_packets =
832 MLX5_GET64(query_vnic_env_out, out,
833 vport_env.nic_receive_steering_discard);
834 }
835
836 /*
837 * This function is called regularly to collect all statistics
838 * counters from the firmware. The values can be viewed through the
839 * sysctl interface. Execution is serialized using the priv's global
840 * configuration lock.
841 */
842 static void
mlx5e_update_stats_locked(struct mlx5e_priv * priv)843 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
844 {
845 struct mlx5_core_dev *mdev = priv->mdev;
846 struct mlx5e_vport_stats *s = &priv->stats.vport;
847 struct mlx5e_sq_stats *sq_stats;
848 #if (__FreeBSD_version < 1100000)
849 struct ifnet *ifp = priv->ifp;
850 #endif
851
852 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
853 u32 *out;
854 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
855 u64 tso_packets = 0;
856 u64 tso_bytes = 0;
857 u64 tx_queue_dropped = 0;
858 u64 tx_defragged = 0;
859 u64 tx_offload_none = 0;
860 u64 lro_packets = 0;
861 u64 lro_bytes = 0;
862 u64 sw_lro_queued = 0;
863 u64 sw_lro_flushed = 0;
864 u64 rx_csum_none = 0;
865 u64 rx_wqe_err = 0;
866 u64 rx_packets = 0;
867 u64 rx_bytes = 0;
868 u32 rx_out_of_buffer = 0;
869 int error;
870 int i;
871 int j;
872
873 out = mlx5_vzalloc(outlen);
874 if (out == NULL)
875 goto free_out;
876
877 /* Collect firts the SW counters and then HW for consistency */
878 for (i = 0; i < priv->params.num_channels; i++) {
879 struct mlx5e_channel *pch = priv->channel + i;
880 struct mlx5e_rq *rq = &pch->rq;
881 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
882
883 /* collect stats from LRO */
884 rq_stats->sw_lro_queued = rq->lro.lro_queued;
885 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
886 sw_lro_queued += rq_stats->sw_lro_queued;
887 sw_lro_flushed += rq_stats->sw_lro_flushed;
888 lro_packets += rq_stats->lro_packets;
889 lro_bytes += rq_stats->lro_bytes;
890 rx_csum_none += rq_stats->csum_none;
891 rx_wqe_err += rq_stats->wqe_err;
892 rx_packets += rq_stats->packets;
893 rx_bytes += rq_stats->bytes;
894
895 for (j = 0; j < priv->num_tc; j++) {
896 sq_stats = &pch->sq[j].stats;
897
898 tso_packets += sq_stats->tso_packets;
899 tso_bytes += sq_stats->tso_bytes;
900 tx_queue_dropped += sq_stats->dropped;
901 tx_queue_dropped += sq_stats->enobuf;
902 tx_defragged += sq_stats->defragged;
903 tx_offload_none += sq_stats->csum_offload_none;
904 }
905 }
906
907 #ifdef RATELIMIT
908 /* Collect statistics from all rate-limit queues */
909 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) {
910 struct mlx5e_rl_worker *rlw = priv->rl.workers + j;
911
912 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) {
913 struct mlx5e_rl_channel *channel = rlw->channels + i;
914 struct mlx5e_sq *sq = channel->sq;
915
916 if (sq == NULL)
917 continue;
918
919 sq_stats = &sq->stats;
920
921 tso_packets += sq_stats->tso_packets;
922 tso_bytes += sq_stats->tso_bytes;
923 tx_queue_dropped += sq_stats->dropped;
924 tx_queue_dropped += sq_stats->enobuf;
925 tx_defragged += sq_stats->defragged;
926 tx_offload_none += sq_stats->csum_offload_none;
927 }
928 }
929 #endif
930
931 /* update counters */
932 s->tso_packets = tso_packets;
933 s->tso_bytes = tso_bytes;
934 s->tx_queue_dropped = tx_queue_dropped;
935 s->tx_defragged = tx_defragged;
936 s->lro_packets = lro_packets;
937 s->lro_bytes = lro_bytes;
938 s->sw_lro_queued = sw_lro_queued;
939 s->sw_lro_flushed = sw_lro_flushed;
940 s->rx_csum_none = rx_csum_none;
941 s->rx_wqe_err = rx_wqe_err;
942 s->rx_packets = rx_packets;
943 s->rx_bytes = rx_bytes;
944
945 mlx5e_grp_vnic_env_update_stats(priv);
946
947 /* HW counters */
948 memset(in, 0, sizeof(in));
949
950 MLX5_SET(query_vport_counter_in, in, opcode,
951 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
952 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
953 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
954
955 memset(out, 0, outlen);
956
957 /* get number of out-of-buffer drops first */
958 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
959 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
960 &rx_out_of_buffer) == 0) {
961 s->rx_out_of_buffer = rx_out_of_buffer;
962 }
963
964 /* get port statistics */
965 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
966 #define MLX5_GET_CTR(out, x) \
967 MLX5_GET64(query_vport_counter_out, out, x)
968
969 s->rx_error_packets =
970 MLX5_GET_CTR(out, received_errors.packets);
971 s->rx_error_bytes =
972 MLX5_GET_CTR(out, received_errors.octets);
973 s->tx_error_packets =
974 MLX5_GET_CTR(out, transmit_errors.packets);
975 s->tx_error_bytes =
976 MLX5_GET_CTR(out, transmit_errors.octets);
977
978 s->rx_unicast_packets =
979 MLX5_GET_CTR(out, received_eth_unicast.packets);
980 s->rx_unicast_bytes =
981 MLX5_GET_CTR(out, received_eth_unicast.octets);
982 s->tx_unicast_packets =
983 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
984 s->tx_unicast_bytes =
985 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
986
987 s->rx_multicast_packets =
988 MLX5_GET_CTR(out, received_eth_multicast.packets);
989 s->rx_multicast_bytes =
990 MLX5_GET_CTR(out, received_eth_multicast.octets);
991 s->tx_multicast_packets =
992 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
993 s->tx_multicast_bytes =
994 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
995
996 s->rx_broadcast_packets =
997 MLX5_GET_CTR(out, received_eth_broadcast.packets);
998 s->rx_broadcast_bytes =
999 MLX5_GET_CTR(out, received_eth_broadcast.octets);
1000 s->tx_broadcast_packets =
1001 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
1002 s->tx_broadcast_bytes =
1003 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
1004
1005 s->tx_packets = s->tx_unicast_packets +
1006 s->tx_multicast_packets + s->tx_broadcast_packets;
1007 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
1008 s->tx_broadcast_bytes;
1009
1010 /* Update calculated offload counters */
1011 s->tx_csum_offload = s->tx_packets - tx_offload_none;
1012 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
1013 }
1014
1015 /* Get physical port counters */
1016 mlx5e_update_pport_counters(priv);
1017
1018 s->tx_jumbo_packets =
1019 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
1020 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
1021 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
1022 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
1023
1024 #if (__FreeBSD_version < 1100000)
1025 /* no get_counters interface in fbsd 10 */
1026 ifp->if_ipackets = s->rx_packets;
1027 ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1028 priv->stats.pport.out_of_range_len +
1029 priv->stats.pport.too_long_errors +
1030 priv->stats.pport.check_seq_err +
1031 priv->stats.pport.alignment_err;
1032 ifp->if_iqdrops = s->rx_out_of_buffer;
1033 ifp->if_opackets = s->tx_packets;
1034 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1035 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1036 ifp->if_ibytes = s->rx_bytes;
1037 ifp->if_obytes = s->tx_bytes;
1038 ifp->if_collisions =
1039 priv->stats.pport.collisions;
1040 #endif
1041
1042 free_out:
1043 kvfree(out);
1044
1045 /* Update diagnostics, if any */
1046 if (priv->params_ethtool.diag_pci_enable ||
1047 priv->params_ethtool.diag_general_enable) {
1048 error = mlx5_core_get_diagnostics_full(mdev,
1049 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1050 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1051 if (error != 0)
1052 mlx5_en_err(priv->ifp,
1053 "Failed reading diagnostics: %d\n", error);
1054 }
1055
1056 /* Update FEC, if any */
1057 error = mlx5e_fec_update(priv);
1058 if (error != 0 && error != EOPNOTSUPP) {
1059 mlx5_en_err(priv->ifp,
1060 "Updating FEC failed: %d\n", error);
1061 }
1062
1063 /* Update temperature, if any */
1064 if (priv->params_ethtool.hw_num_temp != 0) {
1065 error = mlx5e_hw_temperature_update(priv);
1066 if (error != 0 && error != EOPNOTSUPP) {
1067 mlx5_en_err(priv->ifp,
1068 "Updating temperature failed: %d\n", error);
1069 }
1070 }
1071 }
1072
1073 static void
mlx5e_update_stats_work(struct work_struct * work)1074 mlx5e_update_stats_work(struct work_struct *work)
1075 {
1076 struct mlx5e_priv *priv;
1077
1078 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1079 PRIV_LOCK(priv);
1080 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1081 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1082 mlx5e_update_stats_locked(priv);
1083 PRIV_UNLOCK(priv);
1084 }
1085
1086 static void
mlx5e_update_stats(void * arg)1087 mlx5e_update_stats(void *arg)
1088 {
1089 struct mlx5e_priv *priv = arg;
1090
1091 queue_work(priv->wq, &priv->update_stats_work);
1092
1093 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv);
1094 }
1095
1096 static void
mlx5e_async_event_sub(struct mlx5e_priv * priv,enum mlx5_dev_event event)1097 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1098 enum mlx5_dev_event event)
1099 {
1100 switch (event) {
1101 case MLX5_DEV_EVENT_PORT_UP:
1102 case MLX5_DEV_EVENT_PORT_DOWN:
1103 queue_work(priv->wq, &priv->update_carrier_work);
1104 break;
1105
1106 default:
1107 break;
1108 }
1109 }
1110
1111 static void
mlx5e_async_event(struct mlx5_core_dev * mdev,void * vpriv,enum mlx5_dev_event event,unsigned long param)1112 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1113 enum mlx5_dev_event event, unsigned long param)
1114 {
1115 struct mlx5e_priv *priv = vpriv;
1116
1117 mtx_lock(&priv->async_events_mtx);
1118 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1119 mlx5e_async_event_sub(priv, event);
1120 mtx_unlock(&priv->async_events_mtx);
1121 }
1122
1123 static void
mlx5e_enable_async_events(struct mlx5e_priv * priv)1124 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1125 {
1126 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1127 }
1128
1129 static void
mlx5e_disable_async_events(struct mlx5e_priv * priv)1130 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1131 {
1132 mtx_lock(&priv->async_events_mtx);
1133 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1134 mtx_unlock(&priv->async_events_mtx);
1135 }
1136
1137 static void mlx5e_calibration_callout(void *arg);
1138 static int mlx5e_calibration_duration = 20;
1139 static int mlx5e_fast_calibration = 1;
1140 static int mlx5e_normal_calibration = 30;
1141
1142 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
1143 "MLX5 timestamp calibration parameteres");
1144
1145 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1146 &mlx5e_calibration_duration, 0,
1147 "Duration of initial calibration");
1148 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1149 &mlx5e_fast_calibration, 0,
1150 "Recalibration interval during initial calibration");
1151 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1152 &mlx5e_normal_calibration, 0,
1153 "Recalibration interval during normal operations");
1154
1155 /*
1156 * Ignites the calibration process.
1157 */
1158 static void
mlx5e_reset_calibration_callout(struct mlx5e_priv * priv)1159 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1160 {
1161
1162 if (priv->clbr_done == 0)
1163 mlx5e_calibration_callout(priv);
1164 else
1165 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1166 mlx5e_calibration_duration ? mlx5e_fast_calibration :
1167 mlx5e_normal_calibration) * SBT_1S, 0,
1168 mlx5e_calibration_callout, priv, C_DIRECT_EXEC);
1169 }
1170
1171 static uint64_t
mlx5e_timespec2usec(const struct timespec * ts)1172 mlx5e_timespec2usec(const struct timespec *ts)
1173 {
1174
1175 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1176 }
1177
1178 static uint64_t
mlx5e_hw_clock(struct mlx5e_priv * priv)1179 mlx5e_hw_clock(struct mlx5e_priv *priv)
1180 {
1181 struct mlx5_init_seg *iseg;
1182 uint32_t hw_h, hw_h1, hw_l;
1183
1184 iseg = priv->mdev->iseg;
1185 do {
1186 hw_h = ioread32be(&iseg->internal_timer_h);
1187 hw_l = ioread32be(&iseg->internal_timer_l);
1188 hw_h1 = ioread32be(&iseg->internal_timer_h);
1189 } while (hw_h1 != hw_h);
1190 return (((uint64_t)hw_h << 32) | hw_l);
1191 }
1192
1193 /*
1194 * The calibration callout, it runs either in the context of the
1195 * thread which enables calibration, or in callout. It takes the
1196 * snapshot of system and adapter clocks, then advances the pointers to
1197 * the calibration point to allow rx path to read the consistent data
1198 * lockless.
1199 */
1200 static void
mlx5e_calibration_callout(void * arg)1201 mlx5e_calibration_callout(void *arg)
1202 {
1203 struct mlx5e_priv *priv;
1204 struct mlx5e_clbr_point *next, *curr;
1205 struct timespec ts;
1206 int clbr_curr_next;
1207
1208 priv = arg;
1209 curr = &priv->clbr_points[priv->clbr_curr];
1210 clbr_curr_next = priv->clbr_curr + 1;
1211 if (clbr_curr_next >= nitems(priv->clbr_points))
1212 clbr_curr_next = 0;
1213 next = &priv->clbr_points[clbr_curr_next];
1214
1215 next->base_prev = curr->base_curr;
1216 next->clbr_hw_prev = curr->clbr_hw_curr;
1217
1218 next->clbr_hw_curr = mlx5e_hw_clock(priv);
1219 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1220 0) {
1221 if (priv->clbr_done != 0) {
1222 mlx5_en_err(priv->ifp,
1223 "HW failed tstmp frozen %#jx %#jx, disabling\n",
1224 next->clbr_hw_curr, curr->clbr_hw_prev);
1225 priv->clbr_done = 0;
1226 }
1227 atomic_store_rel_int(&curr->clbr_gen, 0);
1228 return;
1229 }
1230
1231 nanouptime(&ts);
1232 next->base_curr = mlx5e_timespec2usec(&ts);
1233
1234 curr->clbr_gen = 0;
1235 atomic_thread_fence_rel();
1236 priv->clbr_curr = clbr_curr_next;
1237 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1238
1239 if (priv->clbr_done < mlx5e_calibration_duration)
1240 priv->clbr_done++;
1241 mlx5e_reset_calibration_callout(priv);
1242 }
1243
1244 static const char *mlx5e_rq_stats_desc[] = {
1245 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1246 };
1247
1248 static int
mlx5e_create_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1249 mlx5e_create_rq(struct mlx5e_channel *c,
1250 struct mlx5e_rq_param *param,
1251 struct mlx5e_rq *rq)
1252 {
1253 struct mlx5e_priv *priv = c->priv;
1254 struct mlx5_core_dev *mdev = priv->mdev;
1255 char buffer[16];
1256 void *rqc = param->rqc;
1257 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1258 int wq_sz;
1259 int err;
1260 int i;
1261 u32 nsegs, wqe_sz;
1262
1263 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1264 if (err != 0)
1265 goto done;
1266
1267 /* Create DMA descriptor TAG */
1268 if ((err = -bus_dma_tag_create(
1269 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1270 1, /* any alignment */
1271 0, /* no boundary */
1272 BUS_SPACE_MAXADDR, /* lowaddr */
1273 BUS_SPACE_MAXADDR, /* highaddr */
1274 NULL, NULL, /* filter, filterarg */
1275 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1276 nsegs, /* nsegments */
1277 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1278 0, /* flags */
1279 NULL, NULL, /* lockfunc, lockfuncarg */
1280 &rq->dma_tag)))
1281 goto done;
1282
1283 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1284 &rq->wq_ctrl);
1285 if (err)
1286 goto err_free_dma_tag;
1287
1288 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1289
1290 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1291 if (err != 0)
1292 goto err_rq_wq_destroy;
1293
1294 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1295
1296 err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
1297 if (err)
1298 goto err_rq_wq_destroy;
1299
1300 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1301 for (i = 0; i != wq_sz; i++) {
1302 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1303 int j;
1304
1305 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1306 if (err != 0) {
1307 while (i--)
1308 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1309 goto err_rq_mbuf_free;
1310 }
1311
1312 /* set value for constant fields */
1313 for (j = 0; j < rq->nsegs; j++)
1314 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1315 }
1316
1317 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1318 if (priv->params.rx_cq_moderation_mode < 2) {
1319 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1320 } else {
1321 void *cqc = container_of(param,
1322 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1323
1324 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1325 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1326 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1327 break;
1328 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1329 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1330 break;
1331 default:
1332 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1333 break;
1334 }
1335 }
1336
1337 rq->ifp = c->tag.m_snd_tag.ifp;
1338 rq->channel = c;
1339 rq->ix = c->ix;
1340
1341 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1342 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1343 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1344 rq->stats.arg);
1345 return (0);
1346
1347 err_rq_mbuf_free:
1348 free(rq->mbuf, M_MLX5EN);
1349 tcp_lro_free(&rq->lro);
1350 err_rq_wq_destroy:
1351 mlx5_wq_destroy(&rq->wq_ctrl);
1352 err_free_dma_tag:
1353 bus_dma_tag_destroy(rq->dma_tag);
1354 done:
1355 return (err);
1356 }
1357
1358 static void
mlx5e_destroy_rq(struct mlx5e_rq * rq)1359 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1360 {
1361 int wq_sz;
1362 int i;
1363
1364 /* destroy all sysctl nodes */
1365 sysctl_ctx_free(&rq->stats.ctx);
1366
1367 /* free leftover LRO packets, if any */
1368 tcp_lro_free(&rq->lro);
1369
1370 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1371 for (i = 0; i != wq_sz; i++) {
1372 if (rq->mbuf[i].mbuf != NULL) {
1373 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1374 m_freem(rq->mbuf[i].mbuf);
1375 }
1376 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1377 }
1378 free(rq->mbuf, M_MLX5EN);
1379 mlx5_wq_destroy(&rq->wq_ctrl);
1380 bus_dma_tag_destroy(rq->dma_tag);
1381 }
1382
1383 static int
mlx5e_enable_rq(struct mlx5e_rq * rq,struct mlx5e_rq_param * param)1384 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1385 {
1386 struct mlx5e_channel *c = rq->channel;
1387 struct mlx5e_priv *priv = c->priv;
1388 struct mlx5_core_dev *mdev = priv->mdev;
1389
1390 void *in;
1391 void *rqc;
1392 void *wq;
1393 int inlen;
1394 int err;
1395
1396 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1397 sizeof(u64) * rq->wq_ctrl.buf.npages;
1398 in = mlx5_vzalloc(inlen);
1399 if (in == NULL)
1400 return (-ENOMEM);
1401
1402 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1403 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1404
1405 memcpy(rqc, param->rqc, sizeof(param->rqc));
1406
1407 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1408 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1409 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1410 if (priv->counter_set_id >= 0)
1411 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1412 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1413 PAGE_SHIFT);
1414 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1415
1416 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1417 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1418
1419 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1420
1421 kvfree(in);
1422
1423 return (err);
1424 }
1425
1426 static int
mlx5e_modify_rq(struct mlx5e_rq * rq,int curr_state,int next_state)1427 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1428 {
1429 struct mlx5e_channel *c = rq->channel;
1430 struct mlx5e_priv *priv = c->priv;
1431 struct mlx5_core_dev *mdev = priv->mdev;
1432
1433 void *in;
1434 void *rqc;
1435 int inlen;
1436 int err;
1437
1438 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1439 in = mlx5_vzalloc(inlen);
1440 if (in == NULL)
1441 return (-ENOMEM);
1442
1443 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1444
1445 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1446 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1447 MLX5_SET(rqc, rqc, state, next_state);
1448
1449 err = mlx5_core_modify_rq(mdev, in, inlen);
1450
1451 kvfree(in);
1452
1453 return (err);
1454 }
1455
1456 static void
mlx5e_disable_rq(struct mlx5e_rq * rq)1457 mlx5e_disable_rq(struct mlx5e_rq *rq)
1458 {
1459 struct mlx5e_channel *c = rq->channel;
1460 struct mlx5e_priv *priv = c->priv;
1461 struct mlx5_core_dev *mdev = priv->mdev;
1462
1463 mlx5_core_destroy_rq(mdev, rq->rqn);
1464 }
1465
1466 static int
mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq * rq)1467 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1468 {
1469 struct mlx5e_channel *c = rq->channel;
1470 struct mlx5e_priv *priv = c->priv;
1471 struct mlx5_wq_ll *wq = &rq->wq;
1472 int i;
1473
1474 for (i = 0; i < 1000; i++) {
1475 if (wq->cur_sz >= priv->params.min_rx_wqes)
1476 return (0);
1477
1478 msleep(4);
1479 }
1480 return (-ETIMEDOUT);
1481 }
1482
1483 static int
mlx5e_open_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1484 mlx5e_open_rq(struct mlx5e_channel *c,
1485 struct mlx5e_rq_param *param,
1486 struct mlx5e_rq *rq)
1487 {
1488 int err;
1489
1490 err = mlx5e_create_rq(c, param, rq);
1491 if (err)
1492 return (err);
1493
1494 err = mlx5e_enable_rq(rq, param);
1495 if (err)
1496 goto err_destroy_rq;
1497
1498 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1499 if (err)
1500 goto err_disable_rq;
1501
1502 c->rq.enabled = 1;
1503
1504 return (0);
1505
1506 err_disable_rq:
1507 mlx5e_disable_rq(rq);
1508 err_destroy_rq:
1509 mlx5e_destroy_rq(rq);
1510
1511 return (err);
1512 }
1513
1514 static void
mlx5e_close_rq(struct mlx5e_rq * rq)1515 mlx5e_close_rq(struct mlx5e_rq *rq)
1516 {
1517 mtx_lock(&rq->mtx);
1518 rq->enabled = 0;
1519 callout_stop(&rq->watchdog);
1520 mtx_unlock(&rq->mtx);
1521
1522 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1523 }
1524
1525 static void
mlx5e_close_rq_wait(struct mlx5e_rq * rq)1526 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1527 {
1528
1529 mlx5e_disable_rq(rq);
1530 mlx5e_close_cq(&rq->cq);
1531 cancel_work_sync(&rq->dim.work);
1532 mlx5e_destroy_rq(rq);
1533 }
1534
1535 void
mlx5e_free_sq_db(struct mlx5e_sq * sq)1536 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1537 {
1538 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1539 int x;
1540
1541 for (x = 0; x != wq_sz; x++) {
1542 if (sq->mbuf[x].mbuf != NULL) {
1543 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1544 m_freem(sq->mbuf[x].mbuf);
1545 }
1546 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1547 }
1548 free(sq->mbuf, M_MLX5EN);
1549 }
1550
1551 int
mlx5e_alloc_sq_db(struct mlx5e_sq * sq)1552 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1553 {
1554 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1555 int err;
1556 int x;
1557
1558 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1559
1560 /* Create DMA descriptor MAPs */
1561 for (x = 0; x != wq_sz; x++) {
1562 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1563 if (err != 0) {
1564 while (x--)
1565 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1566 free(sq->mbuf, M_MLX5EN);
1567 return (err);
1568 }
1569 }
1570 return (0);
1571 }
1572
1573 static const char *mlx5e_sq_stats_desc[] = {
1574 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1575 };
1576
1577 void
mlx5e_update_sq_inline(struct mlx5e_sq * sq)1578 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1579 {
1580 sq->max_inline = sq->priv->params.tx_max_inline;
1581 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1582
1583 /*
1584 * Check if trust state is DSCP or if inline mode is NONE which
1585 * indicates CX-5 or newer hardware.
1586 */
1587 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1588 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1589 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1590 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1591 else
1592 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1593 } else {
1594 sq->min_insert_caps = 0;
1595 }
1596 }
1597
1598 static void
mlx5e_refresh_sq_inline_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)1599 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1600 {
1601 int i;
1602
1603 for (i = 0; i != priv->num_tc; i++) {
1604 mtx_lock(&c->sq[i].lock);
1605 mlx5e_update_sq_inline(&c->sq[i]);
1606 mtx_unlock(&c->sq[i].lock);
1607 }
1608 }
1609
1610 void
mlx5e_refresh_sq_inline(struct mlx5e_priv * priv)1611 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1612 {
1613 int i;
1614
1615 /* check if channels are closed */
1616 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1617 return;
1618
1619 for (i = 0; i < priv->params.num_channels; i++)
1620 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1621 }
1622
1623 static int
mlx5e_create_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1624 mlx5e_create_sq(struct mlx5e_channel *c,
1625 int tc,
1626 struct mlx5e_sq_param *param,
1627 struct mlx5e_sq *sq)
1628 {
1629 struct mlx5e_priv *priv = c->priv;
1630 struct mlx5_core_dev *mdev = priv->mdev;
1631 char buffer[16];
1632 void *sqc = param->sqc;
1633 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1634 int err;
1635
1636 /* Create DMA descriptor TAG */
1637 if ((err = -bus_dma_tag_create(
1638 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1639 1, /* any alignment */
1640 0, /* no boundary */
1641 BUS_SPACE_MAXADDR, /* lowaddr */
1642 BUS_SPACE_MAXADDR, /* highaddr */
1643 NULL, NULL, /* filter, filterarg */
1644 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1645 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1646 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1647 0, /* flags */
1648 NULL, NULL, /* lockfunc, lockfuncarg */
1649 &sq->dma_tag)))
1650 goto done;
1651
1652 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1653 if (err)
1654 goto err_free_dma_tag;
1655
1656 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1657 &sq->wq_ctrl);
1658 if (err)
1659 goto err_unmap_free_uar;
1660
1661 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1662 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1663
1664 err = mlx5e_alloc_sq_db(sq);
1665 if (err)
1666 goto err_sq_wq_destroy;
1667
1668 sq->mkey_be = cpu_to_be32(priv->mr.key);
1669 sq->ifp = priv->ifp;
1670 sq->priv = priv;
1671 sq->tc = tc;
1672
1673 mlx5e_update_sq_inline(sq);
1674
1675 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1676 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1677 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1678 sq->stats.arg);
1679
1680 return (0);
1681
1682 err_sq_wq_destroy:
1683 mlx5_wq_destroy(&sq->wq_ctrl);
1684
1685 err_unmap_free_uar:
1686 mlx5_unmap_free_uar(mdev, &sq->uar);
1687
1688 err_free_dma_tag:
1689 bus_dma_tag_destroy(sq->dma_tag);
1690 done:
1691 return (err);
1692 }
1693
1694 static void
mlx5e_destroy_sq(struct mlx5e_sq * sq)1695 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1696 {
1697 /* destroy all sysctl nodes */
1698 sysctl_ctx_free(&sq->stats.ctx);
1699
1700 mlx5e_free_sq_db(sq);
1701 mlx5_wq_destroy(&sq->wq_ctrl);
1702 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1703 bus_dma_tag_destroy(sq->dma_tag);
1704 }
1705
1706 int
mlx5e_enable_sq(struct mlx5e_sq * sq,struct mlx5e_sq_param * param,int tis_num)1707 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1708 int tis_num)
1709 {
1710 void *in;
1711 void *sqc;
1712 void *wq;
1713 int inlen;
1714 int err;
1715
1716 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1717 sizeof(u64) * sq->wq_ctrl.buf.npages;
1718 in = mlx5_vzalloc(inlen);
1719 if (in == NULL)
1720 return (-ENOMEM);
1721
1722 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1723 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1724
1725 memcpy(sqc, param->sqc, sizeof(param->sqc));
1726
1727 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1728 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1729 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1730 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1731 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1732
1733 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1734 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1735 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1736 PAGE_SHIFT);
1737 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1738
1739 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1740 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1741
1742 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1743
1744 kvfree(in);
1745
1746 return (err);
1747 }
1748
1749 int
mlx5e_modify_sq(struct mlx5e_sq * sq,int curr_state,int next_state)1750 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1751 {
1752 void *in;
1753 void *sqc;
1754 int inlen;
1755 int err;
1756
1757 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1758 in = mlx5_vzalloc(inlen);
1759 if (in == NULL)
1760 return (-ENOMEM);
1761
1762 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1763
1764 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1765 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1766 MLX5_SET(sqc, sqc, state, next_state);
1767
1768 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1769
1770 kvfree(in);
1771
1772 return (err);
1773 }
1774
1775 void
mlx5e_disable_sq(struct mlx5e_sq * sq)1776 mlx5e_disable_sq(struct mlx5e_sq *sq)
1777 {
1778
1779 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1780 }
1781
1782 static int
mlx5e_open_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1783 mlx5e_open_sq(struct mlx5e_channel *c,
1784 int tc,
1785 struct mlx5e_sq_param *param,
1786 struct mlx5e_sq *sq)
1787 {
1788 int err;
1789
1790 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1791
1792 /* ensure the TX completion event factor is not zero */
1793 if (sq->cev_factor == 0)
1794 sq->cev_factor = 1;
1795
1796 err = mlx5e_create_sq(c, tc, param, sq);
1797 if (err)
1798 return (err);
1799
1800 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1801 if (err)
1802 goto err_destroy_sq;
1803
1804 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1805 if (err)
1806 goto err_disable_sq;
1807
1808 WRITE_ONCE(sq->running, 1);
1809
1810 return (0);
1811
1812 err_disable_sq:
1813 mlx5e_disable_sq(sq);
1814 err_destroy_sq:
1815 mlx5e_destroy_sq(sq);
1816
1817 return (err);
1818 }
1819
1820 static void
mlx5e_sq_send_nops_locked(struct mlx5e_sq * sq,int can_sleep)1821 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1822 {
1823 /* fill up remainder with NOPs */
1824 while (sq->cev_counter != 0) {
1825 while (!mlx5e_sq_has_room_for(sq, 1)) {
1826 if (can_sleep != 0) {
1827 mtx_unlock(&sq->lock);
1828 msleep(4);
1829 mtx_lock(&sq->lock);
1830 } else {
1831 goto done;
1832 }
1833 }
1834 /* send a single NOP */
1835 mlx5e_send_nop(sq, 1);
1836 atomic_thread_fence_rel();
1837 }
1838 done:
1839 /* Check if we need to write the doorbell */
1840 if (likely(sq->doorbell.d64 != 0)) {
1841 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1842 sq->doorbell.d64 = 0;
1843 }
1844 }
1845
1846 void
mlx5e_sq_cev_timeout(void * arg)1847 mlx5e_sq_cev_timeout(void *arg)
1848 {
1849 struct mlx5e_sq *sq = arg;
1850
1851 mtx_assert(&sq->lock, MA_OWNED);
1852
1853 /* check next state */
1854 switch (sq->cev_next_state) {
1855 case MLX5E_CEV_STATE_SEND_NOPS:
1856 /* fill TX ring with NOPs, if any */
1857 mlx5e_sq_send_nops_locked(sq, 0);
1858
1859 /* check if completed */
1860 if (sq->cev_counter == 0) {
1861 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1862 return;
1863 }
1864 break;
1865 default:
1866 /* send NOPs on next timeout */
1867 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1868 break;
1869 }
1870
1871 /* restart timer */
1872 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1873 }
1874
1875 void
mlx5e_drain_sq(struct mlx5e_sq * sq)1876 mlx5e_drain_sq(struct mlx5e_sq *sq)
1877 {
1878 int error;
1879 struct mlx5_core_dev *mdev= sq->priv->mdev;
1880
1881 /*
1882 * Check if already stopped.
1883 *
1884 * NOTE: Serialization of this function is managed by the
1885 * caller ensuring the priv's state lock is locked or in case
1886 * of rate limit support, a single thread manages drain and
1887 * resume of SQs. The "running" variable can therefore safely
1888 * be read without any locks.
1889 */
1890 if (READ_ONCE(sq->running) == 0)
1891 return;
1892
1893 /* don't put more packets into the SQ */
1894 WRITE_ONCE(sq->running, 0);
1895
1896 /* serialize access to DMA rings */
1897 mtx_lock(&sq->lock);
1898
1899 /* teardown event factor timer, if any */
1900 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1901 callout_stop(&sq->cev_callout);
1902
1903 /* send dummy NOPs in order to flush the transmit ring */
1904 mlx5e_sq_send_nops_locked(sq, 1);
1905 mtx_unlock(&sq->lock);
1906
1907 /* wait till SQ is empty or link is down */
1908 mtx_lock(&sq->lock);
1909 while (sq->cc != sq->pc &&
1910 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1911 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1912 mtx_unlock(&sq->lock);
1913 msleep(1);
1914 sq->cq.mcq.comp(&sq->cq.mcq, NULL);
1915 mtx_lock(&sq->lock);
1916 }
1917 mtx_unlock(&sq->lock);
1918
1919 /* error out remaining requests */
1920 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1921 if (error != 0) {
1922 mlx5_en_err(sq->ifp,
1923 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1924 }
1925
1926 /* wait till SQ is empty */
1927 mtx_lock(&sq->lock);
1928 while (sq->cc != sq->pc &&
1929 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1930 mtx_unlock(&sq->lock);
1931 msleep(1);
1932 sq->cq.mcq.comp(&sq->cq.mcq, NULL);
1933 mtx_lock(&sq->lock);
1934 }
1935 mtx_unlock(&sq->lock);
1936 }
1937
1938 static void
mlx5e_close_sq_wait(struct mlx5e_sq * sq)1939 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1940 {
1941
1942 mlx5e_drain_sq(sq);
1943 mlx5e_disable_sq(sq);
1944 mlx5e_destroy_sq(sq);
1945 }
1946
1947 static int
mlx5e_create_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)1948 mlx5e_create_cq(struct mlx5e_priv *priv,
1949 struct mlx5e_cq_param *param,
1950 struct mlx5e_cq *cq,
1951 mlx5e_cq_comp_t *comp,
1952 int eq_ix)
1953 {
1954 struct mlx5_core_dev *mdev = priv->mdev;
1955 struct mlx5_core_cq *mcq = &cq->mcq;
1956 int eqn_not_used;
1957 int irqn;
1958 int err;
1959 u32 i;
1960
1961 param->wq.buf_numa_node = 0;
1962 param->wq.db_numa_node = 0;
1963
1964 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1965 if (err)
1966 return (err);
1967
1968 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1969 &cq->wq_ctrl);
1970 if (err)
1971 return (err);
1972
1973 mcq->cqe_sz = 64;
1974 mcq->set_ci_db = cq->wq_ctrl.db.db;
1975 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1976 *mcq->set_ci_db = 0;
1977 *mcq->arm_db = 0;
1978 mcq->vector = eq_ix;
1979 mcq->comp = comp;
1980 mcq->event = mlx5e_cq_error_event;
1981 mcq->irqn = irqn;
1982 mcq->uar = &priv->cq_uar;
1983
1984 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1985 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1986
1987 cqe->op_own = 0xf1;
1988 }
1989
1990 cq->priv = priv;
1991
1992 return (0);
1993 }
1994
1995 static void
mlx5e_destroy_cq(struct mlx5e_cq * cq)1996 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1997 {
1998 mlx5_wq_destroy(&cq->wq_ctrl);
1999 }
2000
2001 static int
mlx5e_enable_cq(struct mlx5e_cq * cq,struct mlx5e_cq_param * param,int eq_ix)2002 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
2003 {
2004 struct mlx5_core_cq *mcq = &cq->mcq;
2005 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
2006 void *in;
2007 void *cqc;
2008 int inlen;
2009 int irqn_not_used;
2010 int eqn;
2011 int err;
2012
2013 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2014 sizeof(u64) * cq->wq_ctrl.buf.npages;
2015 in = mlx5_vzalloc(inlen);
2016 if (in == NULL)
2017 return (-ENOMEM);
2018
2019 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2020
2021 memcpy(cqc, param->cqc, sizeof(param->cqc));
2022
2023 mlx5_fill_page_array(&cq->wq_ctrl.buf,
2024 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
2025
2026 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2027
2028 MLX5_SET(cqc, cqc, c_eqn, eqn);
2029 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
2030 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2031 PAGE_SHIFT);
2032 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2033
2034 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out));
2035
2036 kvfree(in);
2037
2038 if (err)
2039 return (err);
2040
2041 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2042
2043 return (0);
2044 }
2045
2046 static void
mlx5e_disable_cq(struct mlx5e_cq * cq)2047 mlx5e_disable_cq(struct mlx5e_cq *cq)
2048 {
2049
2050 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2051 }
2052
2053 int
mlx5e_open_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)2054 mlx5e_open_cq(struct mlx5e_priv *priv,
2055 struct mlx5e_cq_param *param,
2056 struct mlx5e_cq *cq,
2057 mlx5e_cq_comp_t *comp,
2058 int eq_ix)
2059 {
2060 int err;
2061
2062 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2063 if (err)
2064 return (err);
2065
2066 err = mlx5e_enable_cq(cq, param, eq_ix);
2067 if (err)
2068 goto err_destroy_cq;
2069
2070 return (0);
2071
2072 err_destroy_cq:
2073 mlx5e_destroy_cq(cq);
2074
2075 return (err);
2076 }
2077
2078 void
mlx5e_close_cq(struct mlx5e_cq * cq)2079 mlx5e_close_cq(struct mlx5e_cq *cq)
2080 {
2081 mlx5e_disable_cq(cq);
2082 mlx5e_destroy_cq(cq);
2083 }
2084
2085 static int
mlx5e_open_tx_cqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)2086 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2087 struct mlx5e_channel_param *cparam)
2088 {
2089 int err;
2090 int tc;
2091
2092 for (tc = 0; tc < c->priv->num_tc; tc++) {
2093 /* open completion queue */
2094 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2095 &mlx5e_tx_cq_comp, c->ix);
2096 if (err)
2097 goto err_close_tx_cqs;
2098 }
2099 return (0);
2100
2101 err_close_tx_cqs:
2102 for (tc--; tc >= 0; tc--)
2103 mlx5e_close_cq(&c->sq[tc].cq);
2104
2105 return (err);
2106 }
2107
2108 static void
mlx5e_close_tx_cqs(struct mlx5e_channel * c)2109 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2110 {
2111 int tc;
2112
2113 for (tc = 0; tc < c->priv->num_tc; tc++)
2114 mlx5e_close_cq(&c->sq[tc].cq);
2115 }
2116
2117 static int
mlx5e_open_sqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)2118 mlx5e_open_sqs(struct mlx5e_channel *c,
2119 struct mlx5e_channel_param *cparam)
2120 {
2121 int err;
2122 int tc;
2123
2124 for (tc = 0; tc < c->priv->num_tc; tc++) {
2125 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2126 if (err)
2127 goto err_close_sqs;
2128 }
2129
2130 return (0);
2131
2132 err_close_sqs:
2133 for (tc--; tc >= 0; tc--)
2134 mlx5e_close_sq_wait(&c->sq[tc]);
2135
2136 return (err);
2137 }
2138
2139 static void
mlx5e_close_sqs_wait(struct mlx5e_channel * c)2140 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2141 {
2142 int tc;
2143
2144 for (tc = 0; tc < c->priv->num_tc; tc++)
2145 mlx5e_close_sq_wait(&c->sq[tc]);
2146 }
2147
2148 static void
mlx5e_chan_static_init(struct mlx5e_priv * priv,struct mlx5e_channel * c,int ix)2149 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2150 {
2151 int tc;
2152
2153 /* setup priv and channel number */
2154 c->priv = priv;
2155 c->ix = ix;
2156
2157 /* setup send tag */
2158 c->tag.m_snd_tag.ifp = priv->ifp;
2159 c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2160
2161 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2162
2163 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2164
2165 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2166 struct mlx5e_sq *sq = c->sq + tc;
2167
2168 mtx_init(&sq->lock, "mlx5tx",
2169 MTX_NETWORK_LOCK " TX", MTX_DEF);
2170 mtx_init(&sq->comp_lock, "mlx5comp",
2171 MTX_NETWORK_LOCK " TX", MTX_DEF);
2172
2173 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2174 }
2175 }
2176
2177 static void
mlx5e_chan_static_destroy(struct mlx5e_channel * c)2178 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2179 {
2180 int tc;
2181
2182 callout_drain(&c->rq.watchdog);
2183
2184 mtx_destroy(&c->rq.mtx);
2185
2186 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2187 callout_drain(&c->sq[tc].cev_callout);
2188 mtx_destroy(&c->sq[tc].lock);
2189 mtx_destroy(&c->sq[tc].comp_lock);
2190 }
2191 }
2192
2193 static int
mlx5e_open_channel(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam,struct mlx5e_channel * c)2194 mlx5e_open_channel(struct mlx5e_priv *priv,
2195 struct mlx5e_channel_param *cparam,
2196 struct mlx5e_channel *c)
2197 {
2198 struct epoch_tracker et;
2199 int i, err;
2200
2201 /* zero non-persistent data */
2202 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2203 for (i = 0; i != priv->num_tc; i++)
2204 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2205
2206 /* open transmit completion queue */
2207 err = mlx5e_open_tx_cqs(c, cparam);
2208 if (err)
2209 goto err_free;
2210
2211 /* open receive completion queue */
2212 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2213 &mlx5e_rx_cq_comp, c->ix);
2214 if (err)
2215 goto err_close_tx_cqs;
2216
2217 err = mlx5e_open_sqs(c, cparam);
2218 if (err)
2219 goto err_close_rx_cq;
2220
2221 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2222 if (err)
2223 goto err_close_sqs;
2224
2225 /* poll receive queue initially */
2226 NET_EPOCH_ENTER_ET(et);
2227 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL);
2228 NET_EPOCH_EXIT_ET(et);
2229
2230 return (0);
2231
2232 err_close_sqs:
2233 mlx5e_close_sqs_wait(c);
2234
2235 err_close_rx_cq:
2236 mlx5e_close_cq(&c->rq.cq);
2237
2238 err_close_tx_cqs:
2239 mlx5e_close_tx_cqs(c);
2240
2241 err_free:
2242 return (err);
2243 }
2244
2245 static void
mlx5e_close_channel(struct mlx5e_channel * c)2246 mlx5e_close_channel(struct mlx5e_channel *c)
2247 {
2248 mlx5e_close_rq(&c->rq);
2249 }
2250
2251 static void
mlx5e_close_channel_wait(struct mlx5e_channel * c)2252 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2253 {
2254 mlx5e_close_rq_wait(&c->rq);
2255 mlx5e_close_sqs_wait(c);
2256 mlx5e_close_tx_cqs(c);
2257 }
2258
2259 static int
mlx5e_get_wqe_sz(struct mlx5e_priv * priv,u32 * wqe_sz,u32 * nsegs)2260 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2261 {
2262 u32 r, n;
2263
2264 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2265 MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2266 if (r > MJUM16BYTES)
2267 return (-ENOMEM);
2268
2269 if (r > MJUM9BYTES)
2270 r = MJUM16BYTES;
2271 else if (r > MJUMPAGESIZE)
2272 r = MJUM9BYTES;
2273 else if (r > MCLBYTES)
2274 r = MJUMPAGESIZE;
2275 else
2276 r = MCLBYTES;
2277
2278 /*
2279 * n + 1 must be a power of two, because stride size must be.
2280 * Stride size is 16 * (n + 1), as the first segment is
2281 * control.
2282 */
2283 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2284 ;
2285
2286 if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2287 return (-ENOMEM);
2288
2289 *wqe_sz = r;
2290 *nsegs = n;
2291 return (0);
2292 }
2293
2294 static void
mlx5e_build_rq_param(struct mlx5e_priv * priv,struct mlx5e_rq_param * param)2295 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2296 struct mlx5e_rq_param *param)
2297 {
2298 void *rqc = param->rqc;
2299 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2300 u32 wqe_sz, nsegs;
2301
2302 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2303 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2304 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2305 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2306 nsegs * sizeof(struct mlx5_wqe_data_seg)));
2307 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2308 MLX5_SET(wq, wq, pd, priv->pdn);
2309
2310 param->wq.buf_numa_node = 0;
2311 param->wq.db_numa_node = 0;
2312 param->wq.linear = 1;
2313 }
2314
2315 static void
mlx5e_build_sq_param(struct mlx5e_priv * priv,struct mlx5e_sq_param * param)2316 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2317 struct mlx5e_sq_param *param)
2318 {
2319 void *sqc = param->sqc;
2320 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2321
2322 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2323 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2324 MLX5_SET(wq, wq, pd, priv->pdn);
2325
2326 param->wq.buf_numa_node = 0;
2327 param->wq.db_numa_node = 0;
2328 param->wq.linear = 1;
2329 }
2330
2331 static void
mlx5e_build_common_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2332 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2333 struct mlx5e_cq_param *param)
2334 {
2335 void *cqc = param->cqc;
2336
2337 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2338 }
2339
2340 static void
mlx5e_get_default_profile(struct mlx5e_priv * priv,int mode,struct net_dim_cq_moder * ptr)2341 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2342 {
2343
2344 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2345
2346 /* apply LRO restrictions */
2347 if (priv->params.hw_lro_en &&
2348 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2349 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2350 }
2351 }
2352
2353 static void
mlx5e_build_rx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2354 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2355 struct mlx5e_cq_param *param)
2356 {
2357 struct net_dim_cq_moder curr;
2358 void *cqc = param->cqc;
2359
2360 /*
2361 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2362 * format is more beneficial for FreeBSD use case.
2363 *
2364 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2365 * in mlx5e_decompress_cqe.
2366 */
2367 if (priv->params.cqe_zipping_en) {
2368 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2369 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2370 }
2371
2372 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2373
2374 switch (priv->params.rx_cq_moderation_mode) {
2375 case 0:
2376 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2377 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2378 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2379 break;
2380 case 1:
2381 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2382 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2383 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2384 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2385 else
2386 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2387 break;
2388 case 2:
2389 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2390 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2391 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2392 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2393 break;
2394 case 3:
2395 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2396 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2397 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2398 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2399 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2400 else
2401 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2402 break;
2403 default:
2404 break;
2405 }
2406
2407 mlx5e_dim_build_cq_param(priv, param);
2408
2409 mlx5e_build_common_cq_param(priv, param);
2410 }
2411
2412 static void
mlx5e_build_tx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2413 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2414 struct mlx5e_cq_param *param)
2415 {
2416 void *cqc = param->cqc;
2417
2418 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2419 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2420 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2421
2422 switch (priv->params.tx_cq_moderation_mode) {
2423 case 0:
2424 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2425 break;
2426 default:
2427 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2428 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2429 else
2430 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2431 break;
2432 }
2433
2434 mlx5e_build_common_cq_param(priv, param);
2435 }
2436
2437 static void
mlx5e_build_channel_param(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam)2438 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2439 struct mlx5e_channel_param *cparam)
2440 {
2441 memset(cparam, 0, sizeof(*cparam));
2442
2443 mlx5e_build_rq_param(priv, &cparam->rq);
2444 mlx5e_build_sq_param(priv, &cparam->sq);
2445 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2446 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2447 }
2448
2449 static int
mlx5e_open_channels(struct mlx5e_priv * priv)2450 mlx5e_open_channels(struct mlx5e_priv *priv)
2451 {
2452 struct mlx5e_channel_param *cparam;
2453 int err;
2454 int i;
2455 int j;
2456
2457 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2458
2459 mlx5e_build_channel_param(priv, cparam);
2460 for (i = 0; i < priv->params.num_channels; i++) {
2461 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2462 if (err)
2463 goto err_close_channels;
2464 }
2465
2466 for (j = 0; j < priv->params.num_channels; j++) {
2467 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2468 if (err)
2469 goto err_close_channels;
2470 }
2471 free(cparam, M_MLX5EN);
2472 return (0);
2473
2474 err_close_channels:
2475 while (i--) {
2476 mlx5e_close_channel(&priv->channel[i]);
2477 mlx5e_close_channel_wait(&priv->channel[i]);
2478 }
2479 free(cparam, M_MLX5EN);
2480 return (err);
2481 }
2482
2483 static void
mlx5e_close_channels(struct mlx5e_priv * priv)2484 mlx5e_close_channels(struct mlx5e_priv *priv)
2485 {
2486 int i;
2487
2488 for (i = 0; i < priv->params.num_channels; i++)
2489 mlx5e_close_channel(&priv->channel[i]);
2490 for (i = 0; i < priv->params.num_channels; i++)
2491 mlx5e_close_channel_wait(&priv->channel[i]);
2492 }
2493
2494 static int
mlx5e_refresh_sq_params(struct mlx5e_priv * priv,struct mlx5e_sq * sq)2495 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2496 {
2497
2498 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2499 uint8_t cq_mode;
2500
2501 switch (priv->params.tx_cq_moderation_mode) {
2502 case 0:
2503 case 2:
2504 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2505 break;
2506 default:
2507 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2508 break;
2509 }
2510
2511 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2512 priv->params.tx_cq_moderation_usec,
2513 priv->params.tx_cq_moderation_pkts,
2514 cq_mode));
2515 }
2516
2517 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2518 priv->params.tx_cq_moderation_usec,
2519 priv->params.tx_cq_moderation_pkts));
2520 }
2521
2522 static int
mlx5e_refresh_rq_params(struct mlx5e_priv * priv,struct mlx5e_rq * rq)2523 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2524 {
2525
2526 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2527 uint8_t cq_mode;
2528 uint8_t dim_mode;
2529 int retval;
2530
2531 switch (priv->params.rx_cq_moderation_mode) {
2532 case 0:
2533 case 2:
2534 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2535 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2536 break;
2537 default:
2538 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2539 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2540 break;
2541 }
2542
2543 /* tear down dynamic interrupt moderation */
2544 mtx_lock(&rq->mtx);
2545 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2546 mtx_unlock(&rq->mtx);
2547
2548 /* wait for dynamic interrupt moderation work task, if any */
2549 cancel_work_sync(&rq->dim.work);
2550
2551 if (priv->params.rx_cq_moderation_mode >= 2) {
2552 struct net_dim_cq_moder curr;
2553
2554 mlx5e_get_default_profile(priv, dim_mode, &curr);
2555
2556 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2557 curr.usec, curr.pkts, cq_mode);
2558
2559 /* set dynamic interrupt moderation mode and zero defaults */
2560 mtx_lock(&rq->mtx);
2561 rq->dim.mode = dim_mode;
2562 rq->dim.state = 0;
2563 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2564 mtx_unlock(&rq->mtx);
2565 } else {
2566 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2567 priv->params.rx_cq_moderation_usec,
2568 priv->params.rx_cq_moderation_pkts,
2569 cq_mode);
2570 }
2571 return (retval);
2572 }
2573
2574 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2575 priv->params.rx_cq_moderation_usec,
2576 priv->params.rx_cq_moderation_pkts));
2577 }
2578
2579 static int
mlx5e_refresh_channel_params_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)2580 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2581 {
2582 int err;
2583 int i;
2584
2585 err = mlx5e_refresh_rq_params(priv, &c->rq);
2586 if (err)
2587 goto done;
2588
2589 for (i = 0; i != priv->num_tc; i++) {
2590 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2591 if (err)
2592 goto done;
2593 }
2594 done:
2595 return (err);
2596 }
2597
2598 int
mlx5e_refresh_channel_params(struct mlx5e_priv * priv)2599 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2600 {
2601 int i;
2602
2603 /* check if channels are closed */
2604 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2605 return (EINVAL);
2606
2607 for (i = 0; i < priv->params.num_channels; i++) {
2608 int err;
2609
2610 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2611 if (err)
2612 return (err);
2613 }
2614 return (0);
2615 }
2616
2617 static int
mlx5e_open_tis(struct mlx5e_priv * priv,int tc)2618 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2619 {
2620 struct mlx5_core_dev *mdev = priv->mdev;
2621 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2622 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2623
2624 memset(in, 0, sizeof(in));
2625
2626 MLX5_SET(tisc, tisc, prio, tc);
2627 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2628
2629 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2630 }
2631
2632 static void
mlx5e_close_tis(struct mlx5e_priv * priv,int tc)2633 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2634 {
2635 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2636 }
2637
2638 static int
mlx5e_open_tises(struct mlx5e_priv * priv)2639 mlx5e_open_tises(struct mlx5e_priv *priv)
2640 {
2641 int num_tc = priv->num_tc;
2642 int err;
2643 int tc;
2644
2645 for (tc = 0; tc < num_tc; tc++) {
2646 err = mlx5e_open_tis(priv, tc);
2647 if (err)
2648 goto err_close_tises;
2649 }
2650
2651 return (0);
2652
2653 err_close_tises:
2654 for (tc--; tc >= 0; tc--)
2655 mlx5e_close_tis(priv, tc);
2656
2657 return (err);
2658 }
2659
2660 static void
mlx5e_close_tises(struct mlx5e_priv * priv)2661 mlx5e_close_tises(struct mlx5e_priv *priv)
2662 {
2663 int num_tc = priv->num_tc;
2664 int tc;
2665
2666 for (tc = 0; tc < num_tc; tc++)
2667 mlx5e_close_tis(priv, tc);
2668 }
2669
2670 static int
mlx5e_open_rqt(struct mlx5e_priv * priv)2671 mlx5e_open_rqt(struct mlx5e_priv *priv)
2672 {
2673 struct mlx5_core_dev *mdev = priv->mdev;
2674 u32 *in;
2675 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2676 void *rqtc;
2677 int inlen;
2678 int err;
2679 int sz;
2680 int i;
2681
2682 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2683
2684 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2685 in = mlx5_vzalloc(inlen);
2686 if (in == NULL)
2687 return (-ENOMEM);
2688 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2689
2690 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2691 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2692
2693 for (i = 0; i < sz; i++) {
2694 int ix = i;
2695 #ifdef RSS
2696 ix = rss_get_indirection_to_bucket(ix);
2697 #endif
2698 /* ensure we don't overflow */
2699 ix %= priv->params.num_channels;
2700
2701 /* apply receive side scaling stride, if any */
2702 ix -= ix % (int)priv->params.channels_rsss;
2703
2704 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2705 }
2706
2707 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2708
2709 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2710 if (!err)
2711 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2712
2713 kvfree(in);
2714
2715 return (err);
2716 }
2717
2718 static void
mlx5e_close_rqt(struct mlx5e_priv * priv)2719 mlx5e_close_rqt(struct mlx5e_priv *priv)
2720 {
2721 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2722 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2723
2724 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2725 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2726
2727 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2728 }
2729
2730 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */
2731
2732 static void
mlx5e_get_rss_key(void * key_ptr)2733 mlx5e_get_rss_key(void *key_ptr)
2734 {
2735 #ifdef RSS
2736 rss_getkey(key_ptr);
2737 #else
2738 static const u32 rsskey[] = {
2739 cpu_to_be32(0xD181C62C),
2740 cpu_to_be32(0xF7F4DB5B),
2741 cpu_to_be32(0x1983A2FC),
2742 cpu_to_be32(0x943E1ADB),
2743 cpu_to_be32(0xD9389E6B),
2744 cpu_to_be32(0xD1039C2C),
2745 cpu_to_be32(0xA74499AD),
2746 cpu_to_be32(0x593D56D9),
2747 cpu_to_be32(0xF3253C06),
2748 cpu_to_be32(0x2ADC1FFC),
2749 };
2750 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE);
2751 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE);
2752 #endif
2753 }
2754
2755 static void
mlx5e_build_tir_ctx(struct mlx5e_priv * priv,u32 * tirc,int tt)2756 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2757 {
2758 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2759 __be32 *hkey;
2760
2761 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2762
2763 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2764
2765 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2766 MLX5_HASH_FIELD_SEL_DST_IP)
2767
2768 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2769 MLX5_HASH_FIELD_SEL_DST_IP |\
2770 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2771 MLX5_HASH_FIELD_SEL_L4_DPORT)
2772
2773 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2774 MLX5_HASH_FIELD_SEL_DST_IP |\
2775 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2776
2777 if (priv->params.hw_lro_en) {
2778 MLX5_SET(tirc, tirc, lro_enable_mask,
2779 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2780 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2781 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2782 (priv->params.lro_wqe_sz -
2783 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2784 /* TODO: add the option to choose timer value dynamically */
2785 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2786 MLX5_CAP_ETH(priv->mdev,
2787 lro_timer_supported_periods[2]));
2788 }
2789
2790 /* setup parameters for hashing TIR type, if any */
2791 switch (tt) {
2792 case MLX5E_TT_ANY:
2793 MLX5_SET(tirc, tirc, disp_type,
2794 MLX5_TIRC_DISP_TYPE_DIRECT);
2795 MLX5_SET(tirc, tirc, inline_rqn,
2796 priv->channel[0].rq.rqn);
2797 break;
2798 default:
2799 MLX5_SET(tirc, tirc, disp_type,
2800 MLX5_TIRC_DISP_TYPE_INDIRECT);
2801 MLX5_SET(tirc, tirc, indirect_table,
2802 priv->rqtn);
2803 MLX5_SET(tirc, tirc, rx_hash_fn,
2804 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2805 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2806
2807 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >=
2808 MLX5E_RSS_KEY_SIZE);
2809 #ifdef RSS
2810 /*
2811 * The FreeBSD RSS implementation does currently not
2812 * support symmetric Toeplitz hashes:
2813 */
2814 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2815 #else
2816 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2817 #endif
2818 mlx5e_get_rss_key(hkey);
2819 break;
2820 }
2821
2822 switch (tt) {
2823 case MLX5E_TT_IPV4_TCP:
2824 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2825 MLX5_L3_PROT_TYPE_IPV4);
2826 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2827 MLX5_L4_PROT_TYPE_TCP);
2828 #ifdef RSS
2829 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2830 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2831 MLX5_HASH_IP);
2832 } else
2833 #endif
2834 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2835 MLX5_HASH_ALL);
2836 break;
2837
2838 case MLX5E_TT_IPV6_TCP:
2839 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2840 MLX5_L3_PROT_TYPE_IPV6);
2841 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2842 MLX5_L4_PROT_TYPE_TCP);
2843 #ifdef RSS
2844 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2845 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2846 MLX5_HASH_IP);
2847 } else
2848 #endif
2849 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2850 MLX5_HASH_ALL);
2851 break;
2852
2853 case MLX5E_TT_IPV4_UDP:
2854 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2855 MLX5_L3_PROT_TYPE_IPV4);
2856 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2857 MLX5_L4_PROT_TYPE_UDP);
2858 #ifdef RSS
2859 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2860 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2861 MLX5_HASH_IP);
2862 } else
2863 #endif
2864 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2865 MLX5_HASH_ALL);
2866 break;
2867
2868 case MLX5E_TT_IPV6_UDP:
2869 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2870 MLX5_L3_PROT_TYPE_IPV6);
2871 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2872 MLX5_L4_PROT_TYPE_UDP);
2873 #ifdef RSS
2874 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2875 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2876 MLX5_HASH_IP);
2877 } else
2878 #endif
2879 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2880 MLX5_HASH_ALL);
2881 break;
2882
2883 case MLX5E_TT_IPV4_IPSEC_AH:
2884 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2885 MLX5_L3_PROT_TYPE_IPV4);
2886 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2887 MLX5_HASH_IP_IPSEC_SPI);
2888 break;
2889
2890 case MLX5E_TT_IPV6_IPSEC_AH:
2891 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2892 MLX5_L3_PROT_TYPE_IPV6);
2893 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2894 MLX5_HASH_IP_IPSEC_SPI);
2895 break;
2896
2897 case MLX5E_TT_IPV4_IPSEC_ESP:
2898 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2899 MLX5_L3_PROT_TYPE_IPV4);
2900 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2901 MLX5_HASH_IP_IPSEC_SPI);
2902 break;
2903
2904 case MLX5E_TT_IPV6_IPSEC_ESP:
2905 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2906 MLX5_L3_PROT_TYPE_IPV6);
2907 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2908 MLX5_HASH_IP_IPSEC_SPI);
2909 break;
2910
2911 case MLX5E_TT_IPV4:
2912 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2913 MLX5_L3_PROT_TYPE_IPV4);
2914 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2915 MLX5_HASH_IP);
2916 break;
2917
2918 case MLX5E_TT_IPV6:
2919 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2920 MLX5_L3_PROT_TYPE_IPV6);
2921 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2922 MLX5_HASH_IP);
2923 break;
2924
2925 default:
2926 break;
2927 }
2928 }
2929
2930 static int
mlx5e_open_tir(struct mlx5e_priv * priv,int tt)2931 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2932 {
2933 struct mlx5_core_dev *mdev = priv->mdev;
2934 u32 *in;
2935 void *tirc;
2936 int inlen;
2937 int err;
2938
2939 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2940 in = mlx5_vzalloc(inlen);
2941 if (in == NULL)
2942 return (-ENOMEM);
2943 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2944
2945 mlx5e_build_tir_ctx(priv, tirc, tt);
2946
2947 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2948
2949 kvfree(in);
2950
2951 return (err);
2952 }
2953
2954 static void
mlx5e_close_tir(struct mlx5e_priv * priv,int tt)2955 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2956 {
2957 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2958 }
2959
2960 static int
mlx5e_open_tirs(struct mlx5e_priv * priv)2961 mlx5e_open_tirs(struct mlx5e_priv *priv)
2962 {
2963 int err;
2964 int i;
2965
2966 for (i = 0; i < MLX5E_NUM_TT; i++) {
2967 err = mlx5e_open_tir(priv, i);
2968 if (err)
2969 goto err_close_tirs;
2970 }
2971
2972 return (0);
2973
2974 err_close_tirs:
2975 for (i--; i >= 0; i--)
2976 mlx5e_close_tir(priv, i);
2977
2978 return (err);
2979 }
2980
2981 static void
mlx5e_close_tirs(struct mlx5e_priv * priv)2982 mlx5e_close_tirs(struct mlx5e_priv *priv)
2983 {
2984 int i;
2985
2986 for (i = 0; i < MLX5E_NUM_TT; i++)
2987 mlx5e_close_tir(priv, i);
2988 }
2989
2990 /*
2991 * SW MTU does not include headers,
2992 * HW MTU includes all headers and checksums.
2993 */
2994 static int
mlx5e_set_dev_port_mtu(struct ifnet * ifp,int sw_mtu)2995 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2996 {
2997 struct mlx5e_priv *priv = ifp->if_softc;
2998 struct mlx5_core_dev *mdev = priv->mdev;
2999 int hw_mtu;
3000 int err;
3001
3002 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
3003
3004 err = mlx5_set_port_mtu(mdev, hw_mtu);
3005 if (err) {
3006 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
3007 sw_mtu, err);
3008 return (err);
3009 }
3010
3011 /* Update vport context MTU */
3012 err = mlx5_set_vport_mtu(mdev, hw_mtu);
3013 if (err) {
3014 mlx5_en_err(ifp,
3015 "Failed updating vport context with MTU size, err=%d\n",
3016 err);
3017 }
3018
3019 ifp->if_mtu = sw_mtu;
3020
3021 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
3022 if (err || !hw_mtu) {
3023 /* fallback to port oper mtu */
3024 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
3025 }
3026 if (err) {
3027 mlx5_en_err(ifp,
3028 "Query port MTU, after setting new MTU value, failed\n");
3029 return (err);
3030 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3031 err = -E2BIG,
3032 mlx5_en_err(ifp,
3033 "Port MTU %d is smaller than ifp mtu %d\n",
3034 hw_mtu, sw_mtu);
3035 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3036 err = -EINVAL;
3037 mlx5_en_err(ifp,
3038 "Port MTU %d is bigger than ifp mtu %d\n",
3039 hw_mtu, sw_mtu);
3040 }
3041 priv->params_ethtool.hw_mtu = hw_mtu;
3042
3043 return (err);
3044 }
3045
3046 int
mlx5e_open_locked(struct ifnet * ifp)3047 mlx5e_open_locked(struct ifnet *ifp)
3048 {
3049 struct mlx5e_priv *priv = ifp->if_softc;
3050 int err;
3051 u16 set_id;
3052
3053 /* check if already opened */
3054 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3055 return (0);
3056
3057 #ifdef RSS
3058 if (rss_getnumbuckets() > priv->params.num_channels) {
3059 mlx5_en_info(ifp,
3060 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3061 rss_getnumbuckets(), priv->params.num_channels);
3062 }
3063 #endif
3064 err = mlx5e_open_tises(priv);
3065 if (err) {
3066 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3067 return (err);
3068 }
3069 err = mlx5_vport_alloc_q_counter(priv->mdev,
3070 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3071 if (err) {
3072 mlx5_en_err(priv->ifp,
3073 "mlx5_vport_alloc_q_counter failed: %d\n", err);
3074 goto err_close_tises;
3075 }
3076 /* store counter set ID */
3077 priv->counter_set_id = set_id;
3078
3079 err = mlx5e_open_channels(priv);
3080 if (err) {
3081 mlx5_en_err(ifp,
3082 "mlx5e_open_channels failed, %d\n", err);
3083 goto err_dalloc_q_counter;
3084 }
3085 err = mlx5e_open_rqt(priv);
3086 if (err) {
3087 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
3088 goto err_close_channels;
3089 }
3090 err = mlx5e_open_tirs(priv);
3091 if (err) {
3092 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
3093 goto err_close_rqls;
3094 }
3095 err = mlx5e_open_flow_table(priv);
3096 if (err) {
3097 mlx5_en_err(ifp,
3098 "mlx5e_open_flow_table failed, %d\n", err);
3099 goto err_close_tirs;
3100 }
3101 err = mlx5e_add_all_vlan_rules(priv);
3102 if (err) {
3103 mlx5_en_err(ifp,
3104 "mlx5e_add_all_vlan_rules failed, %d\n", err);
3105 goto err_close_flow_table;
3106 }
3107 set_bit(MLX5E_STATE_OPENED, &priv->state);
3108
3109 mlx5e_update_carrier(priv);
3110 mlx5e_set_rx_mode_core(priv);
3111
3112 return (0);
3113
3114 err_close_flow_table:
3115 mlx5e_close_flow_table(priv);
3116
3117 err_close_tirs:
3118 mlx5e_close_tirs(priv);
3119
3120 err_close_rqls:
3121 mlx5e_close_rqt(priv);
3122
3123 err_close_channels:
3124 mlx5e_close_channels(priv);
3125
3126 err_dalloc_q_counter:
3127 mlx5_vport_dealloc_q_counter(priv->mdev,
3128 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3129
3130 err_close_tises:
3131 mlx5e_close_tises(priv);
3132
3133 return (err);
3134 }
3135
3136 static void
mlx5e_open(void * arg)3137 mlx5e_open(void *arg)
3138 {
3139 struct mlx5e_priv *priv = arg;
3140
3141 PRIV_LOCK(priv);
3142 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3143 mlx5_en_err(priv->ifp,
3144 "Setting port status to up failed\n");
3145
3146 mlx5e_open_locked(priv->ifp);
3147 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3148 PRIV_UNLOCK(priv);
3149 }
3150
3151 int
mlx5e_close_locked(struct ifnet * ifp)3152 mlx5e_close_locked(struct ifnet *ifp)
3153 {
3154 struct mlx5e_priv *priv = ifp->if_softc;
3155
3156 /* check if already closed */
3157 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3158 return (0);
3159
3160 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3161
3162 mlx5e_set_rx_mode_core(priv);
3163 mlx5e_del_all_vlan_rules(priv);
3164 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3165 mlx5e_close_flow_table(priv);
3166 mlx5e_close_tirs(priv);
3167 mlx5e_close_rqt(priv);
3168 mlx5e_close_channels(priv);
3169 mlx5_vport_dealloc_q_counter(priv->mdev,
3170 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3171 mlx5e_close_tises(priv);
3172
3173 return (0);
3174 }
3175
3176 #if (__FreeBSD_version >= 1100000)
3177 static uint64_t
mlx5e_get_counter(struct ifnet * ifp,ift_counter cnt)3178 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3179 {
3180 struct mlx5e_priv *priv = ifp->if_softc;
3181 u64 retval;
3182
3183 /* PRIV_LOCK(priv); XXX not allowed */
3184 switch (cnt) {
3185 case IFCOUNTER_IPACKETS:
3186 retval = priv->stats.vport.rx_packets;
3187 break;
3188 case IFCOUNTER_IERRORS:
3189 retval = priv->stats.pport.in_range_len_errors +
3190 priv->stats.pport.out_of_range_len +
3191 priv->stats.pport.too_long_errors +
3192 priv->stats.pport.check_seq_err +
3193 priv->stats.pport.alignment_err;
3194 break;
3195 case IFCOUNTER_IQDROPS:
3196 retval = priv->stats.vport.rx_out_of_buffer;
3197 break;
3198 case IFCOUNTER_OPACKETS:
3199 retval = priv->stats.vport.tx_packets;
3200 break;
3201 case IFCOUNTER_OERRORS:
3202 retval = priv->stats.port_stats_debug.out_discards;
3203 break;
3204 case IFCOUNTER_IBYTES:
3205 retval = priv->stats.vport.rx_bytes;
3206 break;
3207 case IFCOUNTER_OBYTES:
3208 retval = priv->stats.vport.tx_bytes;
3209 break;
3210 case IFCOUNTER_IMCASTS:
3211 retval = priv->stats.vport.rx_multicast_packets;
3212 break;
3213 case IFCOUNTER_OMCASTS:
3214 retval = priv->stats.vport.tx_multicast_packets;
3215 break;
3216 case IFCOUNTER_OQDROPS:
3217 retval = priv->stats.vport.tx_queue_dropped;
3218 break;
3219 case IFCOUNTER_COLLISIONS:
3220 retval = priv->stats.pport.collisions;
3221 break;
3222 default:
3223 retval = if_get_counter_default(ifp, cnt);
3224 break;
3225 }
3226 /* PRIV_UNLOCK(priv); XXX not allowed */
3227 return (retval);
3228 }
3229 #endif
3230
3231 static void
mlx5e_set_rx_mode(struct ifnet * ifp)3232 mlx5e_set_rx_mode(struct ifnet *ifp)
3233 {
3234 struct mlx5e_priv *priv = ifp->if_softc;
3235
3236 queue_work(priv->wq, &priv->set_rx_mode_work);
3237 }
3238
3239 static int
mlx5e_ioctl(struct ifnet * ifp,u_long command,caddr_t data)3240 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3241 {
3242 struct mlx5e_priv *priv;
3243 struct ifreq *ifr;
3244 struct ifdownreason *ifdr;
3245 struct ifi2creq i2c;
3246 struct ifrsskey *ifrk;
3247 struct ifrsshash *ifrh;
3248 int error = 0;
3249 int mask = 0;
3250 int size_read = 0;
3251 int module_status;
3252 int module_num;
3253 int max_mtu;
3254 uint8_t read_addr;
3255
3256 priv = ifp->if_softc;
3257
3258 /* check if detaching */
3259 if (priv == NULL || priv->gone != 0)
3260 return (ENXIO);
3261
3262 switch (command) {
3263 case SIOCSIFMTU:
3264 ifr = (struct ifreq *)data;
3265
3266 PRIV_LOCK(priv);
3267 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3268
3269 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3270 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3271 int was_opened;
3272
3273 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3274 if (was_opened)
3275 mlx5e_close_locked(ifp);
3276
3277 /* set new MTU */
3278 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3279
3280 if (was_opened)
3281 mlx5e_open_locked(ifp);
3282 } else {
3283 error = EINVAL;
3284 mlx5_en_err(ifp,
3285 "Invalid MTU value. Min val: %d, Max val: %d\n",
3286 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3287 }
3288 PRIV_UNLOCK(priv);
3289 break;
3290 case SIOCSIFFLAGS:
3291 if ((ifp->if_flags & IFF_UP) &&
3292 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3293 mlx5e_set_rx_mode(ifp);
3294 break;
3295 }
3296 PRIV_LOCK(priv);
3297 if (ifp->if_flags & IFF_UP) {
3298 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3299 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3300 mlx5e_open_locked(ifp);
3301 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3302 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3303 }
3304 } else {
3305 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3306 mlx5_set_port_status(priv->mdev,
3307 MLX5_PORT_DOWN);
3308 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3309 mlx5e_close_locked(ifp);
3310 mlx5e_update_carrier(priv);
3311 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3312 }
3313 }
3314 PRIV_UNLOCK(priv);
3315 break;
3316 case SIOCADDMULTI:
3317 case SIOCDELMULTI:
3318 mlx5e_set_rx_mode(ifp);
3319 break;
3320 case SIOCSIFMEDIA:
3321 case SIOCGIFMEDIA:
3322 case SIOCGIFXMEDIA:
3323 ifr = (struct ifreq *)data;
3324 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3325 break;
3326 case SIOCSIFCAP:
3327 ifr = (struct ifreq *)data;
3328 PRIV_LOCK(priv);
3329 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3330
3331 if (mask & IFCAP_TXCSUM) {
3332 ifp->if_capenable ^= IFCAP_TXCSUM;
3333 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3334
3335 if (IFCAP_TSO4 & ifp->if_capenable &&
3336 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3337 mask &= ~IFCAP_TSO4;
3338 ifp->if_capenable &= ~IFCAP_TSO4;
3339 ifp->if_hwassist &= ~CSUM_IP_TSO;
3340 mlx5_en_err(ifp,
3341 "tso4 disabled due to -txcsum.\n");
3342 }
3343 }
3344 if (mask & IFCAP_TXCSUM_IPV6) {
3345 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3346 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3347
3348 if (IFCAP_TSO6 & ifp->if_capenable &&
3349 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3350 mask &= ~IFCAP_TSO6;
3351 ifp->if_capenable &= ~IFCAP_TSO6;
3352 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3353 mlx5_en_err(ifp,
3354 "tso6 disabled due to -txcsum6.\n");
3355 }
3356 }
3357 if (mask & IFCAP_RXCSUM)
3358 ifp->if_capenable ^= IFCAP_RXCSUM;
3359 if (mask & IFCAP_RXCSUM_IPV6)
3360 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3361 if (mask & IFCAP_TSO4) {
3362 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3363 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3364 mlx5_en_err(ifp, "enable txcsum first.\n");
3365 error = EAGAIN;
3366 goto out;
3367 }
3368 ifp->if_capenable ^= IFCAP_TSO4;
3369 ifp->if_hwassist ^= CSUM_IP_TSO;
3370 }
3371 if (mask & IFCAP_TSO6) {
3372 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3373 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3374 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3375 error = EAGAIN;
3376 goto out;
3377 }
3378 ifp->if_capenable ^= IFCAP_TSO6;
3379 ifp->if_hwassist ^= CSUM_IP6_TSO;
3380 }
3381 if (mask & IFCAP_VLAN_HWTSO)
3382 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3383 if (mask & IFCAP_VLAN_HWFILTER) {
3384 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3385 mlx5e_disable_vlan_filter(priv);
3386 else
3387 mlx5e_enable_vlan_filter(priv);
3388
3389 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3390 }
3391 if (mask & IFCAP_VLAN_HWTAGGING)
3392 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3393 if (mask & IFCAP_WOL_MAGIC)
3394 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3395
3396 VLAN_CAPABILITIES(ifp);
3397 /* turn off LRO means also turn of HW LRO - if it's on */
3398 if (mask & IFCAP_LRO) {
3399 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3400 bool need_restart = false;
3401
3402 ifp->if_capenable ^= IFCAP_LRO;
3403
3404 /* figure out if updating HW LRO is needed */
3405 if (!(ifp->if_capenable & IFCAP_LRO)) {
3406 if (priv->params.hw_lro_en) {
3407 priv->params.hw_lro_en = false;
3408 need_restart = true;
3409 }
3410 } else {
3411 if (priv->params.hw_lro_en == false &&
3412 priv->params_ethtool.hw_lro != 0) {
3413 priv->params.hw_lro_en = true;
3414 need_restart = true;
3415 }
3416 }
3417 if (was_opened && need_restart) {
3418 mlx5e_close_locked(ifp);
3419 mlx5e_open_locked(ifp);
3420 }
3421 }
3422 if (mask & IFCAP_HWRXTSTMP) {
3423 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3424 if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3425 if (priv->clbr_done == 0)
3426 mlx5e_reset_calibration_callout(priv);
3427 } else {
3428 callout_drain(&priv->tstmp_clbr);
3429 priv->clbr_done = 0;
3430 }
3431 }
3432 out:
3433 PRIV_UNLOCK(priv);
3434 break;
3435
3436 case SIOCGI2C:
3437 ifr = (struct ifreq *)data;
3438
3439 /*
3440 * Copy from the user-space address ifr_data to the
3441 * kernel-space address i2c
3442 */
3443 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3444 if (error)
3445 break;
3446
3447 if (i2c.len > sizeof(i2c.data)) {
3448 error = EINVAL;
3449 break;
3450 }
3451
3452 PRIV_LOCK(priv);
3453 /* Get module_num which is required for the query_eeprom */
3454 error = mlx5_query_module_num(priv->mdev, &module_num);
3455 if (error) {
3456 mlx5_en_err(ifp,
3457 "Query module num failed, eeprom reading is not supported\n");
3458 error = EINVAL;
3459 goto err_i2c;
3460 }
3461 /* Check if module is present before doing an access */
3462 module_status = mlx5_query_module_status(priv->mdev, module_num);
3463 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3464 error = EINVAL;
3465 goto err_i2c;
3466 }
3467 /*
3468 * Currently 0XA0 and 0xA2 are the only addresses permitted.
3469 * The internal conversion is as follows:
3470 */
3471 if (i2c.dev_addr == 0xA0)
3472 read_addr = MLX5_I2C_ADDR_LOW;
3473 else if (i2c.dev_addr == 0xA2)
3474 read_addr = MLX5_I2C_ADDR_HIGH;
3475 else {
3476 mlx5_en_err(ifp,
3477 "Query eeprom failed, Invalid Address: %X\n",
3478 i2c.dev_addr);
3479 error = EINVAL;
3480 goto err_i2c;
3481 }
3482 error = mlx5_query_eeprom(priv->mdev,
3483 read_addr, MLX5_EEPROM_LOW_PAGE,
3484 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3485 (uint32_t *)i2c.data, &size_read);
3486 if (error) {
3487 mlx5_en_err(ifp,
3488 "Query eeprom failed, eeprom reading is not supported\n");
3489 error = EINVAL;
3490 goto err_i2c;
3491 }
3492
3493 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3494 error = mlx5_query_eeprom(priv->mdev,
3495 read_addr, MLX5_EEPROM_LOW_PAGE,
3496 (uint32_t)(i2c.offset + size_read),
3497 (uint32_t)(i2c.len - size_read), module_num,
3498 (uint32_t *)(i2c.data + size_read), &size_read);
3499 }
3500 if (error) {
3501 mlx5_en_err(ifp,
3502 "Query eeprom failed, eeprom reading is not supported\n");
3503 error = EINVAL;
3504 goto err_i2c;
3505 }
3506
3507 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3508 err_i2c:
3509 PRIV_UNLOCK(priv);
3510 break;
3511 case SIOCGIFDOWNREASON:
3512 ifdr = (struct ifdownreason *)data;
3513 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3514 PRIV_LOCK(priv);
3515 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL,
3516 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3517 PRIV_UNLOCK(priv);
3518 if (error == 0)
3519 ifdr->ifdr_reason = IFDR_REASON_MSG;
3520 break;
3521
3522 case SIOCGIFRSSKEY:
3523 ifrk = (struct ifrsskey *)data;
3524 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ;
3525 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE;
3526 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE);
3527 mlx5e_get_rss_key(ifrk->ifrk_key);
3528 break;
3529
3530 case SIOCGIFRSSHASH:
3531 ifrh = (struct ifrsshash *)data;
3532 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ;
3533 ifrh->ifrh_types =
3534 RSS_TYPE_IPV4 |
3535 RSS_TYPE_TCP_IPV4 |
3536 RSS_TYPE_UDP_IPV4 |
3537 RSS_TYPE_IPV6 |
3538 RSS_TYPE_TCP_IPV6 |
3539 RSS_TYPE_UDP_IPV6;
3540 break;
3541
3542 default:
3543 error = ether_ioctl(ifp, command, data);
3544 break;
3545 }
3546 return (error);
3547 }
3548
3549 static int
mlx5e_check_required_hca_cap(struct mlx5_core_dev * mdev)3550 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3551 {
3552 /*
3553 * TODO: uncoment once FW really sets all these bits if
3554 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3555 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3556 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3557 * -ENOTSUPP;
3558 */
3559
3560 /* TODO: add more must-to-have features */
3561
3562 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3563 return (-ENODEV);
3564
3565 return (0);
3566 }
3567
3568 static u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev * mdev)3569 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3570 {
3571 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN;
3572 const int max_size = MLX5E_MAX_TX_INLINE;
3573 const int bf_buf_size =
3574 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) -
3575 (sizeof(struct mlx5e_tx_wqe) - 2);
3576
3577 /* verify against driver limits */
3578 if (bf_buf_size > max_size)
3579 return (max_size);
3580 else if (bf_buf_size < min_size)
3581 return (min_size);
3582 else
3583 return (bf_buf_size);
3584 }
3585
3586 static int
mlx5e_build_ifp_priv(struct mlx5_core_dev * mdev,struct mlx5e_priv * priv,int num_comp_vectors)3587 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3588 struct mlx5e_priv *priv,
3589 int num_comp_vectors)
3590 {
3591 int err;
3592
3593 /*
3594 * TODO: Consider link speed for setting "log_sq_size",
3595 * "log_rq_size" and "cq_moderation_xxx":
3596 */
3597 priv->params.log_sq_size =
3598 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3599 priv->params.log_rq_size =
3600 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3601 priv->params.rx_cq_moderation_usec =
3602 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3603 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3604 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3605 priv->params.rx_cq_moderation_mode =
3606 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3607 priv->params.rx_cq_moderation_pkts =
3608 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3609 priv->params.tx_cq_moderation_usec =
3610 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3611 priv->params.tx_cq_moderation_pkts =
3612 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3613 priv->params.min_rx_wqes =
3614 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3615 priv->params.rx_hash_log_tbl_sz =
3616 (order_base_2(num_comp_vectors) >
3617 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3618 order_base_2(num_comp_vectors) :
3619 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3620 priv->params.num_tc = 1;
3621 priv->params.default_vlan_prio = 0;
3622 priv->counter_set_id = -1;
3623 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3624
3625 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3626 if (err)
3627 return (err);
3628
3629 /*
3630 * hw lro is currently defaulted to off. when it won't anymore we
3631 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3632 */
3633 priv->params.hw_lro_en = false;
3634 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3635
3636 /*
3637 * CQE zipping is currently defaulted to off. when it won't
3638 * anymore we will consider the HW capability:
3639 * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3640 */
3641 priv->params.cqe_zipping_en = false;
3642
3643 priv->mdev = mdev;
3644 priv->params.num_channels = num_comp_vectors;
3645 priv->params.channels_rsss = 1;
3646 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3647 priv->queue_mapping_channel_mask =
3648 roundup_pow_of_two(num_comp_vectors) - 1;
3649 priv->num_tc = priv->params.num_tc;
3650 priv->default_vlan_prio = priv->params.default_vlan_prio;
3651
3652 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3653 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3654 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3655
3656 return (0);
3657 }
3658
3659 static int
mlx5e_create_mkey(struct mlx5e_priv * priv,u32 pdn,struct mlx5_core_mr * mkey)3660 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3661 struct mlx5_core_mr *mkey)
3662 {
3663 struct ifnet *ifp = priv->ifp;
3664 struct mlx5_core_dev *mdev = priv->mdev;
3665 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3666 void *mkc;
3667 u32 *in;
3668 int err;
3669
3670 in = mlx5_vzalloc(inlen);
3671 if (in == NULL) {
3672 mlx5_en_err(ifp, "failed to allocate inbox\n");
3673 return (-ENOMEM);
3674 }
3675
3676 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3677 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3678 MLX5_SET(mkc, mkc, lw, 1);
3679 MLX5_SET(mkc, mkc, lr, 1);
3680
3681 MLX5_SET(mkc, mkc, pd, pdn);
3682 MLX5_SET(mkc, mkc, length64, 1);
3683 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3684
3685 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3686 if (err)
3687 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3688 err);
3689
3690 kvfree(in);
3691 return (err);
3692 }
3693
3694 static const char *mlx5e_vport_stats_desc[] = {
3695 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3696 };
3697
3698 static const char *mlx5e_pport_stats_desc[] = {
3699 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3700 };
3701
3702 static void
mlx5e_priv_static_init(struct mlx5e_priv * priv,const uint32_t channels)3703 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3704 {
3705 uint32_t x;
3706
3707 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3708 sx_init(&priv->state_lock, "mlx5state");
3709 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3710 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3711 for (x = 0; x != channels; x++)
3712 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3713 }
3714
3715 static void
mlx5e_priv_static_destroy(struct mlx5e_priv * priv,const uint32_t channels)3716 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3717 {
3718 uint32_t x;
3719
3720 for (x = 0; x != channels; x++)
3721 mlx5e_chan_static_destroy(&priv->channel[x]);
3722 callout_drain(&priv->watchdog);
3723 mtx_destroy(&priv->async_events_mtx);
3724 sx_destroy(&priv->state_lock);
3725 }
3726
3727 static int
sysctl_firmware(SYSCTL_HANDLER_ARGS)3728 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3729 {
3730 /*
3731 * %d.%d%.d the string format.
3732 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3733 * We need at most 5 chars to store that.
3734 * It also has: two "." and NULL at the end, which means we need 18
3735 * (5*3 + 3) chars at most.
3736 */
3737 char fw[18];
3738 struct mlx5e_priv *priv = arg1;
3739 int error;
3740
3741 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3742 fw_rev_sub(priv->mdev));
3743 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3744 return (error);
3745 }
3746
3747 static void
mlx5e_disable_tx_dma(struct mlx5e_channel * ch)3748 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3749 {
3750 int i;
3751
3752 for (i = 0; i < ch->priv->num_tc; i++)
3753 mlx5e_drain_sq(&ch->sq[i]);
3754 }
3755
3756 static void
mlx5e_reset_sq_doorbell_record(struct mlx5e_sq * sq)3757 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3758 {
3759
3760 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3761 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3762 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3763 sq->doorbell.d64 = 0;
3764 }
3765
3766 void
mlx5e_resume_sq(struct mlx5e_sq * sq)3767 mlx5e_resume_sq(struct mlx5e_sq *sq)
3768 {
3769 int err;
3770
3771 /* check if already enabled */
3772 if (READ_ONCE(sq->running) != 0)
3773 return;
3774
3775 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3776 MLX5_SQC_STATE_RST);
3777 if (err != 0) {
3778 mlx5_en_err(sq->ifp,
3779 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3780 }
3781
3782 sq->cc = 0;
3783 sq->pc = 0;
3784
3785 /* reset doorbell prior to moving from RST to RDY */
3786 mlx5e_reset_sq_doorbell_record(sq);
3787
3788 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3789 MLX5_SQC_STATE_RDY);
3790 if (err != 0) {
3791 mlx5_en_err(sq->ifp,
3792 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3793 }
3794
3795 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3796 WRITE_ONCE(sq->running, 1);
3797 }
3798
3799 static void
mlx5e_enable_tx_dma(struct mlx5e_channel * ch)3800 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3801 {
3802 int i;
3803
3804 for (i = 0; i < ch->priv->num_tc; i++)
3805 mlx5e_resume_sq(&ch->sq[i]);
3806 }
3807
3808 static void
mlx5e_disable_rx_dma(struct mlx5e_channel * ch)3809 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3810 {
3811 struct mlx5e_rq *rq = &ch->rq;
3812 struct epoch_tracker et;
3813 int err;
3814
3815 mtx_lock(&rq->mtx);
3816 rq->enabled = 0;
3817 callout_stop(&rq->watchdog);
3818 mtx_unlock(&rq->mtx);
3819
3820 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3821 if (err != 0) {
3822 mlx5_en_err(rq->ifp,
3823 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3824 }
3825
3826 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3827 msleep(1);
3828 NET_EPOCH_ENTER_ET(et);
3829 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
3830 NET_EPOCH_EXIT_ET(et);
3831 }
3832
3833 /*
3834 * Transitioning into RST state will allow the FW to track less ERR state queues,
3835 * thus reducing the recv queue flushing time
3836 */
3837 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3838 if (err != 0) {
3839 mlx5_en_err(rq->ifp,
3840 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3841 }
3842 }
3843
3844 static void
mlx5e_enable_rx_dma(struct mlx5e_channel * ch)3845 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3846 {
3847 struct mlx5e_rq *rq = &ch->rq;
3848 struct epoch_tracker et;
3849 int err;
3850
3851 rq->wq.wqe_ctr = 0;
3852 mlx5_wq_ll_update_db_record(&rq->wq);
3853 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3854 if (err != 0) {
3855 mlx5_en_err(rq->ifp,
3856 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3857 }
3858
3859 rq->enabled = 1;
3860
3861 NET_EPOCH_ENTER_ET(et);
3862 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
3863 NET_EPOCH_EXIT_ET(et);
3864 }
3865
3866 void
mlx5e_modify_tx_dma(struct mlx5e_priv * priv,uint8_t value)3867 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3868 {
3869 int i;
3870
3871 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3872 return;
3873
3874 for (i = 0; i < priv->params.num_channels; i++) {
3875 if (value)
3876 mlx5e_disable_tx_dma(&priv->channel[i]);
3877 else
3878 mlx5e_enable_tx_dma(&priv->channel[i]);
3879 }
3880 }
3881
3882 void
mlx5e_modify_rx_dma(struct mlx5e_priv * priv,uint8_t value)3883 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3884 {
3885 int i;
3886
3887 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3888 return;
3889
3890 for (i = 0; i < priv->params.num_channels; i++) {
3891 if (value)
3892 mlx5e_disable_rx_dma(&priv->channel[i]);
3893 else
3894 mlx5e_enable_rx_dma(&priv->channel[i]);
3895 }
3896 }
3897
3898 static void
mlx5e_add_hw_stats(struct mlx5e_priv * priv)3899 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3900 {
3901 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3902 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3903 sysctl_firmware, "A", "HCA firmware version");
3904
3905 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3906 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3907 "Board ID");
3908 }
3909
3910 static int
mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)3911 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3912 {
3913 struct mlx5e_priv *priv = arg1;
3914 uint8_t temp[MLX5E_MAX_PRIORITY];
3915 uint32_t tx_pfc;
3916 int err;
3917 int i;
3918
3919 PRIV_LOCK(priv);
3920
3921 tx_pfc = priv->params.tx_priority_flow_control;
3922
3923 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3924 temp[i] = (tx_pfc >> i) & 1;
3925
3926 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3927 if (err || !req->newptr)
3928 goto done;
3929 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3930 if (err)
3931 goto done;
3932
3933 priv->params.tx_priority_flow_control = 0;
3934
3935 /* range check input value */
3936 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3937 if (temp[i] > 1) {
3938 err = ERANGE;
3939 goto done;
3940 }
3941 priv->params.tx_priority_flow_control |= (temp[i] << i);
3942 }
3943
3944 /* check if update is required */
3945 if (tx_pfc != priv->params.tx_priority_flow_control)
3946 err = -mlx5e_set_port_pfc(priv);
3947 done:
3948 if (err != 0)
3949 priv->params.tx_priority_flow_control= tx_pfc;
3950 PRIV_UNLOCK(priv);
3951
3952 return (err);
3953 }
3954
3955 static int
mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)3956 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3957 {
3958 struct mlx5e_priv *priv = arg1;
3959 uint8_t temp[MLX5E_MAX_PRIORITY];
3960 uint32_t rx_pfc;
3961 int err;
3962 int i;
3963
3964 PRIV_LOCK(priv);
3965
3966 rx_pfc = priv->params.rx_priority_flow_control;
3967
3968 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3969 temp[i] = (rx_pfc >> i) & 1;
3970
3971 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3972 if (err || !req->newptr)
3973 goto done;
3974 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3975 if (err)
3976 goto done;
3977
3978 priv->params.rx_priority_flow_control = 0;
3979
3980 /* range check input value */
3981 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3982 if (temp[i] > 1) {
3983 err = ERANGE;
3984 goto done;
3985 }
3986 priv->params.rx_priority_flow_control |= (temp[i] << i);
3987 }
3988
3989 /* check if update is required */
3990 if (rx_pfc != priv->params.rx_priority_flow_control) {
3991 err = -mlx5e_set_port_pfc(priv);
3992 if (err == 0 && priv->sw_is_port_buf_owner)
3993 err = mlx5e_update_buf_lossy(priv);
3994 }
3995 done:
3996 if (err != 0)
3997 priv->params.rx_priority_flow_control= rx_pfc;
3998 PRIV_UNLOCK(priv);
3999
4000 return (err);
4001 }
4002
4003 static void
mlx5e_setup_pauseframes(struct mlx5e_priv * priv)4004 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
4005 {
4006 #if (__FreeBSD_version < 1100000)
4007 char path[96];
4008 #endif
4009 int error;
4010
4011 /* enable pauseframes by default */
4012 priv->params.tx_pauseframe_control = 1;
4013 priv->params.rx_pauseframe_control = 1;
4014
4015 /* disable ports flow control, PFC, by default */
4016 priv->params.tx_priority_flow_control = 0;
4017 priv->params.rx_priority_flow_control = 0;
4018
4019 #if (__FreeBSD_version < 1100000)
4020 /* compute path for sysctl */
4021 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
4022 device_get_unit(priv->mdev->pdev->dev.bsddev));
4023
4024 /* try to fetch tunable, if any */
4025 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
4026
4027 /* compute path for sysctl */
4028 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
4029 device_get_unit(priv->mdev->pdev->dev.bsddev));
4030
4031 /* try to fetch tunable, if any */
4032 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
4033 #endif
4034
4035 /* register pauseframe SYSCTLs */
4036 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4037 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
4038 &priv->params.tx_pauseframe_control, 0,
4039 "Set to enable TX pause frames. Clear to disable.");
4040
4041 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4042 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
4043 &priv->params.rx_pauseframe_control, 0,
4044 "Set to enable RX pause frames. Clear to disable.");
4045
4046 /* register priority flow control, PFC, SYSCTLs */
4047 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4048 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4049 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4050 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
4051
4052 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4053 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4054 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4055 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4056
4057 PRIV_LOCK(priv);
4058
4059 /* range check */
4060 priv->params.tx_pauseframe_control =
4061 priv->params.tx_pauseframe_control ? 1 : 0;
4062 priv->params.rx_pauseframe_control =
4063 priv->params.rx_pauseframe_control ? 1 : 0;
4064
4065 /* update firmware */
4066 error = mlx5e_set_port_pause_and_pfc(priv);
4067 if (error == -EINVAL) {
4068 mlx5_en_err(priv->ifp,
4069 "Global pauseframes must be disabled before enabling PFC.\n");
4070 priv->params.rx_priority_flow_control = 0;
4071 priv->params.tx_priority_flow_control = 0;
4072
4073 /* update firmware */
4074 (void) mlx5e_set_port_pause_and_pfc(priv);
4075 }
4076 PRIV_UNLOCK(priv);
4077 }
4078
4079 static int
mlx5e_ul_snd_tag_alloc(struct ifnet * ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** ppmt)4080 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
4081 union if_snd_tag_alloc_params *params,
4082 struct m_snd_tag **ppmt)
4083 {
4084 struct mlx5e_priv *priv;
4085 struct mlx5e_channel *pch;
4086
4087 priv = ifp->if_softc;
4088
4089 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4090 return (EOPNOTSUPP);
4091 } else {
4092 /* keep this code synced with mlx5e_select_queue() */
4093 u32 ch = priv->params.num_channels;
4094 #ifdef RSS
4095 u32 temp;
4096
4097 if (rss_hash2bucket(params->hdr.flowid,
4098 params->hdr.flowtype, &temp) == 0)
4099 ch = temp % ch;
4100 else
4101 #endif
4102 ch = (params->hdr.flowid % 128) % ch;
4103
4104 /*
4105 * NOTE: The channels array is only freed at detach
4106 * and it safe to return a pointer to the send tag
4107 * inside the channels structure as long as we
4108 * reference the priv.
4109 */
4110 pch = priv->channel + ch;
4111
4112 /* check if send queue is not running */
4113 if (unlikely(pch->sq[0].running == 0))
4114 return (ENXIO);
4115 mlx5e_ref_channel(priv);
4116 *ppmt = &pch->tag.m_snd_tag;
4117 return (0);
4118 }
4119 }
4120
4121 static int
mlx5e_ul_snd_tag_query(struct m_snd_tag * pmt,union if_snd_tag_query_params * params)4122 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4123 {
4124 struct mlx5e_channel *pch =
4125 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4126
4127 params->unlimited.max_rate = -1ULL;
4128 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4129 return (0);
4130 }
4131
4132 static void
mlx5e_ul_snd_tag_free(struct m_snd_tag * pmt)4133 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4134 {
4135 struct mlx5e_channel *pch =
4136 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4137
4138 mlx5e_unref_channel(pch->priv);
4139 }
4140
4141 static int
mlx5e_snd_tag_alloc(struct ifnet * ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** ppmt)4142 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4143 union if_snd_tag_alloc_params *params,
4144 struct m_snd_tag **ppmt)
4145 {
4146
4147 switch (params->hdr.type) {
4148 #ifdef RATELIMIT
4149 case IF_SND_TAG_TYPE_RATE_LIMIT:
4150 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4151 #endif
4152 case IF_SND_TAG_TYPE_UNLIMITED:
4153 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4154 default:
4155 return (EOPNOTSUPP);
4156 }
4157 }
4158
4159 static int
mlx5e_snd_tag_modify(struct m_snd_tag * pmt,union if_snd_tag_modify_params * params)4160 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4161 {
4162 struct mlx5e_snd_tag *tag =
4163 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4164
4165 switch (tag->type) {
4166 #ifdef RATELIMIT
4167 case IF_SND_TAG_TYPE_RATE_LIMIT:
4168 return (mlx5e_rl_snd_tag_modify(pmt, params));
4169 #endif
4170 case IF_SND_TAG_TYPE_UNLIMITED:
4171 default:
4172 return (EOPNOTSUPP);
4173 }
4174 }
4175
4176 static int
mlx5e_snd_tag_query(struct m_snd_tag * pmt,union if_snd_tag_query_params * params)4177 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4178 {
4179 struct mlx5e_snd_tag *tag =
4180 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4181
4182 switch (tag->type) {
4183 #ifdef RATELIMIT
4184 case IF_SND_TAG_TYPE_RATE_LIMIT:
4185 return (mlx5e_rl_snd_tag_query(pmt, params));
4186 #endif
4187 case IF_SND_TAG_TYPE_UNLIMITED:
4188 return (mlx5e_ul_snd_tag_query(pmt, params));
4189 default:
4190 return (EOPNOTSUPP);
4191 }
4192 }
4193
4194 static void
mlx5e_snd_tag_free(struct m_snd_tag * pmt)4195 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4196 {
4197 struct mlx5e_snd_tag *tag =
4198 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4199
4200 switch (tag->type) {
4201 #ifdef RATELIMIT
4202 case IF_SND_TAG_TYPE_RATE_LIMIT:
4203 mlx5e_rl_snd_tag_free(pmt);
4204 break;
4205 #endif
4206 case IF_SND_TAG_TYPE_UNLIMITED:
4207 mlx5e_ul_snd_tag_free(pmt);
4208 break;
4209 default:
4210 break;
4211 }
4212 }
4213
4214 static void
mlx5e_ifm_add(struct mlx5e_priv * priv,int type)4215 mlx5e_ifm_add(struct mlx5e_priv *priv, int type)
4216 {
4217 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL);
4218 ifmedia_add(&priv->media, type | IFM_ETHER |
4219 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4220 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL);
4221 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL);
4222 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL);
4223 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4224 IFM_ETH_RXPAUSE, 0, NULL);
4225 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4226 IFM_ETH_TXPAUSE, 0, NULL);
4227 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4228 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4229 }
4230
4231 static void *
mlx5e_create_ifp(struct mlx5_core_dev * mdev)4232 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4233 {
4234 struct ifnet *ifp;
4235 struct mlx5e_priv *priv;
4236 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4237 u8 connector_type;
4238 struct sysctl_oid_list *child;
4239 int ncv = mdev->priv.eq_table.num_comp_vectors;
4240 char unit[16];
4241 int err;
4242 int i,j;
4243 u32 eth_proto_cap;
4244 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4245 bool ext = 0;
4246 u32 speeds_num;
4247 struct media media_entry = {};
4248
4249 if (mlx5e_check_required_hca_cap(mdev)) {
4250 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4251 return (NULL);
4252 }
4253 /*
4254 * Try to allocate the priv and make room for worst-case
4255 * number of channel structures:
4256 */
4257 priv = malloc(sizeof(*priv) +
4258 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4259 M_MLX5EN, M_WAITOK | M_ZERO);
4260
4261 ifp = priv->ifp = if_alloc(IFT_ETHER);
4262 if (ifp == NULL) {
4263 mlx5_core_err(mdev, "if_alloc() failed\n");
4264 goto err_free_priv;
4265 }
4266 /* setup all static fields */
4267 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
4268
4269 ifp->if_softc = priv;
4270 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4271 ifp->if_mtu = ETHERMTU;
4272 ifp->if_init = mlx5e_open;
4273 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4274 ifp->if_ioctl = mlx5e_ioctl;
4275 ifp->if_transmit = mlx5e_xmit;
4276 ifp->if_qflush = if_qflush;
4277 #if (__FreeBSD_version >= 1100000)
4278 ifp->if_get_counter = mlx5e_get_counter;
4279 #endif
4280 ifp->if_snd.ifq_maxlen = ifqmaxlen;
4281 /*
4282 * Set driver features
4283 */
4284 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4285 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4286 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4287 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4288 ifp->if_capabilities |= IFCAP_LRO;
4289 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4290 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4291 ifp->if_capabilities |= IFCAP_TXRTLMT;
4292 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4293 ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4294 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4295 ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4296
4297 /* set TSO limits so that we don't have to drop TX packets */
4298 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4299 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4300 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4301
4302 ifp->if_capenable = ifp->if_capabilities;
4303 ifp->if_hwassist = 0;
4304 if (ifp->if_capenable & IFCAP_TSO)
4305 ifp->if_hwassist |= CSUM_TSO;
4306 if (ifp->if_capenable & IFCAP_TXCSUM)
4307 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4308 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4309 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4310
4311 /* ifnet sysctl tree */
4312 sysctl_ctx_init(&priv->sysctl_ctx);
4313 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4314 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
4315 if (priv->sysctl_ifnet == NULL) {
4316 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4317 goto err_free_sysctl;
4318 }
4319 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4320 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4321 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
4322 if (priv->sysctl_ifnet == NULL) {
4323 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4324 goto err_free_sysctl;
4325 }
4326
4327 /* HW sysctl tree */
4328 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4329 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4330 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
4331 if (priv->sysctl_hw == NULL) {
4332 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4333 goto err_free_sysctl;
4334 }
4335
4336 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4337 if (err) {
4338 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4339 goto err_free_sysctl;
4340 }
4341
4342 /* reuse mlx5core's watchdog workqueue */
4343 priv->wq = mdev->priv.health.wq_watchdog;
4344
4345 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4346 if (err) {
4347 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4348 goto err_free_wq;
4349 }
4350 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4351 if (err) {
4352 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4353 goto err_unmap_free_uar;
4354 }
4355 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4356 if (err) {
4357 mlx5_en_err(ifp,
4358 "mlx5_alloc_transport_domain failed, %d\n", err);
4359 goto err_dealloc_pd;
4360 }
4361 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4362 if (err) {
4363 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4364 goto err_dealloc_transport_domain;
4365 }
4366 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4367
4368 /* check if we should generate a random MAC address */
4369 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4370 is_zero_ether_addr(dev_addr)) {
4371 random_ether_addr(dev_addr);
4372 mlx5_en_err(ifp, "Assigned random MAC address\n");
4373 }
4374 #ifdef RATELIMIT
4375 err = mlx5e_rl_init(priv);
4376 if (err) {
4377 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4378 goto err_create_mkey;
4379 }
4380 #endif
4381
4382 /* set default MTU */
4383 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4384
4385 /* Set default media status */
4386 priv->media_status_last = IFM_AVALID;
4387 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX;
4388
4389 /* setup default pauseframes configuration */
4390 mlx5e_setup_pauseframes(priv);
4391
4392 /* Setup supported medias */
4393 //TODO: If we failed to query ptys is it ok to proceed??
4394 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4395 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4396 ptys_extended_ethernet);
4397 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4398 eth_proto_capability);
4399 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4400 connector_type = MLX5_GET(ptys_reg, out,
4401 connector_type);
4402 } else {
4403 eth_proto_cap = 0;
4404 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4405 }
4406
4407 ifmedia_init(&priv->media, IFM_IMASK,
4408 mlx5e_media_change, mlx5e_media_status);
4409
4410 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4411 for (i = 0; i != speeds_num; i++) {
4412 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4413 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4414 mlx5e_mode_table[i][j];
4415 if (media_entry.baudrate == 0)
4416 continue;
4417 if (MLX5E_PROT_MASK(i) & eth_proto_cap)
4418 mlx5e_ifm_add(priv, media_entry.subtype);
4419 }
4420 }
4421
4422 mlx5e_ifm_add(priv, IFM_AUTO);
4423
4424 /* Set autoselect by default */
4425 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4426 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4427 ether_ifattach(ifp, dev_addr);
4428
4429 /* Register for VLAN events */
4430 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4431 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4432 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4433 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4434
4435 /* Link is down by default */
4436 if_link_state_change(ifp, LINK_STATE_DOWN);
4437
4438 mlx5e_enable_async_events(priv);
4439
4440 mlx5e_add_hw_stats(priv);
4441
4442 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4443 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4444 priv->stats.vport.arg);
4445
4446 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4447 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4448 priv->stats.pport.arg);
4449
4450 mlx5e_create_ethtool(priv);
4451
4452 mtx_lock(&priv->async_events_mtx);
4453 mlx5e_update_stats(priv);
4454 mtx_unlock(&priv->async_events_mtx);
4455
4456 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4457 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4458 &priv->clbr_done, 0,
4459 "RX timestamps calibration state");
4460 callout_init(&priv->tstmp_clbr, 1);
4461 mlx5e_reset_calibration_callout(priv);
4462
4463 return (priv);
4464
4465 #ifdef RATELIMIT
4466 err_create_mkey:
4467 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4468 #endif
4469 err_dealloc_transport_domain:
4470 mlx5_dealloc_transport_domain(mdev, priv->tdn);
4471
4472 err_dealloc_pd:
4473 mlx5_core_dealloc_pd(mdev, priv->pdn);
4474
4475 err_unmap_free_uar:
4476 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4477
4478 err_free_wq:
4479 flush_workqueue(priv->wq);
4480
4481 err_free_sysctl:
4482 sysctl_ctx_free(&priv->sysctl_ctx);
4483 if (priv->sysctl_debug)
4484 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4485 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4486 if_free(ifp);
4487
4488 err_free_priv:
4489 free(priv, M_MLX5EN);
4490 return (NULL);
4491 }
4492
4493 static void
mlx5e_destroy_ifp(struct mlx5_core_dev * mdev,void * vpriv)4494 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4495 {
4496 struct mlx5e_priv *priv = vpriv;
4497 struct ifnet *ifp = priv->ifp;
4498
4499 /* don't allow more IOCTLs */
4500 priv->gone = 1;
4501
4502 /* XXX wait a bit to allow IOCTL handlers to complete */
4503 pause("W", hz);
4504
4505 #ifdef RATELIMIT
4506 /*
4507 * The kernel can have reference(s) via the m_snd_tag's into
4508 * the ratelimit channels, and these must go away before
4509 * detaching:
4510 */
4511 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4512 mlx5_en_err(priv->ifp,
4513 "Waiting for all ratelimit connections to terminate\n");
4514 pause("W", hz);
4515 }
4516 #endif
4517 /* stop watchdog timer */
4518 callout_drain(&priv->watchdog);
4519
4520 callout_drain(&priv->tstmp_clbr);
4521
4522 if (priv->vlan_attach != NULL)
4523 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4524 if (priv->vlan_detach != NULL)
4525 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4526
4527 /* make sure device gets closed */
4528 PRIV_LOCK(priv);
4529 mlx5e_close_locked(ifp);
4530 PRIV_UNLOCK(priv);
4531
4532 /* wait for all unlimited send tags to go away */
4533 while (priv->channel_refs != 0) {
4534 mlx5_en_err(priv->ifp,
4535 "Waiting for all unlimited connections to terminate\n");
4536 pause("W", hz);
4537 }
4538
4539 /* unregister device */
4540 ifmedia_removeall(&priv->media);
4541 ether_ifdetach(ifp);
4542
4543 #ifdef RATELIMIT
4544 mlx5e_rl_cleanup(priv);
4545 #endif
4546 /* destroy all remaining sysctl nodes */
4547 sysctl_ctx_free(&priv->stats.vport.ctx);
4548 sysctl_ctx_free(&priv->stats.pport.ctx);
4549 if (priv->sysctl_debug)
4550 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4551 sysctl_ctx_free(&priv->sysctl_ctx);
4552
4553 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4554 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4555 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4556 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4557 mlx5e_disable_async_events(priv);
4558 flush_workqueue(priv->wq);
4559 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4560 if_free(ifp);
4561 free(priv, M_MLX5EN);
4562 }
4563
4564 static void *
mlx5e_get_ifp(void * vpriv)4565 mlx5e_get_ifp(void *vpriv)
4566 {
4567 struct mlx5e_priv *priv = vpriv;
4568
4569 return (priv->ifp);
4570 }
4571
4572 static struct mlx5_interface mlx5e_interface = {
4573 .add = mlx5e_create_ifp,
4574 .remove = mlx5e_destroy_ifp,
4575 .event = mlx5e_async_event,
4576 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4577 .get_dev = mlx5e_get_ifp,
4578 };
4579
4580 void
mlx5e_init(void)4581 mlx5e_init(void)
4582 {
4583 mlx5_register_interface(&mlx5e_interface);
4584 }
4585
4586 void
mlx5e_cleanup(void)4587 mlx5e_cleanup(void)
4588 {
4589 mlx5_unregister_interface(&mlx5e_interface);
4590 }
4591
4592 static void
mlx5e_show_version(void __unused * arg)4593 mlx5e_show_version(void __unused *arg)
4594 {
4595
4596 printf("%s", mlx5e_version);
4597 }
4598 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4599
4600 module_init_order(mlx5e_init, SI_ORDER_SIXTH);
4601 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH);
4602
4603 #if (__FreeBSD_version >= 1100000)
4604 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4605 #endif
4606 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4607 MODULE_VERSION(mlx5en, 1);
4608