1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
31 */
32 #include <sys/cdefs.h>
33 #ifdef HAVE_KERNEL_OPTION_HEADERS
34 #include "opt_device_polling.h"
35 #endif
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/endian.h>
41 #include <sys/mbuf.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
47
48 #include <net/bpf.h>
49 #include <net/ethernet.h>
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
57
58 #include <netinet/in_systm.h>
59 #include <netinet/in.h>
60 #include <netinet/ip.h>
61
62 #include <machine/bus.h>
63
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
66
67 #include <dev/tsec/if_tsec.h>
68 #include <dev/tsec/if_tsecreg.h>
69
70 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
71 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
72 const char *dname);
73 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
74 static void tsec_encap(struct ifnet *ifp, struct tsec_softc *sc,
75 struct mbuf *m0, uint16_t fcb_flags, int *start_tx);
76 static void tsec_free_dma(struct tsec_softc *sc);
77 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
78 static int tsec_ifmedia_upd(struct ifnet *ifp);
79 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
80 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
81 struct mbuf **mbufp, uint32_t *paddr);
82 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
83 int nseg, int error);
84 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
85 static void tsec_init(void *xsc);
86 static void tsec_init_locked(struct tsec_softc *sc);
87 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
88 static void tsec_reset_mac(struct tsec_softc *sc);
89 static void tsec_setfilter(struct tsec_softc *sc);
90 static void tsec_set_mac_address(struct tsec_softc *sc);
91 static void tsec_start(struct ifnet *ifp);
92 static void tsec_start_locked(struct ifnet *ifp);
93 static void tsec_stop(struct tsec_softc *sc);
94 static void tsec_tick(void *arg);
95 static void tsec_watchdog(struct tsec_softc *sc);
96 static void tsec_add_sysctls(struct tsec_softc *sc);
97 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
98 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
99 static void tsec_set_rxic(struct tsec_softc *sc);
100 static void tsec_set_txic(struct tsec_softc *sc);
101 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
102 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
103 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
104 static void tsec_offload_setup(struct tsec_softc *sc);
105 static void tsec_offload_process_frame(struct tsec_softc *sc,
106 struct mbuf *m);
107 static void tsec_setup_multicast(struct tsec_softc *sc);
108 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
109
110 devclass_t tsec_devclass;
111 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
112 MODULE_DEPEND(tsec, ether, 1, 1, 1);
113 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
114
115 struct mtx tsec_phy_mtx;
116
117 int
tsec_attach(struct tsec_softc * sc)118 tsec_attach(struct tsec_softc *sc)
119 {
120 uint8_t hwaddr[ETHER_ADDR_LEN];
121 struct ifnet *ifp;
122 int error = 0;
123 int i;
124
125 /* Initialize global (because potentially shared) MII lock */
126 if (!mtx_initialized(&tsec_phy_mtx))
127 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
128
129 /* Reset all TSEC counters */
130 TSEC_TX_RX_COUNTERS_INIT(sc);
131
132 /* Stop DMA engine if enabled by firmware */
133 tsec_dma_ctl(sc, 0);
134
135 /* Reset MAC */
136 tsec_reset_mac(sc);
137
138 /* Disable interrupts for now */
139 tsec_intrs_ctl(sc, 0);
140
141 /* Configure defaults for interrupts coalescing */
142 sc->rx_ic_time = 768;
143 sc->rx_ic_count = 16;
144 sc->tx_ic_time = 768;
145 sc->tx_ic_count = 16;
146 tsec_set_rxic(sc);
147 tsec_set_txic(sc);
148 tsec_add_sysctls(sc);
149
150 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
151 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
152 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
153 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
154
155 if (error) {
156 tsec_detach(sc);
157 return (ENXIO);
158 }
159
160 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
161 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
162 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
163 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
164 if (error) {
165 tsec_detach(sc);
166 return (ENXIO);
167 }
168
169 /* Allocate a busdma tag for TX mbufs. */
170 error = bus_dma_tag_create(NULL, /* parent */
171 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
172 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
173 BUS_SPACE_MAXADDR, /* highaddr */
174 NULL, NULL, /* filtfunc, filtfuncarg */
175 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
176 TSEC_TX_MAX_DMA_SEGS, /* nsegments */
177 MCLBYTES, 0, /* maxsegsz, flags */
178 NULL, NULL, /* lockfunc, lockfuncarg */
179 &sc->tsec_tx_mtag); /* dmat */
180 if (error) {
181 device_printf(sc->dev, "failed to allocate busdma tag "
182 "(tx mbufs)\n");
183 tsec_detach(sc);
184 return (ENXIO);
185 }
186
187 /* Allocate a busdma tag for RX mbufs. */
188 error = bus_dma_tag_create(NULL, /* parent */
189 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
190 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
191 BUS_SPACE_MAXADDR, /* highaddr */
192 NULL, NULL, /* filtfunc, filtfuncarg */
193 MCLBYTES, /* maxsize */
194 1, /* nsegments */
195 MCLBYTES, 0, /* maxsegsz, flags */
196 NULL, NULL, /* lockfunc, lockfuncarg */
197 &sc->tsec_rx_mtag); /* dmat */
198 if (error) {
199 device_printf(sc->dev, "failed to allocate busdma tag "
200 "(rx mbufs)\n");
201 tsec_detach(sc);
202 return (ENXIO);
203 }
204
205 /* Create TX busdma maps */
206 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
207 error = bus_dmamap_create(sc->tsec_tx_mtag, 0,
208 &sc->tx_bufmap[i].map);
209 if (error) {
210 device_printf(sc->dev, "failed to init TX ring\n");
211 tsec_detach(sc);
212 return (ENXIO);
213 }
214 sc->tx_bufmap[i].map_initialized = 1;
215 }
216
217 /* Create RX busdma maps and zero mbuf handlers */
218 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
219 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
220 &sc->rx_data[i].map);
221 if (error) {
222 device_printf(sc->dev, "failed to init RX ring\n");
223 tsec_detach(sc);
224 return (ENXIO);
225 }
226 sc->rx_data[i].mbuf = NULL;
227 }
228
229 /* Create mbufs for RX buffers */
230 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
231 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
232 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
233 if (error) {
234 device_printf(sc->dev, "can't load rx DMA map %d, "
235 "error = %d\n", i, error);
236 tsec_detach(sc);
237 return (error);
238 }
239 }
240
241 /* Create network interface for upper layers */
242 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
243 ifp->if_softc = sc;
244 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
245 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
246 ifp->if_init = tsec_init;
247 ifp->if_start = tsec_start;
248 ifp->if_ioctl = tsec_ioctl;
249
250 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
251 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
252 IFQ_SET_READY(&ifp->if_snd);
253
254 ifp->if_capabilities = IFCAP_VLAN_MTU;
255 if (sc->is_etsec)
256 ifp->if_capabilities |= IFCAP_HWCSUM;
257
258 ifp->if_capenable = ifp->if_capabilities;
259
260 #ifdef DEVICE_POLLING
261 /* Advertise that polling is supported */
262 ifp->if_capabilities |= IFCAP_POLLING;
263 #endif
264
265 /* Attach PHY(s) */
266 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
267 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
268 0);
269 if (error) {
270 device_printf(sc->dev, "attaching PHYs failed\n");
271 if_free(ifp);
272 sc->tsec_ifp = NULL;
273 tsec_detach(sc);
274 return (error);
275 }
276 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
277
278 /* Set MAC address */
279 tsec_get_hwaddr(sc, hwaddr);
280 ether_ifattach(ifp, hwaddr);
281
282 return (0);
283 }
284
285 int
tsec_detach(struct tsec_softc * sc)286 tsec_detach(struct tsec_softc *sc)
287 {
288
289 if (sc->tsec_ifp != NULL) {
290 #ifdef DEVICE_POLLING
291 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
292 ether_poll_deregister(sc->tsec_ifp);
293 #endif
294
295 /* Stop TSEC controller and free TX queue */
296 if (sc->sc_rres)
297 tsec_shutdown(sc->dev);
298
299 /* Detach network interface */
300 ether_ifdetach(sc->tsec_ifp);
301 if_free(sc->tsec_ifp);
302 sc->tsec_ifp = NULL;
303 }
304
305 /* Free DMA resources */
306 tsec_free_dma(sc);
307
308 return (0);
309 }
310
311 int
tsec_shutdown(device_t dev)312 tsec_shutdown(device_t dev)
313 {
314 struct tsec_softc *sc;
315
316 sc = device_get_softc(dev);
317
318 TSEC_GLOBAL_LOCK(sc);
319 tsec_stop(sc);
320 TSEC_GLOBAL_UNLOCK(sc);
321 return (0);
322 }
323
324 int
tsec_suspend(device_t dev)325 tsec_suspend(device_t dev)
326 {
327
328 /* TODO not implemented! */
329 return (0);
330 }
331
332 int
tsec_resume(device_t dev)333 tsec_resume(device_t dev)
334 {
335
336 /* TODO not implemented! */
337 return (0);
338 }
339
340 static void
tsec_init(void * xsc)341 tsec_init(void *xsc)
342 {
343 struct tsec_softc *sc = xsc;
344
345 TSEC_GLOBAL_LOCK(sc);
346 tsec_init_locked(sc);
347 TSEC_GLOBAL_UNLOCK(sc);
348 }
349
350 static int
tsec_mii_wait(struct tsec_softc * sc,uint32_t flags)351 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags)
352 {
353 int timeout;
354
355 /*
356 * The status indicators are not set immediately after a command.
357 * Discard the first value.
358 */
359 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND);
360
361 timeout = TSEC_READ_RETRY;
362 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout)
363 DELAY(TSEC_READ_DELAY);
364
365 return (timeout == 0);
366 }
367
368 static void
tsec_init_locked(struct tsec_softc * sc)369 tsec_init_locked(struct tsec_softc *sc)
370 {
371 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
372 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
373 struct ifnet *ifp = sc->tsec_ifp;
374 uint32_t val, i;
375 int timeout;
376
377 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
378 return;
379
380 TSEC_GLOBAL_LOCK_ASSERT(sc);
381 tsec_stop(sc);
382
383 /*
384 * These steps are according to the MPC8555E PowerQUICCIII RM:
385 * 14.7 Initialization/Application Information
386 */
387
388 /* Step 1: soft reset MAC */
389 tsec_reset_mac(sc);
390
391 /* Step 2: Initialize MACCFG2 */
392 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
393 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
394 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
395 TSEC_MACCFG2_GMII | /* I/F Mode bit */
396 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
397 );
398
399 /* Step 3: Initialize ECNTRL
400 * While the documentation states that R100M is ignored if RPM is
401 * not set, it does seem to be needed to get the orange boxes to
402 * work (which have a Marvell 88E1111 PHY). Go figure.
403 */
404
405 /*
406 * XXX kludge - use circumstancial evidence to program ECNTRL
407 * correctly. Ideally we need some board information to guide
408 * us here.
409 */
410 i = TSEC_READ(sc, TSEC_REG_ID2);
411 val = (i & 0xffff)
412 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
413 : TSEC_ECNTRL_R100M; /* Orange + CDS */
414 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
415
416 /* Step 4: Initialize MAC station address */
417 tsec_set_mac_address(sc);
418
419 /*
420 * Step 5: Assign a Physical address to the TBI so as to not conflict
421 * with the external PHY physical address
422 */
423 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
424
425 TSEC_PHY_LOCK(sc);
426
427 /* Step 6: Reset the management interface */
428 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
429
430 /* Step 7: Setup the MII Mgmt clock speed */
431 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
432
433 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
434 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
435
436 TSEC_PHY_UNLOCK(sc);
437 if (timeout) {
438 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
439 return;
440 }
441
442 /* Step 9: Setup the MII Mgmt */
443 mii_mediachg(sc->tsec_mii);
444
445 /* Step 10: Clear IEVENT register */
446 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
447
448 /* Step 11: Enable interrupts */
449 #ifdef DEVICE_POLLING
450 /*
451 * ...only if polling is not turned on. Disable interrupts explicitly
452 * if polling is enabled.
453 */
454 if (ifp->if_capenable & IFCAP_POLLING )
455 tsec_intrs_ctl(sc, 0);
456 else
457 #endif /* DEVICE_POLLING */
458 tsec_intrs_ctl(sc, 1);
459
460 /* Step 12: Initialize IADDRn */
461 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
462 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
463 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
464 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
465 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
466 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
467 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
468 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
469
470 /* Step 13: Initialize GADDRn */
471 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
472 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
473 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
474 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
475 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
476 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
477 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
478 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
479
480 /* Step 14: Initialize RCTRL */
481 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
482
483 /* Step 15: Initialize DMACTRL */
484 tsec_dma_ctl(sc, 1);
485
486 /* Step 16: Initialize FIFO_PAUSE_CTRL */
487 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
488
489 /*
490 * Step 17: Initialize transmit/receive descriptor rings.
491 * Initialize TBASE and RBASE.
492 */
493 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
494 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
495
496 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
497 tx_desc[i].bufptr = 0;
498 tx_desc[i].length = 0;
499 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
500 TSEC_TXBD_W : 0);
501 }
502 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
503 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
504
505 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
506 rx_desc[i].bufptr = sc->rx_data[i].paddr;
507 rx_desc[i].length = 0;
508 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
509 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
510 }
511 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
512 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
513
514 /* Step 18: Initialize the maximum receive buffer length */
515 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
516
517 /* Step 19: Configure ethernet frame sizes */
518 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
519 tsec_set_mtu(sc, ifp->if_mtu);
520
521 /* Step 20: Enable Rx and RxBD sdata snooping */
522 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
523 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
524
525 /* Step 21: Reset collision counters in hardware */
526 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
527 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
528 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
529 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
530 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
531
532 /* Step 22: Mask all CAM interrupts */
533 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
534 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
535
536 /* Step 23: Enable Rx and Tx */
537 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
538 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
539 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
540
541 /* Step 24: Reset TSEC counters for Tx and Rx rings */
542 TSEC_TX_RX_COUNTERS_INIT(sc);
543
544 /* Step 25: Setup TCP/IP Off-Load engine */
545 if (sc->is_etsec)
546 tsec_offload_setup(sc);
547
548 /* Step 26: Setup multicast filters */
549 tsec_setup_multicast(sc);
550
551 /* Step 27: Activate network interface */
552 ifp->if_drv_flags |= IFF_DRV_RUNNING;
553 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
554 sc->tsec_if_flags = ifp->if_flags;
555 sc->tsec_watchdog = 0;
556
557 /* Schedule watchdog timeout */
558 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
559 }
560
561 static void
tsec_set_mac_address(struct tsec_softc * sc)562 tsec_set_mac_address(struct tsec_softc *sc)
563 {
564 uint32_t macbuf[2] = { 0, 0 };
565 char *macbufp, *curmac;
566 int i;
567
568 TSEC_GLOBAL_LOCK_ASSERT(sc);
569
570 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
571 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN,
572 sizeof(macbuf)));
573
574 macbufp = (char *)macbuf;
575 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
576
577 /* Correct order of MAC address bytes */
578 for (i = 1; i <= ETHER_ADDR_LEN; i++)
579 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
580
581 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
582 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
583 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
584 }
585
586 /*
587 * DMA control function, if argument state is:
588 * 0 - DMA engine will be disabled
589 * 1 - DMA engine will be enabled
590 */
591 static void
tsec_dma_ctl(struct tsec_softc * sc,int state)592 tsec_dma_ctl(struct tsec_softc *sc, int state)
593 {
594 device_t dev;
595 uint32_t dma_flags, timeout;
596
597 dev = sc->dev;
598
599 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
600
601 switch (state) {
602 case 0:
603 /* Temporarily clear stop graceful stop bits. */
604 tsec_dma_ctl(sc, 1000);
605
606 /* Set it again */
607 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
608 break;
609 case 1000:
610 case 1:
611 /* Set write with response (WWR), wait (WOP) and snoop bits */
612 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
613 DMACTRL_WWR | DMACTRL_WOP);
614
615 /* Clear graceful stop bits */
616 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
617 break;
618 default:
619 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
620 state);
621 }
622
623 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
624
625 switch (state) {
626 case 0:
627 /* Wait for DMA stop */
628 timeout = TSEC_READ_RETRY;
629 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
630 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
631 DELAY(TSEC_READ_DELAY);
632
633 if (timeout == 0)
634 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
635 break;
636 case 1:
637 /* Restart transmission function */
638 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
639 }
640 }
641
642 /*
643 * Interrupts control function, if argument state is:
644 * 0 - all TSEC interrupts will be masked
645 * 1 - all TSEC interrupts will be unmasked
646 */
647 static void
tsec_intrs_ctl(struct tsec_softc * sc,int state)648 tsec_intrs_ctl(struct tsec_softc *sc, int state)
649 {
650 device_t dev;
651
652 dev = sc->dev;
653
654 switch (state) {
655 case 0:
656 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
657 break;
658 case 1:
659 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
660 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
661 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
662 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
663 break;
664 default:
665 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
666 state);
667 }
668 }
669
670 static void
tsec_reset_mac(struct tsec_softc * sc)671 tsec_reset_mac(struct tsec_softc *sc)
672 {
673 uint32_t maccfg1_flags;
674
675 /* Set soft reset bit */
676 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
677 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
678 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
679
680 /* Clear soft reset bit */
681 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
682 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
683 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
684 }
685
686 static void
tsec_watchdog(struct tsec_softc * sc)687 tsec_watchdog(struct tsec_softc *sc)
688 {
689 struct ifnet *ifp;
690
691 TSEC_GLOBAL_LOCK_ASSERT(sc);
692
693 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
694 return;
695
696 ifp = sc->tsec_ifp;
697 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
698 if_printf(ifp, "watchdog timeout\n");
699
700 tsec_stop(sc);
701 tsec_init_locked(sc);
702 }
703
704 static void
tsec_start(struct ifnet * ifp)705 tsec_start(struct ifnet *ifp)
706 {
707 struct tsec_softc *sc = ifp->if_softc;
708
709 TSEC_TRANSMIT_LOCK(sc);
710 tsec_start_locked(ifp);
711 TSEC_TRANSMIT_UNLOCK(sc);
712 }
713
714 static void
tsec_start_locked(struct ifnet * ifp)715 tsec_start_locked(struct ifnet *ifp)
716 {
717 struct tsec_softc *sc;
718 struct mbuf *m0;
719 struct tsec_tx_fcb *tx_fcb;
720 int csum_flags;
721 int start_tx;
722 uint16_t fcb_flags;
723
724 sc = ifp->if_softc;
725 start_tx = 0;
726
727 TSEC_TRANSMIT_LOCK_ASSERT(sc);
728
729 if (sc->tsec_link == 0)
730 return;
731
732 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
733 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
734
735 for (;;) {
736 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) {
737 /* No free descriptors */
738 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
739 break;
740 }
741
742 /* Get packet from the queue */
743 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
744 if (m0 == NULL)
745 break;
746
747 /* Insert TCP/IP Off-load frame control block */
748 fcb_flags = 0;
749 csum_flags = m0->m_pkthdr.csum_flags;
750 if (csum_flags) {
751 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
752 if (m0 == NULL)
753 break;
754
755 if (csum_flags & CSUM_IP)
756 fcb_flags |= TSEC_TX_FCB_IP4 |
757 TSEC_TX_FCB_CSUM_IP;
758
759 if (csum_flags & CSUM_TCP)
760 fcb_flags |= TSEC_TX_FCB_TCP |
761 TSEC_TX_FCB_CSUM_TCP_UDP;
762
763 if (csum_flags & CSUM_UDP)
764 fcb_flags |= TSEC_TX_FCB_UDP |
765 TSEC_TX_FCB_CSUM_TCP_UDP;
766
767 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
768 tx_fcb->flags = fcb_flags;
769 tx_fcb->l3_offset = ETHER_HDR_LEN;
770 tx_fcb->l4_offset = sizeof(struct ip);
771 }
772
773 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx);
774 }
775 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
776 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
777
778 if (start_tx) {
779 /* Enable transmitter and watchdog timer */
780 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
781 sc->tsec_watchdog = 5;
782 }
783 }
784
785 static void
tsec_encap(struct ifnet * ifp,struct tsec_softc * sc,struct mbuf * m0,uint16_t fcb_flags,int * start_tx)786 tsec_encap(struct ifnet *ifp, struct tsec_softc *sc, struct mbuf *m0,
787 uint16_t fcb_flags, int *start_tx)
788 {
789 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS];
790 int error, i, nsegs;
791 struct tsec_bufmap *tx_bufmap;
792 uint32_t tx_idx;
793 uint16_t flags;
794
795 TSEC_TRANSMIT_LOCK_ASSERT(sc);
796
797 tx_idx = sc->tx_idx_head;
798 tx_bufmap = &sc->tx_bufmap[tx_idx];
799
800 /* Create mapping in DMA memory */
801 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0,
802 segs, &nsegs, BUS_DMA_NOWAIT);
803 if (error == EFBIG) {
804 /* Too many segments! Defrag and try again. */
805 struct mbuf *m = m_defrag(m0, M_NOWAIT);
806
807 if (m == NULL) {
808 m_freem(m0);
809 return;
810 }
811 m0 = m;
812 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
813 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
814 }
815 if (error != 0) {
816 /* Give up. */
817 m_freem(m0);
818 return;
819 }
820
821 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
822 BUS_DMASYNC_PREWRITE);
823 tx_bufmap->mbuf = m0;
824
825 /*
826 * Fill in the TX descriptors back to front so that READY bit in first
827 * descriptor is set last.
828 */
829 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1);
830 sc->tx_idx_head = tx_idx;
831 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC;
832 for (i = nsegs - 1; i >= 0; i--) {
833 struct tsec_desc *tx_desc;
834
835 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1);
836 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
837 tx_desc->length = segs[i].ds_len;
838 tx_desc->bufptr = segs[i].ds_addr;
839
840 if (i == 0) {
841 wmb();
842
843 if (fcb_flags != 0)
844 flags |= TSEC_TXBD_TOE;
845 }
846
847 /*
848 * Set flags:
849 * - wrap
850 * - checksum
851 * - ready to send
852 * - transmit the CRC sequence after the last data byte
853 * - interrupt after the last buffer
854 */
855 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ?
856 TSEC_TXBD_W : 0) | flags;
857
858 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I);
859 }
860
861 BPF_MTAP(ifp, m0);
862 *start_tx = 1;
863 }
864
865 static void
tsec_setfilter(struct tsec_softc * sc)866 tsec_setfilter(struct tsec_softc *sc)
867 {
868 struct ifnet *ifp;
869 uint32_t flags;
870
871 ifp = sc->tsec_ifp;
872 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
873
874 /* Promiscuous mode */
875 if (ifp->if_flags & IFF_PROMISC)
876 flags |= TSEC_RCTRL_PROM;
877 else
878 flags &= ~TSEC_RCTRL_PROM;
879
880 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
881 }
882
883 #ifdef DEVICE_POLLING
884 static poll_handler_t tsec_poll;
885
886 static int
tsec_poll(struct ifnet * ifp,enum poll_cmd cmd,int count)887 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
888 {
889 uint32_t ie;
890 struct tsec_softc *sc = ifp->if_softc;
891 int rx_npkts;
892
893 rx_npkts = 0;
894
895 TSEC_GLOBAL_LOCK(sc);
896 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
897 TSEC_GLOBAL_UNLOCK(sc);
898 return (rx_npkts);
899 }
900
901 if (cmd == POLL_AND_CHECK_STATUS) {
902 tsec_error_intr_locked(sc, count);
903
904 /* Clear all events reported */
905 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
906 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
907 }
908
909 tsec_transmit_intr_locked(sc);
910
911 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
912
913 rx_npkts = tsec_receive_intr_locked(sc, count);
914
915 TSEC_RECEIVE_UNLOCK(sc);
916
917 return (rx_npkts);
918 }
919 #endif /* DEVICE_POLLING */
920
921 static int
tsec_ioctl(struct ifnet * ifp,u_long command,caddr_t data)922 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
923 {
924 struct tsec_softc *sc = ifp->if_softc;
925 struct ifreq *ifr = (struct ifreq *)data;
926 int mask, error = 0;
927
928 switch (command) {
929 case SIOCSIFMTU:
930 TSEC_GLOBAL_LOCK(sc);
931 if (tsec_set_mtu(sc, ifr->ifr_mtu))
932 ifp->if_mtu = ifr->ifr_mtu;
933 else
934 error = EINVAL;
935 TSEC_GLOBAL_UNLOCK(sc);
936 break;
937 case SIOCSIFFLAGS:
938 TSEC_GLOBAL_LOCK(sc);
939 if (ifp->if_flags & IFF_UP) {
940 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
941 if ((sc->tsec_if_flags ^ ifp->if_flags) &
942 IFF_PROMISC)
943 tsec_setfilter(sc);
944
945 if ((sc->tsec_if_flags ^ ifp->if_flags) &
946 IFF_ALLMULTI)
947 tsec_setup_multicast(sc);
948 } else
949 tsec_init_locked(sc);
950 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
951 tsec_stop(sc);
952
953 sc->tsec_if_flags = ifp->if_flags;
954 TSEC_GLOBAL_UNLOCK(sc);
955 break;
956 case SIOCADDMULTI:
957 case SIOCDELMULTI:
958 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
959 TSEC_GLOBAL_LOCK(sc);
960 tsec_setup_multicast(sc);
961 TSEC_GLOBAL_UNLOCK(sc);
962 }
963 case SIOCGIFMEDIA:
964 case SIOCSIFMEDIA:
965 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
966 command);
967 break;
968 case SIOCSIFCAP:
969 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
970 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
971 TSEC_GLOBAL_LOCK(sc);
972 ifp->if_capenable &= ~IFCAP_HWCSUM;
973 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
974 tsec_offload_setup(sc);
975 TSEC_GLOBAL_UNLOCK(sc);
976 }
977 #ifdef DEVICE_POLLING
978 if (mask & IFCAP_POLLING) {
979 if (ifr->ifr_reqcap & IFCAP_POLLING) {
980 error = ether_poll_register(tsec_poll, ifp);
981 if (error)
982 return (error);
983
984 TSEC_GLOBAL_LOCK(sc);
985 /* Disable interrupts */
986 tsec_intrs_ctl(sc, 0);
987 ifp->if_capenable |= IFCAP_POLLING;
988 TSEC_GLOBAL_UNLOCK(sc);
989 } else {
990 error = ether_poll_deregister(ifp);
991 TSEC_GLOBAL_LOCK(sc);
992 /* Enable interrupts */
993 tsec_intrs_ctl(sc, 1);
994 ifp->if_capenable &= ~IFCAP_POLLING;
995 TSEC_GLOBAL_UNLOCK(sc);
996 }
997 }
998 #endif
999 break;
1000
1001 default:
1002 error = ether_ioctl(ifp, command, data);
1003 }
1004
1005 /* Flush buffers if not empty */
1006 if (ifp->if_flags & IFF_UP)
1007 tsec_start(ifp);
1008 return (error);
1009 }
1010
1011 static int
tsec_ifmedia_upd(struct ifnet * ifp)1012 tsec_ifmedia_upd(struct ifnet *ifp)
1013 {
1014 struct tsec_softc *sc = ifp->if_softc;
1015 struct mii_data *mii;
1016
1017 TSEC_TRANSMIT_LOCK(sc);
1018
1019 mii = sc->tsec_mii;
1020 mii_mediachg(mii);
1021
1022 TSEC_TRANSMIT_UNLOCK(sc);
1023 return (0);
1024 }
1025
1026 static void
tsec_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1027 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1028 {
1029 struct tsec_softc *sc = ifp->if_softc;
1030 struct mii_data *mii;
1031
1032 TSEC_TRANSMIT_LOCK(sc);
1033
1034 mii = sc->tsec_mii;
1035 mii_pollstat(mii);
1036
1037 ifmr->ifm_active = mii->mii_media_active;
1038 ifmr->ifm_status = mii->mii_media_status;
1039
1040 TSEC_TRANSMIT_UNLOCK(sc);
1041 }
1042
1043 static int
tsec_new_rxbuf(bus_dma_tag_t tag,bus_dmamap_t map,struct mbuf ** mbufp,uint32_t * paddr)1044 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1045 uint32_t *paddr)
1046 {
1047 struct mbuf *new_mbuf;
1048 bus_dma_segment_t seg[1];
1049 int error, nsegs;
1050
1051 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1052
1053 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1054 if (new_mbuf == NULL)
1055 return (ENOBUFS);
1056 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1057
1058 if (*mbufp) {
1059 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1060 bus_dmamap_unload(tag, map);
1061 }
1062
1063 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1064 BUS_DMA_NOWAIT);
1065 KASSERT(nsegs == 1, ("Too many segments returned!"));
1066 if (nsegs != 1 || error)
1067 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1068
1069 #if 0
1070 if (error) {
1071 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1072 error);
1073 m_freem(new_mbuf);
1074 return (ENOBUFS);
1075 }
1076 #endif
1077
1078 #if 0
1079 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1080 ("Wrong alignment of RX buffer!"));
1081 #endif
1082 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1083
1084 (*mbufp) = new_mbuf;
1085 (*paddr) = seg->ds_addr;
1086 return (0);
1087 }
1088
1089 static void
tsec_map_dma_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)1090 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1091 {
1092 u_int32_t *paddr;
1093
1094 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1095 paddr = arg;
1096 *paddr = segs->ds_addr;
1097 }
1098
1099 static int
tsec_alloc_dma_desc(device_t dev,bus_dma_tag_t * dtag,bus_dmamap_t * dmap,bus_size_t dsize,void ** vaddr,void * raddr,const char * dname)1100 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1101 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1102 {
1103 int error;
1104
1105 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1106 error = bus_dma_tag_create(NULL, /* parent */
1107 PAGE_SIZE, 0, /* alignment, boundary */
1108 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1109 BUS_SPACE_MAXADDR, /* highaddr */
1110 NULL, NULL, /* filtfunc, filtfuncarg */
1111 dsize, 1, /* maxsize, nsegments */
1112 dsize, 0, /* maxsegsz, flags */
1113 NULL, NULL, /* lockfunc, lockfuncarg */
1114 dtag); /* dmat */
1115
1116 if (error) {
1117 device_printf(dev, "failed to allocate busdma %s tag\n",
1118 dname);
1119 (*vaddr) = NULL;
1120 return (ENXIO);
1121 }
1122
1123 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1124 dmap);
1125 if (error) {
1126 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1127 dname);
1128 bus_dma_tag_destroy(*dtag);
1129 (*vaddr) = NULL;
1130 return (ENXIO);
1131 }
1132
1133 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1134 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1135 if (error) {
1136 device_printf(dev, "cannot get address of the %s "
1137 "descriptors\n", dname);
1138 bus_dmamem_free(*dtag, *vaddr, *dmap);
1139 bus_dma_tag_destroy(*dtag);
1140 (*vaddr) = NULL;
1141 return (ENXIO);
1142 }
1143
1144 return (0);
1145 }
1146
1147 static void
tsec_free_dma_desc(bus_dma_tag_t dtag,bus_dmamap_t dmap,void * vaddr)1148 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1149 {
1150
1151 if (vaddr == NULL)
1152 return;
1153
1154 /* Unmap descriptors from DMA memory */
1155 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1156 BUS_DMASYNC_POSTWRITE);
1157 bus_dmamap_unload(dtag, dmap);
1158
1159 /* Free descriptors memory */
1160 bus_dmamem_free(dtag, vaddr, dmap);
1161
1162 /* Destroy descriptors tag */
1163 bus_dma_tag_destroy(dtag);
1164 }
1165
1166 static void
tsec_free_dma(struct tsec_softc * sc)1167 tsec_free_dma(struct tsec_softc *sc)
1168 {
1169 int i;
1170
1171 /* Free TX maps */
1172 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1173 if (sc->tx_bufmap[i].map_initialized)
1174 bus_dmamap_destroy(sc->tsec_tx_mtag,
1175 sc->tx_bufmap[i].map);
1176 /* Destroy tag for TX mbufs */
1177 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1178
1179 /* Free RX mbufs and maps */
1180 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1181 if (sc->rx_data[i].mbuf) {
1182 /* Unload buffer from DMA */
1183 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1184 BUS_DMASYNC_POSTREAD);
1185 bus_dmamap_unload(sc->tsec_rx_mtag,
1186 sc->rx_data[i].map);
1187
1188 /* Free buffer */
1189 m_freem(sc->rx_data[i].mbuf);
1190 }
1191 /* Destroy map for this buffer */
1192 if (sc->rx_data[i].map != NULL)
1193 bus_dmamap_destroy(sc->tsec_rx_mtag,
1194 sc->rx_data[i].map);
1195 }
1196 /* Destroy tag for RX mbufs */
1197 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1198
1199 /* Unload TX/RX descriptors */
1200 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1201 sc->tsec_tx_vaddr);
1202 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1203 sc->tsec_rx_vaddr);
1204 }
1205
1206 static void
tsec_stop(struct tsec_softc * sc)1207 tsec_stop(struct tsec_softc *sc)
1208 {
1209 struct ifnet *ifp;
1210 uint32_t tmpval;
1211
1212 TSEC_GLOBAL_LOCK_ASSERT(sc);
1213
1214 ifp = sc->tsec_ifp;
1215
1216 /* Disable interface and watchdog timer */
1217 callout_stop(&sc->tsec_callout);
1218 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1219 sc->tsec_watchdog = 0;
1220
1221 /* Disable all interrupts and stop DMA */
1222 tsec_intrs_ctl(sc, 0);
1223 tsec_dma_ctl(sc, 0);
1224
1225 /* Remove pending data from TX queue */
1226 while (sc->tx_idx_tail != sc->tx_idx_head) {
1227 bus_dmamap_sync(sc->tsec_tx_mtag,
1228 sc->tx_bufmap[sc->tx_idx_tail].map,
1229 BUS_DMASYNC_POSTWRITE);
1230 bus_dmamap_unload(sc->tsec_tx_mtag,
1231 sc->tx_bufmap[sc->tx_idx_tail].map);
1232 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf);
1233 sc->tx_idx_tail = (sc->tx_idx_tail + 1)
1234 & (TSEC_TX_NUM_DESC - 1);
1235 }
1236
1237 /* Disable RX and TX */
1238 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1239 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1240 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1241 DELAY(10);
1242 }
1243
1244 static void
tsec_tick(void * arg)1245 tsec_tick(void *arg)
1246 {
1247 struct tsec_softc *sc = arg;
1248 struct ifnet *ifp;
1249 int link;
1250
1251 TSEC_GLOBAL_LOCK(sc);
1252
1253 tsec_watchdog(sc);
1254
1255 ifp = sc->tsec_ifp;
1256 link = sc->tsec_link;
1257
1258 mii_tick(sc->tsec_mii);
1259
1260 if (link == 0 && sc->tsec_link == 1 &&
1261 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1262 tsec_start_locked(ifp);
1263
1264 /* Schedule another timeout one second from now. */
1265 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1266
1267 TSEC_GLOBAL_UNLOCK(sc);
1268 }
1269
1270 /*
1271 * This is the core RX routine. It replenishes mbufs in the descriptor and
1272 * sends data which have been dma'ed into host memory to upper layer.
1273 *
1274 * Loops at most count times if count is > 0, or until done if count < 0.
1275 */
1276 static int
tsec_receive_intr_locked(struct tsec_softc * sc,int count)1277 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1278 {
1279 struct tsec_desc *rx_desc;
1280 struct ifnet *ifp;
1281 struct rx_data_type *rx_data;
1282 struct mbuf *m;
1283 uint32_t i;
1284 int c, rx_npkts;
1285 uint16_t flags;
1286
1287 TSEC_RECEIVE_LOCK_ASSERT(sc);
1288
1289 ifp = sc->tsec_ifp;
1290 rx_data = sc->rx_data;
1291 rx_npkts = 0;
1292
1293 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1294 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1295
1296 for (c = 0; ; c++) {
1297 if (count >= 0 && count-- == 0)
1298 break;
1299
1300 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1301 flags = rx_desc->flags;
1302
1303 /* Check if there is anything to receive */
1304 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1305 /*
1306 * Avoid generating another interrupt
1307 */
1308 if (flags & TSEC_RXBD_E)
1309 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1310 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1311 /*
1312 * We didn't consume current descriptor and have to
1313 * return it to the queue
1314 */
1315 TSEC_BACK_CUR_RX_DESC(sc);
1316 break;
1317 }
1318
1319 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1320 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1321 rx_desc->length = 0;
1322 rx_desc->flags = (rx_desc->flags &
1323 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1324
1325 if (sc->frame != NULL) {
1326 m_free(sc->frame);
1327 sc->frame = NULL;
1328 }
1329
1330 continue;
1331 }
1332
1333 /* Ok... process frame */
1334 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1335 m = rx_data[i].mbuf;
1336 m->m_len = rx_desc->length;
1337
1338 if (sc->frame != NULL) {
1339 if ((flags & TSEC_RXBD_L) != 0)
1340 m->m_len -= m_length(sc->frame, NULL);
1341
1342 m->m_flags &= ~M_PKTHDR;
1343 m_cat(sc->frame, m);
1344 } else {
1345 sc->frame = m;
1346 }
1347
1348 m = NULL;
1349
1350 if ((flags & TSEC_RXBD_L) != 0) {
1351 m = sc->frame;
1352 sc->frame = NULL;
1353 }
1354
1355 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1356 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1357 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1358 /*
1359 * We ran out of mbufs; didn't consume current
1360 * descriptor and have to return it to the queue.
1361 */
1362 TSEC_BACK_CUR_RX_DESC(sc);
1363 break;
1364 }
1365
1366 /* Attach new buffer to descriptor and clear flags */
1367 rx_desc->bufptr = rx_data[i].paddr;
1368 rx_desc->length = 0;
1369 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1370 TSEC_RXBD_E | TSEC_RXBD_I;
1371
1372 if (m != NULL) {
1373 m->m_pkthdr.rcvif = ifp;
1374
1375 m_fixhdr(m);
1376 m_adj(m, -ETHER_CRC_LEN);
1377
1378 if (sc->is_etsec)
1379 tsec_offload_process_frame(sc, m);
1380
1381 TSEC_RECEIVE_UNLOCK(sc);
1382 (*ifp->if_input)(ifp, m);
1383 TSEC_RECEIVE_LOCK(sc);
1384 rx_npkts++;
1385 }
1386 }
1387
1388 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1390
1391 /*
1392 * Make sure TSEC receiver is not halted.
1393 *
1394 * Various conditions can stop the TSEC receiver, but not all are
1395 * signaled and handled by error interrupt, so make sure the receiver
1396 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1397 * halted, and is harmless if already running.
1398 */
1399 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1400 return (rx_npkts);
1401 }
1402
1403 void
tsec_receive_intr(void * arg)1404 tsec_receive_intr(void *arg)
1405 {
1406 struct tsec_softc *sc = arg;
1407
1408 TSEC_RECEIVE_LOCK(sc);
1409
1410 #ifdef DEVICE_POLLING
1411 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1412 TSEC_RECEIVE_UNLOCK(sc);
1413 return;
1414 }
1415 #endif
1416
1417 /* Confirm the interrupt was received by driver */
1418 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1419 tsec_receive_intr_locked(sc, -1);
1420
1421 TSEC_RECEIVE_UNLOCK(sc);
1422 }
1423
1424 static void
tsec_transmit_intr_locked(struct tsec_softc * sc)1425 tsec_transmit_intr_locked(struct tsec_softc *sc)
1426 {
1427 struct ifnet *ifp;
1428 uint32_t tx_idx;
1429
1430 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1431
1432 ifp = sc->tsec_ifp;
1433
1434 /* Update collision statistics */
1435 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1436
1437 /* Reset collision counters in hardware */
1438 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1439 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1440 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1441 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1442 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1443
1444 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1445 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1446
1447 tx_idx = sc->tx_idx_tail;
1448 while (tx_idx != sc->tx_idx_head) {
1449 struct tsec_desc *tx_desc;
1450 struct tsec_bufmap *tx_bufmap;
1451
1452 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
1453 if (tx_desc->flags & TSEC_TXBD_R) {
1454 break;
1455 }
1456
1457 tx_bufmap = &sc->tx_bufmap[tx_idx];
1458 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1);
1459 if (tx_bufmap->mbuf == NULL)
1460 continue;
1461
1462 /*
1463 * This is the last buf in this packet, so unmap and free it.
1464 */
1465 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
1466 BUS_DMASYNC_POSTWRITE);
1467 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map);
1468 m_freem(tx_bufmap->mbuf);
1469 tx_bufmap->mbuf = NULL;
1470
1471 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1472 }
1473 sc->tx_idx_tail = tx_idx;
1474 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1475 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1476
1477 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1478 tsec_start_locked(ifp);
1479
1480 if (sc->tx_idx_tail == sc->tx_idx_head)
1481 sc->tsec_watchdog = 0;
1482 }
1483
1484 void
tsec_transmit_intr(void * arg)1485 tsec_transmit_intr(void *arg)
1486 {
1487 struct tsec_softc *sc = arg;
1488
1489 TSEC_TRANSMIT_LOCK(sc);
1490
1491 #ifdef DEVICE_POLLING
1492 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1493 TSEC_TRANSMIT_UNLOCK(sc);
1494 return;
1495 }
1496 #endif
1497 /* Confirm the interrupt was received by driver */
1498 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1499 tsec_transmit_intr_locked(sc);
1500
1501 TSEC_TRANSMIT_UNLOCK(sc);
1502 }
1503
1504 static void
tsec_error_intr_locked(struct tsec_softc * sc,int count)1505 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1506 {
1507 struct ifnet *ifp;
1508 uint32_t eflags;
1509
1510 TSEC_GLOBAL_LOCK_ASSERT(sc);
1511
1512 ifp = sc->tsec_ifp;
1513
1514 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1515
1516 /* Clear events bits in hardware */
1517 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1518 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1519 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1520 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1521
1522 /* Check transmitter errors */
1523 if (eflags & TSEC_IEVENT_TXE) {
1524 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1525
1526 if (eflags & TSEC_IEVENT_LC)
1527 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1528
1529 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1530 }
1531
1532 /* Check for discarded frame due to a lack of buffers */
1533 if (eflags & TSEC_IEVENT_BSY) {
1534 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1535 }
1536
1537 if (ifp->if_flags & IFF_DEBUG)
1538 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1539 eflags);
1540
1541 if (eflags & TSEC_IEVENT_EBERR) {
1542 if_printf(ifp, "System bus error occurred during"
1543 "DMA transaction (flags: 0x%x)\n", eflags);
1544 tsec_init_locked(sc);
1545 }
1546
1547 if (eflags & TSEC_IEVENT_BABT)
1548 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1549
1550 if (eflags & TSEC_IEVENT_BABR)
1551 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1552 }
1553
1554 void
tsec_error_intr(void * arg)1555 tsec_error_intr(void *arg)
1556 {
1557 struct tsec_softc *sc = arg;
1558
1559 TSEC_GLOBAL_LOCK(sc);
1560 tsec_error_intr_locked(sc, -1);
1561 TSEC_GLOBAL_UNLOCK(sc);
1562 }
1563
1564 int
tsec_miibus_readreg(device_t dev,int phy,int reg)1565 tsec_miibus_readreg(device_t dev, int phy, int reg)
1566 {
1567 struct tsec_softc *sc;
1568 int timeout;
1569 int rv;
1570
1571 sc = device_get_softc(dev);
1572
1573 TSEC_PHY_LOCK();
1574 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1575 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1576 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1577
1578 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY);
1579 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1580 TSEC_PHY_UNLOCK();
1581
1582 if (timeout)
1583 device_printf(dev, "Timeout while reading from PHY!\n");
1584
1585 return (rv);
1586 }
1587
1588 int
tsec_miibus_writereg(device_t dev,int phy,int reg,int value)1589 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1590 {
1591 struct tsec_softc *sc;
1592 int timeout;
1593
1594 sc = device_get_softc(dev);
1595
1596 TSEC_PHY_LOCK();
1597 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1598 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1599 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
1600 TSEC_PHY_UNLOCK();
1601
1602 if (timeout)
1603 device_printf(dev, "Timeout while writing to PHY!\n");
1604
1605 return (0);
1606 }
1607
1608 void
tsec_miibus_statchg(device_t dev)1609 tsec_miibus_statchg(device_t dev)
1610 {
1611 struct tsec_softc *sc;
1612 struct mii_data *mii;
1613 uint32_t ecntrl, id, tmp;
1614 int link;
1615
1616 sc = device_get_softc(dev);
1617 mii = sc->tsec_mii;
1618 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1619
1620 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1621
1622 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1623 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1624 else
1625 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1626
1627 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1628 case IFM_1000_T:
1629 case IFM_1000_SX:
1630 tmp |= TSEC_MACCFG2_GMII;
1631 sc->tsec_link = link;
1632 break;
1633 case IFM_100_TX:
1634 case IFM_10_T:
1635 tmp |= TSEC_MACCFG2_MII;
1636 sc->tsec_link = link;
1637 break;
1638 case IFM_NONE:
1639 if (link)
1640 device_printf(dev, "No speed selected but link "
1641 "active!\n");
1642 sc->tsec_link = 0;
1643 return;
1644 default:
1645 sc->tsec_link = 0;
1646 device_printf(dev, "Unknown speed (%d), link %s!\n",
1647 IFM_SUBTYPE(mii->mii_media_active),
1648 ((link) ? "up" : "down"));
1649 return;
1650 }
1651 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1652
1653 /* XXX kludge - use circumstantial evidence for reduced mode. */
1654 id = TSEC_READ(sc, TSEC_REG_ID2);
1655 if (id & 0xffff) {
1656 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1657 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1658 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1659 }
1660 }
1661
1662 static void
tsec_add_sysctls(struct tsec_softc * sc)1663 tsec_add_sysctls(struct tsec_softc *sc)
1664 {
1665 struct sysctl_ctx_list *ctx;
1666 struct sysctl_oid_list *children;
1667 struct sysctl_oid *tree;
1668
1669 ctx = device_get_sysctl_ctx(sc->dev);
1670 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1671 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1672 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "TSEC Interrupts coalescing");
1673 children = SYSCTL_CHILDREN(tree);
1674
1675 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1676 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX,
1677 tsec_sysctl_ic_time, "I", "IC RX time threshold (0-65535)");
1678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1679 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX,
1680 tsec_sysctl_ic_count, "I", "IC RX frame count threshold (0-255)");
1681
1682 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1683 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX,
1684 tsec_sysctl_ic_time, "I", "IC TX time threshold (0-65535)");
1685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1686 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX,
1687 tsec_sysctl_ic_count, "I", "IC TX frame count threshold (0-255)");
1688 }
1689
1690 /*
1691 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1692 * interrupt is raised either upon:
1693 *
1694 * - threshold-defined period of time elapsed, or
1695 * - threshold-defined number of frames is received/transmitted,
1696 * whichever occurs first.
1697 *
1698 * The following sysctls regulate IC behaviour (for TX/RX separately):
1699 *
1700 * dev.tsec.<unit>.int_coal.rx_time
1701 * dev.tsec.<unit>.int_coal.rx_count
1702 * dev.tsec.<unit>.int_coal.tx_time
1703 * dev.tsec.<unit>.int_coal.tx_count
1704 *
1705 * Values:
1706 *
1707 * - 0 for either time or count disables IC on the given TX/RX path
1708 *
1709 * - count: 1-255 (expresses frame count number; note that value of 1 is
1710 * effectively IC off)
1711 *
1712 * - time: 1-65535 (value corresponds to a real time period and is
1713 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1714 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1715 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1716 * TSEC reference manual.
1717 */
1718 static int
tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)1719 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1720 {
1721 int error;
1722 uint32_t time;
1723 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1724
1725 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1726
1727 error = sysctl_handle_int(oidp, &time, 0, req);
1728 if (error != 0)
1729 return (error);
1730
1731 if (time > 65535)
1732 return (EINVAL);
1733
1734 TSEC_IC_LOCK(sc);
1735 if (arg2 == TSEC_IC_RX) {
1736 sc->rx_ic_time = time;
1737 tsec_set_rxic(sc);
1738 } else {
1739 sc->tx_ic_time = time;
1740 tsec_set_txic(sc);
1741 }
1742 TSEC_IC_UNLOCK(sc);
1743
1744 return (0);
1745 }
1746
1747 static int
tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)1748 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1749 {
1750 int error;
1751 uint32_t count;
1752 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1753
1754 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1755
1756 error = sysctl_handle_int(oidp, &count, 0, req);
1757 if (error != 0)
1758 return (error);
1759
1760 if (count > 255)
1761 return (EINVAL);
1762
1763 TSEC_IC_LOCK(sc);
1764 if (arg2 == TSEC_IC_RX) {
1765 sc->rx_ic_count = count;
1766 tsec_set_rxic(sc);
1767 } else {
1768 sc->tx_ic_count = count;
1769 tsec_set_txic(sc);
1770 }
1771 TSEC_IC_UNLOCK(sc);
1772
1773 return (0);
1774 }
1775
1776 static void
tsec_set_rxic(struct tsec_softc * sc)1777 tsec_set_rxic(struct tsec_softc *sc)
1778 {
1779 uint32_t rxic_val;
1780
1781 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1782 /* Disable RX IC */
1783 rxic_val = 0;
1784 else {
1785 rxic_val = 0x80000000;
1786 rxic_val |= (sc->rx_ic_count << 21);
1787 rxic_val |= sc->rx_ic_time;
1788 }
1789
1790 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1791 }
1792
1793 static void
tsec_set_txic(struct tsec_softc * sc)1794 tsec_set_txic(struct tsec_softc *sc)
1795 {
1796 uint32_t txic_val;
1797
1798 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1799 /* Disable TX IC */
1800 txic_val = 0;
1801 else {
1802 txic_val = 0x80000000;
1803 txic_val |= (sc->tx_ic_count << 21);
1804 txic_val |= sc->tx_ic_time;
1805 }
1806
1807 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1808 }
1809
1810 static void
tsec_offload_setup(struct tsec_softc * sc)1811 tsec_offload_setup(struct tsec_softc *sc)
1812 {
1813 struct ifnet *ifp = sc->tsec_ifp;
1814 uint32_t reg;
1815
1816 TSEC_GLOBAL_LOCK_ASSERT(sc);
1817
1818 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1819 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1820
1821 if (ifp->if_capenable & IFCAP_TXCSUM)
1822 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1823 else
1824 ifp->if_hwassist = 0;
1825
1826 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1827
1828 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1829 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1830 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1831
1832 if (ifp->if_capenable & IFCAP_RXCSUM)
1833 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1834 TSEC_RCTRL_PRSDEP_PARSE_L234;
1835
1836 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1837 }
1838
1839 static void
tsec_offload_process_frame(struct tsec_softc * sc,struct mbuf * m)1840 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1841 {
1842 struct tsec_rx_fcb rx_fcb;
1843 int csum_flags = 0;
1844 int protocol, flags;
1845
1846 TSEC_RECEIVE_LOCK_ASSERT(sc);
1847
1848 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1849 flags = rx_fcb.flags;
1850 protocol = rx_fcb.protocol;
1851
1852 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1853 csum_flags |= CSUM_IP_CHECKED;
1854
1855 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1856 csum_flags |= CSUM_IP_VALID;
1857 }
1858
1859 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1860 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1861 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1862 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1863 m->m_pkthdr.csum_data = 0xFFFF;
1864 }
1865
1866 m->m_pkthdr.csum_flags = csum_flags;
1867
1868 if (flags & TSEC_RX_FCB_VLAN) {
1869 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1870 m->m_flags |= M_VLANTAG;
1871 }
1872
1873 m_adj(m, sizeof(struct tsec_rx_fcb));
1874 }
1875
1876 static u_int
tsec_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1877 tsec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1878 {
1879 uint32_t h, *hashtable = arg;
1880
1881 h = (ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 24) & 0xFF;
1882 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1883
1884 return (1);
1885 }
1886
1887 static void
tsec_setup_multicast(struct tsec_softc * sc)1888 tsec_setup_multicast(struct tsec_softc *sc)
1889 {
1890 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1891 struct ifnet *ifp = sc->tsec_ifp;
1892 int i;
1893
1894 TSEC_GLOBAL_LOCK_ASSERT(sc);
1895
1896 if (ifp->if_flags & IFF_ALLMULTI) {
1897 for (i = 0; i < 8; i++)
1898 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1899
1900 return;
1901 }
1902
1903 if_foreach_llmaddr(ifp, tsec_hash_maddr, &hashtable);
1904
1905 for (i = 0; i < 8; i++)
1906 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1907 }
1908
1909 static int
tsec_set_mtu(struct tsec_softc * sc,unsigned int mtu)1910 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1911 {
1912
1913 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1914
1915 TSEC_GLOBAL_LOCK_ASSERT(sc);
1916
1917 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1918 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);
1919 return (mtu);
1920 }
1921
1922 return (0);
1923 }
1924