1 /* -*-C++-*- $NetBSD: sh3_dev.cpp,v 1.6 2008/04/28 20:23:20 martin Exp $ */
2
3 /*-
4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <hpcboot.h>
33 #include <hpcmenu.h>
34 #include <console.h>
35
36 #include <sh3/cpu/sh3.h>
37 #include <sh3/dev/sh.h>
38 #include <sh3/dev/sh_dev.h>
39 #include <sh3/dev/hd64461.h>
40
41 static void __tmu_channel_info(int, paddr_t, paddr_t, paddr_t);
42
43 struct SH3dev::intr_priority SH3dev::_ipr_table[] = {
44 { "TMU0", SH3_IPRA, 12 },
45 { "TMU1", SH3_IPRA, 8 },
46 { "TMU2", SH3_IPRA, 4 },
47 { "RTC", SH3_IPRA, 0 },
48 { "WDT", SH3_IPRB, 12 },
49 { "REF", SH3_IPRB, 8 },
50 { "SCI", SH3_IPRB, 4 },
51 { "reserve", SH3_IPRB, 0 },
52 { "IRQ3", SH3_IPRC, 12 },
53 { "IRQ2", SH3_IPRC, 8 },
54 { "IRQ1", SH3_IPRC, 4 },
55 { "IRQ0", SH3_IPRC, 0 },
56 { "PINT0-7", SH3_IPRD, 12 },
57 { "PINT8-15", SH3_IPRD, 8 },
58 { "IRQ5", SH3_IPRD, 4 },
59 { "IRQ4", SH3_IPRD, 0 },
60 { "DMAC", SH3_IPRE, 12 },
61 { "IrDA", SH3_IPRE, 8 },
62 { "SCIF", SH3_IPRE, 4 },
63 { "ADC", SH3_IPRE, 0 },
64 { 0, 0, 0} /* terminator */
65 };
66
67 void
dump(uint8_t bit)68 SH3dev::dump(uint8_t bit)
69 {
70 int kmode;
71
72 super::dump(bit);
73
74 kmode = SetKMode(1);
75
76 if (bit & DUMP_DEV) {
77 // INTC
78 icu_dump();
79
80 // BSC
81 bsc_dump();
82
83 // TMU
84 tmu_dump();
85
86 // PFC , I/O port
87 pfc_dump();
88 }
89
90 if (bit & DUMP_COMPANION) {
91 // HD64461
92 platid_t platform;
93 platform.dw.dw0 = _menu->_pref.platid_hi;
94 platform.dw.dw1 = _menu->_pref.platid_lo;
95 hd64461_dump(platform);
96 }
97
98 SetKMode(kmode);
99 }
100
101 void
icu_dump()102 SH3dev::icu_dump()
103 {
104
105 super::icu_dump_priority(_ipr_table);
106 icu_control();
107 DPRINTF((TEXT("ICR0 0x%08x\n"), _reg_read_2(SH3_ICR0)));
108 DPRINTF((TEXT("ICR1 0x%08x\n"), _reg_read_2(SH3_ICR1)));
109 DPRINTF((TEXT("ICR2 0x%08x\n"), _reg_read_2(SH3_ICR2)));
110 DPRINTF((TEXT("PINTER 0x%08x\n"), _reg_read_2(SH3_PINTER)));
111 DPRINTF((TEXT("IPRA 0x%08x\n"), _reg_read_2(SH3_IPRA)));
112 DPRINTF((TEXT("IPRB 0x%08x\n"), _reg_read_2(SH3_IPRB)));
113 DPRINTF((TEXT("IPRC 0x%08x\n"), _reg_read_2(SH3_IPRC)));
114 DPRINTF((TEXT("IPRD 0x%08x\n"), _reg_read_2(SH3_IPRD)));
115 DPRINTF((TEXT("IPRE 0x%08x\n"), _reg_read_2(SH3_IPRE)));
116 DPRINTF((TEXT("IRR0 0x%08x\n"), _reg_read_1(SH3_IRR0)));
117 DPRINTF((TEXT("IRR1 0x%08x\n"), _reg_read_1(SH3_IRR1)));
118 DPRINTF((TEXT("IRR2 0x%08x\n"), _reg_read_1(SH3_IRR2)));
119 }
120
121 void
icu_control()122 SH3dev::icu_control()
123 {
124 const char *sense_select[] = {
125 "falling edge",
126 "raising edge",
127 "low level",
128 "reserved",
129 };
130 uint16_t r;
131
132 // PINT0-15
133 DPRINTF((TEXT("PINT enable(on |) :")));
134 bitdisp(_reg_read_2(SH3_PINTER));
135 DPRINTF((TEXT("PINT detect(high |):")));
136 bitdisp(_reg_read_2(SH3_ICR2));
137 // NMI
138 r = _reg_read_2(SH3_ICR0);
139 DPRINTF((TEXT("NMI(%S %S-edge),"),
140 r & SH3_ICR0_NMIL ? "High" : "Low",
141 r & SH3_ICR0_NMIE ? "raising" : "falling"));
142 r = _reg_read_2(SH3_ICR1);
143 DPRINTF((TEXT(" %S maskable,"), r & SH3_ICR1_MAI ? "" : "never"));
144 DPRINTF((TEXT(" SR.BL %S\n"),
145 r & SH3_ICR1_BLMSK ? "ignored" : "maskable"));
146 // IRQ0-5
147 DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"),
148 r & SH3_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]"));
149 if (r & SH3_ICR1_IRQLVL) {
150 DPRINTF((TEXT("IRLS[0:3] %S\n"),
151 r & SH3_ICR1_IRLSEN ? "enabled" : "disabled"));
152 }
153 // sense select
154 for (int i = 5; i >= 0; i--) {
155 DPRINTF((TEXT("IRQ[%d] %S\n"), i,
156 sense_select [
157 (r >>(i * 2)) & SH3_SENSE_SELECT_MASK]));
158 }
159 }
160
161 //
162 // Debug Functions.
163 //
164 void
bsc_dump()165 SH3dev::bsc_dump()
166 {
167
168 DPRINTF((TEXT("<<<Bus State Controller>>>\n")));
169 #define DUMP_BSC_REG(x) \
170 DPRINTF((TEXT("%-8S"), #x)); \
171 bitdisp(_reg_read_2(SH3_ ## x))
172 DUMP_BSC_REG(BCR1);
173 DUMP_BSC_REG(BCR2);
174 DUMP_BSC_REG(WCR1);
175 DUMP_BSC_REG(WCR2);
176 DUMP_BSC_REG(MCR);
177 DUMP_BSC_REG(DCR);
178 DUMP_BSC_REG(PCR);
179 DUMP_BSC_REG(RTCSR);
180 DUMP_BSC_REG(RTCNT);
181 DUMP_BSC_REG(RTCOR);
182 DUMP_BSC_REG(RFCR);
183 DUMP_BSC_REG(BCR3);
184 #undef DUMP_BSC_REG
185 }
186
187 void
pfc_dump()188 SH3dev::pfc_dump()
189 {
190 DPRINTF((TEXT("<<<Pin Function Controller>>>\n")));
191 DPRINTF((TEXT("[control]\n")));
192 #define DUMP_PFC_REG(x) \
193 DPRINTF((TEXT("P%SCR :"), #x)); \
194 bitdisp(_reg_read_2(SH3_P##x##CR))
195 DUMP_PFC_REG(A);
196 DUMP_PFC_REG(B);
197 DUMP_PFC_REG(C);
198 DUMP_PFC_REG(D);
199 DUMP_PFC_REG(E);
200 DUMP_PFC_REG(F);
201 DUMP_PFC_REG(G);
202 DUMP_PFC_REG(H);
203 DUMP_PFC_REG(J);
204 DUMP_PFC_REG(K);
205 DUMP_PFC_REG(L);
206 #undef DUMP_PFC_REG
207 DPRINTF((TEXT("SCPCR :")));
208 bitdisp(_reg_read_2(SH3_SCPCR));
209 DPRINTF((TEXT("\n[data]\n")));
210 #define DUMP_IOPORT_REG(x) \
211 DPRINTF((TEXT("P%SDR :"), #x)); \
212 bitdisp(_reg_read_1(SH3_P##x##DR))
213 DUMP_IOPORT_REG(A);
214 DUMP_IOPORT_REG(B);
215 DUMP_IOPORT_REG(C);
216 DUMP_IOPORT_REG(D);
217 DUMP_IOPORT_REG(E);
218 DUMP_IOPORT_REG(F);
219 DUMP_IOPORT_REG(G);
220 DUMP_IOPORT_REG(H);
221 DUMP_IOPORT_REG(J);
222 DUMP_IOPORT_REG(K);
223 DUMP_IOPORT_REG(L);
224 #undef DUMP_IOPORT_REG
225 DPRINTF((TEXT("SCPDR :")));
226 bitdisp(_reg_read_1(SH3_SCPDR));
227 }
228
229 void
tmu_dump()230 SH3dev::tmu_dump()
231 {
232 uint8_t r8;
233
234 DPRINTF((TEXT("<<<TMU>>>\n")));
235 /* Common */
236 /* TOCR timer output control register */
237 r8 = _reg_read_1(SH3_TOCR);
238 DPRINTF((TEXT("TCLK = %S\n"),
239 r8 & SH3_TOCR_TCOE ? "RTC output" : "input"));
240 /* TSTR */
241 r8 = _reg_read_1(SH3_TSTR);
242 DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"),
243 r8 & SH3_TSTR_STR0 ? 'x' : '_',
244 r8 & SH3_TSTR_STR1 ? 'x' : '_',
245 r8 & SH3_TSTR_STR2 ? 'x' : '_'));
246
247 #define CHANNEL_DUMP(a, x) \
248 tmu_channel_dump(x, SH##a##_TCOR##x, \
249 SH##a##_TCNT##x, \
250 SH##a##_TCR##x##)
251 CHANNEL_DUMP(3, 0);
252 CHANNEL_DUMP(3, 1);
253 CHANNEL_DUMP(3, 2);
254 #undef CHANNEL_DUMP
255 DPRINTF((TEXT("\n")));
256 }
257
258 void
tmu_channel_dump(int unit,paddr_t tcor,paddr_t tcnt,paddr_t tcr)259 SH3dev::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt,
260 paddr_t tcr)
261 {
262 uint32_t r32;
263 uint16_t r16;
264
265 DPRINTF((TEXT("TMU#%d:"), unit));
266 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SH3_TCR_##m, #m)
267 /* TCR*/
268 r16 = _reg_read_2(tcr);
269 DBG_BIT_PRINT(r16, UNF);
270 DBG_BIT_PRINT(r16, UNIE);
271 DBG_BIT_PRINT(r16, CKEG1);
272 DBG_BIT_PRINT(r16, CKEG0);
273 DBG_BIT_PRINT(r16, TPSC2);
274 DBG_BIT_PRINT(r16, TPSC1);
275 DBG_BIT_PRINT(r16, TPSC0);
276 /* channel 2 has input capture. */
277 if (unit == 2) {
278 DBG_BIT_PRINT(r16, ICPF);
279 DBG_BIT_PRINT(r16, ICPE1);
280 DBG_BIT_PRINT(r16, ICPE0);
281 }
282 #undef DBG_BIT_PRINT
283 /* TCNT0 timer counter */
284 r32 = _reg_read_4(tcnt);
285 DPRINTF((TEXT("\ncnt=0x%08x"), r32));
286 /* TCOR0 timer constant register */
287 r32 = _reg_read_4(tcor);
288 DPRINTF((TEXT(" constant=0x%04x"), r32));
289
290 if (unit == 2)
291 DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2));
292 else
293 DPRINTF((TEXT("\n")));
294 }
295
296 void
hd64461_dump(platid_t & platform)297 SH3dev::hd64461_dump(platid_t &platform)
298 {
299 uint16_t r16;
300 uint8_t r8;
301
302 #define MATCH(p) \
303 platid_match(&platform, &platid_mask_MACH_##p)
304
305 DPRINTF((TEXT("<<<HD64461>>>\n")));
306 if (!MATCH(HP_LX) &&
307 !MATCH(HP_JORNADA_6XX) &&
308 !MATCH(HITACHI_PERSONA_HPW230JC)) {
309 DPRINTF((TEXT("don't exist.")));
310 return;
311 }
312
313 #if 0
314 DPRINTF((TEXT("frame buffer test start\n")));
315 uint8_t *fb = reinterpret_cast<uint8_t *>(HD64461_FBBASE);
316
317 for (int i = 0; i < 320 * 240 * 2 / 8; i++)
318 *fb++ = 0xff;
319 DPRINTF((TEXT("frame buffer test end\n")));
320 #endif
321 // System
322 DPRINTF((TEXT("STBCR (System Control Register)\n")));
323 r16 = _reg_read_2(HD64461_SYSSTBCR_REG16);
324 bitdisp(r16);
325 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m)
326 DBG_BIT_PRINT(r16, CKIO_STBY);
327 DBG_BIT_PRINT(r16, SAFECKE_IST);
328 DBG_BIT_PRINT(r16, SLCKE_IST);
329 DBG_BIT_PRINT(r16, SAFECKE_OST);
330 DBG_BIT_PRINT(r16, SLCKE_OST);
331 DBG_BIT_PRINT(r16, SMIAST);
332 DBG_BIT_PRINT(r16, SLCDST);
333 DBG_BIT_PRINT(r16, SPC0ST);
334 DBG_BIT_PRINT(r16, SPC1ST);
335 DBG_BIT_PRINT(r16, SAFEST);
336 DBG_BIT_PRINT(r16, STM0ST);
337 DBG_BIT_PRINT(r16, STM1ST);
338 DBG_BIT_PRINT(r16, SIRST);
339 DBG_BIT_PRINT(r16, SURTSD);
340 #undef DBG_BIT_PRINT
341 DPRINTF((TEXT("\n")));
342
343 DPRINTF((TEXT("SYSCR (System Configuration Register)\n")));
344 r16 = _reg_read_2(HD64461_SYSSYSCR_REG16);
345 bitdisp(r16);
346 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m)
347 DBG_BIT_PRINT(r16, SCPU_BUS_IGAT);
348 DBG_BIT_PRINT(r16, SPTA_IR);
349 DBG_BIT_PRINT(r16, SPTA_TM);
350 DBG_BIT_PRINT(r16, SPTB_UR);
351 DBG_BIT_PRINT(r16, WAIT_CTL_SEL);
352 DBG_BIT_PRINT(r16, SMODE1);
353 DBG_BIT_PRINT(r16, SMODE0);
354 #undef DBG_BIT_PRINT
355 DPRINTF((TEXT("\n")));
356
357 DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n")));
358 r16 = _reg_read_2(HD64461_SYSSCPUCR_REG16);
359 bitdisp(r16);
360 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m)
361 DBG_BIT_PRINT(r16, SPDSTOF);
362 DBG_BIT_PRINT(r16, SPDSTIG);
363 DBG_BIT_PRINT(r16, SPCSTOF);
364 DBG_BIT_PRINT(r16, SPCSTIG);
365 DBG_BIT_PRINT(r16, SPBSTOF);
366 DBG_BIT_PRINT(r16, SPBSTIG);
367 DBG_BIT_PRINT(r16, SPASTOF);
368 DBG_BIT_PRINT(r16, SPASTIG);
369 DBG_BIT_PRINT(r16, SLCDSTIG);
370 DBG_BIT_PRINT(r16, SCPU_CS56_EP);
371 DBG_BIT_PRINT(r16, SCPU_CMD_EP);
372 DBG_BIT_PRINT(r16, SCPU_ADDR_EP);
373 DBG_BIT_PRINT(r16, SCPDPU);
374 DBG_BIT_PRINT(r16, SCPU_A2319_EP);
375 #undef DBG_BIT_PRINT
376 DPRINTF((TEXT("\n")));
377
378 DPRINTF((TEXT("\n")));
379
380 // INTC
381 DPRINTF((TEXT("NIRR (Interrupt Request Register)\n")));
382 r16 = _reg_read_2(HD64461_INTCNIRR_REG16);
383 bitdisp(r16);
384 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m)
385 DBG_BIT_PRINT(r16, PCC0R);
386 DBG_BIT_PRINT(r16, PCC1R);
387 DBG_BIT_PRINT(r16, AFER);
388 DBG_BIT_PRINT(r16, GPIOR);
389 DBG_BIT_PRINT(r16, TMU0R);
390 DBG_BIT_PRINT(r16, TMU1R);
391 DBG_BIT_PRINT(r16, IRDAR);
392 DBG_BIT_PRINT(r16, UARTR);
393 #undef DBG_BIT_PRINT
394 DPRINTF((TEXT("\n")));
395
396 DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n")));
397 r16 = _reg_read_2(HD64461_INTCNIMR_REG16);
398 bitdisp(r16);
399 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m)
400 DBG_BIT_PRINT(r16, PCC0M);
401 DBG_BIT_PRINT(r16, PCC1M);
402 DBG_BIT_PRINT(r16, AFEM);
403 DBG_BIT_PRINT(r16, GPIOM);
404 DBG_BIT_PRINT(r16, TMU0M);
405 DBG_BIT_PRINT(r16, TMU1M);
406 DBG_BIT_PRINT(r16, IRDAM);
407 DBG_BIT_PRINT(r16, UARTM);
408 #undef DBG_BIT_PRINT
409 DPRINTF((TEXT("\n")));
410
411 DPRINTF((TEXT("\n")));
412
413 // PCMCIA
414 // PCC0
415 DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n")));
416 DPRINTF((TEXT("PCC0 Interface Status Register\n")));
417 r8 = _reg_read_1(HD64461_PCC0ISR_REG8);
418 bitdisp(r8);
419 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m)
420 DBG_BIT_PRINT(r8, P0READY);
421 DBG_BIT_PRINT(r8, P0MWP);
422 DBG_BIT_PRINT(r8, P0VS2);
423 DBG_BIT_PRINT(r8, P0VS1);
424 DBG_BIT_PRINT(r8, P0CD2);
425 DBG_BIT_PRINT(r8, P0CD1);
426 DBG_BIT_PRINT(r8, P0BVD2);
427 DBG_BIT_PRINT(r8, P0BVD1);
428 #undef DBG_BIT_PRINT
429 DPRINTF((TEXT("\n")));
430
431 DPRINTF((TEXT("PCC0 General Control Register\n")));
432 r8 = _reg_read_1(HD64461_PCC0GCR_REG8);
433 bitdisp(r8);
434 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m)
435 DBG_BIT_PRINT(r8, P0DRVE);
436 DBG_BIT_PRINT(r8, P0PCCR);
437 DBG_BIT_PRINT(r8, P0PCCT);
438 DBG_BIT_PRINT(r8, P0VCC0);
439 DBG_BIT_PRINT(r8, P0MMOD);
440 DBG_BIT_PRINT(r8, P0PA25);
441 DBG_BIT_PRINT(r8, P0PA24);
442 DBG_BIT_PRINT(r8, P0REG);
443 #undef DBG_BIT_PRINT
444 DPRINTF((TEXT("\n")));
445
446 DPRINTF((TEXT("PCC0 Card Status Change Register\n")));
447 r8 = _reg_read_1(HD64461_PCC0CSCR_REG8);
448 bitdisp(r8);
449 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m)
450 DBG_BIT_PRINT(r8, P0SCDI);
451 DBG_BIT_PRINT(r8, P0IREQ);
452 DBG_BIT_PRINT(r8, P0SC);
453 DBG_BIT_PRINT(r8, P0CDC);
454 DBG_BIT_PRINT(r8, P0RC);
455 DBG_BIT_PRINT(r8, P0BW);
456 DBG_BIT_PRINT(r8, P0BD);
457 #undef DBG_BIT_PRINT
458 DPRINTF((TEXT("\n")));
459
460 DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n")));
461 r8 = _reg_read_1(HD64461_PCC0CSCIER_REG8);
462 bitdisp(r8);
463 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m)
464 DBG_BIT_PRINT(r8, P0CRE);
465 DBG_BIT_PRINT(r8, P0SCE);
466 DBG_BIT_PRINT(r8, P0CDE);
467 DBG_BIT_PRINT(r8, P0RE);
468 DBG_BIT_PRINT(r8, P0BWE);
469 DBG_BIT_PRINT(r8, P0BDE);
470 #undef DBG_BIT_PRINT
471 DPRINTF((TEXT("\ninterrupt type: ")));
472 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) {
473 case HD64461_PCC0CSCIER_P0IREQE_NONE:
474 DPRINTF((TEXT("none\n")));
475 break;
476 case HD64461_PCC0CSCIER_P0IREQE_LEVEL:
477 DPRINTF((TEXT("level\n")));
478 break;
479 case HD64461_PCC0CSCIER_P0IREQE_FEDGE:
480 DPRINTF((TEXT("falling edge\n")));
481 break;
482 case HD64461_PCC0CSCIER_P0IREQE_REDGE:
483 DPRINTF((TEXT("rising edge\n")));
484 break;
485 }
486
487 DPRINTF((TEXT("PCC0 Software Control Register\n")));
488 r8 = _reg_read_1(HD64461_PCC0SCR_REG8);
489 bitdisp(r8);
490 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m)
491 DBG_BIT_PRINT(r8, P0VCC1);
492 DBG_BIT_PRINT(r8, P0SWP);
493 #undef DBG_BIT_PRINT
494 DPRINTF((TEXT("\n")));
495
496 // PCC1
497 DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n")));
498 DPRINTF((TEXT("PCC1 Interface Status Register\n")));
499 r8 = _reg_read_1(HD64461_PCC1ISR_REG8);
500 bitdisp(r8);
501 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m)
502 DBG_BIT_PRINT(r8, P1READY);
503 DBG_BIT_PRINT(r8, P1MWP);
504 DBG_BIT_PRINT(r8, P1VS2);
505 DBG_BIT_PRINT(r8, P1VS1);
506 DBG_BIT_PRINT(r8, P1CD2);
507 DBG_BIT_PRINT(r8, P1CD1);
508 DBG_BIT_PRINT(r8, P1BVD2);
509 DBG_BIT_PRINT(r8, P1BVD1);
510 #undef DBG_BIT_PRINT
511 DPRINTF((TEXT("\n")));
512
513 DPRINTF((TEXT("PCC1 General Contorol Register\n")));
514 r8 = _reg_read_1(HD64461_PCC1GCR_REG8);
515 bitdisp(r8);
516 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m)
517 DBG_BIT_PRINT(r8, P1DRVE);
518 DBG_BIT_PRINT(r8, P1PCCR);
519 DBG_BIT_PRINT(r8, P1VCC0);
520 DBG_BIT_PRINT(r8, P1MMOD);
521 DBG_BIT_PRINT(r8, P1PA25);
522 DBG_BIT_PRINT(r8, P1PA24);
523 DBG_BIT_PRINT(r8, P1REG);
524 #undef DBG_BIT_PRINT
525 DPRINTF((TEXT("\n")));
526
527 DPRINTF((TEXT("PCC1 Card Status Change Register\n")));
528 r8 = _reg_read_1(HD64461_PCC1CSCR_REG8);
529 bitdisp(r8);
530 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m)
531 DBG_BIT_PRINT(r8, P1SCDI);
532 DBG_BIT_PRINT(r8, P1CDC);
533 DBG_BIT_PRINT(r8, P1RC);
534 DBG_BIT_PRINT(r8, P1BW);
535 DBG_BIT_PRINT(r8, P1BD);
536 #undef DBG_BIT_PRINT
537 DPRINTF((TEXT("\n")));
538
539 DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n")));
540 r8 = _reg_read_1(HD64461_PCC1CSCIER_REG8);
541 bitdisp(r8);
542 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m)
543 DBG_BIT_PRINT(r8, P1CRE);
544 DBG_BIT_PRINT(r8, P1CDE);
545 DBG_BIT_PRINT(r8, P1RE);
546 DBG_BIT_PRINT(r8, P1BWE);
547 DBG_BIT_PRINT(r8, P1BDE);
548 #undef DBG_BIT_PRINT
549 DPRINTF((TEXT("\n")));
550
551 DPRINTF((TEXT("PCC1 Software Control Register\n")));
552 r8 = _reg_read_1(HD64461_PCC1SCR_REG8);
553 bitdisp(r8);
554 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m)
555 DBG_BIT_PRINT(r8, P1VCC1);
556 DBG_BIT_PRINT(r8, P1SWP);
557 #undef DBG_BIT_PRINT
558 DPRINTF((TEXT("\n")));
559
560 // General Control
561 DPRINTF((TEXT("[General Control]\n")));
562 DPRINTF((TEXT("PCC0 Output pins Control Register\n")));
563 r8 = _reg_read_1(HD64461_PCCP0OCR_REG8);
564 bitdisp(r8);
565 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m)
566 DBG_BIT_PRINT(r8, P0DEPLUP);
567 DBG_BIT_PRINT(r8, P0AEPLUP);
568 #undef DBG_BIT_PRINT
569 DPRINTF((TEXT("\n")));
570
571 DPRINTF((TEXT("PCC1 Output pins Control Register\n")));
572 r8 = _reg_read_1(HD64461_PCCP1OCR_REG8);
573 bitdisp(r8);
574 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m)
575 DBG_BIT_PRINT(r8, P1RST8MA);
576 DBG_BIT_PRINT(r8, P1RST4MA);
577 DBG_BIT_PRINT(r8, P1RAS8MA);
578 DBG_BIT_PRINT(r8, P1RAS4MA);
579 #undef DBG_BIT_PRINT
580 DPRINTF((TEXT("\n")));
581
582 DPRINTF((TEXT("PC Card General Control Register\n")));
583 r8 = _reg_read_1(HD64461_PCCPGCR_REG8);
584 bitdisp(r8);
585 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m)
586 DBG_BIT_PRINT(r8, PSSDIR);
587 DBG_BIT_PRINT(r8, PSSRDWR);
588 #undef DBG_BIT_PRINT
589 DPRINTF((TEXT("\n")));
590
591 // GPIO
592 #define GPIO_DUMP(x) \
593 bitdisp(_reg_read_2(HD64461_GPA##x##R_REG16)); \
594 bitdisp(_reg_read_2(HD64461_GPB##x##R_REG16)); \
595 bitdisp(_reg_read_2(HD64461_GPC##x##R_REG16)); \
596 bitdisp(_reg_read_2(HD64461_GPD##x##R_REG16))
597
598 DPRINTF((TEXT("GPIO Port Control Register\n")));
599 GPIO_DUMP(C);
600 DPRINTF((TEXT("GPIO Port Data Register\n")));
601 GPIO_DUMP(D);
602 DPRINTF((TEXT("GPIO Port Interrupt Control Register\n")));
603 GPIO_DUMP(IC);
604 DPRINTF((TEXT("GPIO Port Interrupt Status Register\n")));
605 GPIO_DUMP(IS);
606 }
607
608 #ifdef SH7709TEST
609 uint32_t sh7707_fb_dma_addr;
610 uint16_t val;
611 int s;
612
613 s = suspendIntr();
614 VOLATILE_REF16(SH7707_LCDAR) = SH7707_LCDAR_LCDDMR0;
615 val = VOLATILE_REF16(SH7707_LCDDMR);
616 sh7707_fb_dma_addr = val;
617 VOLATILE_REF16(SH7707_LCDAR) = SH7707_LCDAR_LCDDMR1;
618 val = VOLATILE_REF16(SH7707_LCDDMR);
619 sh7707_fb_dma_addr |= (val << 16);
620 resumeIntr(s);
621
622 DPRINTF((TEXT("SH7707 frame buffer DMA address: 0x%08x\n"),
623 sh7707_fb_dma_addr));
624 #endif
625