1 /*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
31 * from: i386/isa sio.c,v 1.234
32 */
33
34 #include "opt_compat.h"
35 #include "opt_gdb.h"
36 #include "opt_kdb.h"
37 #include "opt_sio.h"
38
39 /*
40 * Serial driver, based on 386BSD-0.1 com driver.
41 * Mostly rewritten to use pseudo-DMA.
42 * Works for National Semiconductor NS8250-NS16550AF UARTs.
43 * COM driver, based on HP dca driver.
44 *
45 * Changes for PC Card integration:
46 * - Added PC Card driver table and handlers
47 */
48 /*===============================================================
49 * 386BSD(98),FreeBSD-1.1x(98) com driver.
50 * -----
51 * modified for PC9801 by M.Ishii
52 * Kyoto University Microcomputer Club (KMC)
53 * Chou "TEFUTEFU" Hirotomi
54 * Kyoto Univ. the faculty of medicine
55 *===============================================================
56 * FreeBSD-2.0.1(98) sio driver.
57 * -----
58 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
59 * T.Koike(hfc01340@niftyserve.or.jp)
60 * implement kernel device configuration
61 * aizu@orient.center.nitech.ac.jp
62 *
63 * Notes.
64 * -----
65 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
66 * functions.
67 * This driver is under debugging,has bugs.
68 */
69 /*
70 * modified for AIWA B98-01
71 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
72 */
73 /*
74 * Modified by Y.Takahashi of Kogakuin University.
75 */
76 /*
77 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
78 */
79
80 #include <sys/param.h>
81 #include <sys/systm.h>
82 #include <sys/bus.h>
83 #include <sys/conf.h>
84 #include <sys/fcntl.h>
85 #include <sys/interrupt.h>
86 #include <sys/kdb.h>
87 #include <sys/kernel.h>
88 #include <sys/limits.h>
89 #include <sys/lock.h>
90 #include <sys/malloc.h>
91 #include <sys/module.h>
92 #include <sys/mutex.h>
93 #include <sys/proc.h>
94 #include <sys/reboot.h>
95 #include <sys/serial.h>
96 #include <sys/sysctl.h>
97 #include <sys/syslog.h>
98 #include <sys/tty.h>
99 #include <machine/bus.h>
100 #include <sys/rman.h>
101 #include <sys/timepps.h>
102 #include <sys/uio.h>
103 #include <sys/cons.h>
104
105 #include <isa/isavar.h>
106
107 #include <machine/resource.h>
108
109 #include <dev/sio/sioreg.h>
110 #include <dev/sio/siovar.h>
111
112 #ifdef PC98
113 #include <pc98/cbus/cbus.h>
114 #include <pc98/pc98/pc98_machdep.h>
115 #endif
116
117 #ifdef COM_ESP
118 #include <dev/ic/esp.h>
119 #endif
120 #include <dev/ic/ns16550.h>
121 #ifdef PC98
122 #include <dev/ic/i8251.h>
123 #include <dev/ic/i8255.h>
124 #include <dev/ic/rsa.h>
125 #endif
126
127 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
128
129 /*
130 * Meaning of flags:
131 *
132 * 0x00000001 shared IRQs
133 * 0x00000002 disable FIFO
134 * 0x00000008 recover sooner from lost output interrupts
135 * 0x00000010 device is potential system console
136 * 0x00000020 device is forced to become system console
137 * 0x00000040 device is reserved for low-level IO
138 * 0x00000080 use this port for remote kernel debugging
139 * 0x0000??00 minor number of master port
140 * 0x00010000 PPS timestamping on CTS instead of DCD
141 * 0x00080000 IIR_TXRDY bug
142 * 0x00400000 If no comconsole found then mark as a comconsole
143 * 0x1?000000 interface type
144 */
145
146 #ifdef COM_MULTIPORT
147 /* checks in flags for multiport and which is multiport "master chip"
148 * for a given card
149 */
150 #define COM_ISMULTIPORT(flags) ((flags) & 0x01)
151 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
152 #ifndef PC98
153 #define COM_NOTAST4(flags) ((flags) & 0x04)
154 #endif
155 #else
156 #define COM_ISMULTIPORT(flags) (0)
157 #endif /* COM_MULTIPORT */
158
159 #define COM_C_IIR_TXRDYBUG 0x80000
160 #define COM_CONSOLE(flags) ((flags) & 0x10)
161 #define COM_DEBUGGER(flags) ((flags) & 0x80)
162 #ifndef PC98
163 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
164 #endif
165 #define COM_FORCECONSOLE(flags) ((flags) & 0x20)
166 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
167 #define COM_LLCONSOLE(flags) ((flags) & 0x40)
168 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
169 #define COM_NOFIFO(flags) ((flags) & 0x02)
170 #ifndef PC98
171 #define COM_NOSCR(flags) ((flags) & 0x100000)
172 #endif
173 #define COM_PPSCTS(flags) ((flags) & 0x10000)
174 #ifndef PC98
175 #define COM_ST16650A(flags) ((flags) & 0x20000)
176 #define COM_TI16754(flags) ((flags) & 0x200000)
177 #endif
178
179 #define sio_getreg(com, off) \
180 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
181 #define sio_setreg(com, off, value) \
182 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
183
184 /*
185 * com state bits.
186 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
187 * than the other bits so that they can be tested as a group without masking
188 * off the low bits.
189 *
190 * The following com and tty flags correspond closely:
191 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
192 * comstop())
193 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
194 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
195 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
196 * TS_FLUSH is not used.
197 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
198 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
199 */
200 #define CS_BUSY 0x80 /* output in progress */
201 #define CS_TTGO 0x40 /* output not stopped by XOFF */
202 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
203 #define CS_CHECKMSR 1 /* check of MSR scheduled */
204 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
205 #define CS_ODONE 4 /* output completed */
206 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
207 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
208
209 static char const * const error_desc[] = {
210 #define CE_OVERRUN 0
211 "silo overflow",
212 #define CE_INTERRUPT_BUF_OVERFLOW 1
213 "interrupt-level buffer overflow",
214 #define CE_TTY_BUF_OVERFLOW 2
215 "tty-level buffer overflow",
216 };
217
218 #define CE_NTYPES 3
219 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
220
221 /* types. XXX - should be elsewhere */
222 typedef u_int Port_t; /* hardware port */
223 typedef u_char bool_t; /* boolean */
224
225 /* queue of linear buffers */
226 struct lbq {
227 u_char *l_head; /* next char to process */
228 u_char *l_tail; /* one past the last char to process */
229 struct lbq *l_next; /* next in queue */
230 bool_t l_queued; /* nonzero if queued */
231 };
232
233 /* com device structure */
234 struct com_s {
235 u_char state; /* miscellaneous flag bits */
236 u_char cfcr_image; /* copy of value written to CFCR */
237 #ifdef COM_ESP
238 bool_t esp; /* is this unit a hayes esp board? */
239 #endif
240 u_char extra_state; /* more flag bits, separate for order trick */
241 u_char fifo_image; /* copy of value written to FIFO */
242 bool_t hasfifo; /* nonzero for 16550 UARTs */
243 bool_t loses_outints; /* nonzero if device loses output interrupts */
244 u_char mcr_image; /* copy of value written to MCR */
245 #ifdef COM_MULTIPORT
246 bool_t multiport; /* is this unit part of a multiport device? */
247 #endif /* COM_MULTIPORT */
248 bool_t no_irq; /* nonzero if irq is not attached */
249 bool_t gone; /* hardware disappeared */
250 bool_t poll; /* nonzero if polling is required */
251 bool_t poll_output; /* nonzero if polling for output is required */
252 bool_t st16650a; /* nonzero if Startech 16650A compatible */
253 int unit; /* unit number */
254 u_int flags; /* copy of device flags */
255 u_int tx_fifo_size;
256
257 /*
258 * The high level of the driver never reads status registers directly
259 * because there would be too many side effects to handle conveniently.
260 * Instead, it reads copies of the registers stored here by the
261 * interrupt handler.
262 */
263 u_char last_modem_status; /* last MSR read by intr handler */
264 u_char prev_modem_status; /* last MSR handled by high level */
265
266 u_char *ibuf; /* start of input buffer */
267 u_char *ibufend; /* end of input buffer */
268 u_char *ibufold; /* old input buffer, to be freed */
269 u_char *ihighwater; /* threshold in input buffer */
270 u_char *iptr; /* next free spot in input buffer */
271 int ibufsize; /* size of ibuf (not include error bytes) */
272 int ierroff; /* offset of error bytes in ibuf */
273
274 struct lbq obufq; /* head of queue of output buffers */
275 struct lbq obufs[2]; /* output buffers */
276
277 bus_space_tag_t bst;
278 bus_space_handle_t bsh;
279
280 #ifdef PC98
281 Port_t cmd_port;
282 Port_t sts_port;
283 Port_t in_modem_port;
284 Port_t intr_ctrl_port;
285 Port_t rsabase; /* Iobase address of an I/O-DATA RSA board. */
286 int intr_enable;
287 int pc98_prev_modem_status;
288 int pc98_modem_delta;
289 int modem_car_chg_timer;
290 int pc98_prev_siocmd;
291 int pc98_prev_siomod;
292 int modem_checking;
293 int pc98_if_type;
294
295 bool_t pc98_8251fifo;
296 bool_t pc98_8251fifo_enable;
297 #endif /* PC98 */
298 Port_t data_port; /* i/o ports */
299 #ifdef COM_ESP
300 Port_t esp_port;
301 #endif
302 Port_t int_ctl_port;
303 Port_t int_id_port;
304 Port_t modem_ctl_port;
305 Port_t line_status_port;
306 Port_t modem_status_port;
307
308 struct tty *tp; /* cross reference */
309
310 struct pps_state pps;
311 int pps_bit;
312 #ifdef KDB
313 int alt_brk_state;
314 #endif
315
316 u_long bytes_in; /* statistics */
317 u_long bytes_out;
318 u_int delta_error_counts[CE_NTYPES];
319 u_long error_counts[CE_NTYPES];
320
321 u_long rclk;
322
323 struct resource *irqres;
324 struct resource *ioportres;
325 int ioportrid;
326 void *cookie;
327
328 /*
329 * Data area for output buffers. Someday we should build the output
330 * buffer queue without copying data.
331 */
332 #ifdef PC98
333 int obufsize;
334 u_char *obuf1;
335 u_char *obuf2;
336 #else
337 u_char obuf1[256];
338 u_char obuf2[256];
339 #endif
340 };
341
342 #ifdef COM_ESP
343 static int espattach(struct com_s *com, Port_t esp_port);
344 #endif
345
346 static void combreak(struct tty *tp, int sig);
347 static timeout_t siobusycheck;
348 static u_int siodivisor(u_long rclk, speed_t speed);
349 static void comclose(struct tty *tp);
350 static int comopen(struct tty *tp, struct cdev *dev);
351 static void sioinput(struct com_s *com);
352 static void siointr1(struct com_s *com);
353 static int siointr(void *arg);
354 static int commodem(struct tty *tp, int sigon, int sigoff);
355 static int comparam(struct tty *tp, struct termios *t);
356 static void siopoll(void *);
357 static void siosettimeout(void);
358 static int siosetwater(struct com_s *com, speed_t speed);
359 static void comstart(struct tty *tp);
360 static void comstop(struct tty *tp, int rw);
361 static timeout_t comwakeup;
362
363 char sio_driver_name[] = "sio";
364 static struct mtx sio_lock;
365 static int sio_inited;
366
367 /* table and macro for fast conversion from a unit number to its com struct */
368 devclass_t sio_devclass;
369 #define com_addr(unit) ((struct com_s *) \
370 devclass_get_softc(sio_devclass, unit)) /* XXX */
371
372 int comconsole = -1;
373 static volatile speed_t comdefaultrate = CONSPEED;
374 static u_long comdefaultrclk = DEFAULT_RCLK;
375 SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
376 static speed_t gdbdefaultrate = GDBSPEED;
377 SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW,
378 &gdbdefaultrate, GDBSPEED, "");
379 static u_int com_events; /* input chars + weighted output completions */
380 static Port_t siocniobase;
381 static int siocnunit = -1;
382 static void *sio_slow_ih;
383 static void *sio_fast_ih;
384 static int sio_timeout;
385 static int sio_timeouts_until_log;
386 static struct callout_handle sio_timeout_handle
387 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
388 static int sio_numunits;
389
390 #ifdef PC98
391 struct siodev {
392 short if_type;
393 short irq;
394 Port_t cmd, sts, ctrl, mod;
395 };
396 static int sysclock;
397
398 #define COM_INT_DISABLE {int previpri; previpri=spltty();
399 #define COM_INT_ENABLE splx(previpri);}
400 #define IEN_TxFLAG IEN_Tx
401
402 #define COM_CARRIER_DETECT_EMULATE 0
403 #define PC98_CHECK_MODEM_INTERVAL (hz/10)
404 #define DCD_OFF_TOLERANCE 2
405 #define DCD_ON_RECOGNITION 2
406 #define IS_8251(if_type) (!(if_type & 0x10))
407 #define COM1_EXT_CLOCK 0x40000
408
409 static void commint(struct cdev *dev);
410 static void com_tiocm_bis(struct com_s *com, int msr);
411 static void com_tiocm_bic(struct com_s *com, int msr);
412 static int com_tiocm_get(struct com_s *com);
413 static int com_tiocm_get_delta(struct com_s *com);
414 static void pc98_msrint_start(struct cdev *dev);
415 static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed);
416 static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor);
417 static int pc98_get_modem_status(struct com_s *com);
418 static timeout_t pc98_check_msr;
419 static void pc98_set_baud_rate(struct com_s *com, u_int count);
420 static void pc98_i8251_reset(struct com_s *com, int mode, int command);
421 static void pc98_disable_i8251_interrupt(struct com_s *com, int mod);
422 static void pc98_enable_i8251_interrupt(struct com_s *com, int mod);
423 static int pc98_check_i8251_interrupt(struct com_s *com);
424 static int pc98_i8251_get_cmd(struct com_s *com);
425 static int pc98_i8251_get_mod(struct com_s *com);
426 static void pc98_i8251_set_cmd(struct com_s *com, int x);
427 static void pc98_i8251_or_cmd(struct com_s *com, int x);
428 static void pc98_i8251_clear_cmd(struct com_s *com, int x);
429 static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x);
430 static int pc98_check_if_type(device_t dev, struct siodev *iod);
431 static int pc98_check_8251vfast(void);
432 static int pc98_check_8251fifo(void);
433 static void pc98_check_sysclock(void);
434 static void pc98_set_ioport(struct com_s *com);
435
436 #define com_int_Tx_disable(com) \
437 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
438 #define com_int_Tx_enable(com) \
439 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
440 #define com_int_Rx_disable(com) \
441 pc98_disable_i8251_interrupt(com,IEN_Rx)
442 #define com_int_Rx_enable(com) \
443 pc98_enable_i8251_interrupt(com,IEN_Rx)
444 #define com_int_TxRx_disable(com) \
445 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
446 #define com_int_TxRx_enable(com) \
447 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
448 #define com_send_break_on(com) \
449 (IS_8251((com)->pc98_if_type) ? \
450 pc98_i8251_or_cmd((com), CMD8251_SBRK) : \
451 sio_setreg((com), com_cfcr, (com)->cfcr_image |= CFCR_SBREAK))
452 #define com_send_break_off(com) \
453 (IS_8251((com)->pc98_if_type) ? \
454 pc98_i8251_clear_cmd((com), CMD8251_SBRK) : \
455 sio_setreg((com), com_cfcr, (com)->cfcr_image &= ~CFCR_SBREAK))
456
457 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
458 { 0, 0, },
459 { 50, 50, },
460 { 75, 75, },
461 { 150, 150, },
462 { 200, 200, },
463 { 300, 300, },
464 { 600, 600, },
465 { 1200, 1200, },
466 { 2400, 2400, },
467 { 4800, 4800, },
468 { 9600, 9600, },
469 { 19200, 19200, },
470 { 38400, 38400, },
471 { 51200, 51200, },
472 { 76800, 76800, },
473 { 20800, 20800, },
474 { 31200, 31200, },
475 { 41600, 41600, },
476 { 62400, 62400, },
477 { -1, -1 }
478 };
479 static struct speedtab pc98fast_speedtab[] = {
480 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), },
481 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), },
482 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), },
483 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), },
484 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), },
485 { -1, -1 }
486 };
487 static struct speedtab comspeedtab_pio9032b[] = {
488 { 300, 6, },
489 { 600, 5, },
490 { 1200, 4, },
491 { 2400, 3, },
492 { 4800, 2, },
493 { 9600, 1, },
494 { 19200, 0, },
495 { 38400, 7, },
496 { -1, -1 }
497 };
498 static struct speedtab comspeedtab_b98_01[] = {
499 { 75, 11, },
500 { 150, 10, },
501 { 300, 9, },
502 { 600, 8, },
503 { 1200, 7, },
504 { 2400, 6, },
505 { 4800, 5, },
506 { 9600, 4, },
507 { 19200, 3, },
508 { 38400, 2, },
509 { 76800, 1, },
510 { 153600, 0, },
511 { -1, -1 }
512 };
513 static struct speedtab comspeedtab_ind[] = {
514 { 300, 1536, },
515 { 600, 768, },
516 { 1200, 384, },
517 { 2400, 192, },
518 { 4800, 96, },
519 { 9600, 48, },
520 { 19200, 24, },
521 { 38400, 12, },
522 { 57600, 8, },
523 { 115200, 4, },
524 { 153600, 3, },
525 { 230400, 2, },
526 { 460800, 1, },
527 { -1, -1 }
528 };
529
530 struct {
531 char *name;
532 short port_table[7];
533 short irr_mask;
534 struct speedtab *speedtab;
535 short check_irq;
536 } if_8251_type[] = {
537 /* COM_IF_INTERNAL */
538 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
539 -1, pc98speedtab, 1 },
540 /* COM_IF_PC9861K_1 */
541 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
542 3, NULL, 1 },
543 /* COM_IF_PC9861K_2 */
544 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
545 3, NULL, 1 },
546 /* COM_IF_IND_SS_1 */
547 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
548 3, comspeedtab_ind, 1 },
549 /* COM_IF_IND_SS_2 */
550 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
551 3, comspeedtab_ind, 1 },
552 /* COM_IF_PIO9032B_1 */
553 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
554 7, comspeedtab_pio9032b, 1 },
555 /* COM_IF_PIO9032B_2 */
556 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
557 7, comspeedtab_pio9032b, 1 },
558 /* COM_IF_B98_01_1 */
559 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
560 7, comspeedtab_b98_01, 0 },
561 /* COM_IF_B98_01_2 */
562 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
563 7, comspeedtab_b98_01, 0 },
564 };
565 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
566 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
567 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
568 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
569 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
570 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
571 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
572
573 #define I8251F_data 0x130
574 #define I8251F_lsr 0x132
575 #define I8251F_msr 0x134
576 #define I8251F_iir 0x136
577 #define I8251F_fcr 0x138
578 #define I8251F_div 0x13a
579
580
581 static bus_addr_t port_table_0[] =
582 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007};
583 static bus_addr_t port_table_1[] =
584 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e};
585 static bus_addr_t port_table_8[] =
586 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700};
587 static bus_addr_t port_table_rsa[] = {
588 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f,
589 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007
590 };
591
592 struct {
593 char *name;
594 short irr_read;
595 short irr_write;
596 bus_addr_t *iat;
597 bus_size_t iatsz;
598 u_long rclk;
599 } if_16550a_type[] = {
600 /* COM_IF_RSA98 */
601 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
602 /* COM_IF_NS16550 */
603 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
604 /* COM_IF_SECOND_CCU */
605 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
606 /* COM_IF_MC16550II */
607 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE,
608 DEFAULT_RCLK * 4},
609 /* COM_IF_MCRS98 */
610 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4},
611 /* COM_IF_RSB3000 */
612 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10},
613 /* COM_IF_RSB384 */
614 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10},
615 /* COM_IF_MODEM_CARD */
616 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
617 /* COM_IF_RSA98III */
618 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8},
619 /* COM_IF_ESP98 */
620 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4},
621 };
622 #endif /* PC98 */
623
624 #ifdef GDB
625 static Port_t siogdbiobase = 0;
626 #endif
627
628 #ifdef COM_ESP
629 #ifdef PC98
630
631 /* XXX configure this properly. */
632 /* XXX quite broken for new-bus. */
633 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
634 static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
635
636 #define ESP98_CMD1 (ESP_CMD1 * 0x100)
637 #define ESP98_CMD2 (ESP_CMD2 * 0x100)
638 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
639 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
640
641 #else /* PC98 */
642
643 /* XXX configure this properly. */
644 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
645 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
646
647 #endif /* PC98 */
648 #endif
649
650 /*
651 * handle sysctl read/write requests for console speed
652 *
653 * In addition to setting comdefaultrate for I/O through /dev/console,
654 * also set the initial and lock values for the /dev/ttyXX device
655 * if there is one associated with the console. Finally, if the /dev/tty
656 * device has already been open, change the speed on the open running port
657 * itself.
658 */
659
660 static int
sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)661 sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
662 {
663 int error, s;
664 speed_t newspeed;
665 struct com_s *com;
666 struct tty *tp;
667
668 newspeed = comdefaultrate;
669
670 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
671 if (error || !req->newptr)
672 return (error);
673
674 comdefaultrate = newspeed;
675
676 if (comconsole < 0) /* serial console not selected? */
677 return (0);
678
679 com = com_addr(comconsole);
680 if (com == NULL)
681 return (ENXIO);
682
683 tp = com->tp;
684 if (tp == NULL)
685 return (ENXIO);
686
687 /*
688 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
689 * (note, the lock rates really are boolean -- if non-zero, disallow
690 * speed changes)
691 */
692 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed =
693 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed =
694 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed =
695 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate;
696
697 if (tp->t_state & TS_ISOPEN) {
698 tp->t_termios.c_ispeed =
699 tp->t_termios.c_ospeed = comdefaultrate;
700 s = spltty();
701 error = comparam(tp, &tp->t_termios);
702 splx(s);
703 }
704 return error;
705 }
706
707 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
708 0, 0, sysctl_machdep_comdefaultrate, "I", "");
709 TUNABLE_INT("machdep.conspeed", __DEVOLATILE(int *, &comdefaultrate));
710
711 /*
712 * Unload the driver and clear the table.
713 * XXX this is mostly wrong.
714 * XXX TODO:
715 * This is usually called when the card is ejected, but
716 * can be caused by a kldunload of a controller driver.
717 * The idea is to reset the driver's view of the device
718 * and ensure that any driver entry points such as
719 * read and write do not hang.
720 */
721 int
siodetach(device_t dev)722 siodetach(device_t dev)
723 {
724 struct com_s *com;
725
726 com = (struct com_s *) device_get_softc(dev);
727 if (com == NULL) {
728 device_printf(dev, "NULL com in siounload\n");
729 return (0);
730 }
731 com->gone = TRUE;
732 if (com->tp)
733 ttyfree(com->tp);
734 if (com->irqres) {
735 bus_teardown_intr(dev, com->irqres, com->cookie);
736 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
737 }
738 if (com->ioportres)
739 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid,
740 com->ioportres);
741 if (com->ibuf != NULL)
742 free(com->ibuf, M_DEVBUF);
743 #ifdef PC98
744 if (com->obuf1 != NULL)
745 free(com->obuf1, M_DEVBUF);
746 #endif
747
748 device_set_softc(dev, NULL);
749 free(com, M_DEVBUF);
750 return (0);
751 }
752
753 int
sioprobe(dev,xrid,rclk,noprobe)754 sioprobe(dev, xrid, rclk, noprobe)
755 device_t dev;
756 int xrid;
757 u_long rclk;
758 int noprobe;
759 {
760 #if 0
761 static bool_t already_init;
762 device_t xdev;
763 #endif
764 struct com_s *com;
765 u_int divisor;
766 bool_t failures[10];
767 int fn;
768 device_t idev;
769 Port_t iobase;
770 intrmask_t irqmap[4];
771 intrmask_t irqs;
772 u_char mcr_image;
773 int result;
774 u_long xirq;
775 u_int flags = device_get_flags(dev);
776 int rid;
777 struct resource *port;
778 #ifdef PC98
779 int tmp;
780 struct siodev iod;
781 #endif
782
783 #ifdef PC98
784 iod.if_type = GET_IFTYPE(flags);
785 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) &&
786 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2))
787 return ENXIO;
788 #endif
789
790 rid = xrid;
791 #ifdef PC98
792 if (IS_8251(iod.if_type)) {
793 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
794 RF_ACTIVE);
795 } else if (iod.if_type == COM_IF_MODEM_CARD ||
796 iod.if_type == COM_IF_RSA98III ||
797 isa_get_vendorid(dev)) {
798 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
799 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
800 } else {
801 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
802 if_16550a_type[iod.if_type & 0x0f].iat,
803 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
804 }
805 #else
806 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
807 0, ~0, IO_COMSIZE, RF_ACTIVE);
808 #endif
809 if (!port)
810 return (ENXIO);
811 #ifdef PC98
812 if (!IS_8251(iod.if_type)) {
813 if (isa_load_resourcev(port,
814 if_16550a_type[iod.if_type & 0x0f].iat,
815 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) {
816 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
817 return ENXIO;
818 }
819 }
820 #endif
821
822 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO);
823 if (com == NULL) {
824 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
825 return (ENOMEM);
826 }
827 device_set_softc(dev, com);
828 com->bst = rman_get_bustag(port);
829 com->bsh = rman_get_bushandle(port);
830 #ifdef PC98
831 if (!IS_8251(iod.if_type) && rclk == 0)
832 rclk = if_16550a_type[iod.if_type & 0x0f].rclk;
833 #else
834 if (rclk == 0)
835 rclk = DEFAULT_RCLK;
836 #endif
837 com->rclk = rclk;
838
839 while (sio_inited != 2)
840 if (atomic_cmpset_int(&sio_inited, 0, 1)) {
841 mtx_init(&sio_lock, sio_driver_name, NULL,
842 (comconsole != -1) ?
843 MTX_SPIN | MTX_QUIET : MTX_SPIN);
844 atomic_store_rel_int(&sio_inited, 2);
845 }
846
847 #if 0
848 /*
849 * XXX this is broken - when we are first called, there are no
850 * previously configured IO ports. We could hard code
851 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
852 * This code has been doing nothing since the conversion since
853 * "count" is zero the first time around.
854 */
855 if (!already_init) {
856 /*
857 * Turn off MCR_IENABLE for all likely serial ports. An unused
858 * port with its MCR_IENABLE gate open will inhibit interrupts
859 * from any used port that shares the interrupt vector.
860 * XXX the gate enable is elsewhere for some multiports.
861 */
862 device_t *devs;
863 int count, i, xioport;
864 #ifdef PC98
865 int xiftype;
866 #endif
867
868 devclass_get_devices(sio_devclass, &devs, &count);
869 #ifdef PC98
870 for (i = 0; i < count; i++) {
871 xdev = devs[i];
872 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0);
873 xiftype = GET_IFTYPE(device_get_flags(xdev));
874 if (device_is_enabled(xdev) && xioport > 0) {
875 if (IS_8251(xiftype))
876 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2);
877 else
878 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0);
879 }
880 }
881 #else
882 for (i = 0; i < count; i++) {
883 xdev = devs[i];
884 if (device_is_enabled(xdev) &&
885 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
886 NULL) == 0)
887 outb(xioport + com_mcr, 0);
888 }
889 #endif
890 free(devs, M_TEMP);
891 already_init = TRUE;
892 }
893 #endif
894
895 if (COM_LLCONSOLE(flags)) {
896 printf("sio%d: reserved for low-level i/o\n",
897 device_get_unit(dev));
898 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
899 device_set_softc(dev, NULL);
900 free(com, M_DEVBUF);
901 return (ENXIO);
902 }
903
904 #ifdef PC98
905 DELAY(10);
906
907 /*
908 * If the port is i8251 UART (internal, B98_01)
909 */
910 if (pc98_check_if_type(dev, &iod) == -1) {
911 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
912 device_set_softc(dev, NULL);
913 free(com, M_DEVBUF);
914 return (ENXIO);
915 }
916 if (iod.irq > 0)
917 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1);
918 if (IS_8251(iod.if_type)) {
919 outb(iod.cmd, 0);
920 DELAY(10);
921 outb(iod.cmd, 0);
922 DELAY(10);
923 outb(iod.cmd, 0);
924 DELAY(10);
925 outb(iod.cmd, CMD8251_RESET);
926 DELAY(1000); /* for a while...*/
927 outb(iod.cmd, 0xf2); /* MODE (dummy) */
928 DELAY(10);
929 outb(iod.cmd, 0x01); /* CMD (dummy) */
930 DELAY(1000); /* for a while...*/
931 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
932 result = (ENXIO);
933 }
934 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
935 COM_INT_DISABLE
936 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
937 outb( iod.ctrl, tmp|IEN_TxEMP );
938 DELAY(10);
939 result = isa_irq_pending() ? 0 : ENXIO;
940 outb( iod.ctrl, tmp );
941 COM_INT_ENABLE
942 } else {
943 /*
944 * B98_01 doesn't activate TxEMP interrupt line
945 * when being reset, so we can't check irq pending.
946 */
947 result = 0;
948 }
949 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
950 if (result) {
951 device_set_softc(dev, NULL);
952 free(com, M_DEVBUF);
953 }
954 return result;
955 }
956 #endif /* PC98 */
957 /*
958 * If the device is on a multiport card and has an AST/4
959 * compatible interrupt control register, initialize this
960 * register and prepare to leave MCR_IENABLE clear in the mcr.
961 * Otherwise, prepare to set MCR_IENABLE in the mcr.
962 * Point idev to the device struct giving the correct id_irq.
963 * This is the struct for the master device if there is one.
964 */
965 idev = dev;
966 mcr_image = MCR_IENABLE;
967 #ifdef COM_MULTIPORT
968 if (COM_ISMULTIPORT(flags)) {
969 #ifndef PC98
970 Port_t xiobase;
971 u_long io;
972 #endif
973
974 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
975 if (idev == NULL) {
976 printf("sio%d: master device %d not configured\n",
977 device_get_unit(dev), COM_MPMASTER(flags));
978 idev = dev;
979 }
980 #ifndef PC98
981 if (!COM_NOTAST4(flags)) {
982 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
983 NULL) == 0) {
984 xiobase = io;
985 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
986 NULL, NULL) == 0)
987 outb(xiobase + com_scr, 0x80);
988 else
989 outb(xiobase + com_scr, 0);
990 }
991 mcr_image = 0;
992 }
993 #endif
994 }
995 #endif /* COM_MULTIPORT */
996 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
997 mcr_image = 0;
998
999 bzero(failures, sizeof failures);
1000 iobase = rman_get_start(port);
1001
1002 #ifdef PC98
1003 if (iod.if_type == COM_IF_RSA98III) {
1004 mcr_image = 0;
1005
1006 outb(iobase + rsa_msr, 0x04);
1007 outb(iobase + rsa_frr, 0x00);
1008 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) {
1009 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1010 device_set_softc(dev, NULL);
1011 free(com, M_DEVBUF);
1012 return (ENXIO);
1013 }
1014 outb(iobase + rsa_ier, 0x00);
1015 outb(iobase + rsa_frr, 0x00);
1016 outb(iobase + rsa_tivsr, 0x00);
1017 outb(iobase + rsa_tcr, 0x00);
1018 }
1019
1020 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1021 if (tmp != -1) {
1022 /* MC16550II */
1023 int irqout;
1024 switch (isa_get_irq(idev)) {
1025 case 3: irqout = 4; break;
1026 case 5: irqout = 5; break;
1027 case 6: irqout = 6; break;
1028 case 12: irqout = 7; break;
1029 default:
1030 printf("sio%d: irq configuration error\n",
1031 device_get_unit(dev));
1032 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1033 device_set_softc(dev, NULL);
1034 free(com, M_DEVBUF);
1035 return (ENXIO);
1036 }
1037 outb((iobase & 0x00ff) | tmp, irqout);
1038 }
1039 #endif
1040
1041 /*
1042 * We don't want to get actual interrupts, just masked ones.
1043 * Interrupts from this line should already be masked in the ICU,
1044 * but mask them in the processor as well in case there are some
1045 * (misconfigured) shared interrupts.
1046 */
1047 mtx_lock_spin(&sio_lock);
1048 /* EXTRA DELAY? */
1049
1050 /*
1051 * Initialize the speed and the word size and wait long enough to
1052 * drain the maximum of 16 bytes of junk in device output queues.
1053 * The speed is undefined after a master reset and must be set
1054 * before relying on anything related to output. There may be
1055 * junk after a (very fast) soft reboot and (apparently) after
1056 * master reset.
1057 * XXX what about the UART bug avoided by waiting in comparam()?
1058 * We don't want to to wait long enough to drain at 2 bps.
1059 */
1060 if (iobase == siocniobase)
1061 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1062 else {
1063 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1064 divisor = siodivisor(rclk, SIO_TEST_SPEED);
1065 sio_setreg(com, com_dlbl, divisor & 0xff);
1066 sio_setreg(com, com_dlbh, divisor >> 8);
1067 sio_setreg(com, com_cfcr, CFCR_8BITS);
1068 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1069 }
1070
1071 /*
1072 * Enable the interrupt gate and disable device interrupts. This
1073 * should leave the device driving the interrupt line low and
1074 * guarantee an edge trigger if an interrupt can be generated.
1075 */
1076 /* EXTRA DELAY? */
1077 sio_setreg(com, com_mcr, mcr_image);
1078 sio_setreg(com, com_ier, 0);
1079 DELAY(1000); /* XXX */
1080 irqmap[0] = isa_irq_pending();
1081
1082 /*
1083 * Attempt to set loopback mode so that we can send a null byte
1084 * without annoying any external device.
1085 */
1086 /* EXTRA DELAY? */
1087 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
1088
1089 /*
1090 * Attempt to generate an output interrupt. On 8250's, setting
1091 * IER_ETXRDY generates an interrupt independent of the current
1092 * setting and independent of whether the THR is empty. On 16450's,
1093 * setting IER_ETXRDY generates an interrupt independent of the
1094 * current setting. On 16550A's, setting IER_ETXRDY only
1095 * generates an interrupt when IER_ETXRDY is not already set.
1096 */
1097 sio_setreg(com, com_ier, IER_ETXRDY);
1098 #ifdef PC98
1099 if (iod.if_type == COM_IF_RSA98III)
1100 outb(iobase + rsa_ier, 0x04);
1101 #endif
1102
1103 /*
1104 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1105 * an interrupt. They'd better generate one for actually doing
1106 * output. Loopback may be broken on the same incompatibles but
1107 * it's unlikely to do more than allow the null byte out.
1108 */
1109 sio_setreg(com, com_data, 0);
1110 if (iobase == siocniobase)
1111 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10));
1112 else
1113 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1114
1115 /*
1116 * Turn off loopback mode so that the interrupt gate works again
1117 * (MCR_IENABLE was hidden). This should leave the device driving
1118 * an interrupt line high. It doesn't matter if the interrupt
1119 * line oscillates while we are not looking at it, since interrupts
1120 * are disabled.
1121 */
1122 /* EXTRA DELAY? */
1123 sio_setreg(com, com_mcr, mcr_image);
1124
1125 /*
1126 * It seems my Xircom CBEM56G Cardbus modem wants to be reset
1127 * to 8 bits *again*, or else probe test 0 will fail.
1128 * gwk@sgi.com, 4/19/2001
1129 */
1130 sio_setreg(com, com_cfcr, CFCR_8BITS);
1131
1132 /*
1133 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug",
1134 * so we probe for a buggy IIR_TXRDY implementation even in the
1135 * noprobe case. We don't probe for it in the !noprobe case because
1136 * noprobe is always set for PCMCIA cards and the problem is not
1137 * known to affect any other cards.
1138 */
1139 if (noprobe) {
1140 /* Read IIR a few times. */
1141 for (fn = 0; fn < 2; fn ++) {
1142 DELAY(10000);
1143 failures[6] = sio_getreg(com, com_iir);
1144 }
1145
1146 /* IIR_TXRDY should be clear. Is it? */
1147 result = 0;
1148 if (failures[6] & IIR_TXRDY) {
1149 /*
1150 * No. We seem to have the bug. Does our fix for
1151 * it work?
1152 */
1153 sio_setreg(com, com_ier, 0);
1154 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1155 /* Yes. We discovered the TXRDY bug! */
1156 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1157 } else {
1158 /* No. Just fail. XXX */
1159 result = ENXIO;
1160 sio_setreg(com, com_mcr, 0);
1161 }
1162 } else {
1163 /* Yes. No bug. */
1164 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1165 }
1166 sio_setreg(com, com_ier, 0);
1167 sio_setreg(com, com_cfcr, CFCR_8BITS);
1168 mtx_unlock_spin(&sio_lock);
1169 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1170 if (iobase == siocniobase)
1171 result = 0;
1172 if (result != 0) {
1173 device_set_softc(dev, NULL);
1174 free(com, M_DEVBUF);
1175 }
1176 return (result);
1177 }
1178
1179 /*
1180 * Check that
1181 * o the CFCR, IER and MCR in UART hold the values written to them
1182 * (the values happen to be all distinct - this is good for
1183 * avoiding false positive tests from bus echoes).
1184 * o an output interrupt is generated and its vector is correct.
1185 * o the interrupt goes away when the IIR in the UART is read.
1186 */
1187 /* EXTRA DELAY? */
1188 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1189 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1190 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1191 DELAY(10000); /* Some internal modems need this time */
1192 irqmap[1] = isa_irq_pending();
1193 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1194 #ifdef PC98
1195 if (iod.if_type == COM_IF_RSA98III)
1196 inb(iobase + rsa_srr);
1197 #endif
1198 DELAY(1000); /* XXX */
1199 irqmap[2] = isa_irq_pending();
1200 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1201 #ifdef PC98
1202 if (iod.if_type == COM_IF_RSA98III)
1203 inb(iobase + rsa_srr);
1204 #endif
1205
1206 /*
1207 * Turn off all device interrupts and check that they go off properly.
1208 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1209 * the OUT2 output of the UART to
1210 * the ICU input. Closing the gate would give a floating ICU input
1211 * (unless there is another device driving it) and spurious interrupts.
1212 * (On the system that this was first tested on, the input floats high
1213 * and gives a (masked) interrupt as soon as the gate is closed.)
1214 */
1215 sio_setreg(com, com_ier, 0);
1216 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1217 failures[7] = sio_getreg(com, com_ier);
1218 #ifdef PC98
1219 if (iod.if_type == COM_IF_RSA98III)
1220 outb(iobase + rsa_ier, 0x00);
1221 #endif
1222 DELAY(1000); /* XXX */
1223 irqmap[3] = isa_irq_pending();
1224 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1225 #ifdef PC98
1226 if (iod.if_type == COM_IF_RSA98III) {
1227 inb(iobase + rsa_srr);
1228 outb(iobase + rsa_frr, 0x00);
1229 }
1230 #endif
1231
1232 mtx_unlock_spin(&sio_lock);
1233
1234 irqs = irqmap[1] & ~irqmap[0];
1235 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1236 ((1 << xirq) & irqs) == 0) {
1237 printf(
1238 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1239 device_get_unit(dev), xirq, irqs);
1240 printf(
1241 "sio%d: port may not be enabled\n",
1242 device_get_unit(dev));
1243 }
1244 if (bootverbose)
1245 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1246 device_get_unit(dev),
1247 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1248
1249 result = 0;
1250 for (fn = 0; fn < sizeof failures; ++fn)
1251 if (failures[fn]) {
1252 sio_setreg(com, com_mcr, 0);
1253 result = ENXIO;
1254 if (bootverbose) {
1255 printf("sio%d: probe failed test(s):",
1256 device_get_unit(dev));
1257 for (fn = 0; fn < sizeof failures; ++fn)
1258 if (failures[fn])
1259 printf(" %d", fn);
1260 printf("\n");
1261 }
1262 break;
1263 }
1264 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1265 if (iobase == siocniobase)
1266 result = 0;
1267 if (result != 0) {
1268 device_set_softc(dev, NULL);
1269 free(com, M_DEVBUF);
1270 }
1271 return (result);
1272 }
1273
1274 #ifdef COM_ESP
1275 static int
espattach(com,esp_port)1276 espattach(com, esp_port)
1277 struct com_s *com;
1278 Port_t esp_port;
1279 {
1280 u_char dips;
1281 u_char val;
1282
1283 /*
1284 * Check the ESP-specific I/O port to see if we're an ESP
1285 * card. If not, return failure immediately.
1286 */
1287 if ((inb(esp_port) & 0xf3) == 0) {
1288 printf(" port 0x%x is not an ESP board?\n", esp_port);
1289 return (0);
1290 }
1291
1292 /*
1293 * We've got something that claims to be a Hayes ESP card.
1294 * Let's hope so.
1295 */
1296
1297 /* Get the dip-switch configuration */
1298 #ifdef PC98
1299 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1300 dips = inb(esp_port + ESP98_STATUS1);
1301 #else
1302 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1303 dips = inb(esp_port + ESP_STATUS1);
1304 #endif
1305
1306 /*
1307 * Bits 0,1 of dips say which COM port we are.
1308 */
1309 #ifdef PC98
1310 if ((rman_get_start(com->ioportres) & 0xff) ==
1311 likely_com_ports[dips & 0x03])
1312 #else
1313 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1314 #endif
1315 printf(" : ESP");
1316 else {
1317 printf(" esp_port has com %d\n", dips & 0x03);
1318 return (0);
1319 }
1320
1321 /*
1322 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1323 */
1324 #ifdef PC98
1325 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1326 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1327 val = inb(esp_port + ESP98_STATUS2);
1328 #else
1329 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1330 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1331 val = inb(esp_port + ESP_STATUS2);
1332 #endif
1333 if ((val & 0x70) < 0x20) {
1334 printf("-old (%o)", val & 0x70);
1335 return (0);
1336 }
1337
1338 /*
1339 * Check for ability to emulate 16550: bit 7 == 1
1340 */
1341 if ((dips & 0x80) == 0) {
1342 printf(" slave");
1343 return (0);
1344 }
1345
1346 /*
1347 * Okay, we seem to be a Hayes ESP card. Whee.
1348 */
1349 com->esp = TRUE;
1350 com->esp_port = esp_port;
1351 return (1);
1352 }
1353 #endif /* COM_ESP */
1354
1355 int
sioattach(dev,xrid,rclk)1356 sioattach(dev, xrid, rclk)
1357 device_t dev;
1358 int xrid;
1359 u_long rclk;
1360 {
1361 struct com_s *com;
1362 #ifdef COM_ESP
1363 Port_t *espp;
1364 #endif
1365 Port_t iobase;
1366 int unit;
1367 u_int flags;
1368 int rid;
1369 struct resource *port;
1370 int ret;
1371 int error;
1372 struct tty *tp;
1373 #ifdef PC98
1374 u_char *obuf;
1375 u_long obufsize;
1376 int if_type = GET_IFTYPE(device_get_flags(dev));
1377 #endif
1378
1379 rid = xrid;
1380 #ifdef PC98
1381 if (IS_8251(if_type)) {
1382 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1383 RF_ACTIVE);
1384 } else if (if_type == COM_IF_MODEM_CARD ||
1385 if_type == COM_IF_RSA98III ||
1386 isa_get_vendorid(dev)) {
1387 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
1388 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1389 } else {
1390 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1391 if_16550a_type[if_type & 0x0f].iat,
1392 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1393 }
1394 #else
1395 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1396 0, ~0, IO_COMSIZE, RF_ACTIVE);
1397 #endif
1398 if (!port)
1399 return (ENXIO);
1400 #ifdef PC98
1401 if (!IS_8251(if_type)) {
1402 if (isa_load_resourcev(port,
1403 if_16550a_type[if_type & 0x0f].iat,
1404 if_16550a_type[if_type & 0x0f].iatsz) != 0) {
1405 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1406 return ENXIO;
1407 }
1408 }
1409 #endif
1410
1411 iobase = rman_get_start(port);
1412 unit = device_get_unit(dev);
1413 com = device_get_softc(dev);
1414 flags = device_get_flags(dev);
1415
1416 if (unit >= sio_numunits)
1417 sio_numunits = unit + 1;
1418
1419 #ifdef PC98
1420 obufsize = 256;
1421 if (if_type == COM_IF_RSA98III)
1422 obufsize = 2048;
1423 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) {
1424 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1425 return ENXIO;
1426 }
1427 bzero(obuf, obufsize * 2);
1428 #endif
1429
1430 /*
1431 * sioprobe() has initialized the device registers as follows:
1432 * o cfcr = CFCR_8BITS.
1433 * It is most important that CFCR_DLAB is off, so that the
1434 * data port is not hidden when we enable interrupts.
1435 * o ier = 0.
1436 * Interrupts are only enabled when the line is open.
1437 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1438 * interrupt control register or the config specifies no irq.
1439 * Keeping MCR_DTR and MCR_RTS off might stop the external
1440 * device from sending before we are ready.
1441 */
1442 bzero(com, sizeof *com);
1443 com->unit = unit;
1444 com->ioportres = port;
1445 com->ioportrid = rid;
1446 com->bst = rman_get_bustag(port);
1447 com->bsh = rman_get_bushandle(port);
1448 com->cfcr_image = CFCR_8BITS;
1449 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1450 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1451 com->tx_fifo_size = 1;
1452 #ifdef PC98
1453 com->obufsize = obufsize;
1454 com->obuf1 = obuf;
1455 com->obuf2 = obuf + obufsize;
1456 #endif
1457 com->obufs[0].l_head = com->obuf1;
1458 com->obufs[1].l_head = com->obuf2;
1459
1460 #ifdef PC98
1461 com->pc98_if_type = if_type;
1462
1463 if (IS_8251(if_type)) {
1464 pc98_set_ioport(com);
1465
1466 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) {
1467 com->pc98_8251fifo = 1;
1468 com->pc98_8251fifo_enable = 0;
1469 }
1470 } else {
1471 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat;
1472
1473 com->data_port = iobase + iat[com_data];
1474 com->int_ctl_port = iobase + iat[com_ier];
1475 com->int_id_port = iobase + iat[com_iir];
1476 com->modem_ctl_port = iobase + iat[com_mcr];
1477 com->mcr_image = inb(com->modem_ctl_port);
1478 com->line_status_port = iobase + iat[com_lsr];
1479 com->modem_status_port = iobase + iat[com_msr];
1480 }
1481 #else /* not PC98 */
1482 com->data_port = iobase + com_data;
1483 com->int_ctl_port = iobase + com_ier;
1484 com->int_id_port = iobase + com_iir;
1485 com->modem_ctl_port = iobase + com_mcr;
1486 com->mcr_image = inb(com->modem_ctl_port);
1487 com->line_status_port = iobase + com_lsr;
1488 com->modem_status_port = iobase + com_msr;
1489 #endif
1490
1491 tp = com->tp = ttyalloc();
1492 tp->t_oproc = comstart;
1493 tp->t_param = comparam;
1494 tp->t_stop = comstop;
1495 tp->t_modem = commodem;
1496 tp->t_break = combreak;
1497 tp->t_close = comclose;
1498 tp->t_open = comopen;
1499 tp->t_sc = com;
1500
1501 #ifdef PC98
1502 if (!IS_8251(if_type) && rclk == 0)
1503 rclk = if_16550a_type[if_type & 0x0f].rclk;
1504 #else
1505 if (rclk == 0)
1506 rclk = DEFAULT_RCLK;
1507 #endif
1508 com->rclk = rclk;
1509
1510 if (unit == comconsole)
1511 ttyconsolemode(tp, comdefaultrate);
1512 error = siosetwater(com, tp->t_init_in.c_ispeed);
1513 mtx_unlock_spin(&sio_lock);
1514 if (error) {
1515 /*
1516 * Leave i/o resources allocated if this is a `cn'-level
1517 * console, so that other devices can't snarf them.
1518 */
1519 if (iobase != siocniobase)
1520 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1521 return (ENOMEM);
1522 }
1523
1524 /* attempt to determine UART type */
1525 printf("sio%d: type", unit);
1526
1527 #ifndef PC98
1528 if (!COM_ISMULTIPORT(flags) &&
1529 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) {
1530 u_char scr;
1531 u_char scr1;
1532 u_char scr2;
1533
1534 scr = sio_getreg(com, com_scr);
1535 sio_setreg(com, com_scr, 0xa5);
1536 scr1 = sio_getreg(com, com_scr);
1537 sio_setreg(com, com_scr, 0x5a);
1538 scr2 = sio_getreg(com, com_scr);
1539 sio_setreg(com, com_scr, scr);
1540 if (scr1 != 0xa5 || scr2 != 0x5a) {
1541 printf(" 8250 or not responding");
1542 goto determined_type;
1543 }
1544 }
1545 #endif /* !PC98 */
1546 #ifdef PC98
1547 if (IS_8251(com->pc98_if_type)) {
1548 if (com->pc98_8251fifo && !COM_NOFIFO(flags))
1549 com->tx_fifo_size = 16;
1550 com_int_TxRx_disable( com );
1551 com_cflag_and_speed_set( com, tp->t_init_in.c_cflag, comdefaultrate );
1552 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1553 com_send_break_off( com );
1554
1555 if (com->pc98_if_type == COM_IF_INTERNAL) {
1556 printf(" (internal%s%s)",
1557 com->pc98_8251fifo ? " fifo" : "",
1558 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ?
1559 " v-fast" : "");
1560 } else {
1561 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1562 }
1563 } else {
1564 #endif /* PC98 */
1565 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1566 DELAY(100);
1567 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1568 case FIFO_RX_LOW:
1569 printf(" 16450");
1570 break;
1571 case FIFO_RX_MEDL:
1572 printf(" 16450?");
1573 break;
1574 case FIFO_RX_MEDH:
1575 printf(" 16550?");
1576 break;
1577 case FIFO_RX_HIGH:
1578 if (COM_NOFIFO(flags)) {
1579 printf(" 16550A fifo disabled");
1580 break;
1581 }
1582 com->hasfifo = TRUE;
1583 #ifdef PC98
1584 if (com->pc98_if_type == COM_IF_RSA98III) {
1585 com->tx_fifo_size = 2048;
1586 com->rsabase = iobase;
1587 outb(com->rsabase + rsa_ier, 0x00);
1588 outb(com->rsabase + rsa_frr, 0x00);
1589 }
1590 #else
1591 if (COM_ST16650A(flags)) {
1592 printf(" ST16650A");
1593 com->st16650a = TRUE;
1594 com->tx_fifo_size = 32;
1595 break;
1596 }
1597 if (COM_TI16754(flags)) {
1598 printf(" TI16754");
1599 com->tx_fifo_size = 64;
1600 break;
1601 }
1602 #endif
1603 printf(" 16550A");
1604 #ifdef COM_ESP
1605 #ifdef PC98
1606 if (com->pc98_if_type == COM_IF_ESP98)
1607 #endif
1608 for (espp = likely_esp_ports; *espp != 0; espp++)
1609 if (espattach(com, *espp)) {
1610 com->tx_fifo_size = 1024;
1611 break;
1612 }
1613 if (com->esp)
1614 break;
1615 #endif
1616 #ifdef PC98
1617 com->tx_fifo_size = 16;
1618 #else
1619 com->tx_fifo_size = COM_FIFOSIZE(flags);
1620 if (com->tx_fifo_size == 0)
1621 com->tx_fifo_size = 16;
1622 else
1623 printf(" lookalike with %u bytes FIFO",
1624 com->tx_fifo_size);
1625 #endif
1626 break;
1627 }
1628
1629 #ifdef PC98
1630 if (com->pc98_if_type == COM_IF_RSB3000) {
1631 /* Set RSB-2000/3000 Extended Buffer mode. */
1632 u_char lcr;
1633 lcr = sio_getreg(com, com_cfcr);
1634 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB);
1635 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE);
1636 sio_setreg(com, com_cfcr, lcr);
1637 }
1638 #endif
1639
1640 #ifdef COM_ESP
1641 if (com->esp) {
1642 /*
1643 * Set 16550 compatibility mode.
1644 * We don't use the ESP_MODE_SCALE bit to increase the
1645 * fifo trigger levels because we can't handle large
1646 * bursts of input.
1647 * XXX flow control should be set in comparam(), not here.
1648 */
1649 #ifdef PC98
1650 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1651 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1652 #else
1653 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1654 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1655 #endif
1656
1657 /* Set RTS/CTS flow control. */
1658 #ifdef PC98
1659 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1660 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1661 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1662 #else
1663 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1664 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1665 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1666 #endif
1667
1668 /* Set flow-control levels. */
1669 #ifdef PC98
1670 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1671 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1672 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1673 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1674 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1675 #else
1676 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1677 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1678 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1679 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1680 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1681 #endif
1682
1683 #ifdef PC98
1684 /* Set UART clock prescaler. */
1685 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1686 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
1687 #endif
1688 }
1689 #endif /* COM_ESP */
1690 sio_setreg(com, com_fifo, 0);
1691 #ifdef PC98
1692 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1693 #else
1694 determined_type: ;
1695 #endif
1696
1697 #ifdef COM_MULTIPORT
1698 if (COM_ISMULTIPORT(flags)) {
1699 device_t masterdev;
1700
1701 com->multiport = TRUE;
1702 printf(" (multiport");
1703 if (unit == COM_MPMASTER(flags))
1704 printf(" master");
1705 printf(")");
1706 masterdev = devclass_get_device(sio_devclass,
1707 COM_MPMASTER(flags));
1708 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1709 SYS_RES_IRQ, 0, NULL, NULL) != 0);
1710 }
1711 #endif /* COM_MULTIPORT */
1712 #ifdef PC98
1713 }
1714 #endif
1715 if (unit == comconsole)
1716 printf(", console");
1717 if (COM_IIR_TXRDYBUG(flags))
1718 printf(" with a buggy IIR_TXRDY implementation");
1719 printf("\n");
1720
1721 if (sio_fast_ih == NULL) {
1722 swi_add(&tty_intr_event, "sio", siopoll, NULL, SWI_TTY, 0,
1723 &sio_fast_ih);
1724 swi_add(&clk_intr_event, "sio", siopoll, NULL, SWI_CLOCK, 0,
1725 &sio_slow_ih);
1726 }
1727
1728 com->flags = flags;
1729 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1730 tp->t_pps = &com->pps;
1731
1732 if (COM_PPSCTS(flags))
1733 com->pps_bit = MSR_CTS;
1734 else
1735 com->pps_bit = MSR_DCD;
1736 pps_init(&com->pps);
1737
1738 rid = 0;
1739 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
1740 if (com->irqres) {
1741 ret = bus_setup_intr(dev, com->irqres,
1742 INTR_TYPE_TTY,
1743 siointr, NULL, com, &com->cookie);
1744 if (ret) {
1745 ret = bus_setup_intr(dev,
1746 com->irqres, INTR_TYPE_TTY,
1747 NULL, (driver_intr_t *)siointr,
1748 com, &com->cookie);
1749 if (ret == 0)
1750 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1751 }
1752 if (ret)
1753 device_printf(dev, "could not activate interrupt\n");
1754 #if defined(KDB)
1755 /*
1756 * Enable interrupts for early break-to-debugger support
1757 * on the console.
1758 */
1759 if (ret == 0 && unit == comconsole)
1760 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1761 IER_EMSC);
1762 #endif
1763 }
1764
1765 /* We're ready, open the doors... */
1766 ttycreate(tp, TS_CALLOUT, "d%r", unit);
1767
1768 return (0);
1769 }
1770
1771 static int
comopen(struct tty * tp,struct cdev * dev)1772 comopen(struct tty *tp, struct cdev *dev)
1773 {
1774 struct com_s *com;
1775 int i;
1776
1777 com = tp->t_sc;
1778 com->poll = com->no_irq;
1779 com->poll_output = com->loses_outints;
1780 #ifdef PC98
1781 if (IS_8251(com->pc98_if_type)) {
1782 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1783 pc98_msrint_start(dev);
1784 if (com->pc98_8251fifo) {
1785 com->pc98_8251fifo_enable = 1;
1786 outb(I8251F_fcr,
1787 FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST);
1788 }
1789 }
1790 #endif
1791 if (com->hasfifo) {
1792 /*
1793 * (Re)enable and drain fifos.
1794 *
1795 * Certain SMC chips cause problems if the fifos
1796 * are enabled while input is ready. Turn off the
1797 * fifo if necessary to clear the input. We test
1798 * the input ready bit after enabling the fifos
1799 * since we've already enabled them in comparam()
1800 * and to handle races between enabling and fresh
1801 * input.
1802 */
1803 for (i = 0; i < 500; i++) {
1804 sio_setreg(com, com_fifo,
1805 FIFO_RCV_RST | FIFO_XMT_RST | com->fifo_image);
1806 #ifdef PC98
1807 if (com->pc98_if_type == COM_IF_RSA98III)
1808 outb(com->rsabase + rsa_frr , 0x00);
1809 #endif
1810 /*
1811 * XXX the delays are for superstitious
1812 * historical reasons. It must be less than
1813 * the character time at the maximum
1814 * supported speed (87 usec at 115200 bps
1815 * 8N1). Otherwise we might loop endlessly
1816 * if data is streaming in. We used to use
1817 * delays of 100. That usually worked
1818 * because DELAY(100) used to usually delay
1819 * for about 85 usec instead of 100.
1820 */
1821 DELAY(50);
1822 #ifdef PC98
1823 if (com->pc98_if_type == COM_IF_RSA98III ?
1824 !(inb(com->rsabase + rsa_srr) & 0x08) :
1825 !(inb(com->line_status_port) & LSR_RXRDY))
1826 break;
1827 #else
1828 if (!(inb(com->line_status_port) & LSR_RXRDY))
1829 break;
1830 #endif
1831 sio_setreg(com, com_fifo, 0);
1832 DELAY(50);
1833 (void) inb(com->data_port);
1834 }
1835 if (i == 500)
1836 return (EIO);
1837 }
1838
1839 mtx_lock_spin(&sio_lock);
1840 #ifdef PC98
1841 if (IS_8251(com->pc98_if_type)) {
1842 com_tiocm_bis(com, TIOCM_LE);
1843 com->pc98_prev_modem_status = pc98_get_modem_status(com);
1844 com_int_Rx_enable(com);
1845 } else {
1846 #endif
1847 (void) inb(com->line_status_port);
1848 (void) inb(com->data_port);
1849 com->prev_modem_status = com->last_modem_status
1850 = inb(com->modem_status_port);
1851 outb(com->int_ctl_port,
1852 IER_ERXRDY | IER_ERLS | IER_EMSC
1853 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY));
1854 #ifdef PC98
1855 if (com->pc98_if_type == COM_IF_RSA98III) {
1856 outb(com->rsabase + rsa_ier, 0x1d);
1857 outb(com->int_ctl_port, IER_ERLS | IER_EMSC);
1858 }
1859 #endif
1860 #ifdef PC98
1861 }
1862 #endif
1863 mtx_unlock_spin(&sio_lock);
1864 siosettimeout();
1865 /* XXX: should be generic ? */
1866 #ifdef PC98
1867 if ((IS_8251(com->pc98_if_type) &&
1868 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
1869 (!IS_8251(com->pc98_if_type) &&
1870 (com->prev_modem_status & MSR_DCD)) ||
1871 ISCALLOUT(dev))
1872 ttyld_modem(tp, 1);
1873 #else
1874 if (com->prev_modem_status & MSR_DCD || ISCALLOUT(dev))
1875 ttyld_modem(tp, 1);
1876 #endif
1877 return (0);
1878 }
1879
1880 static void
comclose(tp)1881 comclose(tp)
1882 struct tty *tp;
1883 {
1884 int s;
1885 struct com_s *com;
1886
1887 s = spltty();
1888 com = tp->t_sc;
1889 com->poll = FALSE;
1890 com->poll_output = FALSE;
1891 #ifdef PC98
1892 com_send_break_off(com);
1893 #else
1894 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1895 #endif
1896
1897 #if defined(KDB)
1898 /*
1899 * Leave interrupts enabled and don't clear DTR if this is the
1900 * console. This allows us to detect break-to-debugger events
1901 * while the console device is closed.
1902 */
1903 if (com->unit != comconsole)
1904 #endif
1905 {
1906 #ifdef PC98
1907 int tmp;
1908 if (IS_8251(com->pc98_if_type))
1909 com_int_TxRx_disable(com);
1910 else
1911 sio_setreg(com, com_ier, 0);
1912 if (com->pc98_if_type == COM_IF_RSA98III)
1913 outb(com->rsabase + rsa_ier, 0x00);
1914 if (IS_8251(com->pc98_if_type))
1915 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
1916 else
1917 tmp = com->prev_modem_status & MSR_DCD;
1918 #else
1919 sio_setreg(com, com_ier, 0);
1920 #endif
1921 if (tp->t_cflag & HUPCL
1922 /*
1923 * XXX we will miss any carrier drop between here and the
1924 * next open. Perhaps we should watch DCD even when the
1925 * port is closed; it is not sufficient to check it at
1926 * the next open because it might go up and down while
1927 * we're not watching.
1928 */
1929 || (!tp->t_actout
1930 #ifdef PC98
1931 && !(tmp)
1932 #else
1933 && !(com->prev_modem_status & MSR_DCD)
1934 #endif
1935 && !(tp->t_init_in.c_cflag & CLOCAL))
1936 || !(tp->t_state & TS_ISOPEN)) {
1937 #ifdef PC98
1938 if (IS_8251(com->pc98_if_type))
1939 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
1940 else
1941 #endif
1942 (void)commodem(tp, 0, SER_DTR);
1943 ttydtrwaitstart(tp);
1944 }
1945 #ifdef PC98
1946 else {
1947 if (IS_8251(com->pc98_if_type))
1948 com_tiocm_bic(com, TIOCM_LE);
1949 }
1950 #endif
1951 }
1952 #ifdef PC98
1953 if (com->pc98_8251fifo) {
1954 if (com->pc98_8251fifo_enable)
1955 outb(I8251F_fcr, FIFO_XMT_RST | FIFO_RCV_RST);
1956 com->pc98_8251fifo_enable = 0;
1957 }
1958 #endif
1959 if (com->hasfifo) {
1960 /*
1961 * Disable fifos so that they are off after controlled
1962 * reboots. Some BIOSes fail to detect 16550s when the
1963 * fifos are enabled.
1964 */
1965 sio_setreg(com, com_fifo, 0);
1966 }
1967 tp->t_actout = FALSE;
1968 wakeup(&tp->t_actout);
1969 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
1970 siosettimeout();
1971 splx(s);
1972 }
1973
1974 static void
siobusycheck(chan)1975 siobusycheck(chan)
1976 void *chan;
1977 {
1978 struct com_s *com;
1979 int s;
1980
1981 com = (struct com_s *)chan;
1982
1983 /*
1984 * Clear TS_BUSY if low-level output is complete.
1985 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1986 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1987 * called again. Reading the line status port outside of siointr1()
1988 * is safe because CS_BUSY is clear so there are no output interrupts
1989 * to lose.
1990 */
1991 s = spltty();
1992 if (com->state & CS_BUSY)
1993 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1994 #ifdef PC98
1995 else if ((IS_8251(com->pc98_if_type) &&
1996 ((com->pc98_8251fifo_enable &&
1997 (inb(I8251F_lsr) & (FLSR_TxRDY | FLSR_TxEMP))
1998 == (FLSR_TxRDY | FLSR_TxEMP)) ||
1999 (!com->pc98_8251fifo_enable &&
2000 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2001 == (STS8251_TxRDY | STS8251_TxEMP)))) ||
2002 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2003 == (LSR_TSRE | LSR_TXRDY))) {
2004 #else
2005 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2006 == (LSR_TSRE | LSR_TXRDY)) {
2007 #endif
2008 com->tp->t_state &= ~TS_BUSY;
2009 ttwwakeup(com->tp);
2010 com->extra_state &= ~CSE_BUSYCHECK;
2011 } else
2012 timeout(siobusycheck, com, hz / 100);
2013 splx(s);
2014 }
2015
2016 static u_int
siodivisor(rclk,speed)2017 siodivisor(rclk, speed)
2018 u_long rclk;
2019 speed_t speed;
2020 {
2021 long actual_speed;
2022 u_int divisor;
2023 int error;
2024
2025 if (speed == 0)
2026 return (0);
2027 #if UINT_MAX > (ULONG_MAX - 1) / 8
2028 if (speed > (ULONG_MAX - 1) / 8)
2029 return (0);
2030 #endif
2031 divisor = (rclk / (8UL * speed) + 1) / 2;
2032 if (divisor == 0 || divisor >= 65536)
2033 return (0);
2034 actual_speed = rclk / (16UL * divisor);
2035
2036 /* 10 times error in percent: */
2037 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
2038
2039 /* 3.0% maximum error tolerance: */
2040 if (error < -30 || error > 30)
2041 return (0);
2042
2043 return (divisor);
2044 }
2045
2046 /*
2047 * Call this function with the sio_lock mutex held. It will return with the
2048 * lock still held.
2049 */
2050 static void
sioinput(com)2051 sioinput(com)
2052 struct com_s *com;
2053 {
2054 u_char *buf;
2055 int incc;
2056 u_char line_status;
2057 int recv_data;
2058 struct tty *tp;
2059
2060 buf = com->ibuf;
2061 tp = com->tp;
2062 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2063 com_events -= (com->iptr - com->ibuf);
2064 com->iptr = com->ibuf;
2065 return;
2066 }
2067 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2068 /*
2069 * Avoid the grotesquely inefficient lineswitch routine
2070 * (ttyinput) in "raw" mode. It usually takes about 450
2071 * instructions (that's without canonical processing or echo!).
2072 * slinput is reasonably fast (usually 40 instructions plus
2073 * call overhead).
2074 */
2075 do {
2076 /*
2077 * This may look odd, but it is using save-and-enable
2078 * semantics instead of the save-and-disable semantics
2079 * that are used everywhere else.
2080 */
2081 mtx_unlock_spin(&sio_lock);
2082 incc = com->iptr - buf;
2083 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2084 && (com->state & CS_RTS_IFLOW
2085 || tp->t_iflag & IXOFF)
2086 && !(tp->t_state & TS_TBLOCK))
2087 ttyblock(tp);
2088 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2089 += b_to_q((char *)buf, incc, &tp->t_rawq);
2090 buf += incc;
2091 tk_nin += incc;
2092 tk_rawcc += incc;
2093 tp->t_rawcc += incc;
2094 ttwakeup(tp);
2095 if (tp->t_state & TS_TTSTOP
2096 && (tp->t_iflag & IXANY
2097 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2098 tp->t_state &= ~TS_TTSTOP;
2099 tp->t_lflag &= ~FLUSHO;
2100 comstart(tp);
2101 }
2102 mtx_lock_spin(&sio_lock);
2103 } while (buf < com->iptr);
2104 } else {
2105 do {
2106 /*
2107 * This may look odd, but it is using save-and-enable
2108 * semantics instead of the save-and-disable semantics
2109 * that are used everywhere else.
2110 */
2111 mtx_unlock_spin(&sio_lock);
2112 line_status = buf[com->ierroff];
2113 recv_data = *buf++;
2114 if (line_status
2115 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2116 if (line_status & LSR_BI)
2117 recv_data |= TTY_BI;
2118 if (line_status & LSR_FE)
2119 recv_data |= TTY_FE;
2120 if (line_status & LSR_OE)
2121 recv_data |= TTY_OE;
2122 if (line_status & LSR_PE)
2123 recv_data |= TTY_PE;
2124 }
2125 ttyld_rint(tp, recv_data);
2126 mtx_lock_spin(&sio_lock);
2127 } while (buf < com->iptr);
2128 }
2129 com_events -= (com->iptr - com->ibuf);
2130 com->iptr = com->ibuf;
2131
2132 /*
2133 * There is now room for another low-level buffer full of input,
2134 * so enable RTS if it is now disabled and there is room in the
2135 * high-level buffer.
2136 */
2137 #ifdef PC98
2138 if (IS_8251(com->pc98_if_type)) {
2139 if ((com->state & CS_RTS_IFLOW) &&
2140 !(com_tiocm_get(com) & TIOCM_RTS) &&
2141 !(tp->t_state & TS_TBLOCK))
2142 com_tiocm_bis(com, TIOCM_RTS);
2143 } else {
2144 if ((com->state & CS_RTS_IFLOW) &&
2145 !(com->mcr_image & MCR_RTS) &&
2146 !(tp->t_state & TS_TBLOCK))
2147 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2148 }
2149 #else
2150 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2151 !(tp->t_state & TS_TBLOCK))
2152 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2153 #endif
2154 }
2155
2156 static int
siointr(arg)2157 siointr(arg)
2158 void *arg;
2159 {
2160 struct com_s *com;
2161 #if defined(PC98) && defined(COM_MULTIPORT)
2162 u_char rsa_buf_status;
2163 #endif
2164
2165 #ifndef COM_MULTIPORT
2166 com = (struct com_s *)arg;
2167
2168 mtx_lock_spin(&sio_lock);
2169 siointr1(com);
2170 mtx_unlock_spin(&sio_lock);
2171 #else /* COM_MULTIPORT */
2172 bool_t possibly_more_intrs;
2173 int unit;
2174
2175 /*
2176 * Loop until there is no activity on any port. This is necessary
2177 * to get an interrupt edge more than to avoid another interrupt.
2178 * If the IRQ signal is just an OR of the IRQ signals from several
2179 * devices, then the edge from one may be lost because another is
2180 * on.
2181 */
2182 mtx_lock_spin(&sio_lock);
2183 do {
2184 possibly_more_intrs = FALSE;
2185 for (unit = 0; unit < sio_numunits; ++unit) {
2186 com = com_addr(unit);
2187 /*
2188 * XXX COM_LOCK();
2189 * would it work here, or be counter-productive?
2190 */
2191 #ifdef PC98
2192 if (com != NULL
2193 && !com->gone
2194 && IS_8251(com->pc98_if_type)) {
2195 siointr1(com);
2196 } else if (com != NULL
2197 && !com->gone
2198 && com->pc98_if_type == COM_IF_RSA98III) {
2199 rsa_buf_status =
2200 inb(com->rsabase + rsa_srr) & 0xc9;
2201 if ((rsa_buf_status & 0xc8)
2202 || !(rsa_buf_status & 0x01)) {
2203 siointr1(com);
2204 if (rsa_buf_status !=
2205 (inb(com->rsabase + rsa_srr) & 0xc9))
2206 possibly_more_intrs = TRUE;
2207 }
2208 } else
2209 #endif
2210 if (com != NULL
2211 && !com->gone
2212 && (inb(com->int_id_port) & IIR_IMASK)
2213 != IIR_NOPEND) {
2214 siointr1(com);
2215 possibly_more_intrs = TRUE;
2216 }
2217 /* XXX COM_UNLOCK(); */
2218 }
2219 } while (possibly_more_intrs);
2220 mtx_unlock_spin(&sio_lock);
2221 #endif /* COM_MULTIPORT */
2222 return (FILTER_HANDLED);
2223 }
2224
2225 static struct timespec siots[8];
2226 static int siotso;
2227 static int volatile siotsunit = -1;
2228
2229 static int
sysctl_siots(SYSCTL_HANDLER_ARGS)2230 sysctl_siots(SYSCTL_HANDLER_ARGS)
2231 {
2232 char buf[128];
2233 long long delta;
2234 size_t len;
2235 int error, i, tso;
2236
2237 for (i = 1, tso = siotso; i < tso; i++) {
2238 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) *
2239 1000000000 +
2240 (siots[i].tv_nsec - siots[i - 1].tv_nsec);
2241 len = sprintf(buf, "%lld\n", delta);
2242 if (delta >= 110000)
2243 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n",
2244 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1;
2245 if (i == tso - 1)
2246 buf[len - 1] = '\0';
2247 error = SYSCTL_OUT(req, buf, len);
2248 if (error != 0)
2249 return (error);
2250 }
2251 return (0);
2252 }
2253
2254 SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD,
2255 0, 0, sysctl_siots, "A", "sio timestamps");
2256
2257 static void
siointr1(com)2258 siointr1(com)
2259 struct com_s *com;
2260 {
2261 u_char int_ctl;
2262 u_char int_ctl_new;
2263 u_char line_status;
2264 u_char modem_status;
2265 u_char *ioptr;
2266 u_char recv_data;
2267 #ifdef PC98
2268 u_char tmp = 0;
2269 u_char rsa_buf_status = 0;
2270 int rsa_tx_fifo_size = 0;
2271 #endif /* PC98 */
2272 #if defined(KDB)
2273 int kdb_brk;
2274
2275 again:
2276 #endif
2277
2278 if (COM_IIR_TXRDYBUG(com->flags)) {
2279 int_ctl = inb(com->int_ctl_port);
2280 int_ctl_new = int_ctl;
2281 } else {
2282 int_ctl = 0;
2283 int_ctl_new = 0;
2284 }
2285
2286 while (!com->gone) {
2287 #ifdef PC98
2288 status_read:;
2289 if (IS_8251(com->pc98_if_type)) {
2290 if (com->pc98_8251fifo_enable)
2291 tmp = inb(I8251F_lsr);
2292 else
2293 tmp = inb(com->sts_port);
2294 more_intr:
2295 line_status = 0;
2296 if (com->pc98_8251fifo_enable) {
2297 if (tmp & FLSR_TxRDY) line_status |= LSR_TXRDY;
2298 if (tmp & FLSR_RxRDY) line_status |= LSR_RXRDY;
2299 if (tmp & FLSR_TxEMP) line_status |= LSR_TSRE;
2300 if (tmp & FLSR_PE) line_status |= LSR_PE;
2301 if (tmp & FLSR_OE) line_status |= LSR_OE;
2302 if (tmp & FLSR_BI) line_status |= LSR_BI;
2303 } else {
2304 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2305 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2306 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2307 if (tmp & STS8251_PE) line_status |= LSR_PE;
2308 if (tmp & STS8251_OE) line_status |= LSR_OE;
2309 if (tmp & STS8251_FE) line_status |= LSR_FE;
2310 if (tmp & STS8251_BI) line_status |= LSR_BI;
2311 }
2312 } else {
2313 #endif /* PC98 */
2314 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2315 modem_status = inb(com->modem_status_port);
2316 if ((modem_status ^ com->last_modem_status) &
2317 com->pps_bit) {
2318 pps_capture(&com->pps);
2319 pps_event(&com->pps,
2320 (modem_status & com->pps_bit) ?
2321 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2322 }
2323 }
2324 line_status = inb(com->line_status_port);
2325 #ifdef PC98
2326 }
2327 if (com->pc98_if_type == COM_IF_RSA98III)
2328 rsa_buf_status = inb(com->rsabase + rsa_srr);
2329 #endif /* PC98 */
2330
2331 /* input event? (check first to help avoid overruns) */
2332 #ifndef PC98
2333 while (line_status & LSR_RCV_MASK) {
2334 #else
2335 while ((line_status & LSR_RCV_MASK)
2336 || (com->pc98_if_type == COM_IF_RSA98III
2337 && (rsa_buf_status & 0x08))) {
2338 #endif /* PC98 */
2339 /* break/unnattached error bits or real input? */
2340 #ifdef PC98
2341 if (IS_8251(com->pc98_if_type)) {
2342 if (com->pc98_8251fifo_enable) {
2343 recv_data = inb(I8251F_data);
2344 if (tmp &
2345 (FLSR_PE | FLSR_OE | FLSR_BI)) {
2346 pc98_i8251_or_cmd(com, CMD8251_ER);
2347 recv_data = 0;
2348 }
2349 } else {
2350 recv_data = inb(com->data_port);
2351 if (tmp & (STS8251_PE | STS8251_OE |
2352 STS8251_FE | STS8251_BI)) {
2353 pc98_i8251_or_cmd(com, CMD8251_ER);
2354 recv_data = 0;
2355 }
2356 }
2357 } else if (com->pc98_if_type == COM_IF_RSA98III) {
2358 if (!(rsa_buf_status & 0x08))
2359 recv_data = 0;
2360 else
2361 recv_data = inb(com->data_port);
2362 } else
2363 #endif
2364 if (!(line_status & LSR_RXRDY))
2365 recv_data = 0;
2366 else
2367 recv_data = inb(com->data_port);
2368 #ifdef KDB
2369 if (com->unit == comconsole &&
2370 (kdb_brk = kdb_alt_break(recv_data,
2371 &com->alt_brk_state)) != 0) {
2372 goto again;
2373 }
2374 #endif /* KDB */
2375 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2376 /*
2377 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2378 * Otherwise, push the work to a higher level
2379 * (to handle PARMRK) if we're bypassing.
2380 * Otherwise, convert BI/FE and PE+INPCK to 0.
2381 *
2382 * This makes bypassing work right in the
2383 * usual "raw" case (IGNBRK set, and IGNPAR
2384 * and INPCK clear).
2385 *
2386 * Note: BI together with FE/PE means just BI.
2387 */
2388 if (line_status & LSR_BI) {
2389 #if defined(KDB)
2390 if (com->unit == comconsole) {
2391 kdb_enter(KDB_WHY_BREAK,
2392 "Line break on console");
2393 goto cont;
2394 }
2395 #endif
2396 if (com->tp == NULL
2397 || com->tp->t_iflag & IGNBRK)
2398 goto cont;
2399 } else {
2400 if (com->tp == NULL
2401 || com->tp->t_iflag & IGNPAR)
2402 goto cont;
2403 }
2404 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2405 && (line_status & (LSR_BI | LSR_FE)
2406 || com->tp->t_iflag & INPCK))
2407 recv_data = 0;
2408 }
2409 ++com->bytes_in;
2410 if (com->tp != NULL &&
2411 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar)
2412 swi_sched(sio_fast_ih, 0);
2413 ioptr = com->iptr;
2414 if (ioptr >= com->ibufend)
2415 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2416 else {
2417 if (com->tp != NULL && com->tp->t_do_timestamp)
2418 microtime(&com->tp->t_timestamp);
2419 ++com_events;
2420 swi_sched(sio_slow_ih, SWI_DELAY);
2421 #if 0 /* for testing input latency vs efficiency */
2422 if (com->iptr - com->ibuf == 8)
2423 swi_sched(sio_fast_ih, 0);
2424 #endif
2425 ioptr[0] = recv_data;
2426 ioptr[com->ierroff] = line_status;
2427 com->iptr = ++ioptr;
2428 if (ioptr == com->ihighwater
2429 && com->state & CS_RTS_IFLOW)
2430 #ifdef PC98
2431 IS_8251(com->pc98_if_type) ?
2432 com_tiocm_bic(com, TIOCM_RTS) :
2433 #endif
2434 outb(com->modem_ctl_port,
2435 com->mcr_image &= ~MCR_RTS);
2436 if (line_status & LSR_OE)
2437 CE_RECORD(com, CE_OVERRUN);
2438 }
2439 cont:
2440 if (line_status & LSR_TXRDY
2441 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY))
2442 goto txrdy;
2443
2444 /*
2445 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2446 * jump from the top of the loop to here
2447 */
2448 #ifdef PC98
2449 if (IS_8251(com->pc98_if_type))
2450 goto status_read;
2451 else
2452 #endif
2453 line_status = inb(com->line_status_port) & 0x7F;
2454 #ifdef PC98
2455 if (com->pc98_if_type == COM_IF_RSA98III)
2456 rsa_buf_status = inb(com->rsabase + rsa_srr);
2457 #endif /* PC98 */
2458 }
2459
2460 /* modem status change? (always check before doing output) */
2461 #ifdef PC98
2462 if (!IS_8251(com->pc98_if_type)) {
2463 #endif
2464 modem_status = inb(com->modem_status_port);
2465 if (modem_status != com->last_modem_status) {
2466 /*
2467 * Schedule high level to handle DCD changes. Note
2468 * that we don't use the delta bits anywhere. Some
2469 * UARTs mess them up, and it's easy to remember the
2470 * previous bits and calculate the delta.
2471 */
2472 com->last_modem_status = modem_status;
2473 if (!(com->state & CS_CHECKMSR)) {
2474 com_events += LOTS_OF_EVENTS;
2475 com->state |= CS_CHECKMSR;
2476 swi_sched(sio_fast_ih, 0);
2477 }
2478
2479 /* handle CTS change immediately for crisp flow ctl */
2480 if (com->state & CS_CTS_OFLOW) {
2481 if (modem_status & MSR_CTS)
2482 com->state |= CS_ODEVREADY;
2483 else
2484 com->state &= ~CS_ODEVREADY;
2485 }
2486 }
2487 #ifdef PC98
2488 }
2489 #endif
2490
2491 txrdy:
2492 /* output queued and everything ready? */
2493 #ifndef PC98
2494 if (line_status & LSR_TXRDY
2495 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2496 #else
2497 if (((com->pc98_if_type == COM_IF_RSA98III)
2498 ? (rsa_buf_status & 0x02)
2499 : (line_status & LSR_TXRDY))
2500 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2501 #endif
2502 #ifdef PC98
2503 Port_t tmp_data_port;
2504
2505 if (IS_8251(com->pc98_if_type) &&
2506 com->pc98_8251fifo_enable)
2507 tmp_data_port = I8251F_data;
2508 else
2509 tmp_data_port = com->data_port;
2510 #endif
2511
2512 ioptr = com->obufq.l_head;
2513 if (com->tx_fifo_size > 1 && com->unit != siotsunit) {
2514 u_int ocount;
2515
2516 ocount = com->obufq.l_tail - ioptr;
2517 #ifdef PC98
2518 if (com->pc98_if_type == COM_IF_RSA98III) {
2519 rsa_buf_status = inb(com->rsabase + rsa_srr);
2520 rsa_tx_fifo_size = 1024;
2521 if (!(rsa_buf_status & 0x01))
2522 rsa_tx_fifo_size = 2048;
2523 if (ocount > rsa_tx_fifo_size)
2524 ocount = rsa_tx_fifo_size;
2525 } else
2526 #endif
2527 if (ocount > com->tx_fifo_size)
2528 ocount = com->tx_fifo_size;
2529 com->bytes_out += ocount;
2530 do
2531 #ifdef PC98
2532 outb(tmp_data_port, *ioptr++);
2533 #else
2534 outb(com->data_port, *ioptr++);
2535 #endif
2536 while (--ocount != 0);
2537 } else {
2538 #ifdef PC98
2539 outb(tmp_data_port, *ioptr++);
2540 #else
2541 outb(com->data_port, *ioptr++);
2542 #endif
2543 ++com->bytes_out;
2544 if (com->unit == siotsunit
2545 && siotso < sizeof siots / sizeof siots[0])
2546 nanouptime(&siots[siotso++]);
2547 }
2548 #ifdef PC98
2549 if (IS_8251(com->pc98_if_type))
2550 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2551 com_int_Tx_enable(com);
2552 #endif
2553 com->obufq.l_head = ioptr;
2554 if (COM_IIR_TXRDYBUG(com->flags))
2555 int_ctl_new = int_ctl | IER_ETXRDY;
2556 if (ioptr >= com->obufq.l_tail) {
2557 struct lbq *qp;
2558
2559 qp = com->obufq.l_next;
2560 qp->l_queued = FALSE;
2561 qp = qp->l_next;
2562 if (qp != NULL) {
2563 com->obufq.l_head = qp->l_head;
2564 com->obufq.l_tail = qp->l_tail;
2565 com->obufq.l_next = qp;
2566 } else {
2567 /* output just completed */
2568 if (COM_IIR_TXRDYBUG(com->flags))
2569 int_ctl_new = int_ctl
2570 & ~IER_ETXRDY;
2571 com->state &= ~CS_BUSY;
2572 #if defined(PC98)
2573 if (IS_8251(com->pc98_if_type) &&
2574 pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
2575 com_int_Tx_disable(com);
2576 #endif
2577 }
2578 if (!(com->state & CS_ODONE)) {
2579 com_events += LOTS_OF_EVENTS;
2580 com->state |= CS_ODONE;
2581 /* handle at high level ASAP */
2582 swi_sched(sio_fast_ih, 0);
2583 }
2584 }
2585 #ifdef PC98
2586 if (COM_IIR_TXRDYBUG(com->flags)
2587 && int_ctl != int_ctl_new) {
2588 if (com->pc98_if_type == COM_IF_RSA98III) {
2589 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2590 outb(com->int_ctl_port, int_ctl_new);
2591 outb(com->rsabase + rsa_ier, 0x1d);
2592 } else
2593 outb(com->int_ctl_port, int_ctl_new);
2594 }
2595 #else
2596 if (COM_IIR_TXRDYBUG(com->flags)
2597 && int_ctl != int_ctl_new)
2598 outb(com->int_ctl_port, int_ctl_new);
2599 #endif
2600 }
2601 #ifdef PC98
2602 else if (line_status & LSR_TXRDY) {
2603 if (IS_8251(com->pc98_if_type))
2604 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
2605 com_int_Tx_disable(com);
2606 }
2607 if (IS_8251(com->pc98_if_type)) {
2608 if (com->pc98_8251fifo_enable) {
2609 if ((tmp = inb(I8251F_lsr)) & FLSR_RxRDY)
2610 goto more_intr;
2611 } else {
2612 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2613 goto more_intr;
2614 }
2615 }
2616 #endif
2617
2618 /* finished? */
2619 #ifndef COM_MULTIPORT
2620 #ifdef PC98
2621 if (IS_8251(com->pc98_if_type))
2622 return;
2623 #endif
2624 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2625 #endif /* COM_MULTIPORT */
2626 return;
2627 }
2628 }
2629
2630 /* software interrupt handler for SWI_TTY */
2631 static void
siopoll(void * dummy)2632 siopoll(void *dummy)
2633 {
2634 int unit;
2635
2636 if (com_events == 0)
2637 return;
2638 repeat:
2639 for (unit = 0; unit < sio_numunits; ++unit) {
2640 struct com_s *com;
2641 int incc;
2642 struct tty *tp;
2643
2644 com = com_addr(unit);
2645 if (com == NULL)
2646 continue;
2647 tp = com->tp;
2648 if (tp == NULL || com->gone) {
2649 /*
2650 * Discard any events related to never-opened or
2651 * going-away devices.
2652 */
2653 mtx_lock_spin(&sio_lock);
2654 incc = com->iptr - com->ibuf;
2655 com->iptr = com->ibuf;
2656 if (com->state & CS_CHECKMSR) {
2657 incc += LOTS_OF_EVENTS;
2658 com->state &= ~CS_CHECKMSR;
2659 }
2660 com_events -= incc;
2661 mtx_unlock_spin(&sio_lock);
2662 continue;
2663 }
2664 if (com->iptr != com->ibuf) {
2665 mtx_lock_spin(&sio_lock);
2666 sioinput(com);
2667 mtx_unlock_spin(&sio_lock);
2668 }
2669 if (com->state & CS_CHECKMSR) {
2670 u_char delta_modem_status;
2671
2672 #ifdef PC98
2673 if (!IS_8251(com->pc98_if_type)) {
2674 #endif
2675 mtx_lock_spin(&sio_lock);
2676 delta_modem_status = com->last_modem_status
2677 ^ com->prev_modem_status;
2678 com->prev_modem_status = com->last_modem_status;
2679 com_events -= LOTS_OF_EVENTS;
2680 com->state &= ~CS_CHECKMSR;
2681 mtx_unlock_spin(&sio_lock);
2682 if (delta_modem_status & MSR_DCD)
2683 ttyld_modem(tp,
2684 com->prev_modem_status & MSR_DCD);
2685 #ifdef PC98
2686 }
2687 #endif
2688 }
2689 if (com->state & CS_ODONE) {
2690 mtx_lock_spin(&sio_lock);
2691 com_events -= LOTS_OF_EVENTS;
2692 com->state &= ~CS_ODONE;
2693 mtx_unlock_spin(&sio_lock);
2694 if (!(com->state & CS_BUSY)
2695 && !(com->extra_state & CSE_BUSYCHECK)) {
2696 timeout(siobusycheck, com, hz / 100);
2697 com->extra_state |= CSE_BUSYCHECK;
2698 }
2699 ttyld_start(tp);
2700 }
2701 if (com_events == 0)
2702 break;
2703 }
2704 if (com_events >= LOTS_OF_EVENTS)
2705 goto repeat;
2706 }
2707
2708 static void
combreak(tp,sig)2709 combreak(tp, sig)
2710 struct tty *tp;
2711 int sig;
2712 {
2713 struct com_s *com;
2714
2715 com = tp->t_sc;
2716
2717 #ifdef PC98
2718 if (sig)
2719 com_send_break_on(com);
2720 else
2721 com_send_break_off(com);
2722 #else
2723 if (sig)
2724 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2725 else
2726 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2727 #endif
2728 }
2729
2730 static int
comparam(tp,t)2731 comparam(tp, t)
2732 struct tty *tp;
2733 struct termios *t;
2734 {
2735 u_int cfcr;
2736 int cflag;
2737 struct com_s *com;
2738 u_int divisor;
2739 u_char dlbh;
2740 u_char dlbl;
2741 u_char efr_flowbits;
2742 int s;
2743 #ifdef PC98
2744 u_char param = 0;
2745 #endif
2746
2747 com = tp->t_sc;
2748 if (com == NULL)
2749 return (ENODEV);
2750
2751 #ifdef PC98
2752 cfcr = 0;
2753
2754 if (IS_8251(com->pc98_if_type)) {
2755 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0)
2756 return (EINVAL);
2757 } else {
2758 #endif
2759 /* check requested parameters */
2760 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed))
2761 return (EINVAL);
2762 divisor = siodivisor(com->rclk, t->c_ispeed);
2763 if (divisor == 0)
2764 return (EINVAL);
2765 #ifdef PC98
2766 }
2767 #endif
2768
2769 /* parameters are OK, convert them to the com struct and the device */
2770 s = spltty();
2771 #ifdef PC98
2772 if (IS_8251(com->pc98_if_type)) {
2773 if (t->c_ospeed == 0)
2774 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2775 else
2776 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2777 } else
2778 #endif
2779 if (t->c_ospeed == 0)
2780 (void)commodem(tp, 0, SER_DTR); /* hang up line */
2781 else
2782 (void)commodem(tp, SER_DTR, 0);
2783 cflag = t->c_cflag;
2784 #ifdef PC98
2785 if (!IS_8251(com->pc98_if_type)) {
2786 #endif
2787 switch (cflag & CSIZE) {
2788 case CS5:
2789 cfcr = CFCR_5BITS;
2790 break;
2791 case CS6:
2792 cfcr = CFCR_6BITS;
2793 break;
2794 case CS7:
2795 cfcr = CFCR_7BITS;
2796 break;
2797 default:
2798 cfcr = CFCR_8BITS;
2799 break;
2800 }
2801 if (cflag & PARENB) {
2802 cfcr |= CFCR_PENAB;
2803 if (!(cflag & PARODD))
2804 cfcr |= CFCR_PEVEN;
2805 }
2806 if (cflag & CSTOPB)
2807 cfcr |= CFCR_STOPB;
2808
2809 if (com->hasfifo) {
2810 /*
2811 * Use a fifo trigger level low enough so that the input
2812 * latency from the fifo is less than about 16 msec and
2813 * the total latency is less than about 30 msec. These
2814 * latencies are reasonable for humans. Serial comms
2815 * protocols shouldn't expect anything better since modem
2816 * latencies are larger.
2817 *
2818 * The fifo trigger level cannot be set at RX_HIGH for high
2819 * speed connections without further work on reducing
2820 * interrupt disablement times in other parts of the system,
2821 * without producing silo overflow errors.
2822 */
2823 com->fifo_image = com->unit == siotsunit ? 0
2824 : t->c_ispeed <= 4800
2825 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
2826 #ifdef COM_ESP
2827 /*
2828 * The Hayes ESP card needs the fifo DMA mode bit set
2829 * in compatibility mode. If not, it will interrupt
2830 * for each character received.
2831 */
2832 if (com->esp)
2833 com->fifo_image |= FIFO_DMA_MODE;
2834 #endif
2835 sio_setreg(com, com_fifo, com->fifo_image);
2836 }
2837 #ifdef PC98
2838 }
2839 #endif
2840
2841 /*
2842 * This returns with interrupts disabled so that we can complete
2843 * the speed change atomically. Keeping interrupts disabled is
2844 * especially important while com_data is hidden.
2845 */
2846 (void) siosetwater(com, t->c_ispeed);
2847
2848 #ifdef PC98
2849 if (IS_8251(com->pc98_if_type))
2850 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
2851 else {
2852 #endif
2853 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
2854 /*
2855 * Only set the divisor registers if they would change, since on
2856 * some 16550 incompatibles (UMC8669F), setting them while input
2857 * is arriving loses sync until data stops arriving.
2858 */
2859 dlbl = divisor & 0xFF;
2860 if (sio_getreg(com, com_dlbl) != dlbl)
2861 sio_setreg(com, com_dlbl, dlbl);
2862 dlbh = divisor >> 8;
2863 if (sio_getreg(com, com_dlbh) != dlbh)
2864 sio_setreg(com, com_dlbh, dlbh);
2865 #ifdef PC98
2866 }
2867 #endif
2868
2869 efr_flowbits = 0;
2870
2871 if (cflag & CRTS_IFLOW) {
2872 com->state |= CS_RTS_IFLOW;
2873 efr_flowbits |= EFR_AUTORTS;
2874 /*
2875 * If CS_RTS_IFLOW just changed from off to on, the change
2876 * needs to be propagated to MCR_RTS. This isn't urgent,
2877 * so do it later by calling comstart() instead of repeating
2878 * a lot of code from comstart() here.
2879 */
2880 } else if (com->state & CS_RTS_IFLOW) {
2881 com->state &= ~CS_RTS_IFLOW;
2882 /*
2883 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
2884 * on here, since comstart() won't do it later.
2885 */
2886 #ifdef PC98
2887 if (IS_8251(com->pc98_if_type))
2888 com_tiocm_bis(com, TIOCM_RTS);
2889 else
2890 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2891 #else
2892 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2893 #endif
2894 }
2895
2896 /*
2897 * Set up state to handle output flow control.
2898 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2899 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2900 */
2901 com->state |= CS_ODEVREADY;
2902 com->state &= ~CS_CTS_OFLOW;
2903 #ifdef PC98
2904 if (com->pc98_if_type == COM_IF_RSA98III) {
2905 param = inb(com->rsabase + rsa_msr);
2906 outb(com->rsabase + rsa_msr, param & 0x14);
2907 }
2908 #endif
2909 if (cflag & CCTS_OFLOW) {
2910 com->state |= CS_CTS_OFLOW;
2911 efr_flowbits |= EFR_AUTOCTS;
2912 #ifdef PC98
2913 if (IS_8251(com->pc98_if_type)) {
2914 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
2915 com->state &= ~CS_ODEVREADY;
2916 } else if (com->pc98_if_type == COM_IF_RSA98III) {
2917 /* Set automatic flow control mode */
2918 outb(com->rsabase + rsa_msr, param | 0x08);
2919 } else
2920 #endif
2921 if (!(com->last_modem_status & MSR_CTS))
2922 com->state &= ~CS_ODEVREADY;
2923 }
2924
2925 #ifdef PC98
2926 if (!IS_8251(com->pc98_if_type))
2927 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2928 #else
2929 if (com->st16650a) {
2930 sio_setreg(com, com_lcr, LCR_EFR_ENABLE);
2931 sio_setreg(com, com_efr,
2932 (sio_getreg(com, com_efr)
2933 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits);
2934 }
2935 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2936 #endif
2937
2938 /* XXX shouldn't call functions while intrs are disabled. */
2939 ttyldoptim(tp);
2940
2941 mtx_unlock_spin(&sio_lock);
2942 splx(s);
2943 comstart(tp);
2944 if (com->ibufold != NULL) {
2945 free(com->ibufold, M_DEVBUF);
2946 com->ibufold = NULL;
2947 }
2948 return (0);
2949 }
2950
2951 /*
2952 * This function must be called with the sio_lock mutex released and will
2953 * return with it obtained.
2954 */
2955 static int
siosetwater(com,speed)2956 siosetwater(com, speed)
2957 struct com_s *com;
2958 speed_t speed;
2959 {
2960 int cp4ticks;
2961 u_char *ibuf;
2962 int ibufsize;
2963 struct tty *tp;
2964
2965 /*
2966 * Make the buffer size large enough to handle a softtty interrupt
2967 * latency of about 2 ticks without loss of throughput or data
2968 * (about 3 ticks if input flow control is not used or not honoured,
2969 * but a bit less for CS5-CS7 modes).
2970 */
2971 cp4ticks = speed / 10 / hz * 4;
2972 for (ibufsize = 128; ibufsize < cp4ticks;)
2973 ibufsize <<= 1;
2974 #ifdef PC98
2975 if (com->pc98_if_type == COM_IF_RSA98III)
2976 ibufsize = 2048;
2977 #endif
2978 if (ibufsize == com->ibufsize) {
2979 mtx_lock_spin(&sio_lock);
2980 return (0);
2981 }
2982
2983 /*
2984 * Allocate input buffer. The extra factor of 2 in the size is
2985 * to allow for an error byte for each input byte.
2986 */
2987 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
2988 if (ibuf == NULL) {
2989 mtx_lock_spin(&sio_lock);
2990 return (ENOMEM);
2991 }
2992
2993 /* Initialize non-critical variables. */
2994 com->ibufold = com->ibuf;
2995 com->ibufsize = ibufsize;
2996 tp = com->tp;
2997 if (tp != NULL) {
2998 tp->t_ififosize = 2 * ibufsize;
2999 tp->t_ispeedwat = (speed_t)-1;
3000 tp->t_ospeedwat = (speed_t)-1;
3001 }
3002
3003 /*
3004 * Read current input buffer, if any. Continue with interrupts
3005 * disabled.
3006 */
3007 mtx_lock_spin(&sio_lock);
3008 if (com->iptr != com->ibuf)
3009 sioinput(com);
3010
3011 /*-
3012 * Initialize critical variables, including input buffer watermarks.
3013 * The external device is asked to stop sending when the buffer
3014 * exactly reaches high water, or when the high level requests it.
3015 * The high level is notified immediately (rather than at a later
3016 * clock tick) when this watermark is reached.
3017 * The buffer size is chosen so the watermark should almost never
3018 * be reached.
3019 * The low watermark is invisibly 0 since the buffer is always
3020 * emptied all at once.
3021 */
3022 com->iptr = com->ibuf = ibuf;
3023 com->ibufend = ibuf + ibufsize;
3024 com->ierroff = ibufsize;
3025 com->ihighwater = ibuf + 3 * ibufsize / 4;
3026 return (0);
3027 }
3028
3029 static void
comstart(tp)3030 comstart(tp)
3031 struct tty *tp;
3032 {
3033 struct com_s *com;
3034 int s;
3035
3036 com = tp->t_sc;
3037 if (com == NULL)
3038 return;
3039 s = spltty();
3040 mtx_lock_spin(&sio_lock);
3041 if (tp->t_state & TS_TTSTOP)
3042 com->state &= ~CS_TTGO;
3043 else
3044 com->state |= CS_TTGO;
3045 if (tp->t_state & TS_TBLOCK) {
3046 #ifdef PC98
3047 if (IS_8251(com->pc98_if_type)) {
3048 if ((com_tiocm_get(com) & TIOCM_RTS) &&
3049 (com->state & CS_RTS_IFLOW))
3050 com_tiocm_bic(com, TIOCM_RTS);
3051 } else {
3052 if ((com->mcr_image & MCR_RTS) &&
3053 (com->state & CS_RTS_IFLOW))
3054 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3055 }
3056 #else
3057 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3058 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3059 #endif
3060 } else {
3061 #ifdef PC98
3062 if (IS_8251(com->pc98_if_type)) {
3063 if (!(com_tiocm_get(com) & TIOCM_RTS) &&
3064 com->iptr < com->ihighwater &&
3065 com->state & CS_RTS_IFLOW)
3066 com_tiocm_bis(com, TIOCM_RTS);
3067 } else {
3068 if (!(com->mcr_image & MCR_RTS) &&
3069 com->iptr < com->ihighwater &&
3070 com->state & CS_RTS_IFLOW)
3071 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3072 }
3073 #else
3074 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3075 && com->state & CS_RTS_IFLOW)
3076 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3077 #endif
3078 }
3079 mtx_unlock_spin(&sio_lock);
3080 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3081 ttwwakeup(tp);
3082 splx(s);
3083 return;
3084 }
3085 if (tp->t_outq.c_cc != 0) {
3086 struct lbq *qp;
3087 struct lbq *next;
3088
3089 if (!com->obufs[0].l_queued) {
3090 com->obufs[0].l_tail
3091 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3092 #ifdef PC98
3093 com->obufsize);
3094 #else
3095 sizeof com->obuf1);
3096 #endif
3097 com->obufs[0].l_next = NULL;
3098 com->obufs[0].l_queued = TRUE;
3099 mtx_lock_spin(&sio_lock);
3100 if (com->state & CS_BUSY) {
3101 qp = com->obufq.l_next;
3102 while ((next = qp->l_next) != NULL)
3103 qp = next;
3104 qp->l_next = &com->obufs[0];
3105 } else {
3106 com->obufq.l_head = com->obufs[0].l_head;
3107 com->obufq.l_tail = com->obufs[0].l_tail;
3108 com->obufq.l_next = &com->obufs[0];
3109 com->state |= CS_BUSY;
3110 }
3111 mtx_unlock_spin(&sio_lock);
3112 }
3113 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3114 com->obufs[1].l_tail
3115 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3116 #ifdef PC98
3117 com->obufsize);
3118 #else
3119 sizeof com->obuf2);
3120 #endif
3121 com->obufs[1].l_next = NULL;
3122 com->obufs[1].l_queued = TRUE;
3123 mtx_lock_spin(&sio_lock);
3124 if (com->state & CS_BUSY) {
3125 qp = com->obufq.l_next;
3126 while ((next = qp->l_next) != NULL)
3127 qp = next;
3128 qp->l_next = &com->obufs[1];
3129 } else {
3130 com->obufq.l_head = com->obufs[1].l_head;
3131 com->obufq.l_tail = com->obufs[1].l_tail;
3132 com->obufq.l_next = &com->obufs[1];
3133 com->state |= CS_BUSY;
3134 }
3135 mtx_unlock_spin(&sio_lock);
3136 }
3137 tp->t_state |= TS_BUSY;
3138 }
3139 mtx_lock_spin(&sio_lock);
3140 if (com->state >= (CS_BUSY | CS_TTGO))
3141 siointr1(com); /* fake interrupt to start output */
3142 mtx_unlock_spin(&sio_lock);
3143 ttwwakeup(tp);
3144 splx(s);
3145 }
3146
3147 static void
comstop(tp,rw)3148 comstop(tp, rw)
3149 struct tty *tp;
3150 int rw;
3151 {
3152 struct com_s *com;
3153 #ifdef PC98
3154 int rsa98_tmp = 0;
3155 #endif
3156
3157 com = tp->t_sc;
3158 if (com == NULL || com->gone)
3159 return;
3160 mtx_lock_spin(&sio_lock);
3161 if (rw & FWRITE) {
3162 #ifdef PC98
3163 if (!IS_8251(com->pc98_if_type)) {
3164 #endif
3165 if (com->hasfifo)
3166 #ifdef COM_ESP
3167 /* XXX avoid h/w bug. */
3168 if (!com->esp)
3169 #endif
3170 sio_setreg(com, com_fifo,
3171 FIFO_XMT_RST | com->fifo_image);
3172 #ifdef PC98
3173 if (com->pc98_if_type == COM_IF_RSA98III)
3174 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3175 sio_setreg(com, com_fifo,
3176 FIFO_XMT_RST | com->fifo_image);
3177 }
3178 #endif
3179 com->obufs[0].l_queued = FALSE;
3180 com->obufs[1].l_queued = FALSE;
3181 if (com->state & CS_ODONE)
3182 com_events -= LOTS_OF_EVENTS;
3183 com->state &= ~(CS_ODONE | CS_BUSY);
3184 com->tp->t_state &= ~TS_BUSY;
3185 }
3186 if (rw & FREAD) {
3187 #ifdef PC98
3188 if (!IS_8251(com->pc98_if_type)) {
3189 if (com->pc98_if_type == COM_IF_RSA98III)
3190 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3191 sio_getreg(com, com_data);
3192 #endif
3193 if (com->hasfifo)
3194 #ifdef COM_ESP
3195 /* XXX avoid h/w bug. */
3196 if (!com->esp)
3197 #endif
3198 sio_setreg(com, com_fifo,
3199 FIFO_RCV_RST | com->fifo_image);
3200 #ifdef PC98
3201 }
3202 #endif
3203 com_events -= (com->iptr - com->ibuf);
3204 com->iptr = com->ibuf;
3205 }
3206 mtx_unlock_spin(&sio_lock);
3207 comstart(tp);
3208 }
3209
3210 static int
commodem(struct tty * tp,int sigon,int sigoff)3211 commodem(struct tty *tp, int sigon, int sigoff)
3212 {
3213 struct com_s *com;
3214 int bitand, bitor, msr;
3215 #ifdef PC98
3216 int clr, set;
3217 #endif
3218
3219 com = tp->t_sc;
3220 if (com->gone)
3221 return(0);
3222 if (sigon != 0 || sigoff != 0) {
3223 #ifdef PC98
3224 if (IS_8251(com->pc98_if_type)) {
3225 bitand = bitor = 0;
3226 clr = set = 0;
3227 if (sigoff & SER_DTR) {
3228 bitand |= TIOCM_DTR;
3229 clr |= CMD8251_DTR;
3230 }
3231 if (sigoff & SER_RTS) {
3232 bitand |= TIOCM_RTS;
3233 clr |= CMD8251_RxEN | CMD8251_RTS;
3234 }
3235 if (sigon & SER_DTR) {
3236 bitor |= TIOCM_DTR;
3237 set |= CMD8251_TxEN | CMD8251_RxEN |
3238 CMD8251_DTR;
3239 }
3240 if (sigon & SER_RTS) {
3241 bitor |= TIOCM_RTS;
3242 set |= CMD8251_TxEN | CMD8251_RxEN |
3243 CMD8251_RTS;
3244 }
3245 bitand = ~bitand;
3246 mtx_lock_spin(&sio_lock);
3247 com->pc98_prev_modem_status &= bitand;
3248 com->pc98_prev_modem_status |= bitor;
3249 pc98_i8251_clear_or_cmd(com, clr, set);
3250 mtx_unlock_spin(&sio_lock);
3251 return (0);
3252 } else {
3253 #endif
3254 bitand = bitor = 0;
3255 if (sigoff & SER_DTR)
3256 bitand |= MCR_DTR;
3257 if (sigoff & SER_RTS)
3258 bitand |= MCR_RTS;
3259 if (sigon & SER_DTR)
3260 bitor |= MCR_DTR;
3261 if (sigon & SER_RTS)
3262 bitor |= MCR_RTS;
3263 bitand = ~bitand;
3264 mtx_lock_spin(&sio_lock);
3265 com->mcr_image &= bitand;
3266 com->mcr_image |= bitor;
3267 outb(com->modem_ctl_port, com->mcr_image);
3268 mtx_unlock_spin(&sio_lock);
3269 return (0);
3270 #ifdef PC98
3271 }
3272 #endif
3273 } else {
3274 #ifdef PC98
3275 if (IS_8251(com->pc98_if_type))
3276 return (com_tiocm_get(com));
3277 else {
3278 #endif
3279 bitor = 0;
3280 if (com->mcr_image & MCR_DTR)
3281 bitor |= SER_DTR;
3282 if (com->mcr_image & MCR_RTS)
3283 bitor |= SER_RTS;
3284 msr = com->prev_modem_status;
3285 if (msr & MSR_CTS)
3286 bitor |= SER_CTS;
3287 if (msr & MSR_DCD)
3288 bitor |= SER_DCD;
3289 if (msr & MSR_DSR)
3290 bitor |= SER_DSR;
3291 if (msr & MSR_DSR)
3292 bitor |= SER_DSR;
3293 if (msr & (MSR_RI | MSR_TERI))
3294 bitor |= SER_RI;
3295 return (bitor);
3296 #ifdef PC98
3297 }
3298 #endif
3299 }
3300 }
3301
3302 static void
siosettimeout()3303 siosettimeout()
3304 {
3305 struct com_s *com;
3306 bool_t someopen;
3307 int unit;
3308
3309 /*
3310 * Set our timeout period to 1 second if no polled devices are open.
3311 * Otherwise set it to max(1/200, 1/hz).
3312 * Enable timeouts iff some device is open.
3313 */
3314 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3315 sio_timeout = hz;
3316 someopen = FALSE;
3317 for (unit = 0; unit < sio_numunits; ++unit) {
3318 com = com_addr(unit);
3319 if (com != NULL && com->tp != NULL
3320 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3321 someopen = TRUE;
3322 if (com->poll || com->poll_output) {
3323 sio_timeout = hz > 200 ? hz / 200 : 1;
3324 break;
3325 }
3326 }
3327 }
3328 if (someopen) {
3329 sio_timeouts_until_log = hz / sio_timeout;
3330 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3331 sio_timeout);
3332 } else {
3333 /* Flush error messages, if any. */
3334 sio_timeouts_until_log = 1;
3335 comwakeup((void *)NULL);
3336 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3337 }
3338 }
3339
3340 static void
comwakeup(chan)3341 comwakeup(chan)
3342 void *chan;
3343 {
3344 struct com_s *com;
3345 int unit;
3346
3347 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3348
3349 /*
3350 * Recover from lost output interrupts.
3351 * Poll any lines that don't use interrupts.
3352 */
3353 for (unit = 0; unit < sio_numunits; ++unit) {
3354 com = com_addr(unit);
3355 if (com != NULL && !com->gone
3356 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3357 mtx_lock_spin(&sio_lock);
3358 siointr1(com);
3359 mtx_unlock_spin(&sio_lock);
3360 }
3361 }
3362
3363 /*
3364 * Check for and log errors, but not too often.
3365 */
3366 if (--sio_timeouts_until_log > 0)
3367 return;
3368 sio_timeouts_until_log = hz / sio_timeout;
3369 for (unit = 0; unit < sio_numunits; ++unit) {
3370 int errnum;
3371
3372 com = com_addr(unit);
3373 if (com == NULL)
3374 continue;
3375 if (com->gone)
3376 continue;
3377 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3378 u_int delta;
3379 u_long total;
3380
3381 mtx_lock_spin(&sio_lock);
3382 delta = com->delta_error_counts[errnum];
3383 com->delta_error_counts[errnum] = 0;
3384 mtx_unlock_spin(&sio_lock);
3385 if (delta == 0)
3386 continue;
3387 total = com->error_counts[errnum] += delta;
3388 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3389 unit, delta, error_desc[errnum],
3390 delta == 1 ? "" : "s", total);
3391 }
3392 }
3393 }
3394
3395 #ifdef PC98
3396 /* commint is called when modem control line changes */
3397 static void
commint(struct cdev * dev)3398 commint(struct cdev *dev)
3399 {
3400 register struct tty *tp;
3401 int stat,delta;
3402 struct com_s *com;
3403
3404 com = dev->si_drv1;
3405 tp = com->tp;
3406
3407 stat = com_tiocm_get(com);
3408 delta = com_tiocm_get_delta(com);
3409
3410 if (com->state & CS_CTS_OFLOW) {
3411 if (stat & TIOCM_CTS)
3412 com->state |= CS_ODEVREADY;
3413 else
3414 com->state &= ~CS_ODEVREADY;
3415 }
3416 if ((delta & TIOCM_CAR) && (ISCALLOUT(dev)) == 0) {
3417 if (stat & TIOCM_CAR )
3418 (void)ttyld_modem(tp, 1);
3419 else if (ttyld_modem(tp, 0) == 0) {
3420 /* negate DTR, RTS */
3421 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3422 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3423 /* disable IENABLE */
3424 com_int_TxRx_disable( com );
3425 }
3426 }
3427 }
3428 #endif
3429
3430 /*
3431 * Following are all routines needed for SIO to act as console
3432 */
3433 struct siocnstate {
3434 u_char dlbl;
3435 u_char dlbh;
3436 u_char ier;
3437 u_char cfcr;
3438 u_char mcr;
3439 };
3440
3441 /*
3442 * This is a function in order to not replicate "ttyd%d" more
3443 * places than absolutely necessary.
3444 */
3445 static void
siocnset(struct consdev * cd,int unit)3446 siocnset(struct consdev *cd, int unit)
3447 {
3448
3449 cd->cn_unit = unit;
3450 sprintf(cd->cn_name, "ttyd%d", unit);
3451 }
3452
3453 static speed_t siocngetspeed(Port_t, u_long rclk);
3454 static void siocnclose(struct siocnstate *sp, Port_t iobase);
3455 static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed);
3456 static void siocntxwait(Port_t iobase);
3457
3458 static cn_probe_t sio_cnprobe;
3459 static cn_init_t sio_cninit;
3460 static cn_term_t sio_cnterm;
3461 static cn_getc_t sio_cngetc;
3462 static cn_putc_t sio_cnputc;
3463 static cn_grab_t sio_cngrab;
3464 static cn_ungrab_t sio_cnungrab;
3465
3466 CONSOLE_DRIVER(sio);
3467
3468 static void
siocntxwait(iobase)3469 siocntxwait(iobase)
3470 Port_t iobase;
3471 {
3472 int timo;
3473
3474 /*
3475 * Wait for any pending transmission to finish. Required to avoid
3476 * the UART lockup bug when the speed is changed, and for normal
3477 * transmits.
3478 */
3479 timo = 100000;
3480 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3481 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3482 ;
3483 }
3484
3485 /*
3486 * Read the serial port specified and try to figure out what speed
3487 * it's currently running at. We're assuming the serial port has
3488 * been initialized and is basicly idle. This routine is only intended
3489 * to be run at system startup.
3490 *
3491 * If the value read from the serial port doesn't make sense, return 0.
3492 */
3493
3494 static speed_t
siocngetspeed(iobase,rclk)3495 siocngetspeed(iobase, rclk)
3496 Port_t iobase;
3497 u_long rclk;
3498 {
3499 u_int divisor;
3500 u_char dlbh;
3501 u_char dlbl;
3502 u_char cfcr;
3503
3504 cfcr = inb(iobase + com_cfcr);
3505 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3506
3507 dlbl = inb(iobase + com_dlbl);
3508 dlbh = inb(iobase + com_dlbh);
3509
3510 outb(iobase + com_cfcr, cfcr);
3511
3512 divisor = dlbh << 8 | dlbl;
3513
3514 /* XXX there should be more sanity checking. */
3515 if (divisor == 0)
3516 return (CONSPEED);
3517 return (rclk / (16UL * divisor));
3518 }
3519
3520 static void
siocnopen(sp,iobase,speed)3521 siocnopen(sp, iobase, speed)
3522 struct siocnstate *sp;
3523 Port_t iobase;
3524 int speed;
3525 {
3526 u_int divisor;
3527 u_char dlbh;
3528 u_char dlbl;
3529
3530 /*
3531 * Save all the device control registers except the fifo register
3532 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3533 * We can't save the fifo register since it is read-only.
3534 */
3535 sp->ier = inb(iobase + com_ier);
3536 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3537 siocntxwait(iobase);
3538 sp->cfcr = inb(iobase + com_cfcr);
3539 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3540 sp->dlbl = inb(iobase + com_dlbl);
3541 sp->dlbh = inb(iobase + com_dlbh);
3542 /*
3543 * Only set the divisor registers if they would change, since on
3544 * some 16550 incompatibles (Startech), setting them clears the
3545 * data input register. This also reduces the effects of the
3546 * UMC8669F bug.
3547 */
3548 divisor = siodivisor(comdefaultrclk, speed);
3549 dlbl = divisor & 0xFF;
3550 if (sp->dlbl != dlbl)
3551 outb(iobase + com_dlbl, dlbl);
3552 dlbh = divisor >> 8;
3553 if (sp->dlbh != dlbh)
3554 outb(iobase + com_dlbh, dlbh);
3555 outb(iobase + com_cfcr, CFCR_8BITS);
3556 sp->mcr = inb(iobase + com_mcr);
3557 /*
3558 * We don't want interrupts, but must be careful not to "disable"
3559 * them by clearing the MCR_IENABLE bit, since that might cause
3560 * an interrupt by floating the IRQ line.
3561 */
3562 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
3563 }
3564
3565 static void
siocnclose(sp,iobase)3566 siocnclose(sp, iobase)
3567 struct siocnstate *sp;
3568 Port_t iobase;
3569 {
3570 /*
3571 * Restore the device control registers.
3572 */
3573 siocntxwait(iobase);
3574 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3575 if (sp->dlbl != inb(iobase + com_dlbl))
3576 outb(iobase + com_dlbl, sp->dlbl);
3577 if (sp->dlbh != inb(iobase + com_dlbh))
3578 outb(iobase + com_dlbh, sp->dlbh);
3579 outb(iobase + com_cfcr, sp->cfcr);
3580 /*
3581 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
3582 */
3583 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
3584 outb(iobase + com_ier, sp->ier);
3585 }
3586
3587 static void
sio_cnprobe(cp)3588 sio_cnprobe(cp)
3589 struct consdev *cp;
3590 {
3591 speed_t boot_speed;
3592 u_char cfcr;
3593 u_int divisor;
3594 int s, unit;
3595 struct siocnstate sp;
3596
3597 /*
3598 * Find our first enabled console, if any. If it is a high-level
3599 * console device, then initialize it and return successfully.
3600 * If it is a low-level console device, then initialize it and
3601 * return unsuccessfully. It must be initialized in both cases
3602 * for early use by console drivers and debuggers. Initializing
3603 * the hardware is not necessary in all cases, since the i/o
3604 * routines initialize it on the fly, but it is necessary if
3605 * input might arrive while the hardware is switched back to an
3606 * uninitialized state. We can't handle multiple console devices
3607 * yet because our low-level routines don't take a device arg.
3608 * We trust the user to set the console flags properly so that we
3609 * don't need to probe.
3610 */
3611 cp->cn_pri = CN_DEAD;
3612
3613 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
3614 int flags;
3615
3616 if (resource_disabled("sio", unit))
3617 continue;
3618 if (resource_int_value("sio", unit, "flags", &flags))
3619 continue;
3620 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
3621 int port;
3622 Port_t iobase;
3623
3624 if (resource_int_value("sio", unit, "port", &port))
3625 continue;
3626 iobase = port;
3627 s = spltty();
3628 if ((boothowto & RB_SERIAL) && COM_CONSOLE(flags)) {
3629 boot_speed =
3630 siocngetspeed(iobase, comdefaultrclk);
3631 if (boot_speed)
3632 comdefaultrate = boot_speed;
3633 }
3634
3635 /*
3636 * Initialize the divisor latch. We can't rely on
3637 * siocnopen() to do this the first time, since it
3638 * avoids writing to the latch if the latch appears
3639 * to have the correct value. Also, if we didn't
3640 * just read the speed from the hardware, then we
3641 * need to set the speed in hardware so that
3642 * switching it later is null.
3643 */
3644 cfcr = inb(iobase + com_cfcr);
3645 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3646 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3647 outb(iobase + com_dlbl, divisor & 0xff);
3648 outb(iobase + com_dlbh, divisor >> 8);
3649 outb(iobase + com_cfcr, cfcr);
3650
3651 siocnopen(&sp, iobase, comdefaultrate);
3652
3653 splx(s);
3654 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
3655 siocnset(cp, unit);
3656 cp->cn_pri = COM_FORCECONSOLE(flags)
3657 || boothowto & RB_SERIAL
3658 ? CN_REMOTE : CN_NORMAL;
3659 siocniobase = iobase;
3660 siocnunit = unit;
3661 }
3662 #ifdef GDB
3663 if (COM_DEBUGGER(flags))
3664 siogdbiobase = iobase;
3665 #endif
3666 }
3667 }
3668 }
3669
3670 static void
sio_cninit(cp)3671 sio_cninit(cp)
3672 struct consdev *cp;
3673 {
3674 comconsole = cp->cn_unit;
3675 }
3676
3677 static void
sio_cnterm(cp)3678 sio_cnterm(cp)
3679 struct consdev *cp;
3680 {
3681 comconsole = -1;
3682 }
3683
3684 static void
sio_cngrab(struct consdev * cp)3685 sio_cngrab(struct consdev *cp)
3686 {
3687 }
3688
3689 static void
sio_cnungrab(struct consdev * cp)3690 sio_cnungrab(struct consdev *cp)
3691 {
3692 }
3693
3694 static int
sio_cngetc(struct consdev * cd)3695 sio_cngetc(struct consdev *cd)
3696 {
3697 int c;
3698 Port_t iobase;
3699 int s;
3700 struct siocnstate sp;
3701 speed_t speed;
3702
3703 if (cd != NULL && cd->cn_unit == siocnunit) {
3704 iobase = siocniobase;
3705 speed = comdefaultrate;
3706 } else {
3707 #ifdef GDB
3708 iobase = siogdbiobase;
3709 speed = gdbdefaultrate;
3710 #else
3711 return (-1);
3712 #endif
3713 }
3714 s = spltty();
3715 siocnopen(&sp, iobase, speed);
3716 if (inb(iobase + com_lsr) & LSR_RXRDY)
3717 c = inb(iobase + com_data);
3718 else
3719 c = -1;
3720 siocnclose(&sp, iobase);
3721 splx(s);
3722 return (c);
3723 }
3724
3725 static void
sio_cnputc(struct consdev * cd,int c)3726 sio_cnputc(struct consdev *cd, int c)
3727 {
3728 int need_unlock;
3729 int s;
3730 struct siocnstate sp;
3731 Port_t iobase;
3732 speed_t speed;
3733
3734 if (cd != NULL && cd->cn_unit == siocnunit) {
3735 iobase = siocniobase;
3736 speed = comdefaultrate;
3737 } else {
3738 #ifdef GDB
3739 iobase = siogdbiobase;
3740 speed = gdbdefaultrate;
3741 #else
3742 return;
3743 #endif
3744 }
3745 s = spltty();
3746 need_unlock = 0;
3747 if (!kdb_active && sio_inited == 2 && !mtx_owned(&sio_lock)) {
3748 mtx_lock_spin(&sio_lock);
3749 need_unlock = 1;
3750 }
3751 siocnopen(&sp, iobase, speed);
3752 siocntxwait(iobase);
3753 outb(iobase + com_data, c);
3754 siocnclose(&sp, iobase);
3755 if (need_unlock)
3756 mtx_unlock_spin(&sio_lock);
3757 splx(s);
3758 }
3759
3760 /*
3761 * Remote gdb(1) support.
3762 */
3763
3764 #if defined(GDB)
3765
3766 #include <gdb/gdb.h>
3767
3768 static gdb_probe_f siogdbprobe;
3769 static gdb_init_f siogdbinit;
3770 static gdb_term_f siogdbterm;
3771 static gdb_getc_f siogdbgetc;
3772 static gdb_putc_f siogdbputc;
3773
3774 GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbgetc, siogdbputc);
3775
3776 static int
siogdbprobe(void)3777 siogdbprobe(void)
3778 {
3779 return ((siogdbiobase != 0) ? 0 : -1);
3780 }
3781
3782 static void
siogdbinit(void)3783 siogdbinit(void)
3784 {
3785 }
3786
3787 static void
siogdbterm(void)3788 siogdbterm(void)
3789 {
3790 }
3791
3792 static void
siogdbputc(int c)3793 siogdbputc(int c)
3794 {
3795 sio_cnputc(NULL, c);
3796 }
3797
3798 static int
siogdbgetc(void)3799 siogdbgetc(void)
3800 {
3801 return (sio_cngetc(NULL));
3802 }
3803
3804 #endif
3805
3806 #ifdef PC98
3807 /*
3808 * pc98 local function
3809 */
3810 static void
com_tiocm_bis(struct com_s * com,int msr)3811 com_tiocm_bis(struct com_s *com, int msr)
3812 {
3813 int s;
3814 int tmp = 0;
3815
3816 s=spltty();
3817 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
3818 tmp |= CMD8251_TxEN|CMD8251_RxEN;
3819 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
3820 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
3821
3822 pc98_i8251_or_cmd( com, tmp );
3823 splx(s);
3824 }
3825
3826 static void
com_tiocm_bic(struct com_s * com,int msr)3827 com_tiocm_bic(struct com_s *com, int msr)
3828 {
3829 int s;
3830 int tmp = msr;
3831
3832 s=spltty();
3833 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
3834 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
3835 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
3836
3837 pc98_i8251_clear_cmd( com, tmp );
3838 splx(s);
3839 }
3840
3841 static int
com_tiocm_get(struct com_s * com)3842 com_tiocm_get(struct com_s *com)
3843 {
3844 return( com->pc98_prev_modem_status );
3845 }
3846
3847 static int
com_tiocm_get_delta(struct com_s * com)3848 com_tiocm_get_delta(struct com_s *com)
3849 {
3850 int tmp;
3851
3852 tmp = com->pc98_modem_delta;
3853 com->pc98_modem_delta = 0;
3854 return( tmp );
3855 }
3856
3857 /* convert to TIOCM_?? ( ioctl.h ) */
3858 static int
pc98_get_modem_status(struct com_s * com)3859 pc98_get_modem_status(struct com_s *com)
3860 {
3861 register int msr;
3862
3863 msr = com->pc98_prev_modem_status
3864 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
3865 if (com->pc98_8251fifo_enable) {
3866 int stat2;
3867
3868 stat2 = inb(I8251F_msr);
3869 if ( stat2 & MSR_DCD ) msr |= TIOCM_CAR;
3870 if ( stat2 & MSR_RI ) msr |= TIOCM_RI;
3871 if ( stat2 & MSR_DSR ) msr |= TIOCM_DSR;
3872 if ( stat2 & MSR_CTS ) msr |= TIOCM_CTS;
3873 #if COM_CARRIER_DETECT_EMULATE
3874 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
3875 msr |= TIOCM_CAR;
3876 }
3877 #endif
3878 } else {
3879 int stat, stat2;
3880
3881 stat = inb(com->sts_port);
3882 stat2 = inb(com->in_modem_port);
3883 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
3884 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
3885 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
3886 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
3887 #if COM_CARRIER_DETECT_EMULATE
3888 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
3889 msr |= TIOCM_CAR;
3890 }
3891 #endif
3892 }
3893 return(msr);
3894 }
3895
3896 static void
pc98_check_msr(void * chan)3897 pc98_check_msr(void* chan)
3898 {
3899 int msr, delta;
3900 int s;
3901 register struct tty *tp;
3902 struct com_s *com;
3903 struct cdev *dev;
3904
3905 dev=(struct cdev *)chan;
3906 com = dev->si_drv1;
3907 tp = dev->si_tty;
3908
3909 s = spltty();
3910 msr = pc98_get_modem_status(com);
3911 /* make change flag */
3912 delta = msr ^ com->pc98_prev_modem_status;
3913 if ( delta & TIOCM_CAR ) {
3914 if ( com->modem_car_chg_timer ) {
3915 if ( -- com->modem_car_chg_timer )
3916 msr ^= TIOCM_CAR;
3917 } else {
3918 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
3919 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
3920 msr ^= TIOCM_CAR;
3921 }
3922 } else
3923 com->modem_car_chg_timer = 0;
3924 delta = ( msr ^ com->pc98_prev_modem_status ) &
3925 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
3926 com->pc98_prev_modem_status = msr;
3927 delta = ( com->pc98_modem_delta |= delta );
3928 splx(s);
3929 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
3930 if ( delta ) {
3931 commint(dev);
3932 }
3933 timeout(pc98_check_msr, (caddr_t)dev,
3934 PC98_CHECK_MODEM_INTERVAL);
3935 } else {
3936 com->modem_checking = 0;
3937 }
3938 }
3939
3940 static void
pc98_msrint_start(struct cdev * dev)3941 pc98_msrint_start(struct cdev *dev)
3942 {
3943 struct com_s *com;
3944 int s = spltty();
3945
3946 com = dev->si_drv1;
3947 /* modem control line check routine envoke interval is 1/10 sec */
3948 if ( com->modem_checking == 0 ) {
3949 com->pc98_prev_modem_status = pc98_get_modem_status(com);
3950 com->pc98_modem_delta = 0;
3951 timeout(pc98_check_msr, (caddr_t)dev,
3952 PC98_CHECK_MODEM_INTERVAL);
3953 com->modem_checking = 1;
3954 }
3955 splx(s);
3956 }
3957
3958 static void
pc98_disable_i8251_interrupt(struct com_s * com,int mod)3959 pc98_disable_i8251_interrupt(struct com_s *com, int mod)
3960 {
3961 /* disable interrupt */
3962 register int tmp;
3963
3964 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
3965 COM_INT_DISABLE
3966 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
3967 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
3968 COM_INT_ENABLE
3969 }
3970
3971 static void
pc98_enable_i8251_interrupt(struct com_s * com,int mod)3972 pc98_enable_i8251_interrupt(struct com_s *com, int mod)
3973 {
3974 register int tmp;
3975
3976 COM_INT_DISABLE
3977 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
3978 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
3979 COM_INT_ENABLE
3980 }
3981
3982 static int
pc98_check_i8251_interrupt(struct com_s * com)3983 pc98_check_i8251_interrupt(struct com_s *com)
3984 {
3985 return ( com->intr_enable & 0x07 );
3986 }
3987
3988 static void
pc98_i8251_clear_cmd(struct com_s * com,int x)3989 pc98_i8251_clear_cmd(struct com_s *com, int x)
3990 {
3991 int tmp;
3992
3993 COM_INT_DISABLE
3994 tmp = com->pc98_prev_siocmd & ~(x);
3995 if (com->pc98_8251fifo_enable)
3996 outb(I8251F_fcr, 0);
3997 outb(com->cmd_port, tmp);
3998 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
3999 if (com->pc98_8251fifo_enable)
4000 outb(I8251F_fcr, FIFO_ENABLE);
4001 COM_INT_ENABLE
4002 }
4003
4004 static void
pc98_i8251_or_cmd(struct com_s * com,int x)4005 pc98_i8251_or_cmd(struct com_s *com, int x)
4006 {
4007 int tmp;
4008
4009 COM_INT_DISABLE
4010 if (com->pc98_8251fifo_enable)
4011 outb(I8251F_fcr, 0);
4012 tmp = com->pc98_prev_siocmd | (x);
4013 outb(com->cmd_port, tmp);
4014 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4015 if (com->pc98_8251fifo_enable)
4016 outb(I8251F_fcr, FIFO_ENABLE);
4017 COM_INT_ENABLE
4018 }
4019
4020 static void
pc98_i8251_set_cmd(struct com_s * com,int x)4021 pc98_i8251_set_cmd(struct com_s *com, int x)
4022 {
4023 int tmp;
4024
4025 COM_INT_DISABLE
4026 if (com->pc98_8251fifo_enable)
4027 outb(I8251F_fcr, 0);
4028 tmp = (x);
4029 outb(com->cmd_port, tmp);
4030 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4031 if (com->pc98_8251fifo_enable)
4032 outb(I8251F_fcr, FIFO_ENABLE);
4033 COM_INT_ENABLE
4034 }
4035
4036 static void
pc98_i8251_clear_or_cmd(struct com_s * com,int clr,int x)4037 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4038 {
4039 int tmp;
4040 COM_INT_DISABLE
4041 if (com->pc98_8251fifo_enable)
4042 outb(I8251F_fcr, 0);
4043 tmp = com->pc98_prev_siocmd & ~(clr);
4044 tmp |= (x);
4045 outb(com->cmd_port, tmp);
4046 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4047 if (com->pc98_8251fifo_enable)
4048 outb(I8251F_fcr, FIFO_ENABLE);
4049 COM_INT_ENABLE
4050 }
4051
4052 static int
pc98_i8251_get_cmd(struct com_s * com)4053 pc98_i8251_get_cmd(struct com_s *com)
4054 {
4055 return com->pc98_prev_siocmd;
4056 }
4057
4058 static int
pc98_i8251_get_mod(struct com_s * com)4059 pc98_i8251_get_mod(struct com_s *com)
4060 {
4061 return com->pc98_prev_siomod;
4062 }
4063
4064 static void
pc98_i8251_reset(struct com_s * com,int mode,int command)4065 pc98_i8251_reset(struct com_s *com, int mode, int command)
4066 {
4067 if (com->pc98_8251fifo_enable)
4068 outb(I8251F_fcr, 0);
4069 outb(com->cmd_port, 0); /* dummy */
4070 DELAY(2);
4071 outb(com->cmd_port, 0); /* dummy */
4072 DELAY(2);
4073 outb(com->cmd_port, 0); /* dummy */
4074 DELAY(2);
4075 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4076 DELAY(2);
4077 outb(com->cmd_port, mode ); /* mode register */
4078 com->pc98_prev_siomod = mode;
4079 DELAY(2);
4080 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4081 DELAY(10);
4082 if (com->pc98_8251fifo_enable)
4083 outb(I8251F_fcr, FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST);
4084 }
4085
4086 static void
pc98_check_sysclock(void)4087 pc98_check_sysclock(void)
4088 {
4089 /* get system clock from port */
4090 if ( pc98_machine_type & M_8M ) {
4091 /* 8 MHz system & H98 */
4092 sysclock = 8;
4093 } else {
4094 /* 5 MHz system */
4095 sysclock = 5;
4096 }
4097 }
4098
4099 static void
com_cflag_and_speed_set(struct com_s * com,int cflag,int speed)4100 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4101 {
4102 int cfcr=0;
4103 int previnterrupt;
4104 int tmp;
4105 u_int count;
4106
4107 if (pc98_ttspeedtab(com, speed, &count) != 0)
4108 return;
4109
4110 previnterrupt = pc98_check_i8251_interrupt(com);
4111 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4112
4113 switch ( cflag&CSIZE ) {
4114 case CS5:
4115 cfcr = MOD8251_5BITS; break;
4116 case CS6:
4117 cfcr = MOD8251_6BITS; break;
4118 case CS7:
4119 cfcr = MOD8251_7BITS; break;
4120 case CS8:
4121 cfcr = MOD8251_8BITS; break;
4122 }
4123 if ( cflag&PARENB ) {
4124 if ( cflag&PARODD )
4125 cfcr |= MOD8251_PENAB;
4126 else
4127 cfcr |= MOD8251_PENAB | MOD8251_PEVEN;
4128 }
4129
4130 if ( cflag&CSTOPB )
4131 cfcr |= MOD8251_STOP2;
4132 else
4133 cfcr |= MOD8251_STOP1;
4134
4135 if ( count & 0x10000 )
4136 cfcr |= MOD8251_CLKx1;
4137 else
4138 cfcr |= MOD8251_CLKx16;
4139
4140 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4141 ;
4142
4143 /* set baud rate from ospeed */
4144 pc98_set_baud_rate( com, count );
4145
4146 if ( cfcr != pc98_i8251_get_mod(com) )
4147 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4148
4149 pc98_enable_i8251_interrupt( com, previnterrupt );
4150 }
4151
4152 static int
pc98_ttspeedtab(struct com_s * com,int speed,u_int * divisor)4153 pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor)
4154 {
4155 int if_type, effect_sp, count = -1, mod;
4156
4157 if_type = com->pc98_if_type & 0x0f;
4158
4159 switch (com->pc98_if_type) {
4160 case COM_IF_INTERNAL:
4161 if (PC98SIO_baud_rate_port(if_type) != -1) {
4162 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4163 if (count > 0) {
4164 count |= COM1_EXT_CLOCK;
4165 break;
4166 }
4167 }
4168
4169 /* for *1CLK asynchronous! mode, TEFUTEFU */
4170 mod = (sysclock == 5) ? 2457600 : 1996800;
4171 effect_sp = ttspeedtab( speed, pc98speedtab );
4172 if ( effect_sp < 0 ) /* XXX */
4173 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4174 if ( effect_sp <= 0 )
4175 return effect_sp;
4176 if ( effect_sp == speed )
4177 mod /= 16;
4178 if ( mod % effect_sp )
4179 return(-1);
4180 count = mod / effect_sp;
4181 if ( count > 65535 )
4182 return(-1);
4183 if ( effect_sp != speed )
4184 count |= 0x10000;
4185 break;
4186 case COM_IF_PC9861K_1:
4187 case COM_IF_PC9861K_2:
4188 count = 1;
4189 break;
4190 case COM_IF_IND_SS_1:
4191 case COM_IF_IND_SS_2:
4192 case COM_IF_PIO9032B_1:
4193 case COM_IF_PIO9032B_2:
4194 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4195 break;
4196 case COM_IF_B98_01_1:
4197 case COM_IF_B98_01_2:
4198 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4199 #ifdef B98_01_OLD
4200 if (count == 0 || count == 1) {
4201 count += 4;
4202 count |= 0x20000; /* x1 mode for 76800 and 153600 */
4203 }
4204 #endif
4205 break;
4206 }
4207
4208 if (count < 0)
4209 return count;
4210
4211 *divisor = (u_int) count;
4212 return 0;
4213 }
4214
4215 static void
pc98_set_baud_rate(struct com_s * com,u_int count)4216 pc98_set_baud_rate( struct com_s *com, u_int count )
4217 {
4218 int if_type, io, s;
4219
4220 if_type = com->pc98_if_type & 0x0f;
4221 io = rman_get_start(com->ioportres) & 0xff00;
4222
4223 switch (com->pc98_if_type) {
4224 case COM_IF_INTERNAL:
4225 if (PC98SIO_baud_rate_port(if_type) != -1) {
4226 if (count & COM1_EXT_CLOCK) {
4227 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4228 break;
4229 } else {
4230 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4231 }
4232 }
4233
4234 if (count == 0)
4235 return;
4236
4237 /* set i8253 */
4238 s = splclock();
4239 if (count != 3)
4240 outb( 0x77, 0xb6 );
4241 else
4242 outb( 0x77, 0xb4 );
4243 outb( 0x5f, 0);
4244 outb( 0x75, count & 0xff );
4245 outb( 0x5f, 0);
4246 outb( 0x75, (count >> 8) & 0xff );
4247 splx(s);
4248 break;
4249 case COM_IF_IND_SS_1:
4250 case COM_IF_IND_SS_2:
4251 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4252 outb(io | PC98SIO_baud_rate_port(if_type), 0);
4253 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4254 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4255 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4256 break;
4257 case COM_IF_PIO9032B_1:
4258 case COM_IF_PIO9032B_2:
4259 outb(io | PC98SIO_baud_rate_port(if_type), count);
4260 break;
4261 case COM_IF_B98_01_1:
4262 case COM_IF_B98_01_2:
4263 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4264 #ifdef B98_01_OLD
4265 /*
4266 * Some old B98_01 board should be controlled
4267 * in different way, but this hasn't been tested yet.
4268 */
4269 outb(io | PC98SIO_func_port(if_type),
4270 (count & 0x20000) ? 0xf0 : 0xf2);
4271 #endif
4272 break;
4273 }
4274 }
4275 static int
pc98_check_if_type(device_t dev,struct siodev * iod)4276 pc98_check_if_type(device_t dev, struct siodev *iod)
4277 {
4278 int irr, io, if_type, tmp;
4279 static short irq_tab[2][8] = {
4280 { 3, 5, 6, 9, 10, 12, 13, -1},
4281 { 3, 10, 12, 13, 5, 6, 9, -1}
4282 };
4283
4284 if_type = iod->if_type & 0x0f;
4285 iod->irq = 0;
4286 io = isa_get_port(dev) & 0xff00;
4287
4288 if (IS_8251(iod->if_type)) {
4289 if (PC98SIO_func_port(if_type) != -1) {
4290 outb(io | PC98SIO_func_port(if_type), 0xf2);
4291 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4292 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4293 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4294 }
4295
4296 iod->cmd = io | PC98SIO_cmd_port(if_type);
4297 iod->sts = io | PC98SIO_sts_port(if_type);
4298 iod->mod = io | PC98SIO_in_modem_port(if_type);
4299 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4300
4301 if (iod->if_type == COM_IF_INTERNAL) {
4302 iod->irq = 4;
4303
4304 if (pc98_check_8251vfast()) {
4305 PC98SIO_baud_rate_port(if_type) = I8251F_div;
4306 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4307 }
4308 } else {
4309 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4310 if ((isa_get_port(dev) & 0xff) == IO_COM2)
4311 iod->irq = irq_tab[0][tmp];
4312 else
4313 iod->irq = irq_tab[1][tmp];
4314 }
4315 } else {
4316 irr = if_16550a_type[if_type].irr_read;
4317 #ifdef COM_MULTIPORT
4318 if (!COM_ISMULTIPORT(device_get_flags(dev)) ||
4319 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev)))
4320 #endif
4321 if (irr != -1) {
4322 tmp = inb(io | irr);
4323 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
4324 iod->irq = irq_tab[1][tmp >> 3];
4325 else
4326 iod->irq = irq_tab[0][tmp & 0x07];
4327 }
4328 iod->cmd = 0;
4329 iod->sts = 0;
4330 iod->mod = 0;
4331 iod->ctrl = 0;
4332 }
4333 if ( iod->irq == -1 ) return -1;
4334
4335 return 0;
4336 }
4337 static void
pc98_set_ioport(struct com_s * com)4338 pc98_set_ioport(struct com_s *com)
4339 {
4340 int if_type = com->pc98_if_type & 0x0f;
4341 Port_t io = rman_get_start(com->ioportres) & 0xff00;
4342
4343 pc98_check_sysclock();
4344 com->data_port = io | PC98SIO_data_port(if_type);
4345 com->cmd_port = io | PC98SIO_cmd_port(if_type);
4346 com->sts_port = io | PC98SIO_sts_port(if_type);
4347 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
4348 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
4349 }
4350 static int
pc98_check_8251vfast(void)4351 pc98_check_8251vfast(void)
4352 {
4353 int i;
4354
4355 outb(I8251F_div, 0x8c);
4356 DELAY(10);
4357 for (i = 0; i < 100; i++) {
4358 if ((inb(I8251F_div) & 0x80) != 0) {
4359 i = 0;
4360 break;
4361 }
4362 DELAY(1);
4363 }
4364 outb(I8251F_div, 0);
4365 DELAY(10);
4366 for (; i < 100; i++) {
4367 if ((inb(I8251F_div) & 0x80) == 0)
4368 return 1;
4369 DELAY(1);
4370 }
4371
4372 return 0;
4373 }
4374 static int
pc98_check_8251fifo(void)4375 pc98_check_8251fifo(void)
4376 {
4377 u_char tmp1, tmp2;
4378
4379 tmp1 = inb(I8251F_iir);
4380 DELAY(10);
4381 tmp2 = inb(I8251F_iir);
4382 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0)
4383 return 1;
4384
4385 return 0;
4386 }
4387 #endif /* PC98 defined */
4388