1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef _DCE_CLOCKS_H_ 28 #define _DCE_CLOCKS_H_ 29 30 #include "display_clock.h" 31 32 #define CLK_COMMON_REG_LIST_DCE_BASE() \ 33 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \ 34 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL 35 36 #define CLK_COMMON_REG_LIST_DCN_BASE() \ 37 SR(DENTIST_DISPCLK_CNTL) 38 39 #define CLK_SF(reg_name, field_name, post_fix)\ 40 .field_name = reg_name ## __ ## field_name ## post_fix 41 42 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 43 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ 44 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh) 45 46 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ 47 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ 48 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) 49 50 #define CLK_REG_FIELD_LIST(type) \ 51 type DPREFCLK_SRC_SEL; \ 52 type DENTIST_DPREFCLK_WDIVIDER; \ 53 type DENTIST_DISPCLK_WDIVIDER; \ 54 type DENTIST_DISPCLK_CHG_DONE; 55 56 struct dccg_shift { 57 CLK_REG_FIELD_LIST(uint8_t) 58 }; 59 60 struct dccg_mask { 61 CLK_REG_FIELD_LIST(uint32_t) 62 }; 63 64 struct dccg_registers { 65 uint32_t DPREFCLK_CNTL; 66 uint32_t DENTIST_DISPCLK_CNTL; 67 }; 68 69 struct dce_dccg { 70 struct dccg base; 71 const struct dccg_registers *regs; 72 const struct dccg_shift *clk_shift; 73 const struct dccg_mask *clk_mask; 74 75 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES]; 76 77 int dentist_vco_freq_khz; 78 79 /* Cache the status of DFS-bypass feature*/ 80 bool dfs_bypass_enabled; 81 /* Cache the display clock returned by VBIOS if DFS-bypass is enabled. 82 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */ 83 int dfs_bypass_disp_clk; 84 85 /* Flag for Enabled SS on DPREFCLK */ 86 bool ss_on_dprefclk; 87 /* DPREFCLK SS percentage (if down-spread enabled) */ 88 int dprefclk_ss_percentage; 89 /* DPREFCLK SS percentage Divider (100 or 1000) */ 90 int dprefclk_ss_divider; 91 }; 92 93 94 struct dccg *dce_dccg_create( 95 struct dc_context *ctx, 96 const struct dccg_registers *regs, 97 const struct dccg_shift *clk_shift, 98 const struct dccg_mask *clk_mask); 99 100 struct dccg *dce110_dccg_create( 101 struct dc_context *ctx, 102 const struct dccg_registers *regs, 103 const struct dccg_shift *clk_shift, 104 const struct dccg_mask *clk_mask); 105 106 struct dccg *dce112_dccg_create( 107 struct dc_context *ctx, 108 const struct dccg_registers *regs, 109 const struct dccg_shift *clk_shift, 110 const struct dccg_mask *clk_mask); 111 112 struct dccg *dce120_dccg_create(struct dc_context *ctx); 113 114 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 115 struct dccg *dcn1_dccg_create(struct dc_context *ctx); 116 #endif 117 118 void dce_dccg_destroy(struct dccg **dccg); 119 120 #endif /* _DCE_CLOCKS_H_ */ 121