1 /*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * machdep.c
38 *
39 * Machine dependent functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46 #include "opt_kstack_pages.h"
47 #include "opt_platform.h"
48
49 #include <sys/cdefs.h>
50 __FBSDID("$FreeBSD$");
51
52 #define _ARM32_BUS_DMA_PRIVATE
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/sysproto.h>
56 #include <sys/signalvar.h>
57 #include <sys/imgact.h>
58 #include <sys/kernel.h>
59 #include <sys/ktr.h>
60 #include <sys/linker.h>
61 #include <sys/lock.h>
62 #include <sys/malloc.h>
63 #include <sys/mutex.h>
64 #include <sys/pcpu.h>
65 #include <sys/proc.h>
66 #include <sys/ptrace.h>
67 #include <sys/cons.h>
68 #include <sys/bio.h>
69 #include <sys/bus.h>
70 #include <sys/buf.h>
71 #include <sys/exec.h>
72 #include <sys/kdb.h>
73 #include <sys/msgbuf.h>
74 #include <sys/devmap.h>
75 #include <machine/physmem.h>
76 #include <machine/reg.h>
77 #include <machine/cpu.h>
78 #include <machine/board.h>
79
80 #include <vm/vm.h>
81 #include <vm/pmap.h>
82 #include <vm/vm_object.h>
83 #include <vm/vm_page.h>
84 #include <vm/vm_map.h>
85 #include <machine/vmparam.h>
86 #include <machine/pcb.h>
87 #include <machine/undefined.h>
88 #include <machine/machdep.h>
89 #include <machine/metadata.h>
90 #include <machine/armreg.h>
91 #include <machine/bus.h>
92 #include <sys/reboot.h>
93
94 #include <arm/at91/at91board.h>
95 #include <arm/at91/at91var.h>
96 #include <arm/at91/at91soc.h>
97 #include <arm/at91/at91_usartreg.h>
98 #include <arm/at91/at91rm92reg.h>
99 #include <arm/at91/at91sam9g20reg.h>
100 #include <arm/at91/at91sam9g45reg.h>
101
102 #ifndef MAXCPU
103 #define MAXCPU 1
104 #endif
105
106 /* Page table for mapping proc0 zero page */
107 #define KERNEL_PT_SYS 0
108 #define KERNEL_PT_KERN 1
109 #define KERNEL_PT_KERN_NUM 22
110 /* L2 table for mapping after kernel */
111 #define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
112 #define KERNEL_PT_AFKERNEL_NUM 5
113
114 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
115 #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
116
117 struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
118
119 /* Static device mappings. */
120 const struct devmap_entry at91_devmap[] = {
121 /*
122 * Map the critical on-board devices. The interrupt vector at
123 * 0xffff0000 makes it impossible to map them PA == VA, so we map all
124 * 0xfffxxxxx addresses to 0xdffxxxxx. This covers all critical devices
125 * on all members of the AT91SAM9 and AT91RM9200 families.
126 */
127 {
128 0xdff00000,
129 0xfff00000,
130 0x00100000,
131 },
132 /* There's a notion that we should do the rest of these lazily. */
133 /*
134 * We can't just map the OHCI registers VA == PA, because
135 * AT91xx_xxx_BASE belongs to the userland address space.
136 * We could just choose a different virtual address, but a better
137 * solution would probably be to just use pmap_mapdev() to allocate
138 * KVA, as we don't need the OHCI controller before the vm
139 * initialization is done. However, the AT91 resource allocation
140 * system doesn't know how to use pmap_mapdev() yet.
141 * Care must be taken to ensure PA and VM address do not overlap
142 * between entries.
143 */
144 {
145 /*
146 * Add the ohci controller, and anything else that might be
147 * on this chip select for a VA/PA mapping.
148 */
149 /* Internal Memory 1MB */
150 AT91RM92_OHCI_VA_BASE,
151 AT91RM92_OHCI_BASE,
152 0x00100000,
153 },
154 {
155 /* CompactFlash controller. Portion of EBI CS4 1MB */
156 AT91RM92_CF_VA_BASE,
157 AT91RM92_CF_BASE,
158 0x00100000,
159 },
160 /*
161 * The next two should be good for the 9260, 9261 and 9G20 since
162 * addresses mapping is the same.
163 */
164 {
165 /* Internal Memory 1MB */
166 AT91SAM9G20_OHCI_VA_BASE,
167 AT91SAM9G20_OHCI_BASE,
168 0x00100000,
169 },
170 {
171 /* EBI CS3 256MB */
172 AT91SAM9G20_NAND_VA_BASE,
173 AT91SAM9G20_NAND_BASE,
174 AT91SAM9G20_NAND_SIZE,
175 },
176 /*
177 * The next should be good for the 9G45.
178 */
179 {
180 /* Internal Memory 1MB */
181 AT91SAM9G45_OHCI_VA_BASE,
182 AT91SAM9G45_OHCI_BASE,
183 0x00100000,
184 },
185 { 0, 0, 0, }
186 };
187
188 #ifdef LINUX_BOOT_ABI
189 static int membanks;
190 static int memsize[];
191 #endif
192
193 long
at91_ramsize(void)194 at91_ramsize(void)
195 {
196 uint32_t cr, mdr, mr, *SDRAMC;
197 int banks, rows, cols, bw;
198 #ifdef LINUX_BOOT_ABI
199 /*
200 * If we found any ATAGs that were for memory, return the first bank.
201 */
202 if (membanks > 0)
203 return (memsize[0]);
204 #endif
205
206 if (at91_is_rm92()) {
207 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
208 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
209 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
210 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
211 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
212 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
213 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
214 } else if (at91_cpu_is(AT91_T_SAM9G45)) {
215 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE);
216 cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4];
217 mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4];
218 banks = 0;
219 rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11;
220 cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8;
221 bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2;
222
223 /* Fix the calculation for DDR memory */
224 mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK;
225 if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 ||
226 mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) {
227 /* The cols value is 1 higher for DDR */
228 cols += 1;
229 /* DDR has 4 internal banks. */
230 banks = 2;
231 }
232 } else {
233 /*
234 * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
235 * as addresses and registers are the same.
236 */
237 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
238 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
239 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
240 banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
241 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
242 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
243 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
244 }
245
246 return (1 << (cols + rows + banks + bw));
247 }
248
249 static const char *soc_type_name[] = {
250 [AT91_T_CAP9] = "at91cap9",
251 [AT91_T_RM9200] = "at91rm9200",
252 [AT91_T_SAM9260] = "at91sam9260",
253 [AT91_T_SAM9261] = "at91sam9261",
254 [AT91_T_SAM9263] = "at91sam9263",
255 [AT91_T_SAM9G10] = "at91sam9g10",
256 [AT91_T_SAM9G20] = "at91sam9g20",
257 [AT91_T_SAM9G45] = "at91sam9g45",
258 [AT91_T_SAM9N12] = "at91sam9n12",
259 [AT91_T_SAM9RL] = "at91sam9rl",
260 [AT91_T_SAM9X5] = "at91sam9x5",
261 [AT91_T_NONE] = "UNKNOWN"
262 };
263
264 static const char *soc_subtype_name[] = {
265 [AT91_ST_NONE] = "UNKNOWN",
266 [AT91_ST_RM9200_BGA] = "at91rm9200_bga",
267 [AT91_ST_RM9200_PQFP] = "at91rm9200_pqfp",
268 [AT91_ST_SAM9XE] = "at91sam9xe",
269 [AT91_ST_SAM9G45] = "at91sam9g45",
270 [AT91_ST_SAM9M10] = "at91sam9m10",
271 [AT91_ST_SAM9G46] = "at91sam9g46",
272 [AT91_ST_SAM9M11] = "at91sam9m11",
273 [AT91_ST_SAM9G15] = "at91sam9g15",
274 [AT91_ST_SAM9G25] = "at91sam9g25",
275 [AT91_ST_SAM9G35] = "at91sam9g35",
276 [AT91_ST_SAM9X25] = "at91sam9x25",
277 [AT91_ST_SAM9X35] = "at91sam9x35",
278 };
279
280 struct at91_soc_info soc_info;
281
282 /*
283 * Read the SoC ID from the CIDR register and try to match it against the
284 * values we know. If we find a good one, we return true. If not, we
285 * return false. When we find a good one, we also find the subtype
286 * and CPU family.
287 */
288 static int
at91_try_id(uint32_t dbgu_base)289 at91_try_id(uint32_t dbgu_base)
290 {
291 uint32_t socid;
292
293 soc_info.cidr = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
294 DBGU_C1R);
295 socid = soc_info.cidr & ~AT91_CPU_VERSION_MASK;
296
297 soc_info.type = AT91_T_NONE;
298 soc_info.subtype = AT91_ST_NONE;
299 soc_info.family = (soc_info.cidr & AT91_CPU_FAMILY_MASK) >> 20;
300 soc_info.exid = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
301 DBGU_C2R);
302
303 switch (socid) {
304 case AT91_CPU_CAP9:
305 soc_info.type = AT91_T_CAP9;
306 break;
307 case AT91_CPU_RM9200:
308 soc_info.type = AT91_T_RM9200;
309 break;
310 case AT91_CPU_SAM9XE128:
311 case AT91_CPU_SAM9XE256:
312 case AT91_CPU_SAM9XE512:
313 case AT91_CPU_SAM9260:
314 soc_info.type = AT91_T_SAM9260;
315 if (soc_info.family == AT91_FAMILY_SAM9XE)
316 soc_info.subtype = AT91_ST_SAM9XE;
317 break;
318 case AT91_CPU_SAM9261:
319 soc_info.type = AT91_T_SAM9261;
320 break;
321 case AT91_CPU_SAM9263:
322 soc_info.type = AT91_T_SAM9263;
323 break;
324 case AT91_CPU_SAM9G10:
325 soc_info.type = AT91_T_SAM9G10;
326 break;
327 case AT91_CPU_SAM9G20:
328 soc_info.type = AT91_T_SAM9G20;
329 break;
330 case AT91_CPU_SAM9G45:
331 soc_info.type = AT91_T_SAM9G45;
332 break;
333 case AT91_CPU_SAM9N12:
334 soc_info.type = AT91_T_SAM9N12;
335 break;
336 case AT91_CPU_SAM9RL64:
337 soc_info.type = AT91_T_SAM9RL;
338 break;
339 case AT91_CPU_SAM9X5:
340 soc_info.type = AT91_T_SAM9X5;
341 break;
342 default:
343 return (0);
344 }
345
346 switch (soc_info.type) {
347 case AT91_T_SAM9G45:
348 switch (soc_info.exid) {
349 case AT91_EXID_SAM9G45:
350 soc_info.subtype = AT91_ST_SAM9G45;
351 break;
352 case AT91_EXID_SAM9G46:
353 soc_info.subtype = AT91_ST_SAM9G46;
354 break;
355 case AT91_EXID_SAM9M10:
356 soc_info.subtype = AT91_ST_SAM9M10;
357 break;
358 case AT91_EXID_SAM9M11:
359 soc_info.subtype = AT91_ST_SAM9M11;
360 break;
361 }
362 break;
363 case AT91_T_SAM9X5:
364 switch (soc_info.exid) {
365 case AT91_EXID_SAM9G15:
366 soc_info.subtype = AT91_ST_SAM9G15;
367 break;
368 case AT91_EXID_SAM9G25:
369 soc_info.subtype = AT91_ST_SAM9G25;
370 break;
371 case AT91_EXID_SAM9G35:
372 soc_info.subtype = AT91_ST_SAM9G35;
373 break;
374 case AT91_EXID_SAM9X25:
375 soc_info.subtype = AT91_ST_SAM9X25;
376 break;
377 case AT91_EXID_SAM9X35:
378 soc_info.subtype = AT91_ST_SAM9X35;
379 break;
380 }
381 break;
382 default:
383 break;
384 }
385 /*
386 * Disable interrupts in the DBGU unit...
387 */
388 *(volatile uint32_t *)(AT91_BASE + dbgu_base + USART_IDR) = 0xffffffff;
389
390 /*
391 * Save the name for later...
392 */
393 snprintf(soc_info.name, sizeof(soc_info.name), "%s%s%s",
394 soc_type_name[soc_info.type],
395 soc_info.subtype == AT91_ST_NONE ? "" : " subtype ",
396 soc_info.subtype == AT91_ST_NONE ? "" :
397 soc_subtype_name[soc_info.subtype]);
398
399 /*
400 * try to get the matching CPU support.
401 */
402 soc_info.soc_data = at91_match_soc(soc_info.type, soc_info.subtype);
403 soc_info.dbgu_base = AT91_BASE + dbgu_base;
404
405 return (1);
406 }
407
408 void
at91_soc_id(void)409 at91_soc_id(void)
410 {
411
412 if (!at91_try_id(AT91_DBGU0))
413 at91_try_id(AT91_DBGU1);
414 }
415
416 #ifdef ARM_MANY_BOARD
417 /* likely belongs in arm/arm/machdep.c, but since board_init is still at91 only... */
418 SET_DECLARE(arm_board_set, const struct arm_board);
419
420 /* Not yet fully functional, but enough to build ATMEL config */
421 static long
board_init(void)422 board_init(void)
423 {
424 return -1;
425 }
426 #endif
427
428 #ifndef FDT
429 /* Physical and virtual addresses for some global pages */
430
431 struct pv_addr msgbufpv;
432 struct pv_addr kernelstack;
433 struct pv_addr systempage;
434 struct pv_addr irqstack;
435 struct pv_addr abtstack;
436 struct pv_addr undstack;
437
438 void *
initarm(struct arm_boot_params * abp)439 initarm(struct arm_boot_params *abp)
440 {
441 struct pv_addr kernel_l1pt;
442 struct pv_addr dpcpu;
443 int i;
444 u_int l1pagetable;
445 vm_offset_t freemempos;
446 vm_offset_t afterkern;
447 uint32_t memsize;
448 vm_offset_t lastaddr;
449
450 lastaddr = parse_boot_param(abp);
451 arm_physmem_kernaddr = abp->abp_physaddr;
452 set_cpufuncs();
453 pcpu0_init();
454
455 /* Do basic tuning, hz etc */
456 init_param1();
457
458 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
459 /* Define a macro to simplify memory allocation */
460 #define valloc_pages(var, np) \
461 alloc_pages((var).pv_va, (np)); \
462 (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
463
464 #define alloc_pages(var, np) \
465 (var) = freemempos; \
466 freemempos += (np * PAGE_SIZE); \
467 memset((char *)(var), 0, ((np) * PAGE_SIZE));
468
469 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
470 freemempos += PAGE_SIZE;
471 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
472 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
473 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
474 valloc_pages(kernel_pt_table[i],
475 L2_TABLE_SIZE / PAGE_SIZE);
476 } else {
477 kernel_pt_table[i].pv_va = freemempos -
478 (i % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
479 L2_TABLE_SIZE_REAL;
480 kernel_pt_table[i].pv_pa =
481 kernel_pt_table[i].pv_va - KERNVIRTADDR +
482 abp->abp_physaddr;
483 }
484 }
485 /*
486 * Allocate a page for the system page mapped to 0x00000000
487 * or 0xffff0000. This page will just contain the system vectors
488 * and can be shared by all processes.
489 */
490 valloc_pages(systempage, 1);
491
492 /* Allocate dynamic per-cpu area. */
493 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
494 dpcpu_init((void *)dpcpu.pv_va, 0);
495
496 /* Allocate stacks for all modes */
497 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU);
498 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU);
499 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU);
500 valloc_pages(kernelstack, kstack_pages * MAXCPU);
501 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
502
503 /*
504 * Now we start construction of the L1 page table
505 * We start by mapping the L2 page tables into the L1.
506 * This means that we can replace L1 mappings later on if necessary
507 */
508 l1pagetable = kernel_l1pt.pv_va;
509
510 /* Map the L2 pages tables in the L1 page table */
511 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
512 &kernel_pt_table[KERNEL_PT_SYS]);
513 for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
514 pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
515 &kernel_pt_table[KERNEL_PT_KERN + i]);
516 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
517 rounddown2(((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE, PAGE_SIZE),
518 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
519 afterkern = round_page(rounddown2(lastaddr + L1_S_SIZE, L1_S_SIZE));
520 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
521 pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
522 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
523 }
524
525 /* Map the vector page. */
526 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
527 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
528
529 /* Map the DPCPU pages */
530 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
531 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
532
533 /* Map the stack pages */
534 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
535 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
536 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
537 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
538 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
539 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
540 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
541 kstack_pages * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
542
543 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
544 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
545 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
546 msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
547
548 for (i = 0; i < NUM_KERNEL_PTS; ++i) {
549 pmap_map_chunk(l1pagetable, kernel_pt_table[i].pv_va,
550 kernel_pt_table[i].pv_pa, L2_TABLE_SIZE,
551 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
552 }
553
554 devmap_bootstrap(l1pagetable, at91_devmap);
555 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
556 cpu_setttb(kernel_l1pt.pv_pa);
557 cpu_tlb_flushID();
558 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
559
560 at91_soc_id();
561
562 /*
563 * Initialize all the clocks, so that the console can work. We can only
564 * do this if at91_soc_id() was able to fill in the support data. Even
565 * if we can't init the clocks, still try to do a console init so we can
566 * try to print the error message about missing soc support. There's a
567 * chance the printf will work if the bootloader set up the DBGU.
568 */
569 if (soc_info.soc_data != NULL) {
570 soc_info.soc_data->soc_clock_init();
571 at91_pmc_init_clock();
572 }
573
574 cninit();
575
576 if (soc_info.soc_data == NULL)
577 printf("Warning: No soc support for %s found.\n", soc_info.name);
578
579 memsize = board_init();
580 if (memsize == -1) {
581 printf("board_init() failed, cannot determine ram size; "
582 "assuming 16MB\n");
583 memsize = 16 * 1024 * 1024;
584 }
585
586 /* Enable MMU (set SCTLR), and do other cpu-specific setup. */
587 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
588 cpu_setup();
589
590 /*
591 * Pages were allocated during the secondary bootstrap for the
592 * stacks for different CPU modes.
593 * We must now set the r13 registers in the different CPU modes to
594 * point to these stacks.
595 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
596 * of the stack memory.
597 */
598 set_stackptrs(0);
599
600 /*
601 * We must now clean the cache again....
602 * Cleaning may be done by reading new data to displace any
603 * dirty data in the cache. This will have happened in cpu_setttb()
604 * but since we are boot strapping the addresses used for the read
605 * may have just been remapped and thus the cache could be out
606 * of sync. A re-clean after the switch will cure this.
607 * After booting there are no gross relocations of the kernel thus
608 * this problem will not occur after initarm().
609 */
610 cpu_idcache_wbinv_all();
611
612 undefined_init();
613
614 init_proc0(kernelstack.pv_va);
615
616 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
617
618 pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1);
619 /* Always use the 256MB of KVA we have available between the kernel and devices */
620 vm_max_kernel_address = KERNVIRTADDR + (256 << 20);
621 pmap_bootstrap(freemempos, &kernel_l1pt);
622 msgbufp = (void*)msgbufpv.pv_va;
623 msgbufinit(msgbufp, msgbufsize);
624 mutex_init();
625
626 /*
627 * Add the physical ram we have available.
628 *
629 * Exclude the kernel, and all the things we allocated which immediately
630 * follow the kernel, from the VM allocation pool but not from crash
631 * dumps. virtual_avail is a global variable which tracks the kva we've
632 * "allocated" while setting up pmaps.
633 *
634 * Prepare the list of physical memory available to the vm subsystem.
635 */
636 arm_physmem_hardware_region(PHYSADDR, memsize);
637 arm_physmem_exclude_region(abp->abp_physaddr,
638 virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
639 arm_physmem_init_kernel_globals();
640
641 init_param2(physmem);
642 kdb_init();
643 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
644 sizeof(struct pcb)));
645 }
646 #endif
647
648 /*
649 * These functions are handled elsewhere, so make them nops here.
650 */
651 void
cpu_startprofclock(void)652 cpu_startprofclock(void)
653 {
654
655 }
656
657 void
cpu_stopprofclock(void)658 cpu_stopprofclock(void)
659 {
660
661 }
662
663 void
cpu_initclocks(void)664 cpu_initclocks(void)
665 {
666
667 }
668
669 void
DELAY(int n)670 DELAY(int n)
671 {
672
673 if (soc_info.soc_data)
674 soc_info.soc_data->soc_delay(n);
675 }
676
677 void
cpu_reset(void)678 cpu_reset(void)
679 {
680
681 if (soc_info.soc_data)
682 soc_info.soc_data->soc_reset();
683 while (1)
684 continue;
685 }
686