1 /*-
2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Gardner Buchanan.
16 * 4. The name of Gardner Buchanan may not be used to endorse or promote
17 * products derived from this software without specific prior written
18 * permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 /*
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
37 *
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
43 *
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
48 *
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
52 * AUI/TP selection
53 *
54 * Authors:
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
60 *
61 * Sources:
62 * o SMC databook
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
65 *
66 * Known Bugs:
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
69 */
70
71 /*
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
73 *
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
76 */
77 /*
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
80 */
81
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/errno.h>
85 #include <sys/kernel.h>
86 #include <sys/sockio.h>
87 #include <sys/malloc.h>
88 #include <sys/mbuf.h>
89 #include <sys/socket.h>
90 #include <sys/syslog.h>
91
92 #include <sys/module.h>
93 #include <sys/bus.h>
94
95 #include <machine/bus.h>
96 #include <machine/resource.h>
97 #include <sys/rman.h>
98
99 #include <net/ethernet.h>
100 #include <net/if.h>
101 #include <net/if_var.h>
102 #include <net/if_arp.h>
103 #include <net/if_dl.h>
104 #include <net/if_types.h>
105 #include <net/if_mib.h>
106
107 #ifdef INET
108 #include <netinet/in.h>
109 #include <netinet/in_systm.h>
110 #include <netinet/in_var.h>
111 #include <netinet/ip.h>
112 #endif
113
114 #include <net/bpf.h>
115 #include <net/bpfdesc.h>
116
117 #include <dev/sn/if_snreg.h>
118 #include <dev/sn/if_snvar.h>
119
120 /* Exported variables */
121 devclass_t sn_devclass;
122
123 static int snioctl(struct ifnet * ifp, u_long, caddr_t);
124
125 static void snresume(struct ifnet *);
126
127 static void snintr_locked(struct sn_softc *);
128 static void sninit_locked(void *);
129 static void snstart_locked(struct ifnet *);
130
131 static void sninit(void *);
132 static void snread(struct ifnet *);
133 static void snstart(struct ifnet *);
134 static void snstop(struct sn_softc *);
135 static void snwatchdog(void *);
136
137 static void sn_setmcast(struct sn_softc *);
138 static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
139
140 /* I (GB) have been unlucky getting the hardware padding
141 * to work properly.
142 */
143 #define SW_PAD
144
145 static const char *chip_ids[15] = {
146 NULL, NULL, NULL,
147 /* 3 */ "SMC91C90/91C92",
148 /* 4 */ "SMC91C94/91C96",
149 /* 5 */ "SMC91C95",
150 NULL,
151 /* 7 */ "SMC91C100",
152 /* 8 */ "SMC91C100FD",
153 /* 9 */ "SMC91C110",
154 NULL, NULL,
155 NULL, NULL, NULL
156 };
157
158 int
sn_attach(device_t dev)159 sn_attach(device_t dev)
160 {
161 struct sn_softc *sc = device_get_softc(dev);
162 struct ifnet *ifp;
163 uint16_t i;
164 uint8_t *p;
165 int rev;
166 uint16_t address;
167 int err;
168 u_char eaddr[6];
169
170 ifp = sc->ifp = if_alloc(IFT_ETHER);
171 if (ifp == NULL) {
172 device_printf(dev, "can not if_alloc()\n");
173 return (ENOSPC);
174 }
175
176 SN_LOCK_INIT(sc);
177 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
178 snstop(sc);
179 sc->pages_wanted = -1;
180
181 if (bootverbose || 1) {
182 SMC_SELECT_BANK(sc, 3);
183 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
184 if (chip_ids[rev])
185 device_printf(dev, " %s ", chip_ids[rev]);
186 else
187 device_printf(dev, " unsupported chip: rev %d ", rev);
188 SMC_SELECT_BANK(sc, 1);
189 i = CSR_READ_2(sc, CONFIG_REG_W);
190 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
191 }
192
193 /*
194 * Read the station address from the chip. The MAC address is bank 1,
195 * regs 4 - 9
196 */
197 SMC_SELECT_BANK(sc, 1);
198 p = (uint8_t *) eaddr;
199 for (i = 0; i < 6; i += 2) {
200 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
201 p[i + 1] = address >> 8;
202 p[i] = address & 0xFF;
203 }
204 ifp->if_softc = sc;
205 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
206 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
207 ifp->if_start = snstart;
208 ifp->if_ioctl = snioctl;
209 ifp->if_init = sninit;
210 ifp->if_baudrate = 10000000;
211 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
212 ifp->if_snd.ifq_maxlen = ifqmaxlen;
213 IFQ_SET_READY(&ifp->if_snd);
214
215 ether_ifattach(ifp, eaddr);
216
217 /*
218 * Activate the interrupt so we can get card interrupts. This
219 * needs to be done last so that we don't have/hold the lock
220 * during startup to avoid LORs in the network layer.
221 */
222 if ((err = bus_setup_intr(dev, sc->irq_res,
223 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
224 &sc->intrhand)) != 0) {
225 sn_detach(dev);
226 return err;
227 }
228
229 gone_by_fcp101_dev(dev);
230
231 return 0;
232 }
233
234
235 int
sn_detach(device_t dev)236 sn_detach(device_t dev)
237 {
238 struct sn_softc *sc = device_get_softc(dev);
239 struct ifnet *ifp = sc->ifp;
240
241 ether_ifdetach(ifp);
242 SN_LOCK(sc);
243 snstop(sc);
244 SN_UNLOCK(sc);
245 callout_drain(&sc->watchdog);
246 sn_deactivate(dev);
247 if_free(ifp);
248 SN_LOCK_DESTROY(sc);
249 return 0;
250 }
251
252 static void
sninit(void * xsc)253 sninit(void *xsc)
254 {
255 struct sn_softc *sc = xsc;
256 SN_LOCK(sc);
257 sninit_locked(sc);
258 SN_UNLOCK(sc);
259 }
260
261 /*
262 * Reset and initialize the chip
263 */
264 static void
sninit_locked(void * xsc)265 sninit_locked(void *xsc)
266 {
267 struct sn_softc *sc = xsc;
268 struct ifnet *ifp = sc->ifp;
269 int flags;
270 int mask;
271
272 SN_ASSERT_LOCKED(sc);
273
274 /*
275 * This resets the registers mostly to defaults, but doesn't affect
276 * EEPROM. After the reset cycle, we pause briefly for the chip to
277 * be happy.
278 */
279 SMC_SELECT_BANK(sc, 0);
280 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
281 SMC_DELAY(sc);
282 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
283 SMC_DELAY(sc);
284 SMC_DELAY(sc);
285
286 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
287
288 /*
289 * Set the control register to automatically release successfully
290 * transmitted packets (making the best use out of our limited
291 * memory) and to enable the EPH interrupt on certain TX errors.
292 */
293 SMC_SELECT_BANK(sc, 1);
294 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
295 CTR_CR_ENABLE | CTR_LE_ENABLE));
296
297 /* Set squelch level to 240mV (default 480mV) */
298 flags = CSR_READ_2(sc, CONFIG_REG_W);
299 flags |= CR_SET_SQLCH;
300 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
301
302 /*
303 * Reset the MMU and wait for it to be un-busy.
304 */
305 SMC_SELECT_BANK(sc, 2);
306 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
307 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
308 ;
309
310 /*
311 * Disable all interrupts
312 */
313 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
314
315 sn_setmcast(sc);
316
317 /*
318 * Set the transmitter control. We want it enabled.
319 */
320 flags = TCR_ENABLE;
321
322 #ifndef SW_PAD
323 /*
324 * I (GB) have been unlucky getting this to work.
325 */
326 flags |= TCR_PAD_ENABLE;
327 #endif /* SW_PAD */
328
329 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
330
331
332 /*
333 * Now, enable interrupts
334 */
335 SMC_SELECT_BANK(sc, 2);
336
337 mask = IM_EPH_INT |
338 IM_RX_OVRN_INT |
339 IM_RCV_INT |
340 IM_TX_INT;
341
342 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
343 sc->intr_mask = mask;
344 sc->pages_wanted = -1;
345
346
347 /*
348 * Mark the interface running but not active.
349 */
350 ifp->if_drv_flags |= IFF_DRV_RUNNING;
351 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
352 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
353
354 /*
355 * Attempt to push out any waiting packets.
356 */
357 snstart_locked(ifp);
358 }
359
360 static void
snstart(struct ifnet * ifp)361 snstart(struct ifnet *ifp)
362 {
363 struct sn_softc *sc = ifp->if_softc;
364 SN_LOCK(sc);
365 snstart_locked(ifp);
366 SN_UNLOCK(sc);
367 }
368
369
370 static void
snstart_locked(struct ifnet * ifp)371 snstart_locked(struct ifnet *ifp)
372 {
373 struct sn_softc *sc = ifp->if_softc;
374 u_int len;
375 struct mbuf *m;
376 struct mbuf *top;
377 int pad;
378 int mask;
379 uint16_t length;
380 uint16_t numPages;
381 uint8_t packet_no;
382 int time_out;
383 int junk = 0;
384
385 SN_ASSERT_LOCKED(sc);
386
387 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
388 return;
389 if (sc->pages_wanted != -1) {
390 if_printf(ifp, "snstart() while memory allocation pending\n");
391 return;
392 }
393 startagain:
394
395 /*
396 * Sneak a peek at the next packet
397 */
398 m = ifp->if_snd.ifq_head;
399 if (m == NULL)
400 return;
401 /*
402 * Compute the frame length and set pad to give an overall even
403 * number of bytes. Below we assume that the packet length is even.
404 */
405 for (len = 0, top = m; m; m = m->m_next)
406 len += m->m_len;
407
408 pad = (len & 1);
409
410 /*
411 * We drop packets that are too large. Perhaps we should truncate
412 * them instead?
413 */
414 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
415 if_printf(ifp, "large packet discarded (A)\n");
416 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
417 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
418 m_freem(m);
419 goto readcheck;
420 }
421 #ifdef SW_PAD
422
423 /*
424 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
425 */
426 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
427 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
428
429 #endif /* SW_PAD */
430
431 length = pad + len;
432
433 /*
434 * The MMU wants the number of pages to be the number of 256 byte
435 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
436 * include space for the status word, byte count and control bytes in
437 * the allocation request.
438 */
439 numPages = (length + 6) >> 8;
440
441
442 /*
443 * Now, try to allocate the memory
444 */
445 SMC_SELECT_BANK(sc, 2);
446 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
447
448 /*
449 * Wait a short amount of time to see if the allocation request
450 * completes. Otherwise, I enable the interrupt and wait for
451 * completion asynchronously.
452 */
453
454 time_out = MEMORY_WAIT_TIME;
455 do {
456 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
457 break;
458 } while (--time_out);
459
460 if (!time_out || junk > 10) {
461
462 /*
463 * No memory now. Oh well, wait until the chip finds memory
464 * later. Remember how many pages we were asking for and
465 * enable the allocation completion interrupt. Also set a
466 * watchdog in case we miss the interrupt. We mark the
467 * interface active since there is no point in attempting an
468 * snstart() until after the memory is available.
469 */
470 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
471 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
472 sc->intr_mask = mask;
473
474 sc->timer = 1;
475 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
476 sc->pages_wanted = numPages;
477 return;
478 }
479 /*
480 * The memory allocation completed. Check the results.
481 */
482 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
483 if (packet_no & ARR_FAILED) {
484 if (junk++ > 10)
485 if_printf(ifp, "Memory allocation failed\n");
486 goto startagain;
487 }
488 /*
489 * We have a packet number, so tell the card to use it.
490 */
491 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
492
493 /*
494 * Point to the beginning of the packet
495 */
496 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
497
498 /*
499 * Send the packet length (+6 for status, length and control byte)
500 * and the status word (set to zeros)
501 */
502 CSR_WRITE_2(sc, DATA_REG_W, 0);
503 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
504 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
505
506 /*
507 * Get the packet from the kernel. This will include the Ethernet
508 * frame header, MAC Addresses etc.
509 */
510 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
511
512 /*
513 * Push out the data to the card.
514 */
515 for (top = m; m != NULL; m = m->m_next) {
516
517 /*
518 * Push out words.
519 */
520 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
521 m->m_len / 2);
522
523 /*
524 * Push out remaining byte.
525 */
526 if (m->m_len & 1)
527 CSR_WRITE_1(sc, DATA_REG_B,
528 *(mtod(m, caddr_t) + m->m_len - 1));
529 }
530
531 /*
532 * Push out padding.
533 */
534 while (pad > 1) {
535 CSR_WRITE_2(sc, DATA_REG_W, 0);
536 pad -= 2;
537 }
538 if (pad)
539 CSR_WRITE_1(sc, DATA_REG_B, 0);
540
541 /*
542 * Push out control byte and unused packet byte The control byte is 0
543 * meaning the packet is even lengthed and no special CRC handling is
544 * desired.
545 */
546 CSR_WRITE_2(sc, DATA_REG_W, 0);
547
548 /*
549 * Enable the interrupts and let the chipset deal with it Also set a
550 * watchdog in case we miss the interrupt.
551 */
552 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
553 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
554 sc->intr_mask = mask;
555
556 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
557
558 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
559 sc->timer = 1;
560
561 BPF_MTAP(ifp, top);
562
563 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
564 m_freem(top);
565
566
567 readcheck:
568
569 /*
570 * Is another packet coming in? We don't want to overflow the tiny
571 * RX FIFO. If nothing has arrived then attempt to queue another
572 * transmit packet.
573 */
574 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
575 goto startagain;
576 return;
577 }
578
579
580
581 /* Resume a packet transmit operation after a memory allocation
582 * has completed.
583 *
584 * This is basically a hacked up copy of snstart() which handles
585 * a completed memory allocation the same way snstart() does.
586 * It then passes control to snstart to handle any other queued
587 * packets.
588 */
589 static void
snresume(struct ifnet * ifp)590 snresume(struct ifnet *ifp)
591 {
592 struct sn_softc *sc = ifp->if_softc;
593 u_int len;
594 struct mbuf *m;
595 struct mbuf *top;
596 int pad;
597 int mask;
598 uint16_t length;
599 uint16_t numPages;
600 uint16_t pages_wanted;
601 uint8_t packet_no;
602
603 if (sc->pages_wanted < 0)
604 return;
605
606 pages_wanted = sc->pages_wanted;
607 sc->pages_wanted = -1;
608
609 /*
610 * Sneak a peek at the next packet
611 */
612 m = ifp->if_snd.ifq_head;
613 if (m == NULL) {
614 if_printf(ifp, "snresume() with nothing to send\n");
615 return;
616 }
617 /*
618 * Compute the frame length and set pad to give an overall even
619 * number of bytes. Below we assume that the packet length is even.
620 */
621 for (len = 0, top = m; m; m = m->m_next)
622 len += m->m_len;
623
624 pad = (len & 1);
625
626 /*
627 * We drop packets that are too large. Perhaps we should truncate
628 * them instead?
629 */
630 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
631 if_printf(ifp, "large packet discarded (B)\n");
632 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
633 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
634 m_freem(m);
635 return;
636 }
637 #ifdef SW_PAD
638
639 /*
640 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
641 */
642 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
643 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
644
645 #endif /* SW_PAD */
646
647 length = pad + len;
648
649
650 /*
651 * The MMU wants the number of pages to be the number of 256 byte
652 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
653 * include space for the status word, byte count and control bytes in
654 * the allocation request.
655 */
656 numPages = (length + 6) >> 8;
657
658
659 SMC_SELECT_BANK(sc, 2);
660
661 /*
662 * The memory allocation completed. Check the results. If it failed,
663 * we simply set a watchdog timer and hope for the best.
664 */
665 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
666 if (packet_no & ARR_FAILED) {
667 if_printf(ifp, "Memory allocation failed. Weird.\n");
668 sc->timer = 1;
669 goto try_start;
670 }
671 /*
672 * We have a packet number, so tell the card to use it.
673 */
674 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
675
676 /*
677 * Now, numPages should match the pages_wanted recorded when the
678 * memory allocation was initiated.
679 */
680 if (pages_wanted != numPages) {
681 if_printf(ifp, "memory allocation wrong size. Weird.\n");
682 /*
683 * If the allocation was the wrong size we simply release the
684 * memory once it is granted. Wait for the MMU to be un-busy.
685 */
686 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
687 ;
688 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
689
690 return;
691 }
692 /*
693 * Point to the beginning of the packet
694 */
695 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
696
697 /*
698 * Send the packet length (+6 for status, length and control byte)
699 * and the status word (set to zeros)
700 */
701 CSR_WRITE_2(sc, DATA_REG_W, 0);
702 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
703 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
704
705 /*
706 * Get the packet from the kernel. This will include the Ethernet
707 * frame header, MAC Addresses etc.
708 */
709 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
710
711 /*
712 * Push out the data to the card.
713 */
714 for (top = m; m != NULL; m = m->m_next) {
715
716 /*
717 * Push out words.
718 */
719 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
720 m->m_len / 2);
721 /*
722 * Push out remaining byte.
723 */
724 if (m->m_len & 1)
725 CSR_WRITE_1(sc, DATA_REG_B,
726 *(mtod(m, caddr_t) + m->m_len - 1));
727 }
728
729 /*
730 * Push out padding.
731 */
732 while (pad > 1) {
733 CSR_WRITE_2(sc, DATA_REG_W, 0);
734 pad -= 2;
735 }
736 if (pad)
737 CSR_WRITE_1(sc, DATA_REG_B, 0);
738
739 /*
740 * Push out control byte and unused packet byte The control byte is 0
741 * meaning the packet is even lengthed and no special CRC handling is
742 * desired.
743 */
744 CSR_WRITE_2(sc, DATA_REG_W, 0);
745
746 /*
747 * Enable the interrupts and let the chipset deal with it Also set a
748 * watchdog in case we miss the interrupt.
749 */
750 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
751 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
752 sc->intr_mask = mask;
753 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
754
755 BPF_MTAP(ifp, top);
756
757 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
758 m_freem(top);
759
760 try_start:
761
762 /*
763 * Now pass control to snstart() to queue any additional packets
764 */
765 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
766 snstart_locked(ifp);
767
768 /*
769 * We've sent something, so we're active. Set a watchdog in case the
770 * TX_EMPTY interrupt is lost.
771 */
772 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
773 sc->timer = 1;
774
775 return;
776 }
777
778 void
sn_intr(void * arg)779 sn_intr(void *arg)
780 {
781 struct sn_softc *sc = (struct sn_softc *) arg;
782
783 SN_LOCK(sc);
784 snintr_locked(sc);
785 SN_UNLOCK(sc);
786 }
787
788 static void
snintr_locked(struct sn_softc * sc)789 snintr_locked(struct sn_softc *sc)
790 {
791 int status, interrupts;
792 struct ifnet *ifp = sc->ifp;
793
794 /*
795 * Chip state registers
796 */
797 uint8_t mask;
798 uint8_t packet_no;
799 uint16_t tx_status;
800 uint16_t card_stats;
801
802 /*
803 * Clear the watchdog.
804 */
805 sc->timer = 0;
806
807 SMC_SELECT_BANK(sc, 2);
808
809 /*
810 * Obtain the current interrupt mask and clear the hardware mask
811 * while servicing interrupts.
812 */
813 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
814 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
815
816 /*
817 * Get the set of interrupts which occurred and eliminate any which
818 * are masked.
819 */
820 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
821 status = interrupts & mask;
822
823 /*
824 * Now, process each of the interrupt types.
825 */
826
827 /*
828 * Receive Overrun.
829 */
830 if (status & IM_RX_OVRN_INT) {
831 /*
832 * Acknowlege Interrupt
833 */
834 SMC_SELECT_BANK(sc, 2);
835 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
836
837 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
838 }
839 /*
840 * Got a packet.
841 */
842 if (status & IM_RCV_INT) {
843 int packet_number;
844
845 SMC_SELECT_BANK(sc, 2);
846 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
847
848 if (packet_number & FIFO_REMPTY) {
849 /*
850 * we got called , but nothing was on the FIFO
851 */
852 printf("sn: Receive interrupt with nothing on FIFO\n");
853 goto out;
854 }
855 snread(ifp);
856 }
857 /*
858 * An on-card memory allocation came through.
859 */
860 if (status & IM_ALLOC_INT) {
861 /*
862 * Disable this interrupt.
863 */
864 mask &= ~IM_ALLOC_INT;
865 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
866 snresume(ifp);
867 }
868 /*
869 * TX Completion. Handle a transmit error message. This will only be
870 * called when there is an error, because of the AUTO_RELEASE mode.
871 */
872 if (status & IM_TX_INT) {
873 /*
874 * Acknowlege Interrupt
875 */
876 SMC_SELECT_BANK(sc, 2);
877 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
878
879 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
880 packet_no &= FIFO_TX_MASK;
881
882 /*
883 * select this as the packet to read from
884 */
885 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
886
887 /*
888 * Position the pointer to the first word from this packet
889 */
890 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
891
892 /*
893 * Fetch the TX status word. The value found here will be a
894 * copy of the EPH_STATUS_REG_W at the time the transmit
895 * failed.
896 */
897 tx_status = CSR_READ_2(sc, DATA_REG_W);
898
899 if (tx_status & EPHSR_TX_SUC) {
900 device_printf(sc->dev,
901 "Successful packet caused interrupt\n");
902 } else {
903 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
904 }
905
906 if (tx_status & EPHSR_LATCOL)
907 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
908
909 /*
910 * Some of these errors will have disabled transmit.
911 * Re-enable transmit now.
912 */
913 SMC_SELECT_BANK(sc, 0);
914
915 #ifdef SW_PAD
916 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
917 #else
918 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
919 #endif /* SW_PAD */
920
921 /*
922 * kill the failed packet. Wait for the MMU to be un-busy.
923 */
924 SMC_SELECT_BANK(sc, 2);
925 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
926 ;
927 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
928
929 /*
930 * Attempt to queue more transmits.
931 */
932 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
933 snstart_locked(ifp);
934 }
935 /*
936 * Transmit underrun. We use this opportunity to update transmit
937 * statistics from the card.
938 */
939 if (status & IM_TX_EMPTY_INT) {
940
941 /*
942 * Acknowlege Interrupt
943 */
944 SMC_SELECT_BANK(sc, 2);
945 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
946
947 /*
948 * Disable this interrupt.
949 */
950 mask &= ~IM_TX_EMPTY_INT;
951
952 SMC_SELECT_BANK(sc, 0);
953 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
954
955 /*
956 * Single collisions
957 */
958 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, card_stats & ECR_COLN_MASK);
959
960 /*
961 * Multiple collisions
962 */
963 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (card_stats & ECR_MCOLN_MASK) >> 4);
964
965 SMC_SELECT_BANK(sc, 2);
966
967 /*
968 * Attempt to enqueue some more stuff.
969 */
970 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
971 snstart_locked(ifp);
972 }
973 /*
974 * Some other error. Try to fix it by resetting the adapter.
975 */
976 if (status & IM_EPH_INT) {
977 snstop(sc);
978 sninit_locked(sc);
979 }
980
981 out:
982 /*
983 * Handled all interrupt sources.
984 */
985
986 SMC_SELECT_BANK(sc, 2);
987
988 /*
989 * Reestablish interrupts from mask which have not been deselected
990 * during this interrupt. Note that the hardware mask, which was set
991 * to 0x00 at the start of this service routine, may have been
992 * updated by one or more of the interrupt handers and we must let
993 * those new interrupts stay enabled here.
994 */
995 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
996 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
997 sc->intr_mask = mask;
998 }
999
1000 static void
snread(struct ifnet * ifp)1001 snread(struct ifnet *ifp)
1002 {
1003 struct sn_softc *sc = ifp->if_softc;
1004 struct ether_header *eh;
1005 struct mbuf *m;
1006 short status;
1007 int packet_number;
1008 uint16_t packet_length;
1009 uint8_t *data;
1010
1011 SMC_SELECT_BANK(sc, 2);
1012 #if 0
1013 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1014
1015 if (packet_number & FIFO_REMPTY) {
1016
1017 /*
1018 * we got called , but nothing was on the FIFO
1019 */
1020 printf("sn: Receive interrupt with nothing on FIFO\n");
1021 return;
1022 }
1023 #endif
1024 read_another:
1025
1026 /*
1027 * Start reading from the start of the packet. Since PTR_RCV is set,
1028 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1029 */
1030 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1031
1032 /*
1033 * First two words are status and packet_length
1034 */
1035 status = CSR_READ_2(sc, DATA_REG_W);
1036 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1037
1038 /*
1039 * The packet length contains 3 extra words: status, length, and a
1040 * extra word with the control byte.
1041 */
1042 packet_length -= 6;
1043
1044 /*
1045 * Account for receive errors and discard.
1046 */
1047 if (status & RS_ERRORS) {
1048 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1049 goto out;
1050 }
1051 /*
1052 * A packet is received.
1053 */
1054
1055 /*
1056 * Adjust for odd-length packet.
1057 */
1058 if (status & RS_ODDFRAME)
1059 packet_length++;
1060
1061 /*
1062 * Allocate a header mbuf from the kernel.
1063 */
1064 MGETHDR(m, M_NOWAIT, MT_DATA);
1065 if (m == NULL)
1066 goto out;
1067
1068 m->m_pkthdr.rcvif = ifp;
1069 m->m_pkthdr.len = m->m_len = packet_length;
1070
1071 /*
1072 * Attach an mbuf cluster.
1073 */
1074 if (!(MCLGET(m, M_NOWAIT))) {
1075 m_freem(m);
1076 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1077 printf("sn: snread() kernel memory allocation problem\n");
1078 goto out;
1079 }
1080 eh = mtod(m, struct ether_header *);
1081
1082 /*
1083 * Get packet, including link layer address, from interface.
1084 */
1085 data = (uint8_t *) eh;
1086 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1087 if (packet_length & 1) {
1088 data += packet_length & ~1;
1089 *data = CSR_READ_1(sc, DATA_REG_B);
1090 }
1091 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1092
1093 /*
1094 * Remove link layer addresses and whatnot.
1095 */
1096 m->m_pkthdr.len = m->m_len = packet_length;
1097
1098 /*
1099 * Drop locks before calling if_input() since it may re-enter
1100 * snstart() in the netisr case. This would result in a
1101 * lock reversal. Better performance might be obtained by
1102 * chaining all packets received, dropping the lock, and then
1103 * calling if_input() on each one.
1104 */
1105 SN_UNLOCK(sc);
1106 (*ifp->if_input)(ifp, m);
1107 SN_LOCK(sc);
1108
1109 out:
1110
1111 /*
1112 * Error or good, tell the card to get rid of this packet Wait for
1113 * the MMU to be un-busy.
1114 */
1115 SMC_SELECT_BANK(sc, 2);
1116 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1117 ;
1118 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1119
1120 /*
1121 * Check whether another packet is ready
1122 */
1123 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1124 if (packet_number & FIFO_REMPTY) {
1125 return;
1126 }
1127 goto read_another;
1128 }
1129
1130
1131 /*
1132 * Handle IOCTLS. This function is completely stolen from if_ep.c
1133 * As with its progenitor, it does not handle hardware address
1134 * changes.
1135 */
1136 static int
snioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1137 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1138 {
1139 struct sn_softc *sc = ifp->if_softc;
1140 int error = 0;
1141
1142 switch (cmd) {
1143 case SIOCSIFFLAGS:
1144 SN_LOCK(sc);
1145 if ((ifp->if_flags & IFF_UP) == 0 &&
1146 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1147 snstop(sc);
1148 } else {
1149 /* reinitialize card on any parameter change */
1150 sninit_locked(sc);
1151 }
1152 SN_UNLOCK(sc);
1153 break;
1154
1155 case SIOCADDMULTI:
1156 case SIOCDELMULTI:
1157 /* update multicast filter list. */
1158 SN_LOCK(sc);
1159 sn_setmcast(sc);
1160 error = 0;
1161 SN_UNLOCK(sc);
1162 break;
1163 default:
1164 error = ether_ioctl(ifp, cmd, data);
1165 break;
1166 }
1167 return (error);
1168 }
1169
1170 static void
snwatchdog(void * arg)1171 snwatchdog(void *arg)
1172 {
1173 struct sn_softc *sc;
1174
1175 sc = arg;
1176 SN_ASSERT_LOCKED(sc);
1177 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1178 if (sc->timer == 0 || --sc->timer > 0)
1179 return;
1180 snintr_locked(sc);
1181 }
1182
1183
1184 /* 1. zero the interrupt mask
1185 * 2. clear the enable receive flag
1186 * 3. clear the enable xmit flags
1187 */
1188 static void
snstop(struct sn_softc * sc)1189 snstop(struct sn_softc *sc)
1190 {
1191
1192 struct ifnet *ifp = sc->ifp;
1193
1194 /*
1195 * Clear interrupt mask; disable all interrupts.
1196 */
1197 SMC_SELECT_BANK(sc, 2);
1198 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1199
1200 /*
1201 * Disable transmitter and Receiver
1202 */
1203 SMC_SELECT_BANK(sc, 0);
1204 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1205 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1206
1207 /*
1208 * Cancel watchdog.
1209 */
1210 sc->timer = 0;
1211 callout_stop(&sc->watchdog);
1212 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1213 }
1214
1215
1216 int
sn_activate(device_t dev)1217 sn_activate(device_t dev)
1218 {
1219 struct sn_softc *sc = device_get_softc(dev);
1220
1221 sc->port_rid = 0;
1222 sc->port_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1223 &sc->port_rid, SMC_IO_EXTENT, RF_ACTIVE);
1224 if (!sc->port_res) {
1225 if (bootverbose)
1226 device_printf(dev, "Cannot allocate ioport\n");
1227 return ENOMEM;
1228 }
1229
1230 sc->irq_rid = 0;
1231 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1232 RF_ACTIVE);
1233 if (!sc->irq_res) {
1234 if (bootverbose)
1235 device_printf(dev, "Cannot allocate irq\n");
1236 sn_deactivate(dev);
1237 return ENOMEM;
1238 }
1239 return (0);
1240 }
1241
1242 void
sn_deactivate(device_t dev)1243 sn_deactivate(device_t dev)
1244 {
1245 struct sn_softc *sc = device_get_softc(dev);
1246
1247 if (sc->intrhand)
1248 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1249 sc->intrhand = 0;
1250 if (sc->port_res)
1251 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1252 sc->port_res);
1253 sc->port_res = 0;
1254 if (sc->modem_res)
1255 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1256 sc->modem_res);
1257 sc->modem_res = 0;
1258 if (sc->irq_res)
1259 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1260 sc->irq_res);
1261 sc->irq_res = 0;
1262 return;
1263 }
1264
1265 /*
1266 * Function: sn_probe(device_t dev)
1267 *
1268 * Purpose:
1269 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1270 * Tries to cause as little damage as possible if it's not a SMC chip.
1271 * Returns a 0 on success
1272 *
1273 * Algorithm:
1274 * (1) see if the high byte of BANK_SELECT is 0x33
1275 * (2) compare the ioaddr with the base register's address
1276 * (3) see if I recognize the chip ID in the appropriate register
1277 *
1278 *
1279 */
1280 int
sn_probe(device_t dev)1281 sn_probe(device_t dev)
1282 {
1283 struct sn_softc *sc = device_get_softc(dev);
1284 uint16_t bank;
1285 uint16_t revision_register;
1286 uint16_t base_address_register;
1287 int err;
1288
1289 if ((err = sn_activate(dev)) != 0)
1290 return err;
1291
1292 /*
1293 * First, see if the high byte is 0x33
1294 */
1295 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1296 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1297 #ifdef SN_DEBUG
1298 device_printf(dev, "test1 failed\n");
1299 #endif
1300 goto error;
1301 }
1302 /*
1303 * The above MIGHT indicate a device, but I need to write to further
1304 * test this. Go to bank 0, then test that the register still
1305 * reports the high byte is 0x33.
1306 */
1307 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1308 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1309 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1310 #ifdef SN_DEBUG
1311 device_printf(dev, "test2 failed\n");
1312 #endif
1313 goto error;
1314 }
1315 /*
1316 * well, we've already written once, so hopefully another time won't
1317 * hurt. This time, I need to switch the bank register to bank 1, so
1318 * I can access the base address register. The contents of the
1319 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1320 * to match the I/O port address where the adapter is being probed.
1321 */
1322 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1323 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1324
1325 if (rman_get_start(sc->port_res) != base_address_register) {
1326
1327 /*
1328 * Well, the base address register didn't match. Must not
1329 * have been a SMC chip after all.
1330 */
1331 #ifdef SN_DEBUG
1332 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1333 "base_address_register = 0x%x\n",
1334 rman_get_start(sc->port_res), base_address_register);
1335 #endif
1336 goto error;
1337 }
1338
1339 /*
1340 * Check if the revision register is something that I recognize.
1341 * These might need to be added to later, as future revisions could
1342 * be added.
1343 */
1344 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1345 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1346 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1347
1348 /*
1349 * I don't regonize this chip, so...
1350 */
1351 #ifdef SN_DEBUG
1352 device_printf(dev, "test4 failed\n");
1353 #endif
1354 goto error;
1355 }
1356
1357 /*
1358 * at this point I'll assume that the chip is an SMC9xxx. It might be
1359 * prudent to check a listing of MAC addresses against the hardware
1360 * address, or do some other tests.
1361 */
1362 sn_deactivate(dev);
1363 return 0;
1364 error:
1365 sn_deactivate(dev);
1366 return ENXIO;
1367 }
1368
1369 #define MCFSZ 8
1370
1371 static void
sn_setmcast(struct sn_softc * sc)1372 sn_setmcast(struct sn_softc *sc)
1373 {
1374 struct ifnet *ifp = sc->ifp;
1375 int flags;
1376 uint8_t mcf[MCFSZ];
1377
1378 SN_ASSERT_LOCKED(sc);
1379
1380 /*
1381 * Set the receiver filter. We want receive enabled and auto strip
1382 * of CRC from received packet. If we are promiscuous then set that
1383 * bit too.
1384 */
1385 flags = RCR_ENABLE | RCR_STRIP_CRC;
1386
1387 if (ifp->if_flags & IFF_PROMISC) {
1388 flags |= RCR_PROMISC | RCR_ALMUL;
1389 } else if (ifp->if_flags & IFF_ALLMULTI) {
1390 flags |= RCR_ALMUL;
1391 } else {
1392 if (sn_getmcf(ifp, mcf)) {
1393 /* set filter */
1394 SMC_SELECT_BANK(sc, 3);
1395 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1396 ((uint16_t)mcf[1] << 8) | mcf[0]);
1397 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1398 ((uint16_t)mcf[3] << 8) | mcf[2]);
1399 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1400 ((uint16_t)mcf[5] << 8) | mcf[4]);
1401 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1402 ((uint16_t)mcf[7] << 8) | mcf[6]);
1403 } else {
1404 flags |= RCR_ALMUL;
1405 }
1406 }
1407 SMC_SELECT_BANK(sc, 0);
1408 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1409 }
1410
1411 static int
sn_getmcf(struct ifnet * ifp,uint8_t * mcf)1412 sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1413 {
1414 int i;
1415 uint32_t index, index2;
1416 uint8_t *af = mcf;
1417 struct ifmultiaddr *ifma;
1418
1419 bzero(mcf, MCFSZ);
1420
1421 if_maddr_rlock(ifp);
1422 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1423 if (ifma->ifma_addr->sa_family != AF_LINK) {
1424 if_maddr_runlock(ifp);
1425 return 0;
1426 }
1427 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1428 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1429 index2 = 0;
1430 for (i = 0; i < 6; i++) {
1431 index2 <<= 1;
1432 index2 |= (index & 0x01);
1433 index >>= 1;
1434 }
1435 af[index2 >> 3] |= 1 << (index2 & 7);
1436 }
1437 if_maddr_runlock(ifp);
1438 return 1; /* use multicast filter */
1439 }
1440