1 /*-
2 * Copyright (c) 2017 Broadcom. All rights reserved.
3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * $FreeBSD: stable/12/sys/dev/ocs_fc/sli4.c 372674 2022-10-30 03:43:18Z git2svn $
32 */
33
34 /**
35 * @defgroup sli SLI-4 Base APIs
36 */
37
38 /**
39 * @file
40 * All common (i.e. transport-independent) SLI-4 functions are implemented
41 * in this file.
42 */
43
44 #include "sli4.h"
45
46 #if defined(OCS_INCLUDE_DEBUG)
47 #include "ocs_utils.h"
48 #endif
49
50 #define SLI4_BMBX_DELAY_US 1000 /* 1 ms */
51 #define SLI4_INIT_PORT_DELAY_US 10000 /* 10 ms */
52
53 static int32_t sli_fw_init(sli4_t *);
54 static int32_t sli_fw_term(sli4_t *);
55 static int32_t sli_sliport_control(sli4_t *sli4, uint32_t endian);
56 static int32_t sli_cmd_fw_deinitialize(sli4_t *, void *, size_t);
57 static int32_t sli_cmd_fw_initialize(sli4_t *, void *, size_t);
58 static int32_t sli_queue_doorbell(sli4_t *, sli4_queue_t *);
59 static uint8_t sli_queue_entry_is_valid(sli4_queue_t *, uint8_t *, uint8_t);
60
61 const uint8_t sli4_fw_initialize[] = {
62 0xff, 0x12, 0x34, 0xff,
63 0xff, 0x56, 0x78, 0xff,
64 };
65
66 const uint8_t sli4_fw_deinitialize[] = {
67 0xff, 0xaa, 0xbb, 0xff,
68 0xff, 0xcc, 0xdd, 0xff,
69 };
70
71 typedef struct {
72 uint32_t rev_id;
73 uint32_t family; /* generation */
74 sli4_asic_type_e type;
75 sli4_asic_rev_e rev;
76 } sli4_asic_entry_t;
77
78 sli4_asic_entry_t sli4_asic_table[] = {
79 { 0x00, 1, SLI4_ASIC_TYPE_BE3, SLI4_ASIC_REV_A0},
80 { 0x01, 1, SLI4_ASIC_TYPE_BE3, SLI4_ASIC_REV_A1},
81 { 0x02, 1, SLI4_ASIC_TYPE_BE3, SLI4_ASIC_REV_A2},
82 { 0x00, 4, SLI4_ASIC_TYPE_SKYHAWK, SLI4_ASIC_REV_A0},
83 { 0x00, 2, SLI4_ASIC_TYPE_SKYHAWK, SLI4_ASIC_REV_A0},
84 { 0x10, 1, SLI4_ASIC_TYPE_BE3, SLI4_ASIC_REV_B0},
85 { 0x10, 0x04, SLI4_ASIC_TYPE_SKYHAWK, SLI4_ASIC_REV_B0},
86 { 0x11, 0x04, SLI4_ASIC_TYPE_SKYHAWK, SLI4_ASIC_REV_B1},
87 { 0x0, 0x0a, SLI4_ASIC_TYPE_LANCER, SLI4_ASIC_REV_A0},
88 { 0x10, 0x0b, SLI4_ASIC_TYPE_LANCER, SLI4_ASIC_REV_B0},
89 { 0x30, 0x0b, SLI4_ASIC_TYPE_LANCER, SLI4_ASIC_REV_D0},
90 { 0x3, 0x0b, SLI4_ASIC_TYPE_LANCERG6,SLI4_ASIC_REV_A3},
91 { 0x0, 0x0c, SLI4_ASIC_TYPE_LANCERG6,SLI4_ASIC_REV_A0},
92 { 0x1, 0x0c, SLI4_ASIC_TYPE_LANCERG6,SLI4_ASIC_REV_A1},
93 { 0x3, 0x0c, SLI4_ASIC_TYPE_LANCERG6,SLI4_ASIC_REV_A3},
94 { 0x1, 0x0d, SLI4_ASIC_TYPE_LANCERG7,SLI4_ASIC_REV_A1},
95 { 0x10, 0x0d, SLI4_ASIC_TYPE_LANCERG7,SLI4_ASIC_REV_B0},
96 { 0x00, 0x05, SLI4_ASIC_TYPE_CORSAIR, SLI4_ASIC_REV_A0},
97 };
98
99 /*
100 * @brief Convert queue type enum (SLI_QTYPE_*) into a string.
101 */
102 const char *SLI_QNAME[] = {
103 "Event Queue",
104 "Completion Queue",
105 "Mailbox Queue",
106 "Work Queue",
107 "Receive Queue",
108 "Undefined"
109 };
110
111 /**
112 * @brief Define the mapping of registers to their BAR and offset.
113 *
114 * @par Description
115 * Although SLI-4 specification defines a common set of registers, their locations
116 * (both BAR and offset) depend on the interface type. This array maps a register
117 * enum to an array of BAR/offset pairs indexed by the interface type. For
118 * example, to access the bootstrap mailbox register on an interface type 0
119 * device, code can refer to the offset using regmap[SLI4_REG_BMBX][0].offset.
120 *
121 * @b Note: A value of UINT32_MAX for either the register set (rset) or offset (off)
122 * indicates an invalid mapping.
123 */
124 const sli4_reg_t regmap[SLI4_REG_MAX][SLI4_MAX_IF_TYPES] = {
125 /* SLI4_REG_BMBX */
126 {
127 { 2, SLI4_BMBX_REG }, { 0, SLI4_BMBX_REG }, { 0, SLI4_BMBX_REG }, { 0, SLI4_BMBX_REG },
128 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX } , { 0, SLI4_BMBX_REG },
129 },
130 /* SLI4_REG_EQCQ_DOORBELL */
131 {
132 { 2, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG },
133 { 0, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG },
134 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
135 { 1, SLI4_IF6_EQ_DOORBELL_REG }
136 },
137 // SLI4_REG_CQ_DOORBELL
138 {
139 { 2, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG },
140 { 0, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG },
141 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
142 { 1, SLI4_IF6_CQ_DOORBELL_REG }
143 },
144 /* SLI4_REG_FCOE_RQ_DOORBELL */
145 {
146 { 2, SLI4_RQ_DOORBELL_REG }, { 0, SLI4_RQ_DOORBELL_REG },
147 { 0, SLI4_RQ_DOORBELL_REG }, { UINT32_MAX, UINT32_MAX },
148 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
149 { 1, SLI4_IF6_RQ_DOORBELL_REG }
150 },
151 /* SLI4_REG_IO_WQ_DOORBELL */
152 {
153 { 2, SLI4_IO_WQ_DOORBELL_REG }, { 0, SLI4_IO_WQ_DOORBELL_REG },
154 { 0, SLI4_IO_WQ_DOORBELL_REG }, { UINT32_MAX, UINT32_MAX },
155 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
156 { 1, SLI4_IF6_WQ_DOORBELL_REG }
157 },
158 /* SLI4_REG_MQ_DOORBELL */
159 {
160 { 2, SLI4_MQ_DOORBELL_REG }, { 0, SLI4_MQ_DOORBELL_REG },
161 { 0, SLI4_MQ_DOORBELL_REG }, { 0, SLI4_MQ_DOORBELL_REG },
162 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
163 { 1, SLI4_IF6_MQ_DOORBELL_REG }
164 },
165 /* SLI4_REG_PHYSDEV_CONTROL */
166 {
167 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
168 { 0, SLI4_PHSDEV_CONTROL_REG_236 }, { 0, SLI4_PHSDEV_CONTROL_REG_236 },
169 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
170 { 0, SLI4_PHSDEV_CONTROL_REG_236 }
171 },
172 /* SLI4_REG_SLIPORT_CONTROL */
173 {
174 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
175 { 0, SLI4_SLIPORT_CONTROL_REG }, { UINT32_MAX, UINT32_MAX },
176 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
177 { 0, SLI4_SLIPORT_CONTROL_REG },
178 },
179 /* SLI4_REG_SLIPORT_ERROR1 */
180 {
181 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
182 { 0, SLI4_SLIPORT_ERROR1 }, { UINT32_MAX, UINT32_MAX },
183 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
184 { 0, SLI4_SLIPORT_ERROR1 },
185 },
186 /* SLI4_REG_SLIPORT_ERROR2 */
187 {
188 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
189 { 0, SLI4_SLIPORT_ERROR2 }, { UINT32_MAX, UINT32_MAX },
190 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
191 { 0, SLI4_SLIPORT_ERROR2 },
192 },
193 /* SLI4_REG_SLIPORT_SEMAPHORE */
194 {
195 { 1, SLI4_PORT_SEMAPHORE_REG_0 }, { 0, SLI4_PORT_SEMAPHORE_REG_1 },
196 { 0, SLI4_PORT_SEMAPHORE_REG_236 }, { 0, SLI4_PORT_SEMAPHORE_REG_236 },
197 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
198 { 0, SLI4_PORT_SEMAPHORE_REG_236 },
199 },
200 /* SLI4_REG_SLIPORT_STATUS */
201 {
202 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
203 { 0, SLI4_PORT_STATUS_REG_236 }, { 0, SLI4_PORT_STATUS_REG_236 },
204 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
205 { 0, SLI4_PORT_STATUS_REG_236 },
206 },
207 /* SLI4_REG_UERR_MASK_HI */
208 {
209 { 0, SLI4_UERR_MASK_HIGH_REG }, { UINT32_MAX, UINT32_MAX },
210 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
211 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
212 { UINT32_MAX, UINT32_MAX }
213 },
214 /* SLI4_REG_UERR_MASK_LO */
215 {
216 { 0, SLI4_UERR_MASK_LOW_REG }, { UINT32_MAX, UINT32_MAX },
217 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
218 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
219 { UINT32_MAX, UINT32_MAX }
220 },
221 /* SLI4_REG_UERR_STATUS_HI */
222 {
223 { 0, SLI4_UERR_STATUS_HIGH_REG }, { UINT32_MAX, UINT32_MAX },
224 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
225 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
226 { UINT32_MAX, UINT32_MAX }
227 },
228 /* SLI4_REG_UERR_STATUS_LO */
229 {
230 { 0, SLI4_UERR_STATUS_LOW_REG }, { UINT32_MAX, UINT32_MAX },
231 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
232 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
233 { UINT32_MAX, UINT32_MAX }
234 },
235 /* SLI4_REG_SW_UE_CSR1 */
236 {
237 { 1, SLI4_SW_UE_CSR1}, { UINT32_MAX, UINT32_MAX },
238 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
239 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
240 { UINT32_MAX, UINT32_MAX }
241 },
242 /* SLI4_REG_SW_UE_CSR2 */
243 {
244 { 1, SLI4_SW_UE_CSR2}, { UINT32_MAX, UINT32_MAX },
245 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
246 { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX },
247 { UINT32_MAX, UINT32_MAX }
248 },
249 };
250
251 /**
252 * @brief Read the given SLI register.
253 *
254 * @param sli Pointer to the SLI context.
255 * @param reg Register name enum.
256 *
257 * @return Returns the register value.
258 */
259 uint32_t
sli_reg_read(sli4_t * sli,sli4_regname_e reg)260 sli_reg_read(sli4_t *sli, sli4_regname_e reg)
261 {
262 const sli4_reg_t *r = &(regmap[reg][sli->if_type]);
263
264 if ((UINT32_MAX == r->rset) || (UINT32_MAX == r->off)) {
265 ocs_log_err(sli->os, "regname %d not defined for if_type %d\n", reg, sli->if_type);
266 return UINT32_MAX;
267 }
268
269 return ocs_reg_read32(sli->os, r->rset, r->off);
270 }
271
272 /**
273 * @brief Write the value to the given SLI register.
274 *
275 * @param sli Pointer to the SLI context.
276 * @param reg Register name enum.
277 * @param val Value to write.
278 *
279 * @return None.
280 */
281 void
sli_reg_write(sli4_t * sli,sli4_regname_e reg,uint32_t val)282 sli_reg_write(sli4_t *sli, sli4_regname_e reg, uint32_t val)
283 {
284 const sli4_reg_t *r = &(regmap[reg][sli->if_type]);
285
286 if ((UINT32_MAX == r->rset) || (UINT32_MAX == r->off)) {
287 ocs_log_err(sli->os, "regname %d not defined for if_type %d\n", reg, sli->if_type);
288 return;
289 }
290
291 ocs_reg_write32(sli->os, r->rset, r->off, val);
292 }
293
294 /**
295 * @brief Check if the SLI_INTF register is valid.
296 *
297 * @param val 32-bit SLI_INTF register value.
298 *
299 * @return Returns 0 on success, or a non-zero value on failure.
300 */
301 static uint8_t
sli_intf_valid_check(uint32_t val)302 sli_intf_valid_check(uint32_t val)
303 {
304 return ((val >> SLI4_INTF_VALID_SHIFT) & SLI4_INTF_VALID_MASK) != SLI4_INTF_VALID;
305 }
306
307 /**
308 * @brief Retrieve the SLI revision level.
309 *
310 * @param val 32-bit SLI_INTF register value.
311 *
312 * @return Returns the SLI revision level.
313 */
314 static uint8_t
sli_intf_sli_revision(uint32_t val)315 sli_intf_sli_revision(uint32_t val)
316 {
317 return ((val >> SLI4_INTF_SLI_REVISION_SHIFT) & SLI4_INTF_SLI_REVISION_MASK);
318 }
319
320 static uint8_t
sli_intf_sli_family(uint32_t val)321 sli_intf_sli_family(uint32_t val)
322 {
323 return ((val >> SLI4_INTF_SLI_FAMILY_SHIFT) & SLI4_INTF_SLI_FAMILY_MASK);
324 }
325
326 /**
327 * @brief Retrieve the SLI interface type.
328 *
329 * @param val 32-bit SLI_INTF register value.
330 *
331 * @return Returns the SLI interface type.
332 */
333 static uint8_t
sli_intf_if_type(uint32_t val)334 sli_intf_if_type(uint32_t val)
335 {
336 return ((val >> SLI4_INTF_IF_TYPE_SHIFT) & SLI4_INTF_IF_TYPE_MASK);
337 }
338
339 /**
340 * @brief Retrieve PCI revision ID.
341 *
342 * @param val 32-bit PCI CLASS_REVISION register value.
343 *
344 * @return Returns the PCI revision ID.
345 */
346 static uint8_t
sli_pci_rev_id(uint32_t val)347 sli_pci_rev_id(uint32_t val)
348 {
349 return ((val >> SLI4_PCI_REV_ID_SHIFT) & SLI4_PCI_REV_ID_MASK);
350 }
351
352 /**
353 * @brief retrieve SLI ASIC generation
354 *
355 * @param val 32-bit SLI_ASIC_ID register value
356 *
357 * @return SLI ASIC generation
358 */
359 static uint8_t
sli_asic_gen(uint32_t val)360 sli_asic_gen(uint32_t val)
361 {
362 return ((val >> SLI4_ASIC_GEN_SHIFT) & SLI4_ASIC_GEN_MASK);
363 }
364
365 /**
366 * @brief Wait for the bootstrap mailbox to report "ready".
367 *
368 * @param sli4 SLI context pointer.
369 * @param msec Number of milliseconds to wait.
370 *
371 * @return Returns 0 if BMBX is ready, or non-zero otherwise (i.e. time out occurred).
372 */
373 static int32_t
sli_bmbx_wait(sli4_t * sli4,uint32_t msec)374 sli_bmbx_wait(sli4_t *sli4, uint32_t msec)
375 {
376 uint32_t val = 0;
377
378 do {
379 ocs_udelay(SLI4_BMBX_DELAY_US);
380 val = sli_reg_read(sli4, SLI4_REG_BMBX);
381 msec--;
382 } while(msec && !(val & SLI4_BMBX_RDY));
383
384 return(!(val & SLI4_BMBX_RDY));
385 }
386
387 /**
388 * @brief Write bootstrap mailbox.
389 *
390 * @param sli4 SLI context pointer.
391 *
392 * @return Returns 0 if command succeeded, or non-zero otherwise.
393 */
394 static int32_t
sli_bmbx_write(sli4_t * sli4)395 sli_bmbx_write(sli4_t *sli4)
396 {
397 uint32_t val = 0;
398
399 /* write buffer location to bootstrap mailbox register */
400 ocs_dma_sync(&sli4->bmbx, OCS_DMASYNC_PREWRITE);
401 val = SLI4_BMBX_WRITE_HI(sli4->bmbx.phys);
402 sli_reg_write(sli4, SLI4_REG_BMBX, val);
403
404 if (sli_bmbx_wait(sli4, SLI4_BMBX_DELAY_US)) {
405 ocs_log_crit(sli4->os, "BMBX WRITE_HI failed\n");
406 return -1;
407 }
408 val = SLI4_BMBX_WRITE_LO(sli4->bmbx.phys);
409 sli_reg_write(sli4, SLI4_REG_BMBX, val);
410
411 /* wait for SLI Port to set ready bit */
412 return sli_bmbx_wait(sli4, SLI4_BMBX_TIMEOUT_MSEC/*XXX*/);
413 }
414
415 #if defined(OCS_INCLUDE_DEBUG)
416 /**
417 * @ingroup sli
418 * @brief Dump BMBX mailbox command.
419 *
420 * @par Description
421 * Convenience function for dumping BMBX mailbox commands. Takes
422 * into account which mailbox command is given since SLI_CONFIG
423 * commands are special.
424 *
425 * @b Note: This function takes advantage of
426 * the one-command-at-a-time nature of the BMBX to be able to
427 * display non-embedded SLI_CONFIG commands. This will not work
428 * for mailbox commands on the MQ. Luckily, all current non-emb
429 * mailbox commands go through the BMBX.
430 *
431 * @param sli4 SLI context pointer.
432 * @param mbx Pointer to mailbox command to dump.
433 * @param prefix Prefix for dump label.
434 *
435 * @return None.
436 */
437 static void
sli_dump_bmbx_command(sli4_t * sli4,void * mbx,const char * prefix)438 sli_dump_bmbx_command(sli4_t *sli4, void *mbx, const char *prefix)
439 {
440 uint32_t size = 0;
441 char label[64];
442 uint32_t i;
443 /* Mailbox diagnostic logging */
444 sli4_mbox_command_header_t *hdr = (sli4_mbox_command_header_t *)mbx;
445
446 if (!ocs_debug_is_enabled(OCS_DEBUG_ENABLE_MQ_DUMP)) {
447 return;
448 }
449
450 if (hdr->command == SLI4_MBOX_COMMAND_SLI_CONFIG) {
451 sli4_cmd_sli_config_t *sli_config = (sli4_cmd_sli_config_t *)hdr;
452 sli4_req_hdr_t *sli_config_hdr;
453 if (sli_config->emb) {
454 ocs_snprintf(label, sizeof(label), "%s (emb)", prefix);
455
456 /* if embedded, dump entire command */
457 sli_config_hdr = (sli4_req_hdr_t *)sli_config->payload.embed;
458 size = sizeof(*sli_config) - sizeof(sli_config->payload) +
459 sli_config_hdr->request_length + (4*sizeof(uint32_t));
460 ocs_dump32(OCS_DEBUG_ENABLE_MQ_DUMP, sli4->os, label,
461 (uint8_t *)sli4->bmbx.virt, size);
462 } else {
463 sli4_sli_config_pmd_t *pmd;
464 ocs_snprintf(label, sizeof(label), "%s (non-emb hdr)", prefix);
465
466 /* if non-embedded, break up into two parts: SLI_CONFIG hdr
467 and the payload(s) */
468 size = sizeof(*sli_config) - sizeof(sli_config->payload) + (12 * sli_config->pmd_count);
469 ocs_dump32(OCS_DEBUG_ENABLE_MQ_DUMP, sli4->os, label,
470 (uint8_t *)sli4->bmbx.virt, size);
471
472 /* as sanity check, make sure first PMD matches what was saved */
473 pmd = &sli_config->payload.mem;
474 if ((pmd->address_high == ocs_addr32_hi(sli4->bmbx_non_emb_pmd->phys)) &&
475 (pmd->address_low == ocs_addr32_lo(sli4->bmbx_non_emb_pmd->phys))) {
476 for (i = 0; i < sli_config->pmd_count; i++, pmd++) {
477 sli_config_hdr = sli4->bmbx_non_emb_pmd->virt;
478 ocs_snprintf(label, sizeof(label), "%s (non-emb pay[%d])",
479 prefix, i);
480 ocs_dump32(OCS_DEBUG_ENABLE_MQ_DUMP, sli4->os, label,
481 (uint8_t *)sli4->bmbx_non_emb_pmd->virt,
482 sli_config_hdr->request_length + (4*sizeof(uint32_t)));
483 }
484 } else {
485 ocs_log_debug(sli4->os, "pmd addr does not match pmd:%x %x (%x %x)\n",
486 pmd->address_high, pmd->address_low,
487 ocs_addr32_hi(sli4->bmbx_non_emb_pmd->phys),
488 ocs_addr32_lo(sli4->bmbx_non_emb_pmd->phys));
489 }
490
491 }
492 } else {
493 /* not an SLI_CONFIG command, just display first 64 bytes, like we do
494 for MQEs */
495 size = 64;
496 ocs_dump32(OCS_DEBUG_ENABLE_MQ_DUMP, sli4->os, prefix,
497 (uint8_t *)mbx, size);
498 }
499 }
500 #endif
501
502 /**
503 * @ingroup sli
504 * @brief Submit a command to the bootstrap mailbox and check the status.
505 *
506 * @param sli4 SLI context pointer.
507 *
508 * @return Returns 0 on success, or a non-zero value on failure.
509 */
510 int32_t
sli_bmbx_command(sli4_t * sli4)511 sli_bmbx_command(sli4_t *sli4)
512 {
513 void *cqe = (uint8_t *)sli4->bmbx.virt + SLI4_BMBX_SIZE;
514
515 #if defined(OCS_INCLUDE_DEBUG)
516 sli_dump_bmbx_command(sli4, sli4->bmbx.virt, "bmbx cmd");
517 #endif
518
519 if (sli_fw_error_status(sli4) > 0) {
520 ocs_log_crit(sli4->os, "Chip is in an error state - Mailbox "
521 "command rejected status=%#x error1=%#x error2=%#x\n",
522 sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS),
523 sli_reg_read(sli4, SLI4_REG_SLIPORT_ERROR1),
524 sli_reg_read(sli4, SLI4_REG_SLIPORT_ERROR2));
525 return -1;
526 }
527
528 if (sli_bmbx_write(sli4)) {
529 ocs_log_crit(sli4->os, "bootstrap mailbox write fail phys=%p reg=%#x\n",
530 (void*)sli4->bmbx.phys,
531 sli_reg_read(sli4, SLI4_REG_BMBX));
532 return -1;
533 }
534
535 /* check completion queue entry status */
536 ocs_dma_sync(&sli4->bmbx, OCS_DMASYNC_POSTREAD);
537 if (((sli4_mcqe_t *)cqe)->val) {
538 #if defined(OCS_INCLUDE_DEBUG)
539 sli_dump_bmbx_command(sli4, sli4->bmbx.virt, "bmbx cmpl");
540 ocs_dump32(OCS_DEBUG_ENABLE_CQ_DUMP, sli4->os, "bmbx cqe", cqe, sizeof(sli4_mcqe_t));
541 #endif
542 return sli_cqe_mq(cqe);
543 } else {
544 ocs_log_err(sli4->os, "invalid or wrong type\n");
545 return -1;
546 }
547 }
548
549 /****************************************************************************
550 * Messages
551 */
552
553 /**
554 * @ingroup sli
555 * @brief Write a CONFIG_LINK command to the provided buffer.
556 *
557 * @param sli4 SLI context pointer.
558 * @param buf Virtual pointer to the destination buffer.
559 * @param size Buffer size, in bytes.
560 *
561 * @return Returns the number of bytes written.
562 */
563 int32_t
sli_cmd_config_link(sli4_t * sli4,void * buf,size_t size)564 sli_cmd_config_link(sli4_t *sli4, void *buf, size_t size)
565 {
566 sli4_cmd_config_link_t *config_link = buf;
567
568 ocs_memset(buf, 0, size);
569
570 config_link->hdr.command = SLI4_MBOX_COMMAND_CONFIG_LINK;
571
572 /* Port interprets zero in a field as "use default value" */
573
574 return sizeof(sli4_cmd_config_link_t);
575 }
576
577 /**
578 * @ingroup sli
579 * @brief Write a DOWN_LINK command to the provided buffer.
580 *
581 * @param sli4 SLI context pointer.
582 * @param buf Virtual pointer to the destination buffer.
583 * @param size Buffer size, in bytes.
584 *
585 * @return Returns the number of bytes written.
586 */
587 int32_t
sli_cmd_down_link(sli4_t * sli4,void * buf,size_t size)588 sli_cmd_down_link(sli4_t *sli4, void *buf, size_t size)
589 {
590 sli4_mbox_command_header_t *hdr = buf;
591
592 ocs_memset(buf, 0, size);
593
594 hdr->command = SLI4_MBOX_COMMAND_DOWN_LINK;
595
596 /* Port interprets zero in a field as "use default value" */
597
598 return sizeof(sli4_mbox_command_header_t);
599 }
600
601 /**
602 * @ingroup sli
603 * @brief Write a DUMP Type 4 command to the provided buffer.
604 *
605 * @param sli4 SLI context pointer.
606 * @param buf Virtual pointer to the destination buffer.
607 * @param size Buffer size, in bytes.
608 * @param wki The well known item ID.
609 *
610 * @return Returns the number of bytes written.
611 */
612 int32_t
sli_cmd_dump_type4(sli4_t * sli4,void * buf,size_t size,uint16_t wki)613 sli_cmd_dump_type4(sli4_t *sli4, void *buf, size_t size, uint16_t wki)
614 {
615 sli4_cmd_dump4_t *cmd = buf;
616
617 ocs_memset(buf, 0, size);
618
619 cmd->hdr.command = SLI4_MBOX_COMMAND_DUMP;
620 cmd->type = 4;
621 cmd->wki_selection = wki;
622 return sizeof(sli4_cmd_dump4_t);
623 }
624
625 /**
626 * @ingroup sli
627 * @brief Write a COMMON_READ_TRANSCEIVER_DATA command.
628 *
629 * @param sli4 SLI context.
630 * @param buf Destination buffer for the command.
631 * @param size Buffer size, in bytes.
632 * @param page_num The page of SFP data to retrieve (0xa0 or 0xa2).
633 * @param dma DMA structure from which the data will be copied.
634 *
635 * @note This creates a Version 0 message.
636 *
637 * @return Returns the number of bytes written.
638 */
639 int32_t
sli_cmd_common_read_transceiver_data(sli4_t * sli4,void * buf,size_t size,uint32_t page_num,ocs_dma_t * dma)640 sli_cmd_common_read_transceiver_data(sli4_t *sli4, void *buf, size_t size, uint32_t page_num,
641 ocs_dma_t *dma)
642 {
643 sli4_req_common_read_transceiver_data_t *req = NULL;
644 uint32_t sli_config_off = 0;
645 uint32_t payload_size;
646
647 if (dma == NULL) {
648 /* Payload length must accommodate both request and response */
649 payload_size = max(sizeof(sli4_req_common_read_transceiver_data_t),
650 sizeof(sli4_res_common_read_transceiver_data_t));
651 } else {
652 payload_size = dma->size;
653 }
654
655 if (sli4->port_type == SLI4_PORT_TYPE_FC) {
656 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size, dma);
657 }
658
659 if (dma == NULL) {
660 req = (sli4_req_common_read_transceiver_data_t *)((uint8_t *)buf + sli_config_off);
661 } else {
662 req = (sli4_req_common_read_transceiver_data_t *)dma->virt;
663 ocs_memset(req, 0, dma->size);
664 }
665
666 req->hdr.opcode = SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA;
667 req->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
668 req->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
669
670 req->page_number = page_num;
671 req->port = sli4->physical_port;
672
673 return(sli_config_off + sizeof(sli4_req_common_read_transceiver_data_t));
674 }
675
676 /**
677 * @ingroup sli
678 * @brief Write a READ_LINK_STAT command to the provided buffer.
679 *
680 * @param sli4 SLI context pointer.
681 * @param buf Virtual pointer to the destination buffer.
682 * @param size Buffer size, in bytes.
683 * @param req_ext_counters If TRUE, then the extended counters will be requested.
684 * @param clear_overflow_flags If TRUE, then overflow flags will be cleared.
685 * @param clear_all_counters If TRUE, the counters will be cleared.
686 *
687 * @return Returns the number of bytes written.
688 */
689 int32_t
sli_cmd_read_link_stats(sli4_t * sli4,void * buf,size_t size,uint8_t req_ext_counters,uint8_t clear_overflow_flags,uint8_t clear_all_counters)690 sli_cmd_read_link_stats(sli4_t *sli4, void *buf, size_t size,
691 uint8_t req_ext_counters,
692 uint8_t clear_overflow_flags,
693 uint8_t clear_all_counters)
694 {
695 sli4_cmd_read_link_stats_t *cmd = buf;
696
697 ocs_memset(buf, 0, size);
698
699 cmd->hdr.command = SLI4_MBOX_COMMAND_READ_LNK_STAT;
700 cmd->rec = req_ext_counters;
701 cmd->clrc = clear_all_counters;
702 cmd->clof = clear_overflow_flags;
703 return sizeof(sli4_cmd_read_link_stats_t);
704 }
705
706 /**
707 * @ingroup sli
708 * @brief Write a READ_STATUS command to the provided buffer.
709 *
710 * @param sli4 SLI context pointer.
711 * @param buf Virtual pointer to the destination buffer.
712 * @param size Buffer size, in bytes.
713 * @param clear_counters If TRUE, the counters will be cleared.
714 *
715 * @return Returns the number of bytes written.
716 */
717 int32_t
sli_cmd_read_status(sli4_t * sli4,void * buf,size_t size,uint8_t clear_counters)718 sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size,
719 uint8_t clear_counters)
720 {
721 sli4_cmd_read_status_t *cmd = buf;
722
723 ocs_memset(buf, 0, size);
724
725 cmd->hdr.command = SLI4_MBOX_COMMAND_READ_STATUS;
726 cmd->cc = clear_counters;
727 return sizeof(sli4_cmd_read_status_t);
728 }
729
730 /**
731 * @brief Write a FW_DEINITIALIZE command to the provided buffer.
732 *
733 * @param sli4 SLI context pointer.
734 * @param buf Virtual pointer to the destination buffer.
735 * @param size Buffer size, in bytes.
736 *
737 * @return Returns the number of bytes written.
738 */
739 static int32_t
sli_cmd_fw_deinitialize(sli4_t * sli4,void * buf,size_t size)740 sli_cmd_fw_deinitialize(sli4_t *sli4, void *buf, size_t size)
741 {
742
743 ocs_memset(buf, 0, size);
744 ocs_memcpy(buf, sli4_fw_deinitialize, sizeof(sli4_fw_deinitialize));
745
746 return sizeof(sli4_fw_deinitialize);
747 }
748
749 /**
750 * @brief Write a FW_INITIALIZE command to the provided buffer.
751 *
752 * @param sli4 SLI context pointer.
753 * @param buf Virtual pointer to the destination buffer.
754 * @param size Buffer size, in bytes.
755 *
756 * @return Returns the number of bytes written.
757 */
758 static int32_t
sli_cmd_fw_initialize(sli4_t * sli4,void * buf,size_t size)759 sli_cmd_fw_initialize(sli4_t *sli4, void *buf, size_t size)
760 {
761
762 ocs_memset(buf, 0, size);
763 ocs_memcpy(buf, sli4_fw_initialize, sizeof(sli4_fw_initialize));
764
765 return sizeof(sli4_fw_initialize);
766 }
767
768 /**
769 * @ingroup sli
770 * @brief update INIT_LINK flags with the sli config topology.
771 *
772 * @param sli4 SLI context pointer.
773 * @param init_link Pointer to the init link command
774 *
775 * @return Returns 0 on success, -1 on failure
776 */
777 static int32_t
sli4_set_link_flags_config_topo(sli4_t * sli4,sli4_cmd_init_link_t * init_link)778 sli4_set_link_flags_config_topo(sli4_t *sli4, sli4_cmd_init_link_t *init_link)
779 {
780
781 switch (sli4->config.topology) {
782 case SLI4_READ_CFG_TOPO_FC:
783 // Attempt P2P but failover to FC-AL
784 init_link->link_flags.enable_topology_failover = TRUE;
785 init_link->link_flags.topology = SLI4_INIT_LINK_F_P2P_FAIL_OVER;
786 break;
787 case SLI4_READ_CFG_TOPO_FC_AL:
788 init_link->link_flags.topology = SLI4_INIT_LINK_F_FCAL_ONLY;
789 return (!sli_fcal_is_speed_supported(init_link->link_speed_selection_code));
790
791 case SLI4_READ_CFG_TOPO_FC_DA:
792 init_link->link_flags.topology = FC_TOPOLOGY_P2P;
793 break;
794 default:
795 ocs_log_err(sli4->os, "unsupported topology %#x\n", sli4->config.topology);
796 return -1;
797 }
798
799 return 0;
800 }
801
802 /**
803 * @ingroup sli
804 * @brief update INIT_LINK flags with the persistent topology.
805 * PT stores value in compatible form, directly assign to link_flags
806 *
807 * @param sli4 SLI context pointer.
808 * @param init_link Pointer to the init link command
809 *
810 * @return Returns 0 on success, -1 on failure
811 */
812 static int32_t
sli4_set_link_flags_persistent_topo(sli4_t * sli4,sli4_cmd_init_link_t * init_link)813 sli4_set_link_flags_persistent_topo(sli4_t *sli4, sli4_cmd_init_link_t *init_link)
814 {
815 if ((sli4->config.pt == SLI4_INIT_LINK_F_FCAL_ONLY) &&
816 (!sli_fcal_is_speed_supported(init_link->link_speed_selection_code)))
817 return -1;
818
819 init_link->link_flags.enable_topology_failover = sli4->config.tf;
820 init_link->link_flags.topology = sli4->config.pt;
821
822 return 0;
823 }
824
825 /**
826 * @ingroup sli
827 * @brief Write an INIT_LINK command to the provided buffer.
828 *
829 * @param sli4 SLI context pointer.
830 * @param buf Virtual pointer to the destination buffer.
831 * @param size Buffer size, in bytes.
832 * @param speed Link speed.
833 * @param reset_alpa For native FC, this is the selective reset AL_PA
834 *
835 * @return Returns the number of bytes written.
836 */
837 int32_t
sli_cmd_init_link(sli4_t * sli4,void * buf,size_t size,uint32_t speed,uint8_t reset_alpa)838 sli_cmd_init_link(sli4_t *sli4, void *buf, size_t size, uint32_t speed, uint8_t reset_alpa)
839 {
840 sli4_cmd_init_link_t *init_link = buf;
841 int32_t rc = 0;
842
843 ocs_memset(buf, 0, size);
844
845 init_link->hdr.command = SLI4_MBOX_COMMAND_INIT_LINK;
846
847 /* Most fields only have meaning for FC links */
848 if (sli4->config.topology != SLI4_READ_CFG_TOPO_FCOE) {
849 init_link->selective_reset_al_pa = reset_alpa;
850 init_link->link_flags.loopback = FALSE;
851
852 init_link->link_speed_selection_code = speed;
853 switch (speed) {
854 case FC_LINK_SPEED_1G:
855 case FC_LINK_SPEED_2G:
856 case FC_LINK_SPEED_4G:
857 case FC_LINK_SPEED_8G:
858 case FC_LINK_SPEED_16G:
859 case FC_LINK_SPEED_32G:
860 init_link->link_flags.fixed_speed = TRUE;
861 break;
862 case FC_LINK_SPEED_10G:
863 ocs_log_test(sli4->os, "unsupported FC speed %d\n", speed);
864 return 0;
865 }
866
867 init_link->link_flags.unfair = FALSE;
868 init_link->link_flags.skip_lirp_lilp = FALSE;
869 init_link->link_flags.gen_loop_validity_check = FALSE;
870 init_link->link_flags.skip_lisa = FALSE;
871 init_link->link_flags.select_hightest_al_pa = FALSE;
872
873 //update topology in the link flags for link bring up
874 ocs_log_info(sli4->os, "bring up link with topology: %d, PTV: %d, TF: %d, PT: %d \n",
875 sli4->config.topology, sli4->config.ptv, sli4->config.tf, sli4->config.pt);
876 if (sli4->config.ptv)
877 rc = sli4_set_link_flags_persistent_topo(sli4, init_link);
878 else
879 rc = sli4_set_link_flags_config_topo(sli4, init_link);
880
881 }
882
883 return rc ? 0 : sizeof(sli4_cmd_init_link_t);
884 }
885
886 /**
887 * @ingroup sli
888 * @brief Write an INIT_VFI command to the provided buffer.
889 *
890 * @param sli4 SLI context pointer.
891 * @param buf Virtual pointer to the destination buffer.
892 * @param size Buffer size, in bytes.
893 * @param vfi VFI
894 * @param fcfi FCFI
895 * @param vpi VPI (Set to -1 if unused.)
896 *
897 * @return Returns the number of bytes written.
898 */
899 int32_t
sli_cmd_init_vfi(sli4_t * sli4,void * buf,size_t size,uint16_t vfi,uint16_t fcfi,uint16_t vpi)900 sli_cmd_init_vfi(sli4_t *sli4, void *buf, size_t size, uint16_t vfi,
901 uint16_t fcfi, uint16_t vpi)
902 {
903 sli4_cmd_init_vfi_t *init_vfi = buf;
904
905 ocs_memset(buf, 0, size);
906
907 init_vfi->hdr.command = SLI4_MBOX_COMMAND_INIT_VFI;
908
909 init_vfi->vfi = vfi;
910 init_vfi->fcfi = fcfi;
911
912 /*
913 * If the VPI is valid, initialize it at the same time as
914 * the VFI
915 */
916 if (0xffff != vpi) {
917 init_vfi->vp = TRUE;
918 init_vfi->vpi = vpi;
919 }
920
921 return sizeof(sli4_cmd_init_vfi_t);
922 }
923
924 /**
925 * @ingroup sli
926 * @brief Write an INIT_VPI command to the provided buffer.
927 *
928 * @param sli4 SLI context pointer.
929 * @param buf Virtual pointer to the destination buffer.
930 * @param size Buffer size, in bytes.
931 * @param vpi VPI allocated.
932 * @param vfi VFI associated with this VPI.
933 *
934 * @return Returns the number of bytes written.
935 */
936 int32_t
sli_cmd_init_vpi(sli4_t * sli4,void * buf,size_t size,uint16_t vpi,uint16_t vfi)937 sli_cmd_init_vpi(sli4_t *sli4, void *buf, size_t size, uint16_t vpi, uint16_t vfi)
938 {
939 sli4_cmd_init_vpi_t *init_vpi = buf;
940
941 ocs_memset(buf, 0, size);
942
943 init_vpi->hdr.command = SLI4_MBOX_COMMAND_INIT_VPI;
944 init_vpi->vpi = vpi;
945 init_vpi->vfi = vfi;
946
947 return sizeof(sli4_cmd_init_vpi_t);
948 }
949
950 /**
951 * @ingroup sli
952 * @brief Write a POST_XRI command to the provided buffer.
953 *
954 * @param sli4 SLI context pointer.
955 * @param buf Virtual pointer to the destination buffer.
956 * @param size Buffer size, in bytes.
957 * @param xri_base Starting XRI value for range of XRI given to SLI Port.
958 * @param xri_count Number of XRIs provided to the SLI Port.
959 *
960 * @return Returns the number of bytes written.
961 */
962 int32_t
sli_cmd_post_xri(sli4_t * sli4,void * buf,size_t size,uint16_t xri_base,uint16_t xri_count)963 sli_cmd_post_xri(sli4_t *sli4, void *buf, size_t size, uint16_t xri_base, uint16_t xri_count)
964 {
965 sli4_cmd_post_xri_t *post_xri = buf;
966
967 ocs_memset(buf, 0, size);
968
969 post_xri->hdr.command = SLI4_MBOX_COMMAND_POST_XRI;
970 post_xri->xri_base = xri_base;
971 post_xri->xri_count = xri_count;
972
973 if (sli4->config.auto_xfer_rdy == 0) {
974 post_xri->enx = TRUE;
975 post_xri->val = TRUE;
976 }
977
978 return sizeof(sli4_cmd_post_xri_t);
979 }
980
981 /**
982 * @ingroup sli
983 * @brief Write a RELEASE_XRI command to the provided buffer.
984 *
985 * @param sli4 SLI context pointer.
986 * @param buf Virtual pointer to the destination buffer.
987 * @param size Buffer size, in bytes.
988 * @param num_xri The number of XRIs to be released.
989 *
990 * @return Returns the number of bytes written.
991 */
992 int32_t
sli_cmd_release_xri(sli4_t * sli4,void * buf,size_t size,uint8_t num_xri)993 sli_cmd_release_xri(sli4_t *sli4, void *buf, size_t size, uint8_t num_xri)
994 {
995 sli4_cmd_release_xri_t *release_xri = buf;
996
997 ocs_memset(buf, 0, size);
998
999 release_xri->hdr.command = SLI4_MBOX_COMMAND_RELEASE_XRI;
1000 release_xri->xri_count = num_xri;
1001
1002 return sizeof(sli4_cmd_release_xri_t);
1003 }
1004
1005 /**
1006 * @brief Write a READ_CONFIG command to the provided buffer.
1007 *
1008 * @param sli4 SLI context pointer.
1009 * @param buf Virtual pointer to the destination buffer.
1010 * @param size Buffer size, in bytes
1011 *
1012 * @return Returns the number of bytes written.
1013 */
1014 static int32_t
sli_cmd_read_config(sli4_t * sli4,void * buf,size_t size)1015 sli_cmd_read_config(sli4_t *sli4, void *buf, size_t size)
1016 {
1017 sli4_cmd_read_config_t *read_config = buf;
1018
1019 ocs_memset(buf, 0, size);
1020
1021 read_config->hdr.command = SLI4_MBOX_COMMAND_READ_CONFIG;
1022
1023 return sizeof(sli4_cmd_read_config_t);
1024 }
1025
1026 /**
1027 * @brief Write a READ_NVPARMS command to the provided buffer.
1028 *
1029 * @param sli4 SLI context pointer.
1030 * @param buf Virtual pointer to the destination buffer.
1031 * @param size Buffer size, in bytes.
1032 *
1033 * @return Returns the number of bytes written.
1034 */
1035 int32_t
sli_cmd_read_nvparms(sli4_t * sli4,void * buf,size_t size)1036 sli_cmd_read_nvparms(sli4_t *sli4, void *buf, size_t size)
1037 {
1038 sli4_cmd_read_nvparms_t *read_nvparms = buf;
1039
1040 ocs_memset(buf, 0, size);
1041
1042 read_nvparms->hdr.command = SLI4_MBOX_COMMAND_READ_NVPARMS;
1043
1044 return sizeof(sli4_cmd_read_nvparms_t);
1045 }
1046
1047 /**
1048 * @brief Write a WRITE_NVPARMS command to the provided buffer.
1049 *
1050 * @param sli4 SLI context pointer.
1051 * @param buf Virtual pointer to the destination buffer.
1052 * @param size Buffer size, in bytes.
1053 * @param wwpn WWPN to write - pointer to array of 8 uint8_t.
1054 * @param wwnn WWNN to write - pointer to array of 8 uint8_t.
1055 * @param hard_alpa Hard ALPA to write.
1056 * @param preferred_d_id Preferred D_ID to write.
1057 *
1058 * @return Returns the number of bytes written.
1059 */
1060 int32_t
sli_cmd_write_nvparms(sli4_t * sli4,void * buf,size_t size,uint8_t * wwpn,uint8_t * wwnn,uint8_t hard_alpa,uint32_t preferred_d_id)1061 sli_cmd_write_nvparms(sli4_t *sli4, void *buf, size_t size, uint8_t *wwpn, uint8_t *wwnn, uint8_t hard_alpa,
1062 uint32_t preferred_d_id)
1063 {
1064 sli4_cmd_write_nvparms_t *write_nvparms = buf;
1065
1066 ocs_memset(buf, 0, size);
1067
1068 write_nvparms->hdr.command = SLI4_MBOX_COMMAND_WRITE_NVPARMS;
1069 ocs_memcpy(write_nvparms->wwpn, wwpn, 8);
1070 ocs_memcpy(write_nvparms->wwnn, wwnn, 8);
1071 write_nvparms->hard_alpa = hard_alpa;
1072 write_nvparms->preferred_d_id = preferred_d_id;
1073
1074 return sizeof(sli4_cmd_write_nvparms_t);
1075 }
1076
1077 /**
1078 * @brief Write a READ_REV command to the provided buffer.
1079 *
1080 * @param sli4 SLI context pointer.
1081 * @param buf Virtual pointer to the destination buffer.
1082 * @param size Buffer size, in bytes.
1083 * @param vpd Pointer to the buffer.
1084 *
1085 * @return Returns the number of bytes written.
1086 */
1087 static int32_t
sli_cmd_read_rev(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * vpd)1088 sli_cmd_read_rev(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *vpd)
1089 {
1090 sli4_cmd_read_rev_t *read_rev = buf;
1091
1092 ocs_memset(buf, 0, size);
1093
1094 read_rev->hdr.command = SLI4_MBOX_COMMAND_READ_REV;
1095
1096 if (vpd && vpd->size) {
1097 read_rev->vpd = TRUE;
1098
1099 read_rev->available_length = vpd->size;
1100
1101 read_rev->physical_address_low = ocs_addr32_lo(vpd->phys);
1102 read_rev->physical_address_high = ocs_addr32_hi(vpd->phys);
1103 }
1104
1105 return sizeof(sli4_cmd_read_rev_t);
1106 }
1107
1108 /**
1109 * @ingroup sli
1110 * @brief Write a READ_SPARM64 command to the provided buffer.
1111 *
1112 * @param sli4 SLI context pointer.
1113 * @param buf Virtual pointer to the destination buffer.
1114 * @param size Buffer size, in bytes.
1115 * @param dma DMA buffer for the service parameters.
1116 * @param vpi VPI used to determine the WWN.
1117 *
1118 * @return Returns the number of bytes written.
1119 */
1120 int32_t
sli_cmd_read_sparm64(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma,uint16_t vpi)1121 sli_cmd_read_sparm64(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma,
1122 uint16_t vpi)
1123 {
1124 sli4_cmd_read_sparm64_t *read_sparm64 = buf;
1125
1126 ocs_memset(buf, 0, size);
1127
1128 if (SLI4_READ_SPARM64_VPI_SPECIAL == vpi) {
1129 ocs_log_test(sli4->os, "special VPI not supported!!!\n");
1130 return -1;
1131 }
1132
1133 if (!dma || !dma->phys) {
1134 ocs_log_test(sli4->os, "bad DMA buffer\n");
1135 return -1;
1136 }
1137
1138 read_sparm64->hdr.command = SLI4_MBOX_COMMAND_READ_SPARM64;
1139
1140 read_sparm64->bde_64.bde_type = SLI4_BDE_TYPE_BDE_64;
1141 read_sparm64->bde_64.buffer_length = dma->size;
1142 read_sparm64->bde_64.u.data.buffer_address_low = ocs_addr32_lo(dma->phys);
1143 read_sparm64->bde_64.u.data.buffer_address_high = ocs_addr32_hi(dma->phys);
1144
1145 read_sparm64->vpi = vpi;
1146
1147 return sizeof(sli4_cmd_read_sparm64_t);
1148 }
1149
1150 /**
1151 * @ingroup sli
1152 * @brief Write a READ_TOPOLOGY command to the provided buffer.
1153 *
1154 * @param sli4 SLI context pointer.
1155 * @param buf Virtual pointer to the destination buffer.
1156 * @param size Buffer size, in bytes.
1157 * @param dma DMA buffer for loop map (optional).
1158 *
1159 * @return Returns the number of bytes written.
1160 */
1161 int32_t
sli_cmd_read_topology(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma)1162 sli_cmd_read_topology(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma)
1163 {
1164 sli4_cmd_read_topology_t *read_topo = buf;
1165
1166 ocs_memset(buf, 0, size);
1167
1168 read_topo->hdr.command = SLI4_MBOX_COMMAND_READ_TOPOLOGY;
1169
1170 if (dma && dma->size) {
1171 if (dma->size < SLI4_MIN_LOOP_MAP_BYTES) {
1172 ocs_log_test(sli4->os, "loop map buffer too small %jd\n",
1173 dma->size);
1174 return 0;
1175 }
1176
1177 ocs_memset(dma->virt, 0, dma->size);
1178
1179 read_topo->bde_loop_map.bde_type = SLI4_BDE_TYPE_BDE_64;
1180 read_topo->bde_loop_map.buffer_length = dma->size;
1181 read_topo->bde_loop_map.u.data.buffer_address_low = ocs_addr32_lo(dma->phys);
1182 read_topo->bde_loop_map.u.data.buffer_address_high = ocs_addr32_hi(dma->phys);
1183 }
1184
1185 return sizeof(sli4_cmd_read_topology_t);
1186 }
1187
1188 /**
1189 * @ingroup sli
1190 * @brief Write a REG_FCFI command to the provided buffer.
1191 *
1192 * @param sli4 SLI context pointer.
1193 * @param buf Virtual pointer to the destination buffer.
1194 * @param size Buffer size, in bytes.
1195 * @param index FCF index returned by READ_FCF_TABLE.
1196 * @param rq_cfg RQ_ID/R_CTL/TYPE routing information
1197 * @param vlan_id VLAN ID tag.
1198 *
1199 * @return Returns the number of bytes written.
1200 */
1201 int32_t
sli_cmd_reg_fcfi(sli4_t * sli4,void * buf,size_t size,uint16_t index,sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG],uint16_t vlan_id)1202 sli_cmd_reg_fcfi(sli4_t *sli4, void *buf, size_t size, uint16_t index, sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t vlan_id)
1203 {
1204 sli4_cmd_reg_fcfi_t *reg_fcfi = buf;
1205 uint32_t i;
1206
1207 ocs_memset(buf, 0, size);
1208
1209 reg_fcfi->hdr.command = SLI4_MBOX_COMMAND_REG_FCFI;
1210
1211 reg_fcfi->fcf_index = index;
1212
1213 for (i = 0; i < SLI4_CMD_REG_FCFI_NUM_RQ_CFG; i++) {
1214 switch(i) {
1215 case 0: reg_fcfi->rq_id_0 = rq_cfg[0].rq_id; break;
1216 case 1: reg_fcfi->rq_id_1 = rq_cfg[1].rq_id; break;
1217 case 2: reg_fcfi->rq_id_2 = rq_cfg[2].rq_id; break;
1218 case 3: reg_fcfi->rq_id_3 = rq_cfg[3].rq_id; break;
1219 }
1220 reg_fcfi->rq_cfg[i].r_ctl_mask = rq_cfg[i].r_ctl_mask;
1221 reg_fcfi->rq_cfg[i].r_ctl_match = rq_cfg[i].r_ctl_match;
1222 reg_fcfi->rq_cfg[i].type_mask = rq_cfg[i].type_mask;
1223 reg_fcfi->rq_cfg[i].type_match = rq_cfg[i].type_match;
1224 }
1225
1226 if (vlan_id) {
1227 reg_fcfi->vv = TRUE;
1228 reg_fcfi->vlan_tag = vlan_id;
1229 }
1230
1231 return sizeof(sli4_cmd_reg_fcfi_t);
1232 }
1233
1234 /**
1235 * @brief Write REG_FCFI_MRQ to provided command buffer
1236 *
1237 * @param sli4 SLI context pointer.
1238 * @param buf Virtual pointer to the destination buffer.
1239 * @param size Buffer size, in bytes.
1240 * @param fcf_index FCF index returned by READ_FCF_TABLE.
1241 * @param vlan_id VLAN ID tag.
1242 * @param rr_quant Round robin quanta if RQ selection policy is 2
1243 * @param rq_selection_policy RQ selection policy
1244 * @param num_rqs Array of count of RQs per filter
1245 * @param rq_ids Array of RQ ids per filter
1246 * @param rq_cfg RQ_ID/R_CTL/TYPE routing information
1247 *
1248 * @return returns 0 for success, a negative error code value for failure.
1249 */
1250 int32_t
sli_cmd_reg_fcfi_mrq(sli4_t * sli4,void * buf,size_t size,uint8_t mode,uint16_t fcf_index,uint16_t vlan_id,uint8_t rq_selection_policy,uint8_t mrq_bit_mask,uint16_t num_mrqs,sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG])1251 sli_cmd_reg_fcfi_mrq(sli4_t *sli4, void *buf, size_t size, uint8_t mode,
1252 uint16_t fcf_index, uint16_t vlan_id, uint8_t rq_selection_policy,
1253 uint8_t mrq_bit_mask, uint16_t num_mrqs,
1254 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG])
1255 {
1256 sli4_cmd_reg_fcfi_mrq_t *reg_fcfi_mrq = buf;
1257 uint32_t i;
1258
1259 ocs_memset(buf, 0, size);
1260
1261 reg_fcfi_mrq->hdr.command = SLI4_MBOX_COMMAND_REG_FCFI_MRQ;
1262 if (mode == SLI4_CMD_REG_FCFI_SET_FCFI_MODE) {
1263 reg_fcfi_mrq->fcf_index = fcf_index;
1264 if (vlan_id) {
1265 reg_fcfi_mrq->vv = TRUE;
1266 reg_fcfi_mrq->vlan_tag = vlan_id;
1267 }
1268 goto done;
1269 }
1270
1271 reg_fcfi_mrq->mode = mode;
1272 for (i = 0; i < SLI4_CMD_REG_FCFI_NUM_RQ_CFG; i++) {
1273 reg_fcfi_mrq->rq_cfg[i].r_ctl_mask = rq_cfg[i].r_ctl_mask;
1274 reg_fcfi_mrq->rq_cfg[i].r_ctl_match = rq_cfg[i].r_ctl_match;
1275 reg_fcfi_mrq->rq_cfg[i].type_mask = rq_cfg[i].type_mask;
1276 reg_fcfi_mrq->rq_cfg[i].type_match = rq_cfg[i].type_match;
1277
1278 switch(i) {
1279 case 3: reg_fcfi_mrq->rq_id_3 = rq_cfg[i].rq_id; break;
1280 case 2: reg_fcfi_mrq->rq_id_2 = rq_cfg[i].rq_id; break;
1281 case 1: reg_fcfi_mrq->rq_id_1 = rq_cfg[i].rq_id; break;
1282 case 0: reg_fcfi_mrq->rq_id_0 = rq_cfg[i].rq_id; break;
1283 }
1284 }
1285
1286 reg_fcfi_mrq->rq_selection_policy = rq_selection_policy;
1287 reg_fcfi_mrq->mrq_filter_bitmask = mrq_bit_mask;
1288 reg_fcfi_mrq->num_mrq_pairs = num_mrqs;
1289 done:
1290 return sizeof(sli4_cmd_reg_fcfi_mrq_t);
1291 }
1292
1293 /**
1294 * @ingroup sli
1295 * @brief Write a REG_RPI command to the provided buffer.
1296 *
1297 * @param sli4 SLI context pointer.
1298 * @param buf Virtual pointer to the destination buffer.
1299 * @param size Buffer size, in bytes.
1300 * @param nport_id Remote F/N_Port_ID.
1301 * @param rpi Previously-allocated Remote Port Indicator.
1302 * @param vpi Previously-allocated Virtual Port Indicator.
1303 * @param dma DMA buffer that contains the remote port's service parameters.
1304 * @param update Boolean indicating an update to an existing RPI (TRUE)
1305 * or a new registration (FALSE).
1306 *
1307 * @return Returns the number of bytes written.
1308 */
1309 int32_t
sli_cmd_reg_rpi(sli4_t * sli4,void * buf,size_t size,uint32_t nport_id,uint16_t rpi,uint16_t vpi,ocs_dma_t * dma,uint8_t update,uint8_t enable_t10_pi)1310 sli_cmd_reg_rpi(sli4_t *sli4, void *buf, size_t size, uint32_t nport_id, uint16_t rpi,
1311 uint16_t vpi, ocs_dma_t *dma, uint8_t update, uint8_t enable_t10_pi)
1312 {
1313 sli4_cmd_reg_rpi_t *reg_rpi = buf;
1314
1315 ocs_memset(buf, 0, size);
1316
1317 reg_rpi->hdr.command = SLI4_MBOX_COMMAND_REG_RPI;
1318
1319 reg_rpi->rpi = rpi;
1320 reg_rpi->remote_n_port_id = nport_id;
1321 reg_rpi->upd = update;
1322 reg_rpi->etow = enable_t10_pi;
1323
1324 reg_rpi->bde_64.bde_type = SLI4_BDE_TYPE_BDE_64;
1325 reg_rpi->bde_64.buffer_length = SLI4_REG_RPI_BUF_LEN;
1326 reg_rpi->bde_64.u.data.buffer_address_low = ocs_addr32_lo(dma->phys);
1327 reg_rpi->bde_64.u.data.buffer_address_high = ocs_addr32_hi(dma->phys);
1328
1329 reg_rpi->vpi = vpi;
1330
1331 return sizeof(sli4_cmd_reg_rpi_t);
1332 }
1333
1334 /**
1335 * @ingroup sli
1336 * @brief Write a REG_VFI command to the provided buffer.
1337 *
1338 * @param sli4 SLI context pointer.
1339 * @param buf Virtual pointer to the destination buffer.
1340 * @param size Buffer size, in bytes.
1341 * @param domain Pointer to the domain object.
1342 *
1343 * @return Returns the number of bytes written.
1344 */
1345 int32_t
sli_cmd_reg_vfi(sli4_t * sli4,void * buf,size_t size,ocs_domain_t * domain)1346 sli_cmd_reg_vfi(sli4_t *sli4, void *buf, size_t size, ocs_domain_t *domain)
1347 {
1348 sli4_cmd_reg_vfi_t *reg_vfi = buf;
1349
1350 if (!sli4 || !buf || !domain) {
1351 return 0;
1352 }
1353
1354 ocs_memset(buf, 0, size);
1355
1356 reg_vfi->hdr.command = SLI4_MBOX_COMMAND_REG_VFI;
1357
1358 reg_vfi->vfi = domain->indicator;
1359
1360 reg_vfi->fcfi = domain->fcf_indicator;
1361
1362 /* TODO contents of domain->dma only valid if topo == FABRIC */
1363 reg_vfi->sparm.bde_type = SLI4_BDE_TYPE_BDE_64;
1364 reg_vfi->sparm.buffer_length = 0x70;
1365 reg_vfi->sparm.u.data.buffer_address_low = ocs_addr32_lo(domain->dma.phys);
1366 reg_vfi->sparm.u.data.buffer_address_high = ocs_addr32_hi(domain->dma.phys);
1367
1368 reg_vfi->e_d_tov = sli4->config.e_d_tov;
1369 reg_vfi->r_a_tov = sli4->config.r_a_tov;
1370
1371 reg_vfi->vp = TRUE;
1372 reg_vfi->vpi = domain->sport->indicator;
1373 ocs_memcpy(reg_vfi->wwpn, &domain->sport->sli_wwpn, sizeof(reg_vfi->wwpn));
1374 reg_vfi->local_n_port_id = domain->sport->fc_id;
1375
1376 return sizeof(sli4_cmd_reg_vfi_t);
1377 }
1378
1379 /**
1380 * @ingroup sli
1381 * @brief Write a REG_VPI command to the provided buffer.
1382 *
1383 * @param sli4 SLI context pointer.
1384 * @param buf Virtual pointer to the destination buffer.
1385 * @param size Buffer size, in bytes.
1386 * @param sport Point to SLI Port object.
1387 * @param update Boolean indicating whether to update the existing VPI (true)
1388 * or create a new VPI (false).
1389 *
1390 * @return Returns the number of bytes written.
1391 */
1392 int32_t
sli_cmd_reg_vpi(sli4_t * sli4,void * buf,size_t size,ocs_sli_port_t * sport,uint8_t update)1393 sli_cmd_reg_vpi(sli4_t *sli4, void *buf, size_t size, ocs_sli_port_t *sport, uint8_t update)
1394 {
1395 sli4_cmd_reg_vpi_t *reg_vpi = buf;
1396
1397 if (!sli4 || !buf || !sport) {
1398 return 0;
1399 }
1400
1401 ocs_memset(buf, 0, size);
1402
1403 reg_vpi->hdr.command = SLI4_MBOX_COMMAND_REG_VPI;
1404
1405 reg_vpi->local_n_port_id = sport->fc_id;
1406 reg_vpi->upd = update != 0;
1407 ocs_memcpy(reg_vpi->wwpn, &sport->sli_wwpn, sizeof(reg_vpi->wwpn));
1408 reg_vpi->vpi = sport->indicator;
1409 reg_vpi->vfi = sport->domain->indicator;
1410
1411 return sizeof(sli4_cmd_reg_vpi_t);
1412 }
1413
1414 /**
1415 * @brief Write a REQUEST_FEATURES command to the provided buffer.
1416 *
1417 * @param sli4 SLI context pointer.
1418 * @param buf Virtual pointer to the destination buffer.
1419 * @param size Buffer size, in bytes.
1420 * @param mask Features to request.
1421 * @param query Use feature query mode (does not change FW).
1422 *
1423 * @return Returns the number of bytes written.
1424 */
1425 static int32_t
sli_cmd_request_features(sli4_t * sli4,void * buf,size_t size,sli4_features_t mask,uint8_t query)1426 sli_cmd_request_features(sli4_t *sli4, void *buf, size_t size, sli4_features_t mask, uint8_t query)
1427 {
1428 sli4_cmd_request_features_t *features = buf;
1429
1430 ocs_memset(buf, 0, size);
1431
1432 features->hdr.command = SLI4_MBOX_COMMAND_REQUEST_FEATURES;
1433
1434 if (query) {
1435 features->qry = TRUE;
1436 }
1437 features->command.dword = mask.dword;
1438
1439 return sizeof(sli4_cmd_request_features_t);
1440 }
1441
1442 /**
1443 * @ingroup sli
1444 * @brief Write a SLI_CONFIG command to the provided buffer.
1445 *
1446 * @param sli4 SLI context pointer.
1447 * @param buf Virtual pointer to the destination buffer.
1448 * @param size Buffer size, in bytes.
1449 * @param length Length in bytes of attached command.
1450 * @param dma DMA buffer for non-embedded commands.
1451 *
1452 * @return Returns the number of bytes written.
1453 */
1454 int32_t
sli_cmd_sli_config(sli4_t * sli4,void * buf,size_t size,uint32_t length,ocs_dma_t * dma)1455 sli_cmd_sli_config(sli4_t *sli4, void *buf, size_t size, uint32_t length, ocs_dma_t *dma)
1456 {
1457 sli4_cmd_sli_config_t *sli_config = NULL;
1458
1459 if ((length > sizeof(sli_config->payload.embed)) && (dma == NULL)) {
1460 ocs_log_test(sli4->os, "length(%d) > payload(%ld)\n",
1461 length, sizeof(sli_config->payload.embed));
1462 return -1;
1463 }
1464
1465 sli_config = buf;
1466
1467 ocs_memset(buf, 0, size);
1468
1469 sli_config->hdr.command = SLI4_MBOX_COMMAND_SLI_CONFIG;
1470 if (NULL == dma) {
1471 sli_config->emb = TRUE;
1472 sli_config->payload_length = length;
1473 } else {
1474 sli_config->emb = FALSE;
1475
1476 sli_config->pmd_count = 1;
1477
1478 sli_config->payload.mem.address_low = ocs_addr32_lo(dma->phys);
1479 sli_config->payload.mem.address_high = ocs_addr32_hi(dma->phys);
1480 sli_config->payload.mem.length = dma->size;
1481 sli_config->payload_length = dma->size;
1482 #if defined(OCS_INCLUDE_DEBUG)
1483 /* save pointer to DMA for BMBX dumping purposes */
1484 sli4->bmbx_non_emb_pmd = dma;
1485 #endif
1486
1487 }
1488
1489 return offsetof(sli4_cmd_sli_config_t, payload.embed);
1490 }
1491
1492 /**
1493 * @brief Initialize SLI Port control register.
1494 *
1495 * @param sli4 SLI context pointer.
1496 * @param endian Endian value to write.
1497 *
1498 * @return Returns 0 on success, or a negative error code value on failure.
1499 */
1500
1501 static int32_t
sli_sliport_control(sli4_t * sli4,uint32_t endian)1502 sli_sliport_control(sli4_t *sli4, uint32_t endian)
1503 {
1504 uint32_t iter;
1505 int32_t rc;
1506
1507 rc = -1;
1508
1509 /* Initialize port, endian */
1510 sli_reg_write(sli4, SLI4_REG_SLIPORT_CONTROL, endian | SLI4_SLIPORT_CONTROL_IP);
1511
1512 for (iter = 0; iter < 3000; iter ++) {
1513 ocs_udelay(SLI4_INIT_PORT_DELAY_US);
1514 if (sli_fw_ready(sli4) == 1) {
1515 rc = 0;
1516 break;
1517 }
1518 }
1519
1520 if (rc != 0) {
1521 ocs_log_crit(sli4->os, "port failed to become ready after initialization\n");
1522 }
1523
1524 return rc;
1525 }
1526
1527 /**
1528 * @ingroup sli
1529 * @brief Write a UNREG_FCFI command to the provided buffer.
1530 *
1531 * @param sli4 SLI context pointer.
1532 * @param buf Virtual pointer to the destination buffer.
1533 * @param size Buffer size, in bytes.
1534 * @param indicator Indicator value.
1535 *
1536 * @return Returns the number of bytes written.
1537 */
1538 int32_t
sli_cmd_unreg_fcfi(sli4_t * sli4,void * buf,size_t size,uint16_t indicator)1539 sli_cmd_unreg_fcfi(sli4_t *sli4, void *buf, size_t size, uint16_t indicator)
1540 {
1541 sli4_cmd_unreg_fcfi_t *unreg_fcfi = buf;
1542
1543 if (!sli4 || !buf) {
1544 return 0;
1545 }
1546
1547 ocs_memset(buf, 0, size);
1548
1549 unreg_fcfi->hdr.command = SLI4_MBOX_COMMAND_UNREG_FCFI;
1550
1551 unreg_fcfi->fcfi = indicator;
1552
1553 return sizeof(sli4_cmd_unreg_fcfi_t);
1554 }
1555
1556 /**
1557 * @ingroup sli
1558 * @brief Write an UNREG_RPI command to the provided buffer.
1559 *
1560 * @param sli4 SLI context pointer.
1561 * @param buf Virtual pointer to the destination buffer.
1562 * @param size Buffer size, in bytes.
1563 * @param indicator Indicator value.
1564 * @param which Type of unregister, such as node, port, domain, or FCF.
1565 * @param fc_id FC address.
1566 *
1567 * @return Returns the number of bytes written.
1568 */
1569 int32_t
sli_cmd_unreg_rpi(sli4_t * sli4,void * buf,size_t size,uint16_t indicator,sli4_resource_e which,uint32_t fc_id)1570 sli_cmd_unreg_rpi(sli4_t *sli4, void *buf, size_t size, uint16_t indicator, sli4_resource_e which,
1571 uint32_t fc_id)
1572 {
1573 sli4_cmd_unreg_rpi_t *unreg_rpi = buf;
1574 uint8_t index_indicator = 0;
1575
1576 if (!sli4 || !buf) {
1577 return 0;
1578 }
1579
1580 ocs_memset(buf, 0, size);
1581
1582 unreg_rpi->hdr.command = SLI4_MBOX_COMMAND_UNREG_RPI;
1583
1584 switch (which) {
1585 case SLI_RSRC_FCOE_RPI:
1586 index_indicator = SLI4_UNREG_RPI_II_RPI;
1587 if (fc_id != UINT32_MAX) {
1588 unreg_rpi->dp = TRUE;
1589 unreg_rpi->destination_n_port_id = fc_id & 0x00ffffff;
1590 }
1591 break;
1592 case SLI_RSRC_FCOE_VPI:
1593 index_indicator = SLI4_UNREG_RPI_II_VPI;
1594 break;
1595 case SLI_RSRC_FCOE_VFI:
1596 index_indicator = SLI4_UNREG_RPI_II_VFI;
1597 break;
1598 case SLI_RSRC_FCOE_FCFI:
1599 index_indicator = SLI4_UNREG_RPI_II_FCFI;
1600 break;
1601 default:
1602 ocs_log_test(sli4->os, "unknown type %#x\n", which);
1603 return 0;
1604 }
1605
1606 unreg_rpi->ii = index_indicator;
1607 unreg_rpi->index = indicator;
1608
1609 return sizeof(sli4_cmd_unreg_rpi_t);
1610 }
1611
1612 /**
1613 * @ingroup sli
1614 * @brief Write an UNREG_VFI command to the provided buffer.
1615 *
1616 * @param sli4 SLI context pointer.
1617 * @param buf Virtual pointer to the destination buffer.
1618 * @param size Buffer size, in bytes.
1619 * @param domain Pointer to the domain object
1620 * @param which Type of unregister, such as domain, FCFI, or everything.
1621 *
1622 * @return Returns the number of bytes written.
1623 */
1624 int32_t
sli_cmd_unreg_vfi(sli4_t * sli4,void * buf,size_t size,ocs_domain_t * domain,uint32_t which)1625 sli_cmd_unreg_vfi(sli4_t *sli4, void *buf, size_t size, ocs_domain_t *domain, uint32_t which)
1626 {
1627 sli4_cmd_unreg_vfi_t *unreg_vfi = buf;
1628
1629 if (!sli4 || !buf || !domain) {
1630 return 0;
1631 }
1632
1633 ocs_memset(buf, 0, size);
1634
1635 unreg_vfi->hdr.command = SLI4_MBOX_COMMAND_UNREG_VFI;
1636 switch (which) {
1637 case SLI4_UNREG_TYPE_DOMAIN:
1638 unreg_vfi->index = domain->indicator;
1639 break;
1640 case SLI4_UNREG_TYPE_FCF:
1641 unreg_vfi->index = domain->fcf_indicator;
1642 break;
1643 case SLI4_UNREG_TYPE_ALL:
1644 unreg_vfi->index = UINT16_MAX;
1645 break;
1646 default:
1647 return 0;
1648 }
1649
1650 if (SLI4_UNREG_TYPE_DOMAIN != which) {
1651 unreg_vfi->ii = SLI4_UNREG_VFI_II_FCFI;
1652 }
1653
1654 return sizeof(sli4_cmd_unreg_vfi_t);
1655 }
1656
1657 /**
1658 * @ingroup sli
1659 * @brief Write an UNREG_VPI command to the provided buffer.
1660 *
1661 * @param sli4 SLI context pointer.
1662 * @param buf Virtual pointer to the destination buffer.
1663 * @param size Buffer size, in bytes.
1664 * @param indicator Indicator value.
1665 * @param which Type of unregister: port, domain, FCFI, everything
1666 *
1667 * @return Returns the number of bytes written.
1668 */
1669 int32_t
sli_cmd_unreg_vpi(sli4_t * sli4,void * buf,size_t size,uint16_t indicator,uint32_t which)1670 sli_cmd_unreg_vpi(sli4_t *sli4, void *buf, size_t size, uint16_t indicator, uint32_t which)
1671 {
1672 sli4_cmd_unreg_vpi_t *unreg_vpi = buf;
1673
1674 if (!sli4 || !buf) {
1675 return 0;
1676 }
1677
1678 ocs_memset(buf, 0, size);
1679
1680 unreg_vpi->hdr.command = SLI4_MBOX_COMMAND_UNREG_VPI;
1681 unreg_vpi->index = indicator;
1682 switch (which) {
1683 case SLI4_UNREG_TYPE_PORT:
1684 unreg_vpi->ii = SLI4_UNREG_VPI_II_VPI;
1685 break;
1686 case SLI4_UNREG_TYPE_DOMAIN:
1687 unreg_vpi->ii = SLI4_UNREG_VPI_II_VFI;
1688 break;
1689 case SLI4_UNREG_TYPE_FCF:
1690 unreg_vpi->ii = SLI4_UNREG_VPI_II_FCFI;
1691 break;
1692 case SLI4_UNREG_TYPE_ALL:
1693 unreg_vpi->index = UINT16_MAX; /* override indicator */
1694 unreg_vpi->ii = SLI4_UNREG_VPI_II_FCFI;
1695 break;
1696 default:
1697 return 0;
1698 }
1699
1700 return sizeof(sli4_cmd_unreg_vpi_t);
1701 }
1702
1703
1704 /**
1705 * @ingroup sli
1706 * @brief Write an CONFIG_AUTO_XFER_RDY command to the provided buffer.
1707 *
1708 * @param sli4 SLI context pointer.
1709 * @param buf Virtual pointer to the destination buffer.
1710 * @param size Buffer size, in bytes.
1711 * @param max_burst_len if the write FCP_DL is less than this size,
1712 * then the SLI port will generate the auto XFER_RDY.
1713 *
1714 * @return Returns the number of bytes written.
1715 */
1716 int32_t
sli_cmd_config_auto_xfer_rdy(sli4_t * sli4,void * buf,size_t size,uint32_t max_burst_len)1717 sli_cmd_config_auto_xfer_rdy(sli4_t *sli4, void *buf, size_t size, uint32_t max_burst_len)
1718 {
1719 sli4_cmd_config_auto_xfer_rdy_t *req = buf;
1720
1721 if (!sli4 || !buf) {
1722 return 0;
1723 }
1724
1725 ocs_memset(buf, 0, size);
1726
1727 req->hdr.command = SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY;
1728 req->max_burst_len = max_burst_len;
1729
1730 return sizeof(sli4_cmd_config_auto_xfer_rdy_t);
1731 }
1732
1733 /**
1734 * @ingroup sli
1735 * @brief Write an CONFIG_AUTO_XFER_RDY_HP command to the provided buffer.
1736 *
1737 * @param sli4 SLI context pointer.
1738 * @param buf Virtual pointer to the destination buffer.
1739 * @param size Buffer size, in bytes.
1740 * @param max_burst_len if the write FCP_DL is less than this size,
1741 * @param esoc enable start offset computation,
1742 * @param block_size block size,
1743 * then the SLI port will generate the auto XFER_RDY.
1744 *
1745 * @return Returns the number of bytes written.
1746 */
1747 int32_t
sli_cmd_config_auto_xfer_rdy_hp(sli4_t * sli4,void * buf,size_t size,uint32_t max_burst_len,uint32_t esoc,uint32_t block_size)1748 sli_cmd_config_auto_xfer_rdy_hp(sli4_t *sli4, void *buf, size_t size, uint32_t max_burst_len,
1749 uint32_t esoc, uint32_t block_size )
1750 {
1751 sli4_cmd_config_auto_xfer_rdy_hp_t *req = buf;
1752
1753 if (!sli4 || !buf) {
1754 return 0;
1755 }
1756
1757 ocs_memset(buf, 0, size);
1758
1759 req->hdr.command = SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP;
1760 req->max_burst_len = max_burst_len;
1761 req->esoc = esoc;
1762 req->block_size = block_size;
1763 return sizeof(sli4_cmd_config_auto_xfer_rdy_hp_t);
1764 }
1765
1766 /**
1767 * @brief Write a COMMON_FUNCTION_RESET command.
1768 *
1769 * @param sli4 SLI context.
1770 * @param buf Destination buffer for the command.
1771 * @param size Buffer size, in bytes.
1772 *
1773 * @return Returns the number of bytes written.
1774 */
1775 static int32_t
sli_cmd_common_function_reset(sli4_t * sli4,void * buf,size_t size)1776 sli_cmd_common_function_reset(sli4_t *sli4, void *buf, size_t size)
1777 {
1778 sli4_req_common_function_reset_t *reset = NULL;
1779 uint32_t sli_config_off = 0;
1780
1781 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
1782 uint32_t payload_size;
1783
1784 /* Payload length must accommodate both request and response */
1785 payload_size = max(sizeof(sli4_req_common_function_reset_t),
1786 sizeof(sli4_res_common_function_reset_t));
1787
1788 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
1789 NULL);
1790 }
1791 reset = (sli4_req_common_function_reset_t *)((uint8_t *)buf + sli_config_off);
1792
1793 reset->hdr.opcode = SLI4_OPC_COMMON_FUNCTION_RESET;
1794 reset->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
1795
1796 return(sli_config_off + sizeof(sli4_req_common_function_reset_t));
1797 }
1798
1799 /**
1800 * @brief Write a COMMON_CREATE_CQ command.
1801 *
1802 * @param sli4 SLI context.
1803 * @param buf Destination buffer for the command.
1804 * @param size Buffer size, in bytes.
1805 * @param qmem DMA memory for the queue.
1806 * @param eq_id Associated EQ_ID
1807 * @param ignored This parameter carries the ULP which is only used for WQ and RQs
1808 *
1809 * @note This creates a Version 0 message.
1810 *
1811 * @return Returns the number of bytes written.
1812 */
1813 static int32_t
sli_cmd_common_create_cq(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * qmem,uint16_t eq_id,uint16_t ignored)1814 sli_cmd_common_create_cq(sli4_t *sli4, void *buf, size_t size,
1815 ocs_dma_t *qmem, uint16_t eq_id, uint16_t ignored)
1816 {
1817 sli4_req_common_create_cq_v0_t *cqv0 = NULL;
1818 sli4_req_common_create_cq_v2_t *cqv2 = NULL;
1819 uint32_t sli_config_off = 0;
1820 uint32_t p;
1821 uintptr_t addr;
1822 uint32_t if_type = sli4->if_type;
1823 uint32_t page_bytes = 0;
1824 uint32_t num_pages = 0;
1825 uint32_t cmd_size = 0;
1826 uint32_t page_size = 0;
1827 uint32_t n_cqe = 0;
1828
1829 /* First calculate number of pages and the mailbox cmd length */
1830 switch (if_type)
1831 {
1832 case SLI4_IF_TYPE_BE3_SKH_PF:
1833 page_bytes = SLI_PAGE_SIZE;
1834 num_pages = sli_page_count(qmem->size, page_bytes);
1835 cmd_size = sizeof(sli4_req_common_create_cq_v0_t) + (8 * num_pages);
1836 break;
1837 case SLI4_IF_TYPE_LANCER_FC_ETH:
1838 case SLI4_IF_TYPE_LANCER_G7:
1839 n_cqe = qmem->size / SLI4_CQE_BYTES;
1840 switch (n_cqe) {
1841 case 256:
1842 case 512:
1843 case 1024:
1844 case 2048:
1845 page_size = 1;
1846 break;
1847 case 4096:
1848 page_size = 2;
1849 break;
1850 default:
1851 return 0;
1852 }
1853 page_bytes = page_size * SLI_PAGE_SIZE;
1854 num_pages = sli_page_count(qmem->size, page_bytes);
1855 cmd_size = sizeof(sli4_req_common_create_cq_v2_t) + (8 * num_pages);
1856 break;
1857 default:
1858 ocs_log_test(sli4->os, "unsupported IF_TYPE %d\n", if_type);
1859 return -1;
1860 }
1861
1862
1863 /* now that we have the mailbox command size, we can set SLI_CONFIG fields */
1864 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
1865 uint32_t payload_size;
1866
1867 /* Payload length must accommodate both request and response */
1868 payload_size = max((size_t)cmd_size, sizeof(sli4_res_common_create_queue_t));
1869
1870 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
1871 NULL);
1872 }
1873
1874 switch (if_type)
1875 {
1876 case SLI4_IF_TYPE_BE3_SKH_PF:
1877 cqv0 = (sli4_req_common_create_cq_v0_t *)((uint8_t *)buf + sli_config_off);
1878 cqv0->hdr.opcode = SLI4_OPC_COMMON_CREATE_CQ;
1879 cqv0->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
1880 cqv0->hdr.version = 0;
1881 cqv0->hdr.request_length = cmd_size - sizeof(sli4_req_hdr_t);
1882
1883 /* valid values for number of pages: 1, 2, 4 (sec 4.4.3) */
1884 cqv0->num_pages = num_pages;
1885 switch (cqv0->num_pages) {
1886 case 1:
1887 cqv0->cqecnt = SLI4_CQ_CNT_256;
1888 break;
1889 case 2:
1890 cqv0->cqecnt = SLI4_CQ_CNT_512;
1891 break;
1892 case 4:
1893 cqv0->cqecnt = SLI4_CQ_CNT_1024;
1894 break;
1895 default:
1896 ocs_log_test(sli4->os, "num_pages %d not valid\n", cqv0->num_pages);
1897 return -1;
1898 }
1899 cqv0->evt = TRUE;
1900 cqv0->valid = TRUE;
1901 /* TODO cq->nodelay = ???; */
1902 /* TODO cq->clswm = ???; */
1903 cqv0->arm = FALSE;
1904 cqv0->eq_id = eq_id;
1905
1906 for (p = 0, addr = qmem->phys;
1907 p < cqv0->num_pages;
1908 p++, addr += page_bytes) {
1909 cqv0->page_physical_address[p].low = ocs_addr32_lo(addr);
1910 cqv0->page_physical_address[p].high = ocs_addr32_hi(addr);
1911 }
1912
1913 break;
1914 case SLI4_IF_TYPE_LANCER_FC_ETH:
1915 case SLI4_IF_TYPE_LANCER_G7:
1916 {
1917 cqv2 = (sli4_req_common_create_cq_v2_t *)((uint8_t *)buf + sli_config_off);
1918 cqv2->hdr.opcode = SLI4_OPC_COMMON_CREATE_CQ;
1919 cqv2->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
1920 cqv2->hdr.version = 2;
1921 cqv2->hdr.request_length = cmd_size - sizeof(sli4_req_hdr_t);
1922
1923 if (if_type == SLI4_IF_TYPE_LANCER_G7)
1924 cqv2->autovalid = TRUE;
1925
1926 cqv2->page_size = page_size;
1927
1928 /* valid values for number of pages: 1, 2, 4, 8 (sec 4.4.3) */
1929 cqv2->num_pages = num_pages;
1930 if (!cqv2->num_pages || (cqv2->num_pages > SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES)) {
1931 return 0;
1932 }
1933
1934 switch (cqv2->num_pages) {
1935 case 1:
1936 cqv2->cqecnt = SLI4_CQ_CNT_256;
1937 break;
1938 case 2:
1939 cqv2->cqecnt = SLI4_CQ_CNT_512;
1940 break;
1941 case 4:
1942 cqv2->cqecnt = SLI4_CQ_CNT_1024;
1943 break;
1944 case 8:
1945 cqv2->cqecnt = SLI4_CQ_CNT_LARGE;
1946 cqv2->cqe_count = n_cqe;
1947 break;
1948 default:
1949 ocs_log_test(sli4->os, "num_pages %d not valid\n", cqv2->num_pages);
1950 return -1;
1951 }
1952
1953 cqv2->evt = TRUE;
1954 cqv2->valid = TRUE;
1955 /* TODO cq->nodelay = ???; */
1956 /* TODO cq->clswm = ???; */
1957 cqv2->arm = FALSE;
1958 cqv2->eq_id = eq_id;
1959
1960 for (p = 0, addr = qmem->phys;
1961 p < cqv2->num_pages;
1962 p++, addr += page_bytes) {
1963 cqv2->page_physical_address[p].low = ocs_addr32_lo(addr);
1964 cqv2->page_physical_address[p].high = ocs_addr32_hi(addr);
1965 }
1966 }
1967 break;
1968 default:
1969 ocs_log_test(sli4->os, "unsupported IF_TYPE %d\n", if_type);
1970 return -1;
1971 }
1972
1973 return (sli_config_off + cmd_size);
1974 }
1975
1976 /**
1977 * @brief Write a COMMON_DESTROY_CQ command.
1978 *
1979 * @param sli4 SLI context.
1980 * @param buf Destination buffer for the command.
1981 * @param size Buffer size, in bytes.
1982 * @param cq_id CQ ID
1983 *
1984 * @note This creates a Version 0 message.
1985 *
1986 * @return Returns the number of bytes written.
1987 */
1988 static int32_t
sli_cmd_common_destroy_cq(sli4_t * sli4,void * buf,size_t size,uint16_t cq_id)1989 sli_cmd_common_destroy_cq(sli4_t *sli4, void *buf, size_t size, uint16_t cq_id)
1990 {
1991 sli4_req_common_destroy_cq_t *cq = NULL;
1992 uint32_t sli_config_off = 0;
1993
1994 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
1995 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
1996 /* Payload length must accommodate both request and response */
1997 max(sizeof(sli4_req_common_destroy_cq_t),
1998 sizeof(sli4_res_hdr_t)),
1999 NULL);
2000 }
2001 cq = (sli4_req_common_destroy_cq_t *)((uint8_t *)buf + sli_config_off);
2002
2003 cq->hdr.opcode = SLI4_OPC_COMMON_DESTROY_CQ;
2004 cq->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2005 cq->hdr.request_length = sizeof(sli4_req_common_destroy_cq_t) -
2006 sizeof(sli4_req_hdr_t);
2007 cq->cq_id = cq_id;
2008
2009 return(sli_config_off + sizeof(sli4_req_common_destroy_cq_t));
2010 }
2011
2012 /**
2013 * @brief Write a COMMON_MODIFY_EQ_DELAY command.
2014 *
2015 * @param sli4 SLI context.
2016 * @param buf Destination buffer for the command.
2017 * @param size Buffer size, in bytes.
2018 * @param q Queue object array.
2019 * @param num_q Queue object array count.
2020 * @param shift Phase shift for staggering interrupts.
2021 * @param delay_mult Delay multiplier for limiting interrupt frequency.
2022 *
2023 * @return Returns the number of bytes written.
2024 */
2025 static int32_t
sli_cmd_common_modify_eq_delay(sli4_t * sli4,void * buf,size_t size,sli4_queue_t * q,int num_q,uint32_t shift,uint32_t delay_mult)2026 sli_cmd_common_modify_eq_delay(sli4_t *sli4, void *buf, size_t size, sli4_queue_t *q, int num_q, uint32_t shift,
2027 uint32_t delay_mult)
2028 {
2029 sli4_req_common_modify_eq_delay_t *modify_delay = NULL;
2030 uint32_t sli_config_off = 0;
2031 int i;
2032
2033 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2034 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2035 /* Payload length must accommodate both request and response */
2036 max(sizeof(sli4_req_common_modify_eq_delay_t), sizeof(sli4_res_hdr_t)),
2037 NULL);
2038 }
2039
2040 modify_delay = (sli4_req_common_modify_eq_delay_t *)((uint8_t *)buf + sli_config_off);
2041
2042 modify_delay->hdr.opcode = SLI4_OPC_COMMON_MODIFY_EQ_DELAY;
2043 modify_delay->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2044 modify_delay->hdr.request_length = sizeof(sli4_req_common_modify_eq_delay_t) -
2045 sizeof(sli4_req_hdr_t);
2046
2047 modify_delay->num_eq = num_q;
2048
2049 for (i = 0; i<num_q; i++) {
2050 modify_delay->eq_delay_record[i].eq_id = q[i].id;
2051 modify_delay->eq_delay_record[i].phase = shift;
2052 modify_delay->eq_delay_record[i].delay_multiplier = delay_mult;
2053 }
2054
2055 return(sli_config_off + sizeof(sli4_req_common_modify_eq_delay_t));
2056 }
2057
2058 /**
2059 * @brief Write a COMMON_CREATE_EQ command.
2060 *
2061 * @param sli4 SLI context.
2062 * @param buf Destination buffer for the command.
2063 * @param size Buffer size, in bytes.
2064 * @param qmem DMA memory for the queue.
2065 * @param ignored1 Ignored (used for consistency among queue creation functions).
2066 * @param ignored2 Ignored (used for consistency among queue creation functions).
2067 *
2068 * @note Other queue creation routines use the last parameter to pass in
2069 * the associated Q_ID and ULP. EQ doesn't have an associated queue or ULP,
2070 * so these parameters are ignored
2071 *
2072 * @note This creates a Version 0 message
2073 *
2074 * @return Returns the number of bytes written.
2075 */
2076 static int32_t
sli_cmd_common_create_eq(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * qmem,uint16_t ignored1,uint16_t ignored2)2077 sli_cmd_common_create_eq(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *qmem,
2078 uint16_t ignored1, uint16_t ignored2)
2079 {
2080 sli4_req_common_create_eq_t *eq = NULL;
2081 uint32_t sli_config_off = 0;
2082 uint32_t p;
2083 uintptr_t addr;
2084
2085 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2086 uint32_t payload_size;
2087
2088 /* Payload length must accommodate both request and response */
2089 payload_size = max(sizeof(sli4_req_common_create_eq_t),
2090 sizeof(sli4_res_common_create_queue_t));
2091
2092 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
2093 NULL);
2094 }
2095 eq = (sli4_req_common_create_eq_t *)((uint8_t *)buf + sli_config_off);
2096
2097 eq->hdr.opcode = SLI4_OPC_COMMON_CREATE_EQ;
2098 eq->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2099 eq->hdr.request_length = sizeof(sli4_req_common_create_eq_t) -
2100 sizeof(sli4_req_hdr_t);
2101 if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) {
2102 eq->hdr.version = 2;
2103 eq->autovalid = TRUE;
2104 }
2105 /* valid values for number of pages: 1, 2, 4 (sec 4.4.3) */
2106 eq->num_pages = qmem->size / SLI_PAGE_SIZE;
2107 switch (eq->num_pages) {
2108 case 1:
2109 eq->eqesz = SLI4_EQE_SIZE_4;
2110 eq->count = SLI4_EQ_CNT_1024;
2111 break;
2112 case 2:
2113 eq->eqesz = SLI4_EQE_SIZE_4;
2114 eq->count = SLI4_EQ_CNT_2048;
2115 break;
2116 case 4:
2117 eq->eqesz = SLI4_EQE_SIZE_4;
2118 eq->count = SLI4_EQ_CNT_4096;
2119 break;
2120 default:
2121 ocs_log_test(sli4->os, "num_pages %d not valid\n", eq->num_pages);
2122 return -1;
2123 }
2124 eq->valid = TRUE;
2125 eq->arm = FALSE;
2126 eq->delay_multiplier = 32;
2127
2128 for (p = 0, addr = qmem->phys;
2129 p < eq->num_pages;
2130 p++, addr += SLI_PAGE_SIZE) {
2131 eq->page_address[p].low = ocs_addr32_lo(addr);
2132 eq->page_address[p].high = ocs_addr32_hi(addr);
2133 }
2134
2135 return(sli_config_off + sizeof(sli4_req_common_create_eq_t));
2136 }
2137
2138
2139 /**
2140 * @brief Write a COMMON_DESTROY_EQ command.
2141 *
2142 * @param sli4 SLI context.
2143 * @param buf Destination buffer for the command.
2144 * @param size Buffer size, in bytes.
2145 * @param eq_id Queue ID to destroy.
2146 *
2147 * @note Other queue creation routines use the last parameter to pass in
2148 * the associated Q_ID. EQ doesn't have an associated queue so this
2149 * parameter is ignored.
2150 *
2151 * @note This creates a Version 0 message.
2152 *
2153 * @return Returns the number of bytes written.
2154 */
2155 static int32_t
sli_cmd_common_destroy_eq(sli4_t * sli4,void * buf,size_t size,uint16_t eq_id)2156 sli_cmd_common_destroy_eq(sli4_t *sli4, void *buf, size_t size, uint16_t eq_id)
2157 {
2158 sli4_req_common_destroy_eq_t *eq = NULL;
2159 uint32_t sli_config_off = 0;
2160
2161 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2162 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2163 /* Payload length must accommodate both request and response */
2164 max(sizeof(sli4_req_common_destroy_eq_t),
2165 sizeof(sli4_res_hdr_t)),
2166 NULL);
2167 }
2168 eq = (sli4_req_common_destroy_eq_t *)((uint8_t *)buf + sli_config_off);
2169
2170 eq->hdr.opcode = SLI4_OPC_COMMON_DESTROY_EQ;
2171 eq->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2172 eq->hdr.request_length = sizeof(sli4_req_common_destroy_eq_t) -
2173 sizeof(sli4_req_hdr_t);
2174
2175 eq->eq_id = eq_id;
2176
2177 return(sli_config_off + sizeof(sli4_req_common_destroy_eq_t));
2178 }
2179
2180 /**
2181 * @brief Write a LOWLEVEL_SET_WATCHDOG command.
2182 *
2183 * @param sli4 SLI context.
2184 * @param buf Destination buffer for the command.
2185 * @param size Buffer size, in bytes.
2186 * @param timeout watchdog timer timeout in seconds
2187 *
2188 * @return void
2189 */
2190 void
sli4_cmd_lowlevel_set_watchdog(sli4_t * sli4,void * buf,size_t size,uint16_t timeout)2191 sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout)
2192 {
2193
2194 sli4_req_lowlevel_set_watchdog_t *req = NULL;
2195 uint32_t sli_config_off = 0;
2196
2197 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2198 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2199 /* Payload length must accommodate both request and response */
2200 max(sizeof(sli4_req_lowlevel_set_watchdog_t),
2201 sizeof(sli4_res_lowlevel_set_watchdog_t)),
2202 NULL);
2203 }
2204 req = (sli4_req_lowlevel_set_watchdog_t *)((uint8_t *)buf + sli_config_off);
2205
2206 req->hdr.opcode = SLI4_OPC_LOWLEVEL_SET_WATCHDOG;
2207 req->hdr.subsystem = SLI4_SUBSYSTEM_LOWLEVEL;
2208 req->hdr.request_length = sizeof(sli4_req_lowlevel_set_watchdog_t) - sizeof(sli4_req_hdr_t);
2209 req->watchdog_timeout = timeout;
2210
2211 return;
2212 }
2213
2214 static int32_t
sli_cmd_common_get_cntl_attributes(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma)2215 sli_cmd_common_get_cntl_attributes(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma)
2216 {
2217 sli4_req_hdr_t *hdr = NULL;
2218 uint32_t sli_config_off = 0;
2219
2220 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2221 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2222 sizeof(sli4_req_hdr_t),
2223 dma);
2224 }
2225
2226 if (dma == NULL) {
2227 return 0;
2228 }
2229
2230 ocs_memset(dma->virt, 0, dma->size);
2231
2232 hdr = dma->virt;
2233
2234 hdr->opcode = SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES;
2235 hdr->subsystem = SLI4_SUBSYSTEM_COMMON;
2236 hdr->request_length = dma->size;
2237
2238 return(sli_config_off + sizeof(sli4_req_hdr_t));
2239 }
2240
2241 /**
2242 * @brief Write a COMMON_GET_CNTL_ADDL_ATTRIBUTES command.
2243 *
2244 * @param sli4 SLI context.
2245 * @param buf Destination buffer for the command.
2246 * @param size Buffer size, in bytes.
2247 * @param dma DMA structure from which the data will be copied.
2248 *
2249 * @note This creates a Version 0 message.
2250 *
2251 * @return Returns the number of bytes written.
2252 */
2253 static int32_t
sli_cmd_common_get_cntl_addl_attributes(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma)2254 sli_cmd_common_get_cntl_addl_attributes(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma)
2255 {
2256 sli4_req_hdr_t *hdr = NULL;
2257 uint32_t sli_config_off = 0;
2258
2259 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2260 sli_config_off = sli_cmd_sli_config(sli4, buf, size, sizeof(sli4_req_hdr_t), dma);
2261 }
2262
2263 if (dma == NULL) {
2264 return 0;
2265 }
2266
2267 ocs_memset(dma->virt, 0, dma->size);
2268
2269 hdr = dma->virt;
2270
2271 hdr->opcode = SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES;
2272 hdr->subsystem = SLI4_SUBSYSTEM_COMMON;
2273 hdr->request_length = dma->size;
2274
2275 return(sli_config_off + sizeof(sli4_req_hdr_t));
2276 }
2277
2278 /**
2279 * @brief Write a COMMON_CREATE_MQ_EXT command.
2280 *
2281 * @param sli4 SLI context.
2282 * @param buf Destination buffer for the command.
2283 * @param size Buffer size, in bytes.
2284 * @param qmem DMA memory for the queue.
2285 * @param cq_id Associated CQ_ID.
2286 * @param ignored This parameter carries the ULP which is only used for WQ and RQs
2287 *
2288 * @note This creates a Version 0 message.
2289 *
2290 * @return Returns the number of bytes written.
2291 */
2292 static int32_t
sli_cmd_common_create_mq_ext(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * qmem,uint16_t cq_id,uint16_t ignored)2293 sli_cmd_common_create_mq_ext(sli4_t *sli4, void *buf, size_t size,
2294 ocs_dma_t *qmem, uint16_t cq_id, uint16_t ignored)
2295 {
2296 sli4_req_common_create_mq_ext_t *mq = NULL;
2297 uint32_t sli_config_off = 0;
2298 uint32_t p;
2299 uintptr_t addr;
2300
2301 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2302 uint32_t payload_size;
2303
2304 /* Payload length must accommodate both request and response */
2305 payload_size = max(sizeof(sli4_req_common_create_mq_ext_t),
2306 sizeof(sli4_res_common_create_queue_t));
2307
2308 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
2309 NULL);
2310 }
2311 mq = (sli4_req_common_create_mq_ext_t *)((uint8_t *)buf + sli_config_off);
2312
2313 mq->hdr.opcode = SLI4_OPC_COMMON_CREATE_MQ_EXT;
2314 mq->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2315 mq->hdr.request_length = sizeof(sli4_req_common_create_mq_ext_t) -
2316 sizeof(sli4_req_hdr_t);
2317 /* valid values for number of pages: 1, 2, 4, 8 (sec 4.4.12) */
2318 mq->num_pages = qmem->size / SLI_PAGE_SIZE;
2319 switch (mq->num_pages) {
2320 case 1:
2321 mq->ring_size = SLI4_MQE_SIZE_16;
2322 break;
2323 case 2:
2324 mq->ring_size = SLI4_MQE_SIZE_32;
2325 break;
2326 case 4:
2327 mq->ring_size = SLI4_MQE_SIZE_64;
2328 break;
2329 case 8:
2330 mq->ring_size = SLI4_MQE_SIZE_128;
2331 break;
2332 default:
2333 ocs_log_test(sli4->os, "num_pages %d not valid\n", mq->num_pages);
2334 return -1;
2335 }
2336
2337 /* TODO break this down by sli4->config.topology */
2338 mq->async_event_bitmap = SLI4_ASYNC_EVT_FC_FCOE;
2339
2340 if (sli4->config.mq_create_version) {
2341 mq->cq_id_v1 = cq_id;
2342 mq->hdr.version = 1;
2343 }
2344 else {
2345 mq->cq_id_v0 = cq_id;
2346 }
2347 mq->val = TRUE;
2348
2349 for (p = 0, addr = qmem->phys;
2350 p < mq->num_pages;
2351 p++, addr += SLI_PAGE_SIZE) {
2352 mq->page_physical_address[p].low = ocs_addr32_lo(addr);
2353 mq->page_physical_address[p].high = ocs_addr32_hi(addr);
2354 }
2355
2356 return(sli_config_off + sizeof(sli4_req_common_create_mq_ext_t));
2357 }
2358
2359 /**
2360 * @brief Write a COMMON_DESTROY_MQ command.
2361 *
2362 * @param sli4 SLI context.
2363 * @param buf Destination buffer for the command.
2364 * @param size Buffer size, in bytes.
2365 * @param mq_id MQ ID
2366 *
2367 * @note This creates a Version 0 message.
2368 *
2369 * @return Returns the number of bytes written.
2370 */
2371 static int32_t
sli_cmd_common_destroy_mq(sli4_t * sli4,void * buf,size_t size,uint16_t mq_id)2372 sli_cmd_common_destroy_mq(sli4_t *sli4, void *buf, size_t size, uint16_t mq_id)
2373 {
2374 sli4_req_common_destroy_mq_t *mq = NULL;
2375 uint32_t sli_config_off = 0;
2376
2377 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2378 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2379 /* Payload length must accommodate both request and response */
2380 max(sizeof(sli4_req_common_destroy_mq_t),
2381 sizeof(sli4_res_hdr_t)),
2382 NULL);
2383 }
2384 mq = (sli4_req_common_destroy_mq_t *)((uint8_t *)buf + sli_config_off);
2385
2386 mq->hdr.opcode = SLI4_OPC_COMMON_DESTROY_MQ;
2387 mq->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2388 mq->hdr.request_length = sizeof(sli4_req_common_destroy_mq_t) -
2389 sizeof(sli4_req_hdr_t);
2390
2391 mq->mq_id = mq_id;
2392
2393 return(sli_config_off + sizeof(sli4_req_common_destroy_mq_t));
2394 }
2395
2396 /**
2397 * @ingroup sli
2398 * @brief Write a COMMON_NOP command
2399 *
2400 * @param sli4 SLI context.
2401 * @param buf Destination buffer for the command.
2402 * @param size Buffer size, in bytes.
2403 * @param context NOP context value (passed to response, except on FC/FCoE).
2404 *
2405 * @return Returns the number of bytes written.
2406 */
2407 int32_t
sli_cmd_common_nop(sli4_t * sli4,void * buf,size_t size,uint64_t context)2408 sli_cmd_common_nop(sli4_t *sli4, void *buf, size_t size, uint64_t context)
2409 {
2410 sli4_req_common_nop_t *nop = NULL;
2411 uint32_t sli_config_off = 0;
2412
2413 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2414 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2415 /* Payload length must accommodate both request and response */
2416 max(sizeof(sli4_req_common_nop_t), sizeof(sli4_res_common_nop_t)),
2417 NULL);
2418 }
2419
2420 nop = (sli4_req_common_nop_t *)((uint8_t *)buf + sli_config_off);
2421
2422 nop->hdr.opcode = SLI4_OPC_COMMON_NOP;
2423 nop->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2424 nop->hdr.request_length = 8;
2425
2426 ocs_memcpy(&nop->context, &context, sizeof(context));
2427
2428 return(sli_config_off + sizeof(sli4_req_common_nop_t));
2429 }
2430
2431 /**
2432 * @ingroup sli
2433 * @brief Write a COMMON_GET_RESOURCE_EXTENT_INFO command.
2434 *
2435 * @param sli4 SLI context.
2436 * @param buf Destination buffer for the command.
2437 * @param size Buffer size, in bytes.
2438 * @param rtype Resource type (for example, XRI, VFI, VPI, and RPI).
2439 *
2440 * @return Returns the number of bytes written.
2441 */
2442 int32_t
sli_cmd_common_get_resource_extent_info(sli4_t * sli4,void * buf,size_t size,uint16_t rtype)2443 sli_cmd_common_get_resource_extent_info(sli4_t *sli4, void *buf, size_t size, uint16_t rtype)
2444 {
2445 sli4_req_common_get_resource_extent_info_t *extent = NULL;
2446 uint32_t sli_config_off = 0;
2447
2448 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2449 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2450 sizeof(sli4_req_common_get_resource_extent_info_t),
2451 NULL);
2452 }
2453
2454 extent = (sli4_req_common_get_resource_extent_info_t *)((uint8_t *)buf + sli_config_off);
2455
2456 extent->hdr.opcode = SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO;
2457 extent->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2458 extent->hdr.request_length = 4;
2459
2460 extent->resource_type = rtype;
2461
2462 return(sli_config_off + sizeof(sli4_req_common_get_resource_extent_info_t));
2463 }
2464
2465 /**
2466 * @ingroup sli
2467 * @brief Write a COMMON_GET_SLI4_PARAMETERS command.
2468 *
2469 * @param sli4 SLI context.
2470 * @param buf Destination buffer for the command.
2471 * @param size Buffer size, in bytes.
2472 *
2473 * @return Returns the number of bytes written.
2474 */
2475 int32_t
sli_cmd_common_get_sli4_parameters(sli4_t * sli4,void * buf,size_t size)2476 sli_cmd_common_get_sli4_parameters(sli4_t *sli4, void *buf, size_t size)
2477 {
2478 sli4_req_hdr_t *hdr = NULL;
2479 uint32_t sli_config_off = 0;
2480
2481 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2482 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2483 sizeof(sli4_res_common_get_sli4_parameters_t),
2484 NULL);
2485 }
2486
2487 hdr = (sli4_req_hdr_t *)((uint8_t *)buf + sli_config_off);
2488
2489 hdr->opcode = SLI4_OPC_COMMON_GET_SLI4_PARAMETERS;
2490 hdr->subsystem = SLI4_SUBSYSTEM_COMMON;
2491 hdr->request_length = 0x50;
2492
2493 return(sli_config_off + sizeof(sli4_req_hdr_t));
2494 }
2495
2496 /**
2497 * @brief Write a COMMON_QUERY_FW_CONFIG command to the provided buffer.
2498 *
2499 * @param sli4 SLI context pointer.
2500 * @param buf Virtual pointer to destination buffer.
2501 * @param size Buffer size in bytes.
2502 *
2503 * @return Returns the number of bytes written
2504 */
2505 static int32_t
sli_cmd_common_query_fw_config(sli4_t * sli4,void * buf,size_t size)2506 sli_cmd_common_query_fw_config(sli4_t *sli4, void *buf, size_t size)
2507 {
2508 sli4_req_common_query_fw_config_t *fw_config;
2509 uint32_t sli_config_off = 0;
2510 uint32_t payload_size;
2511
2512 /* Payload length must accommodate both request and response */
2513 payload_size = max(sizeof(sli4_req_common_query_fw_config_t),
2514 sizeof(sli4_res_common_query_fw_config_t));
2515
2516 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2517 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2518 payload_size,
2519 NULL);
2520 }
2521
2522 fw_config = (sli4_req_common_query_fw_config_t*)((uint8_t*)buf + sli_config_off);
2523 fw_config->hdr.opcode = SLI4_OPC_COMMON_QUERY_FW_CONFIG;
2524 fw_config->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2525 fw_config->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
2526 return sli_config_off + sizeof(sli4_req_common_query_fw_config_t);
2527 }
2528
2529 /**
2530 * @brief Write a COMMON_GET_PORT_NAME command to the provided buffer.
2531 *
2532 * @param sli4 SLI context pointer.
2533 * @param buf Virtual pointer to destination buffer.
2534 * @param size Buffer size in bytes.
2535 *
2536 * @note Function supports both version 0 and 1 forms of this command via
2537 * the IF_TYPE.
2538 *
2539 * @return Returns the number of bytes written.
2540 */
2541 static int32_t
sli_cmd_common_get_port_name(sli4_t * sli4,void * buf,size_t size)2542 sli_cmd_common_get_port_name(sli4_t *sli4, void *buf, size_t size)
2543 {
2544 sli4_req_common_get_port_name_t *port_name;
2545 uint32_t sli_config_off = 0;
2546 uint32_t payload_size;
2547 uint8_t version = 0;
2548 uint8_t pt = 0;
2549
2550 /* Select command version according to IF_TYPE */
2551 switch (sli4->if_type) {
2552 case SLI4_IF_TYPE_BE3_SKH_PF:
2553 case SLI4_IF_TYPE_BE3_SKH_VF:
2554 version = 0;
2555 break;
2556 case SLI4_IF_TYPE_LANCER_FC_ETH:
2557 case SLI4_IF_TYPE_LANCER_RDMA:
2558 case SLI4_IF_TYPE_LANCER_G7:
2559 version = 1;
2560 break;
2561 default:
2562 ocs_log_test(sli4->os, "unsupported IF_TYPE %d\n", sli4->if_type);
2563 return 0;
2564 }
2565
2566 /* Payload length must accommodate both request and response */
2567 payload_size = max(sizeof(sli4_req_common_get_port_name_t),
2568 sizeof(sli4_res_common_get_port_name_t));
2569
2570 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2571 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2572 payload_size,
2573 NULL);
2574
2575 pt = 1;
2576 }
2577
2578 port_name = (sli4_req_common_get_port_name_t *)((uint8_t *)buf + sli_config_off);
2579
2580 port_name->hdr.opcode = SLI4_OPC_COMMON_GET_PORT_NAME;
2581 port_name->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2582 port_name->hdr.request_length = sizeof(sli4_req_hdr_t) + (version * sizeof(uint32_t));
2583 port_name->hdr.version = version;
2584
2585 /* Set the port type value (ethernet=0, FC=1) for V1 commands */
2586 if (version == 1) {
2587 port_name->pt = pt;
2588 }
2589
2590 return sli_config_off + port_name->hdr.request_length;
2591 }
2592
2593
2594 /**
2595 * @ingroup sli
2596 * @brief Write a COMMON_WRITE_OBJECT command.
2597 *
2598 * @param sli4 SLI context.
2599 * @param buf Destination buffer for the command.
2600 * @param size Buffer size, in bytes.
2601 * @param noc True if the object should be written but not committed to flash.
2602 * @param eof True if this is the last write for this object.
2603 * @param desired_write_length Number of bytes of data to write to the object.
2604 * @param offset Offset, in bytes, from the start of the object.
2605 * @param object_name Name of the object to write.
2606 * @param dma DMA structure from which the data will be copied.
2607 *
2608 * @return Returns the number of bytes written.
2609 */
2610 int32_t
sli_cmd_common_write_object(sli4_t * sli4,void * buf,size_t size,uint16_t noc,uint16_t eof,uint32_t desired_write_length,uint32_t offset,char * object_name,ocs_dma_t * dma)2611 sli_cmd_common_write_object(sli4_t *sli4, void *buf, size_t size,
2612 uint16_t noc, uint16_t eof, uint32_t desired_write_length,
2613 uint32_t offset,
2614 char *object_name,
2615 ocs_dma_t *dma)
2616 {
2617 sli4_req_common_write_object_t *wr_obj = NULL;
2618 uint32_t sli_config_off = 0;
2619 sli4_bde_t *host_buffer;
2620
2621 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2622 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2623 sizeof (sli4_req_common_write_object_t) + sizeof (sli4_bde_t),
2624 NULL);
2625 }
2626
2627 wr_obj = (sli4_req_common_write_object_t *)((uint8_t *)buf + sli_config_off);
2628
2629 wr_obj->hdr.opcode = SLI4_OPC_COMMON_WRITE_OBJECT;
2630 wr_obj->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2631 wr_obj->hdr.request_length = sizeof(*wr_obj) - 4*sizeof(uint32_t) + sizeof(sli4_bde_t);
2632 wr_obj->hdr.timeout = 0;
2633 wr_obj->hdr.version = 0;
2634
2635 wr_obj->noc = noc;
2636 wr_obj->eof = eof;
2637 wr_obj->desired_write_length = desired_write_length;
2638 wr_obj->write_offset = offset;
2639 ocs_strncpy(wr_obj->object_name, object_name, sizeof(wr_obj->object_name));
2640 wr_obj->host_buffer_descriptor_count = 1;
2641
2642 host_buffer = (sli4_bde_t *)wr_obj->host_buffer_descriptor;
2643
2644 /* Setup to transfer xfer_size bytes to device */
2645 host_buffer->bde_type = SLI4_BDE_TYPE_BDE_64;
2646 host_buffer->buffer_length = desired_write_length;
2647 host_buffer->u.data.buffer_address_low = ocs_addr32_lo(dma->phys);
2648 host_buffer->u.data.buffer_address_high = ocs_addr32_hi(dma->phys);
2649
2650
2651 return(sli_config_off + sizeof(sli4_req_common_write_object_t) + sizeof (sli4_bde_t));
2652 }
2653
2654
2655 /**
2656 * @ingroup sli
2657 * @brief Write a COMMON_DELETE_OBJECT command.
2658 *
2659 * @param sli4 SLI context.
2660 * @param buf Destination buffer for the command.
2661 * @param size Buffer size, in bytes.
2662 * @param object_name Name of the object to write.
2663 *
2664 * @return Returns the number of bytes written.
2665 */
2666 int32_t
sli_cmd_common_delete_object(sli4_t * sli4,void * buf,size_t size,char * object_name)2667 sli_cmd_common_delete_object(sli4_t *sli4, void *buf, size_t size,
2668 char *object_name)
2669 {
2670 sli4_req_common_delete_object_t *del_obj = NULL;
2671 uint32_t sli_config_off = 0;
2672
2673 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2674 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2675 sizeof (sli4_req_common_delete_object_t),
2676 NULL);
2677 }
2678
2679 del_obj = (sli4_req_common_delete_object_t *)((uint8_t *)buf + sli_config_off);
2680
2681 del_obj->hdr.opcode = SLI4_OPC_COMMON_DELETE_OBJECT;
2682 del_obj->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2683 del_obj->hdr.request_length = sizeof(*del_obj);
2684 del_obj->hdr.timeout = 0;
2685 del_obj->hdr.version = 0;
2686
2687 ocs_strncpy(del_obj->object_name, object_name, sizeof(del_obj->object_name));
2688 return(sli_config_off + sizeof(sli4_req_common_delete_object_t));
2689 }
2690
2691 /**
2692 * @ingroup sli
2693 * @brief Write a COMMON_READ_OBJECT command.
2694 *
2695 * @param sli4 SLI context.
2696 * @param buf Destination buffer for the command.
2697 * @param size Buffer size, in bytes.
2698 * @param desired_read_length Number of bytes of data to read from the object.
2699 * @param offset Offset, in bytes, from the start of the object.
2700 * @param object_name Name of the object to read.
2701 * @param dma DMA structure from which the data will be copied.
2702 *
2703 * @return Returns the number of bytes written.
2704 */
2705 int32_t
sli_cmd_common_read_object(sli4_t * sli4,void * buf,size_t size,uint32_t desired_read_length,uint32_t offset,char * object_name,ocs_dma_t * dma)2706 sli_cmd_common_read_object(sli4_t *sli4, void *buf, size_t size,
2707 uint32_t desired_read_length,
2708 uint32_t offset,
2709 char *object_name,
2710 ocs_dma_t *dma)
2711 {
2712 sli4_req_common_read_object_t *rd_obj = NULL;
2713 uint32_t sli_config_off = 0;
2714 sli4_bde_t *host_buffer;
2715
2716 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2717 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2718 sizeof (sli4_req_common_read_object_t) + sizeof (sli4_bde_t),
2719 NULL);
2720 }
2721
2722 rd_obj = (sli4_req_common_read_object_t *)((uint8_t *)buf + sli_config_off);
2723
2724 rd_obj->hdr.opcode = SLI4_OPC_COMMON_READ_OBJECT;
2725 rd_obj->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2726 rd_obj->hdr.request_length = sizeof(*rd_obj) - 4*sizeof(uint32_t) + sizeof(sli4_bde_t);
2727 rd_obj->hdr.timeout = 0;
2728 rd_obj->hdr.version = 0;
2729
2730 rd_obj->desired_read_length = desired_read_length;
2731 rd_obj->read_offset = offset;
2732 ocs_strncpy(rd_obj->object_name, object_name, sizeof(rd_obj->object_name));
2733 rd_obj->host_buffer_descriptor_count = 1;
2734
2735 host_buffer = (sli4_bde_t *)rd_obj->host_buffer_descriptor;
2736
2737 /* Setup to transfer xfer_size bytes to device */
2738 host_buffer->bde_type = SLI4_BDE_TYPE_BDE_64;
2739 host_buffer->buffer_length = desired_read_length;
2740 if (dma != NULL) {
2741 host_buffer->u.data.buffer_address_low = ocs_addr32_lo(dma->phys);
2742 host_buffer->u.data.buffer_address_high = ocs_addr32_hi(dma->phys);
2743 } else {
2744 host_buffer->u.data.buffer_address_low = 0;
2745 host_buffer->u.data.buffer_address_high = 0;
2746 }
2747
2748
2749 return(sli_config_off + sizeof(sli4_req_common_read_object_t) + sizeof (sli4_bde_t));
2750 }
2751
2752 /**
2753 * @ingroup sli
2754 * @brief Write a DMTF_EXEC_CLP_CMD command.
2755 *
2756 * @param sli4 SLI context.
2757 * @param buf Destination buffer for the command.
2758 * @param size Buffer size, in bytes.
2759 * @param cmd DMA structure that describes the buffer for the command.
2760 * @param resp DMA structure that describes the buffer for the response.
2761 *
2762 * @return Returns the number of bytes written.
2763 */
2764 int32_t
sli_cmd_dmtf_exec_clp_cmd(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * cmd,ocs_dma_t * resp)2765 sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size,
2766 ocs_dma_t *cmd,
2767 ocs_dma_t *resp)
2768 {
2769 sli4_req_dmtf_exec_clp_cmd_t *clp_cmd = NULL;
2770 uint32_t sli_config_off = 0;
2771
2772 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2773 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2774 sizeof (sli4_req_dmtf_exec_clp_cmd_t),
2775 NULL);
2776 }
2777
2778 clp_cmd = (sli4_req_dmtf_exec_clp_cmd_t*)((uint8_t *)buf + sli_config_off);
2779
2780 clp_cmd->hdr.opcode = SLI4_OPC_DMTF_EXEC_CLP_CMD;
2781 clp_cmd->hdr.subsystem = SLI4_SUBSYSTEM_DMTF;
2782 clp_cmd->hdr.request_length = sizeof(sli4_req_dmtf_exec_clp_cmd_t) -
2783 sizeof(sli4_req_hdr_t);
2784 clp_cmd->hdr.timeout = 0;
2785 clp_cmd->hdr.version = 0;
2786 clp_cmd->cmd_buf_length = cmd->size;
2787 clp_cmd->cmd_buf_addr_low = ocs_addr32_lo(cmd->phys);
2788 clp_cmd->cmd_buf_addr_high = ocs_addr32_hi(cmd->phys);
2789 clp_cmd->resp_buf_length = resp->size;
2790 clp_cmd->resp_buf_addr_low = ocs_addr32_lo(resp->phys);
2791 clp_cmd->resp_buf_addr_high = ocs_addr32_hi(resp->phys);
2792
2793 return(sli_config_off + sizeof(sli4_req_dmtf_exec_clp_cmd_t));
2794 }
2795
2796 /**
2797 * @ingroup sli
2798 * @brief Write a COMMON_SET_DUMP_LOCATION command.
2799 *
2800 * @param sli4 SLI context.
2801 * @param buf Destination buffer for the command.
2802 * @param size Buffer size, in bytes.
2803 * @param query Zero to set dump location, non-zero to query dump size
2804 * @param is_buffer_list Set to one if the buffer is a set of buffer descriptors or
2805 * set to 0 if the buffer is a contiguous dump area.
2806 * @param buffer DMA structure to which the dump will be copied.
2807 *
2808 * @return Returns the number of bytes written.
2809 */
2810 int32_t
sli_cmd_common_set_dump_location(sli4_t * sli4,void * buf,size_t size,uint8_t query,uint8_t is_buffer_list,ocs_dma_t * buffer,uint8_t fdb)2811 sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size,
2812 uint8_t query, uint8_t is_buffer_list,
2813 ocs_dma_t *buffer, uint8_t fdb)
2814 {
2815 sli4_req_common_set_dump_location_t *set_dump_loc = NULL;
2816 uint32_t sli_config_off = 0;
2817
2818 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2819 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2820 sizeof (sli4_req_common_set_dump_location_t),
2821 NULL);
2822 }
2823
2824 set_dump_loc = (sli4_req_common_set_dump_location_t *)((uint8_t *)buf + sli_config_off);
2825
2826 set_dump_loc->hdr.opcode = SLI4_OPC_COMMON_SET_DUMP_LOCATION;
2827 set_dump_loc->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2828 set_dump_loc->hdr.request_length = sizeof(sli4_req_common_set_dump_location_t) - sizeof(sli4_req_hdr_t);
2829 set_dump_loc->hdr.timeout = 0;
2830 set_dump_loc->hdr.version = 0;
2831
2832 set_dump_loc->blp = is_buffer_list;
2833 set_dump_loc->qry = query;
2834 set_dump_loc->fdb = fdb;
2835
2836 if (buffer) {
2837 set_dump_loc->buf_addr_low = ocs_addr32_lo(buffer->phys);
2838 set_dump_loc->buf_addr_high = ocs_addr32_hi(buffer->phys);
2839 set_dump_loc->buffer_length = buffer->len;
2840 } else {
2841 set_dump_loc->buf_addr_low = 0;
2842 set_dump_loc->buf_addr_high = 0;
2843 set_dump_loc->buffer_length = 0;
2844 }
2845
2846 return(sli_config_off + sizeof(sli4_req_common_set_dump_location_t));
2847 }
2848
2849
2850 /**
2851 * @ingroup sli
2852 * @brief Write a COMMON_SET_FEATURES command.
2853 *
2854 * @param sli4 SLI context.
2855 * @param buf Destination buffer for the command.
2856 * @param size Buffer size, in bytes.
2857 * @param feature Feature to set.
2858 * @param param_len Length of the parameter (must be a multiple of 4 bytes).
2859 * @param parameter Pointer to the parameter value.
2860 *
2861 * @return Returns the number of bytes written.
2862 */
2863 int32_t
sli_cmd_common_set_features(sli4_t * sli4,void * buf,size_t size,uint32_t feature,uint32_t param_len,void * parameter)2864 sli_cmd_common_set_features(sli4_t *sli4, void *buf, size_t size,
2865 uint32_t feature,
2866 uint32_t param_len,
2867 void* parameter)
2868 {
2869 sli4_req_common_set_features_t *cmd = NULL;
2870 uint32_t sli_config_off = 0;
2871
2872 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2873 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2874 sizeof (sli4_req_common_set_features_t),
2875 NULL);
2876 }
2877
2878 cmd = (sli4_req_common_set_features_t *)((uint8_t *)buf + sli_config_off);
2879
2880 cmd->hdr.opcode = SLI4_OPC_COMMON_SET_FEATURES;
2881 cmd->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2882 cmd->hdr.request_length = sizeof(sli4_req_common_set_features_t) - sizeof(sli4_req_hdr_t);
2883 cmd->hdr.timeout = 0;
2884 cmd->hdr.version = 0;
2885
2886 cmd->feature = feature;
2887 cmd->param_len = param_len;
2888 ocs_memcpy(cmd->params, parameter, param_len);
2889
2890 return(sli_config_off + sizeof(sli4_req_common_set_features_t));
2891 }
2892
2893 /**
2894 * @ingroup sli
2895 * @brief Write a COMMON_COMMON_GET_PROFILE_CONFIG command.
2896 *
2897 * @param sli4 SLI context.
2898 * @param buf Destination buffer for the command.
2899 * @param size Buffer size in bytes.
2900 * @param dma DMA capable memory used to retrieve profile.
2901 *
2902 * @return Returns the number of bytes written.
2903 */
2904 int32_t
sli_cmd_common_get_profile_config(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma)2905 sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma)
2906 {
2907 sli4_req_common_get_profile_config_t *req = NULL;
2908 uint32_t sli_config_off = 0;
2909 uint32_t payload_size;
2910
2911 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2912 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
2913 sizeof (sli4_req_common_get_profile_config_t),
2914 dma);
2915 }
2916
2917 if (dma != NULL) {
2918 req = dma->virt;
2919 ocs_memset(req, 0, dma->size);
2920 payload_size = dma->size;
2921 } else {
2922 req = (sli4_req_common_get_profile_config_t *)((uint8_t *)buf + sli_config_off);
2923 payload_size = sizeof(sli4_req_common_get_profile_config_t);
2924 }
2925
2926 req->hdr.opcode = SLI4_OPC_COMMON_GET_PROFILE_CONFIG;
2927 req->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2928 req->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
2929 req->hdr.version = 1;
2930
2931 return(sli_config_off + sizeof(sli4_req_common_get_profile_config_t));
2932 }
2933
2934 /**
2935 * @ingroup sli
2936 * @brief Write a COMMON_COMMON_SET_PROFILE_CONFIG command.
2937 *
2938 * @param sli4 SLI context.
2939 * @param buf Destination buffer for the command.
2940 * @param size Buffer size, in bytes.
2941 * @param dma DMA capable memory containing profile.
2942 * @param profile_id Profile ID to configure.
2943 * @param descriptor_count Number of descriptors in DMA buffer.
2944 * @param isap Implicit Set Active Profile value to use.
2945 *
2946 * @return Returns the number of bytes written.
2947 */
2948 int32_t
sli_cmd_common_set_profile_config(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma,uint8_t profile_id,uint32_t descriptor_count,uint8_t isap)2949 sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma,
2950 uint8_t profile_id, uint32_t descriptor_count, uint8_t isap)
2951 {
2952 sli4_req_common_set_profile_config_t *req = NULL;
2953 uint32_t cmd_off = 0;
2954 uint32_t payload_size;
2955
2956 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
2957 cmd_off = sli_cmd_sli_config(sli4, buf, size,
2958 sizeof (sli4_req_common_set_profile_config_t),
2959 dma);
2960 }
2961
2962 if (dma != NULL) {
2963 req = dma->virt;
2964 ocs_memset(req, 0, dma->size);
2965 payload_size = dma->size;
2966 } else {
2967 req = (sli4_req_common_set_profile_config_t *)((uint8_t *)buf + cmd_off);
2968 payload_size = sizeof(sli4_req_common_set_profile_config_t);
2969 }
2970
2971 req->hdr.opcode = SLI4_OPC_COMMON_SET_PROFILE_CONFIG;
2972 req->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
2973 req->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
2974 req->hdr.version = 1;
2975 req->profile_id = profile_id;
2976 req->desc_count = descriptor_count;
2977 req->isap = isap;
2978
2979 return(cmd_off + sizeof(sli4_req_common_set_profile_config_t));
2980 }
2981
2982 /**
2983 * @ingroup sli
2984 * @brief Write a COMMON_COMMON_GET_PROFILE_LIST command.
2985 *
2986 * @param sli4 SLI context.
2987 * @param buf Destination buffer for the command.
2988 * @param size Buffer size in bytes.
2989 * @param start_profile_index First profile index to return.
2990 * @param dma Buffer into which the list will be written.
2991 *
2992 * @return Returns the number of bytes written.
2993 */
2994 int32_t
sli_cmd_common_get_profile_list(sli4_t * sli4,void * buf,size_t size,uint32_t start_profile_index,ocs_dma_t * dma)2995 sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf, size_t size,
2996 uint32_t start_profile_index, ocs_dma_t *dma)
2997 {
2998 sli4_req_common_get_profile_list_t *req = NULL;
2999 uint32_t cmd_off = 0;
3000 uint32_t payload_size;
3001
3002 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
3003 cmd_off = sli_cmd_sli_config(sli4, buf, size,
3004 sizeof (sli4_req_common_get_profile_list_t),
3005 dma);
3006 }
3007
3008 if (dma != NULL) {
3009 req = dma->virt;
3010 ocs_memset(req, 0, dma->size);
3011 payload_size = dma->size;
3012 } else {
3013 req = (sli4_req_common_get_profile_list_t *)((uint8_t *)buf + cmd_off);
3014 payload_size = sizeof(sli4_req_common_get_profile_list_t);
3015 }
3016
3017 req->hdr.opcode = SLI4_OPC_COMMON_GET_PROFILE_LIST;
3018 req->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
3019 req->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
3020 req->hdr.version = 0;
3021
3022 req->start_profile_index = start_profile_index;
3023
3024 return(cmd_off + sizeof(sli4_req_common_get_profile_list_t));
3025 }
3026
3027 /**
3028 * @ingroup sli
3029 * @brief Write a COMMON_COMMON_GET_ACTIVE_PROFILE command.
3030 *
3031 * @param sli4 SLI context.
3032 * @param buf Destination buffer for the command.
3033 * @param size Buffer size in bytes.
3034 *
3035 * @return Returns the number of bytes written.
3036 */
3037 int32_t
sli_cmd_common_get_active_profile(sli4_t * sli4,void * buf,size_t size)3038 sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf, size_t size)
3039 {
3040 sli4_req_common_get_active_profile_t *req = NULL;
3041 uint32_t cmd_off = 0;
3042 uint32_t payload_size;
3043
3044 /* Payload length must accommodate both request and response */
3045 payload_size = max(sizeof(sli4_req_common_get_active_profile_t),
3046 sizeof(sli4_res_common_get_active_profile_t));
3047
3048 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
3049 cmd_off = sli_cmd_sli_config(sli4, buf, size,
3050 payload_size,
3051 NULL);
3052 }
3053
3054 req = (sli4_req_common_get_active_profile_t *)
3055 ((uint8_t*)buf + cmd_off);
3056
3057 req->hdr.opcode = SLI4_OPC_COMMON_GET_ACTIVE_PROFILE;
3058 req->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
3059 req->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
3060 req->hdr.version = 0;
3061
3062 return(cmd_off + sizeof(sli4_req_common_get_active_profile_t));
3063 }
3064
3065 /**
3066 * @ingroup sli
3067 * @brief Write a COMMON_COMMON_SET_ACTIVE_PROFILE command.
3068 *
3069 * @param sli4 SLI context.
3070 * @param buf Destination buffer for the command.
3071 * @param size Buffer size in bytes.
3072 * @param fd If non-zero, set profile to factory default.
3073 * @param active_profile_id ID of new active profile.
3074 *
3075 * @return Returns the number of bytes written.
3076 */
3077 int32_t
sli_cmd_common_set_active_profile(sli4_t * sli4,void * buf,size_t size,uint32_t fd,uint32_t active_profile_id)3078 sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf, size_t size,
3079 uint32_t fd, uint32_t active_profile_id)
3080 {
3081 sli4_req_common_set_active_profile_t *req = NULL;
3082 uint32_t cmd_off = 0;
3083 uint32_t payload_size;
3084
3085 /* Payload length must accommodate both request and response */
3086 payload_size = max(sizeof(sli4_req_common_set_active_profile_t),
3087 sizeof(sli4_res_common_set_active_profile_t));
3088
3089 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
3090 cmd_off = sli_cmd_sli_config(sli4, buf, size,
3091 payload_size,
3092 NULL);
3093 }
3094
3095 req = (sli4_req_common_set_active_profile_t *)
3096 ((uint8_t*)buf + cmd_off);
3097
3098 req->hdr.opcode = SLI4_OPC_COMMON_SET_ACTIVE_PROFILE;
3099 req->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
3100 req->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
3101 req->hdr.version = 0;
3102 req->fd = fd;
3103 req->active_profile_id = active_profile_id;
3104
3105 return(cmd_off + sizeof(sli4_req_common_set_active_profile_t));
3106 }
3107
3108 /**
3109 * @ingroup sli
3110 * @brief Write a COMMON_GET_RECONFIG_LINK_INFO command.
3111 *
3112 * @param sli4 SLI context.
3113 * @param buf Destination buffer for the command.
3114 * @param size Buffer size in bytes.
3115 * @param dma Buffer to store the supported link configuration modes from the physical device.
3116 *
3117 * @return Returns the number of bytes written.
3118 */
3119 int32_t
sli_cmd_common_get_reconfig_link_info(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma)3120 sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma)
3121 {
3122 sli4_req_common_get_reconfig_link_info_t *req = NULL;
3123 uint32_t cmd_off = 0;
3124 uint32_t payload_size;
3125
3126 /* Payload length must accommodate both request and response */
3127 payload_size = max(sizeof(sli4_req_common_get_reconfig_link_info_t),
3128 sizeof(sli4_res_common_get_reconfig_link_info_t));
3129
3130 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
3131 cmd_off = sli_cmd_sli_config(sli4, buf, size,
3132 payload_size,
3133 dma);
3134 }
3135
3136 if (dma != NULL) {
3137 req = dma->virt;
3138 ocs_memset(req, 0, dma->size);
3139 payload_size = dma->size;
3140 } else {
3141 req = (sli4_req_common_get_reconfig_link_info_t *)((uint8_t *)buf + cmd_off);
3142 payload_size = sizeof(sli4_req_common_get_reconfig_link_info_t);
3143 }
3144
3145 req->hdr.opcode = SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO;
3146 req->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
3147 req->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
3148 req->hdr.version = 0;
3149
3150 return(cmd_off + sizeof(sli4_req_common_get_reconfig_link_info_t));
3151 }
3152
3153 /**
3154 * @ingroup sli
3155 * @brief Write a COMMON_SET_RECONFIG_LINK_ID command.
3156 *
3157 * @param sli4 SLI context.
3158 * @param buf destination buffer for the command.
3159 * @param size buffer size in bytes.
3160 * @param fd If non-zero, set link config to factory default.
3161 * @param active_link_config_id ID of new active profile.
3162 * @param dma Buffer to assign the link configuration mode that is to become active from the physical device.
3163 *
3164 * @return Returns the number of bytes written.
3165 */
3166 int32_t
sli_cmd_common_set_reconfig_link_id(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma,uint32_t fd,uint32_t active_link_config_id)3167 sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma,
3168 uint32_t fd, uint32_t active_link_config_id)
3169 {
3170 sli4_req_common_set_reconfig_link_id_t *req = NULL;
3171 uint32_t cmd_off = 0;
3172 uint32_t payload_size;
3173
3174 /* Payload length must accommodate both request and response */
3175 payload_size = max(sizeof(sli4_req_common_set_reconfig_link_id_t),
3176 sizeof(sli4_res_common_set_reconfig_link_id_t));
3177
3178 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
3179 cmd_off = sli_cmd_sli_config(sli4, buf, size,
3180 payload_size,
3181 NULL);
3182 }
3183
3184 if (dma != NULL) {
3185 req = dma->virt;
3186 ocs_memset(req, 0, dma->size);
3187 payload_size = dma->size;
3188 } else {
3189 req = (sli4_req_common_set_reconfig_link_id_t *)((uint8_t *)buf + cmd_off);
3190 payload_size = sizeof(sli4_req_common_set_reconfig_link_id_t);
3191 }
3192
3193 req->hdr.opcode = SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID;
3194 req->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;
3195 req->hdr.request_length = payload_size - sizeof(sli4_req_hdr_t);
3196 req->hdr.version = 0;
3197 req->fd = fd;
3198 req->next_link_config_id = active_link_config_id;
3199
3200 return(cmd_off + sizeof(sli4_req_common_set_reconfig_link_id_t));
3201 }
3202
3203
3204 /**
3205 * @ingroup sli
3206 * @brief Check the mailbox/queue completion entry.
3207 *
3208 * @param buf Pointer to the MCQE.
3209 *
3210 * @return Returns 0 on success, or a non-zero value on failure.
3211 */
3212 int32_t
sli_cqe_mq(void * buf)3213 sli_cqe_mq(void *buf)
3214 {
3215 sli4_mcqe_t *mcqe = buf;
3216
3217 /*
3218 * Firmware can split mbx completions into two MCQEs: first with only
3219 * the "consumed" bit set and a second with the "complete" bit set.
3220 * Thus, ignore MCQE unless "complete" is set.
3221 */
3222 if (!mcqe->cmp) {
3223 return -2;
3224 }
3225
3226 if (mcqe->completion_status) {
3227 ocs_log_debug(NULL, "bad status (cmpl=%#x ext=%#x con=%d cmp=%d ae=%d val=%d)\n",
3228 mcqe->completion_status,
3229 mcqe->extended_status,
3230 mcqe->con,
3231 mcqe->cmp,
3232 mcqe->ae,
3233 mcqe->val);
3234 }
3235
3236 return mcqe->completion_status;
3237 }
3238
3239 /**
3240 * @ingroup sli
3241 * @brief Check the asynchronous event completion entry.
3242 *
3243 * @param sli4 SLI context.
3244 * @param buf Pointer to the ACQE.
3245 *
3246 * @return Returns 0 on success, or a non-zero value on failure.
3247 */
3248 int32_t
sli_cqe_async(sli4_t * sli4,void * buf)3249 sli_cqe_async(sli4_t *sli4, void *buf)
3250 {
3251 sli4_acqe_t *acqe = buf;
3252 int32_t rc = -1;
3253
3254 if (!sli4 || !buf) {
3255 ocs_log_err(NULL, "bad parameter sli4=%p buf=%p\n", sli4, buf);
3256 return -1;
3257 }
3258
3259 switch (acqe->event_code) {
3260 case SLI4_ACQE_EVENT_CODE_LINK_STATE:
3261 rc = sli_fc_process_link_state(sli4, buf);
3262 break;
3263 case SLI4_ACQE_EVENT_CODE_FCOE_FIP:
3264 rc = sli_fc_process_fcoe(sli4, buf);
3265 break;
3266 case SLI4_ACQE_EVENT_CODE_GRP_5:
3267 /*TODO*/ocs_log_debug(sli4->os, "ACQE GRP5\n");
3268 break;
3269 case SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT:
3270 ocs_log_debug(sli4->os,"ACQE SLI Port, type=0x%x, data1,2=0x%08x,0x%08x\n",
3271 acqe->event_type, acqe->event_data[0], acqe->event_data[1]);
3272 #if defined(OCS_INCLUDE_DEBUG)
3273 ocs_dump32(OCS_DEBUG_ALWAYS, sli4->os, "acq", acqe, sizeof(*acqe));
3274 #endif
3275 break;
3276 case SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT:
3277 rc = sli_fc_process_link_attention(sli4, buf);
3278 break;
3279 default:
3280 /*TODO*/ocs_log_test(sli4->os, "ACQE unknown=%#x\n", acqe->event_code);
3281 }
3282
3283 return rc;
3284 }
3285
3286 /**
3287 * @brief Check the SLI_CONFIG response.
3288 *
3289 * @par Description
3290 * Function checks the SLI_CONFIG response and the payload status.
3291 *
3292 * @param buf Pointer to SLI_CONFIG response.
3293 *
3294 * @return Returns 0 on success, or a non-zero value on failure.
3295 */
3296 static int32_t
sli_res_sli_config(void * buf)3297 sli_res_sli_config(void *buf)
3298 {
3299 sli4_cmd_sli_config_t *sli_config = buf;
3300
3301 if (!buf || (SLI4_MBOX_COMMAND_SLI_CONFIG != sli_config->hdr.command)) {
3302 ocs_log_err(NULL, "bad parameter buf=%p cmd=%#x\n", buf,
3303 buf ? sli_config->hdr.command : -1);
3304 return -1;
3305 }
3306
3307 if (sli_config->hdr.status) {
3308 return sli_config->hdr.status;
3309 }
3310
3311 if (sli_config->emb) {
3312 return sli_config->payload.embed[4];
3313 } else {
3314 ocs_log_test(NULL, "external buffers not supported\n");
3315 return -1;
3316 }
3317 }
3318
3319 /**
3320 * @brief Issue a COMMON_FUNCTION_RESET command.
3321 *
3322 * @param sli4 SLI context.
3323 *
3324 * @return Returns 0 on success, or a non-zero value on failure.
3325 */
3326 static int32_t
sli_common_function_reset(sli4_t * sli4)3327 sli_common_function_reset(sli4_t *sli4)
3328 {
3329
3330 if (sli_cmd_common_function_reset(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE)) {
3331 if (sli_bmbx_command(sli4)) {
3332 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (COM_FUNC_RESET)\n");
3333 return -1;
3334 }
3335 if (sli_res_sli_config(sli4->bmbx.virt)) {
3336 ocs_log_err(sli4->os, "bad status COM_FUNC_RESET\n");
3337 return -1;
3338 }
3339 } else {
3340 ocs_log_err(sli4->os, "bad COM_FUNC_RESET write\n");
3341 return -1;
3342 }
3343
3344 return 0;
3345 }
3346
3347
3348 /**
3349 * @brief check to see if the FW is ready.
3350 *
3351 * @par Description
3352 * Based on <i>SLI-4 Architecture Specification, Revision 4.x0-13 (2012).</i>.
3353 *
3354 * @param sli4 SLI context.
3355 * @param timeout_ms Time, in milliseconds, to wait for the port to be ready
3356 * before failing.
3357 *
3358 * @return Returns TRUE for ready, or FALSE otherwise.
3359 */
3360 static int32_t
sli_wait_for_fw_ready(sli4_t * sli4,uint32_t timeout_ms)3361 sli_wait_for_fw_ready(sli4_t *sli4, uint32_t timeout_ms)
3362 {
3363 uint32_t iter = timeout_ms / (SLI4_INIT_PORT_DELAY_US / 1000);
3364 uint32_t ready = FALSE;
3365
3366 do {
3367 iter--;
3368 ocs_udelay(SLI4_INIT_PORT_DELAY_US);
3369 if (sli_fw_ready(sli4) == 1) {
3370 ready = TRUE;
3371 }
3372 } while (!ready && (iter > 0));
3373
3374 return ready;
3375 }
3376
3377 /**
3378 * @brief Initialize the firmware.
3379 *
3380 * @par Description
3381 * Based on <i>SLI-4 Architecture Specification, Revision 4.x0-13 (2012).</i>.
3382 *
3383 * @param sli4 SLI context.
3384 *
3385 * @return Returns 0 on success, or a non-zero value on failure.
3386 */
3387 static int32_t
sli_fw_init(sli4_t * sli4)3388 sli_fw_init(sli4_t *sli4)
3389 {
3390 uint32_t ready;
3391 uint32_t endian;
3392
3393 /*
3394 * Is firmware ready for operation?
3395 */
3396 ready = sli_wait_for_fw_ready(sli4, SLI4_FW_READY_TIMEOUT_MSEC);
3397 if (!ready) {
3398 ocs_log_crit(sli4->os, "FW status is NOT ready\n");
3399 return -1;
3400 }
3401
3402 /*
3403 * Reset port to a known state
3404 */
3405 switch (sli4->if_type) {
3406 case SLI4_IF_TYPE_BE3_SKH_PF:
3407 case SLI4_IF_TYPE_BE3_SKH_VF:
3408 /* No SLIPORT_CONTROL register so use command sequence instead */
3409 if (sli_bmbx_wait(sli4, SLI4_BMBX_DELAY_US)) {
3410 ocs_log_crit(sli4->os, "bootstrap mailbox not ready\n");
3411 return -1;
3412 }
3413
3414 if (sli_cmd_fw_initialize(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE)) {
3415 if (sli_bmbx_command(sli4)) {
3416 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (FW_INIT)\n");
3417 return -1;
3418 }
3419 } else {
3420 ocs_log_crit(sli4->os, "bad FW_INIT write\n");
3421 return -1;
3422 }
3423
3424 if (sli_common_function_reset(sli4)) {
3425 ocs_log_err(sli4->os, "bad COM_FUNC_RESET write\n");
3426 return -1;
3427 }
3428 break;
3429 case SLI4_IF_TYPE_LANCER_FC_ETH:
3430 case SLI4_IF_TYPE_LANCER_G7:
3431 #if BYTE_ORDER == LITTLE_ENDIAN
3432 endian = SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN;
3433 #else
3434 endian = SLI4_SLIPORT_CONTROL_BIG_ENDIAN;
3435 #endif
3436
3437 if (sli_sliport_control(sli4, endian))
3438 return -1;
3439 break;
3440 default:
3441 ocs_log_test(sli4->os, "if_type %d not supported\n", sli4->if_type);
3442 return -1;
3443 }
3444
3445 return 0;
3446 }
3447
3448 /**
3449 * @brief Terminate the firmware.
3450 *
3451 * @param sli4 SLI context.
3452 *
3453 * @return Returns 0 on success, or a non-zero value on failure.
3454 */
3455 static int32_t
sli_fw_term(sli4_t * sli4)3456 sli_fw_term(sli4_t *sli4)
3457 {
3458 uint32_t endian;
3459
3460 if (sli4->if_type == SLI4_IF_TYPE_BE3_SKH_PF ||
3461 sli4->if_type == SLI4_IF_TYPE_BE3_SKH_VF) {
3462 /* No SLIPORT_CONTROL register so use command sequence instead */
3463 if (sli_bmbx_wait(sli4, SLI4_BMBX_DELAY_US)) {
3464 ocs_log_crit(sli4->os, "bootstrap mailbox not ready\n");
3465 return -1;
3466 }
3467
3468 if (sli_common_function_reset(sli4)) {
3469 ocs_log_err(sli4->os, "bad COM_FUNC_RESET write\n");
3470 return -1;
3471 }
3472
3473 if (sli_cmd_fw_deinitialize(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE)) {
3474 if (sli_bmbx_command(sli4)) {
3475 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (FW_DEINIT)\n");
3476 return -1;
3477 }
3478 } else {
3479 ocs_log_test(sli4->os, "bad FW_DEINIT write\n");
3480 return -1;
3481 }
3482 } else {
3483 #if BYTE_ORDER == LITTLE_ENDIAN
3484 endian = SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN;
3485 #else
3486 endian = SLI4_SLIPORT_CONTROL_BIG_ENDIAN;
3487 #endif
3488 /* type 2 etc. use SLIPORT_CONTROL to initialize port */
3489 sli_sliport_control(sli4, endian);
3490 }
3491 return 0;
3492 }
3493
3494 /**
3495 * @brief Write the doorbell register associated with the queue object.
3496 *
3497 * @param sli4 SLI context.
3498 * @param q Queue object.
3499 *
3500 * @return Returns 0 on success, or a non-zero value on failure.
3501 */
3502 static int32_t
sli_queue_doorbell(sli4_t * sli4,sli4_queue_t * q)3503 sli_queue_doorbell(sli4_t *sli4, sli4_queue_t *q)
3504 {
3505 uint32_t val = 0;
3506
3507 switch (q->type) {
3508 case SLI_QTYPE_EQ:
3509 if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7)
3510 val = sli_iftype6_eq_doorbell(q->n_posted, q->id, FALSE);
3511 else
3512 val = sli_eq_doorbell(q->n_posted, q->id, FALSE);
3513 ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val);
3514 break;
3515 case SLI_QTYPE_CQ:
3516 if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7)
3517 val = sli_iftype6_cq_doorbell(q->n_posted, q->id, FALSE);
3518 else
3519 val = sli_cq_doorbell(q->n_posted, q->id, FALSE);
3520 ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val);
3521 break;
3522 case SLI_QTYPE_MQ:
3523 val = SLI4_MQ_DOORBELL(q->n_posted, q->id);
3524 ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val);
3525 break;
3526 case SLI_QTYPE_RQ:
3527 {
3528 uint32_t n_posted = q->n_posted;
3529 /*
3530 * FC/FCoE has different rules for Receive Queues. The host
3531 * should only update the doorbell of the RQ-pair containing
3532 * the headers since the header / payload RQs are treated
3533 * as a matched unit.
3534 */
3535 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
3536 /*
3537 * In RQ-pair, an RQ either contains the FC header
3538 * (i.e. is_hdr == TRUE) or the payload.
3539 *
3540 * Don't ring doorbell for payload RQ
3541 */
3542 if (!q->u.flag.is_hdr) {
3543 break;
3544 }
3545 /*
3546 * Some RQ cannot be incremented one entry at a time. Instead,
3547 * the driver collects a number of entries and updates the
3548 * RQ in batches.
3549 */
3550 if (q->u.flag.rq_batch) {
3551 if (((q->index + q->n_posted) % SLI4_QUEUE_RQ_BATCH)) {
3552 break;
3553 }
3554 n_posted = SLI4_QUEUE_RQ_BATCH;
3555 }
3556 }
3557
3558 val = SLI4_RQ_DOORBELL(n_posted, q->id);
3559 ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val);
3560 break;
3561 }
3562 case SLI_QTYPE_WQ:
3563 if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) {
3564 val = SLI4_WQ_DOORBELL(q->n_posted, 0, q->id);
3565 } else {
3566 /* For iftype = 2 and 3, q->index value is ignored */
3567 val = SLI4_WQ_DOORBELL(q->n_posted, q->index, q->id);
3568 }
3569
3570 ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val);
3571 break;
3572 default:
3573 ocs_log_test(sli4->os, "bad queue type %d\n", q->type);
3574 return -1;
3575 }
3576
3577 return 0;
3578 }
3579
3580 static int32_t
sli_request_features(sli4_t * sli4,sli4_features_t * features,uint8_t query)3581 sli_request_features(sli4_t *sli4, sli4_features_t *features, uint8_t query)
3582 {
3583
3584 if (sli_cmd_request_features(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE,
3585 *features, query)) {
3586 sli4_cmd_request_features_t *req_features = sli4->bmbx.virt;
3587
3588 if (sli_bmbx_command(sli4)) {
3589 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (REQUEST_FEATURES)\n");
3590 return -1;
3591 }
3592 if (req_features->hdr.status) {
3593 ocs_log_err(sli4->os, "REQUEST_FEATURES bad status %#x\n",
3594 req_features->hdr.status);
3595 return -1;
3596 }
3597 features->dword = req_features->response.dword;
3598 } else {
3599 ocs_log_err(sli4->os, "bad REQUEST_FEATURES write\n");
3600 return -1;
3601 }
3602
3603 return 0;
3604 }
3605
3606 /**
3607 * @brief Calculate max queue entries.
3608 *
3609 * @param sli4 SLI context.
3610 *
3611 * @return Returns 0 on success, or a non-zero value on failure.
3612 */
3613 void
sli_calc_max_qentries(sli4_t * sli4)3614 sli_calc_max_qentries(sli4_t *sli4)
3615 {
3616 sli4_qtype_e q;
3617 uint32_t alloc_size, qentries, qentry_size;
3618
3619 for (q = SLI_QTYPE_EQ; q < SLI_QTYPE_MAX; q++) {
3620 sli4->config.max_qentries[q] = sli_convert_mask_to_count(sli4->config.count_method[q],
3621 sli4->config.count_mask[q]);
3622 }
3623
3624 /* single, continguous DMA allocations will be called for each queue
3625 * of size (max_qentries * queue entry size); since these can be large,
3626 * check against the OS max DMA allocation size
3627 */
3628 for (q = SLI_QTYPE_EQ; q < SLI_QTYPE_MAX; q++) {
3629 qentries = sli4->config.max_qentries[q];
3630 qentry_size = sli_get_queue_entry_size(sli4, q);
3631 alloc_size = qentries * qentry_size;
3632 if (alloc_size > ocs_max_dma_alloc(sli4->os, SLI_PAGE_SIZE)) {
3633 while (alloc_size > ocs_max_dma_alloc(sli4->os, SLI_PAGE_SIZE)) {
3634 /* cut the qentries in hwf until alloc_size <= max DMA alloc size */
3635 qentries >>= 1;
3636 alloc_size = qentries * qentry_size;
3637 }
3638 ocs_log_debug(sli4->os, "[%s]: max_qentries from %d to %d (max dma %d)\n",
3639 SLI_QNAME[q], sli4->config.max_qentries[q],
3640 qentries, ocs_max_dma_alloc(sli4->os, SLI_PAGE_SIZE));
3641 sli4->config.max_qentries[q] = qentries;
3642 }
3643 }
3644 }
3645
3646 /**
3647 * @brief Issue a FW_CONFIG mailbox command and store the results.
3648 *
3649 * @param sli4 SLI context.
3650 *
3651 * @return Returns 0 on success, or a non-zero value on failure.
3652 */
3653 static int32_t
sli_query_fw_config(sli4_t * sli4)3654 sli_query_fw_config(sli4_t *sli4)
3655 {
3656 /*
3657 * Read the device configuration
3658 *
3659 * Note: Only ulp0 fields contain values
3660 */
3661 if (sli_cmd_common_query_fw_config(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE)) {
3662 sli4_res_common_query_fw_config_t *fw_config =
3663 (sli4_res_common_query_fw_config_t *)
3664 (((uint8_t *)sli4->bmbx.virt) + offsetof(sli4_cmd_sli_config_t, payload.embed));
3665
3666 if (sli_bmbx_command(sli4)) {
3667 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (QUERY_FW_CONFIG)\n");
3668 return -1;
3669 }
3670 if (fw_config->hdr.status) {
3671 ocs_log_err(sli4->os, "COMMON_QUERY_FW_CONFIG bad status %#x\n",
3672 fw_config->hdr.status);
3673 return -1;
3674 }
3675
3676 sli4->physical_port = fw_config->physical_port;
3677 sli4->config.dual_ulp_capable = ((fw_config->function_mode & SLI4_FUNCTION_MODE_DUA_MODE) == 0 ? 0 : 1);
3678 sli4->config.is_ulp_fc[0] = ((fw_config->ulp0_mode &
3679 (SLI4_ULP_MODE_FCOE_INI |
3680 SLI4_ULP_MODE_FCOE_TGT)) == 0 ? 0 : 1);
3681 sli4->config.is_ulp_fc[1] = ((fw_config->ulp1_mode &
3682 (SLI4_ULP_MODE_FCOE_INI |
3683 SLI4_ULP_MODE_FCOE_TGT)) == 0 ? 0 : 1);
3684
3685 if (sli4->config.dual_ulp_capable) {
3686 /*
3687 * Lancer will not support this, so we use the values
3688 * from the READ_CONFIG.
3689 */
3690 if (sli4->config.is_ulp_fc[0] &&
3691 sli4->config.is_ulp_fc[1]) {
3692 sli4->config.max_qcount[SLI_QTYPE_WQ] = fw_config->ulp0_toe_wq_total + fw_config->ulp1_toe_wq_total;
3693 sli4->config.max_qcount[SLI_QTYPE_RQ] = fw_config->ulp0_toe_defrq_total + fw_config->ulp1_toe_defrq_total;
3694 } else if (sli4->config.is_ulp_fc[0]) {
3695 sli4->config.max_qcount[SLI_QTYPE_WQ] = fw_config->ulp0_toe_wq_total;
3696 sli4->config.max_qcount[SLI_QTYPE_RQ] = fw_config->ulp0_toe_defrq_total;
3697 } else {
3698 sli4->config.max_qcount[SLI_QTYPE_WQ] = fw_config->ulp1_toe_wq_total;
3699 sli4->config.max_qcount[SLI_QTYPE_RQ] = fw_config->ulp1_toe_defrq_total;
3700 }
3701 }
3702 } else {
3703 ocs_log_err(sli4->os, "bad QUERY_FW_CONFIG write\n");
3704 return -1;
3705 }
3706 return 0;
3707 }
3708
3709
3710 static int32_t
sli_get_config(sli4_t * sli4)3711 sli_get_config(sli4_t *sli4)
3712 {
3713 ocs_dma_t get_cntl_addl_data;
3714
3715 /*
3716 * Read the device configuration
3717 */
3718 if (sli_cmd_read_config(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE)) {
3719 sli4_res_read_config_t *read_config = sli4->bmbx.virt;
3720 uint32_t i;
3721 uint32_t total;
3722
3723 if (sli_bmbx_command(sli4)) {
3724 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (READ_CONFIG)\n");
3725 return -1;
3726 }
3727 if (read_config->hdr.status) {
3728 ocs_log_err(sli4->os, "READ_CONFIG bad status %#x\n",
3729 read_config->hdr.status);
3730 return -1;
3731 }
3732
3733 sli4->config.has_extents = read_config->ext;
3734 if (FALSE == sli4->config.has_extents) {
3735 uint32_t i = 0;
3736 uint32_t *base = sli4->config.extent[0].base;
3737
3738 if (!base) {
3739 if (NULL == (base = ocs_malloc(sli4->os, SLI_RSRC_MAX * sizeof(uint32_t),
3740 OCS_M_ZERO | OCS_M_NOWAIT))) {
3741 ocs_log_err(sli4->os, "memory allocation failed for sli4_resource_t\n");
3742 return -1;
3743 }
3744 }
3745
3746 for (i = 0; i < SLI_RSRC_MAX; i++) {
3747 sli4->config.extent[i].number = 1;
3748 sli4->config.extent[i].n_alloc = 0;
3749 sli4->config.extent[i].base = &base[i];
3750 }
3751
3752 sli4->config.extent[SLI_RSRC_FCOE_VFI].base[0] = read_config->vfi_base;
3753 sli4->config.extent[SLI_RSRC_FCOE_VFI].size = read_config->vfi_count;
3754
3755 sli4->config.extent[SLI_RSRC_FCOE_VPI].base[0] = read_config->vpi_base;
3756 sli4->config.extent[SLI_RSRC_FCOE_VPI].size = read_config->vpi_count;
3757
3758 sli4->config.extent[SLI_RSRC_FCOE_RPI].base[0] = read_config->rpi_base;
3759 sli4->config.extent[SLI_RSRC_FCOE_RPI].size = read_config->rpi_count;
3760
3761 sli4->config.extent[SLI_RSRC_FCOE_XRI].base[0] = read_config->xri_base;
3762 sli4->config.extent[SLI_RSRC_FCOE_XRI].size = OCS_MIN(255,read_config->xri_count);
3763
3764 sli4->config.extent[SLI_RSRC_FCOE_FCFI].base[0] = 0;
3765 sli4->config.extent[SLI_RSRC_FCOE_FCFI].size = read_config->fcfi_count;
3766 } else {
3767 /* TODO extents*/
3768 ;
3769 }
3770
3771 for (i = 0; i < SLI_RSRC_MAX; i++) {
3772 total = sli4->config.extent[i].number * sli4->config.extent[i].size;
3773 sli4->config.extent[i].use_map = ocs_bitmap_alloc(total);
3774 if (NULL == sli4->config.extent[i].use_map) {
3775 ocs_log_err(sli4->os, "bitmap memory allocation failed "
3776 "resource %d\n", i);
3777 return -1;
3778 }
3779 sli4->config.extent[i].map_size = total;
3780 }
3781
3782 sli4->config.topology = read_config->topology;
3783 sli4->config.ptv = read_config->ptv;
3784 if (sli4->config.ptv){
3785 sli4->config.tf = read_config->tf;
3786 sli4->config.pt = read_config->pt;
3787 }
3788 ocs_log_info(sli4->os, "Persistent Topology: PTV: %d, TF: %d, PT: %d \n",
3789 sli4->config.topology, sli4->config.ptv, sli4->config.tf, sli4->config.pt);
3790
3791 switch (sli4->config.topology) {
3792 case SLI4_READ_CFG_TOPO_FCOE:
3793 ocs_log_debug(sli4->os, "FCoE\n");
3794 break;
3795 case SLI4_READ_CFG_TOPO_FC:
3796 ocs_log_debug(sli4->os, "FC (unknown)\n");
3797 break;
3798 case SLI4_READ_CFG_TOPO_FC_DA:
3799 ocs_log_debug(sli4->os, "FC (direct attach)\n");
3800 break;
3801 case SLI4_READ_CFG_TOPO_FC_AL:
3802 ocs_log_debug(sli4->os, "FC (arbitrated loop)\n");
3803 break;
3804 default:
3805 ocs_log_test(sli4->os, "bad topology %#x\n", sli4->config.topology);
3806 }
3807
3808 sli4->config.e_d_tov = read_config->e_d_tov;
3809 sli4->config.r_a_tov = read_config->r_a_tov;
3810
3811 sli4->config.link_module_type = read_config->lmt;
3812
3813 sli4->config.max_qcount[SLI_QTYPE_EQ] = read_config->eq_count;
3814 sli4->config.max_qcount[SLI_QTYPE_CQ] = read_config->cq_count;
3815 sli4->config.max_qcount[SLI_QTYPE_WQ] = read_config->wq_count;
3816 sli4->config.max_qcount[SLI_QTYPE_RQ] = read_config->rq_count;
3817
3818 /*
3819 * READ_CONFIG doesn't give the max number of MQ. Applications
3820 * will typically want 1, but we may need another at some future
3821 * date. Dummy up a "max" MQ count here.
3822 */
3823 sli4->config.max_qcount[SLI_QTYPE_MQ] = SLI_USER_MQ_COUNT;
3824 } else {
3825 ocs_log_err(sli4->os, "bad READ_CONFIG write\n");
3826 return -1;
3827 }
3828
3829 if (sli_cmd_common_get_sli4_parameters(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE)) {
3830 sli4_res_common_get_sli4_parameters_t *parms = (sli4_res_common_get_sli4_parameters_t *)
3831 (((uint8_t *)sli4->bmbx.virt) + offsetof(sli4_cmd_sli_config_t, payload.embed));
3832
3833 if (sli_bmbx_command(sli4)) {
3834 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (COMMON_GET_SLI4_PARAMETERS)\n");
3835 return -1;
3836 } else if (parms->hdr.status) {
3837 ocs_log_err(sli4->os, "COMMON_GET_SLI4_PARAMETERS bad status %#x att'l %#x\n",
3838 parms->hdr.status, parms->hdr.additional_status);
3839 return -1;
3840 }
3841
3842 sli4->config.auto_reg = parms->areg;
3843 sli4->config.auto_xfer_rdy = parms->agxf;
3844 sli4->config.hdr_template_req = parms->hdrr;
3845 sli4->config.t10_dif_inline_capable = parms->timm;
3846 sli4->config.t10_dif_separate_capable = parms->tsmm;
3847
3848 sli4->config.mq_create_version = parms->mqv;
3849 sli4->config.cq_create_version = parms->cqv;
3850 sli4->config.rq_min_buf_size = parms->min_rq_buffer_size;
3851 sli4->config.rq_max_buf_size = parms->max_rq_buffer_size;
3852
3853 sli4->config.qpage_count[SLI_QTYPE_EQ] = parms->eq_page_cnt;
3854 sli4->config.qpage_count[SLI_QTYPE_CQ] = parms->cq_page_cnt;
3855 sli4->config.qpage_count[SLI_QTYPE_MQ] = parms->mq_page_cnt;
3856 sli4->config.qpage_count[SLI_QTYPE_WQ] = parms->wq_page_cnt;
3857 sli4->config.qpage_count[SLI_QTYPE_RQ] = parms->rq_page_cnt;
3858
3859 /* save count methods and masks for each queue type */
3860 sli4->config.count_mask[SLI_QTYPE_EQ] = parms->eqe_count_mask;
3861 sli4->config.count_method[SLI_QTYPE_EQ] = parms->eqe_count_method;
3862 sli4->config.count_mask[SLI_QTYPE_CQ] = parms->cqe_count_mask;
3863 sli4->config.count_method[SLI_QTYPE_CQ] = parms->cqe_count_method;
3864 sli4->config.count_mask[SLI_QTYPE_MQ] = parms->mqe_count_mask;
3865 sli4->config.count_method[SLI_QTYPE_MQ] = parms->mqe_count_method;
3866 sli4->config.count_mask[SLI_QTYPE_WQ] = parms->wqe_count_mask;
3867 sli4->config.count_method[SLI_QTYPE_WQ] = parms->wqe_count_method;
3868 sli4->config.count_mask[SLI_QTYPE_RQ] = parms->rqe_count_mask;
3869 sli4->config.count_method[SLI_QTYPE_RQ] = parms->rqe_count_method;
3870
3871 /* now calculate max queue entries */
3872 sli_calc_max_qentries(sli4);
3873
3874 sli4->config.max_sgl_pages = parms->sgl_page_cnt; /* max # of pages */
3875 sli4->config.sgl_page_sizes = parms->sgl_page_sizes; /* bit map of available sizes */
3876 /* ignore HLM here. Use value from REQUEST_FEATURES */
3877
3878 sli4->config.sge_supported_length = parms->sge_supported_length;
3879 if (sli4->config.sge_supported_length > OCS_MAX_SGE_SIZE)
3880 sli4->config.sge_supported_length = OCS_MAX_SGE_SIZE;
3881
3882 sli4->config.sgl_pre_registration_required = parms->sglr;
3883 /* default to using pre-registered SGL's */
3884 sli4->config.sgl_pre_registered = TRUE;
3885
3886 sli4->config.perf_hint = parms->phon;
3887 sli4->config.perf_wq_id_association = parms->phwq;
3888
3889 sli4->config.rq_batch = parms->rq_db_window;
3890
3891 /* save the fields for skyhawk SGL chaining */
3892 sli4->config.sgl_chaining_params.chaining_capable =
3893 (parms->sglc == 1);
3894 sli4->config.sgl_chaining_params.frag_num_field_offset =
3895 parms->frag_num_field_offset;
3896 sli4->config.sgl_chaining_params.frag_num_field_mask =
3897 (1ull << parms->frag_num_field_size) - 1;
3898 sli4->config.sgl_chaining_params.sgl_index_field_offset =
3899 parms->sgl_index_field_offset;
3900 sli4->config.sgl_chaining_params.sgl_index_field_mask =
3901 (1ull << parms->sgl_index_field_size) - 1;
3902 sli4->config.sgl_chaining_params.chain_sge_initial_value_lo =
3903 parms->chain_sge_initial_value_lo;
3904 sli4->config.sgl_chaining_params.chain_sge_initial_value_hi =
3905 parms->chain_sge_initial_value_hi;
3906
3907 /* Use the highest available WQE size. */
3908 if (parms->wqe_sizes & SLI4_128BYTE_WQE_SUPPORT) {
3909 sli4->config.wqe_size = SLI4_WQE_EXT_BYTES;
3910 } else {
3911 sli4->config.wqe_size = SLI4_WQE_BYTES;
3912 }
3913 }
3914
3915 if (sli_query_fw_config(sli4)) {
3916 ocs_log_err(sli4->os, "Error sending QUERY_FW_CONFIG\n");
3917 return -1;
3918 }
3919
3920 sli4->config.port_number = 0;
3921
3922 /*
3923 * Issue COMMON_GET_CNTL_ATTRIBUTES to get port_number. Temporarily
3924 * uses VPD DMA buffer as the response won't fit in the embedded
3925 * buffer.
3926 */
3927 if (sli_cmd_common_get_cntl_attributes(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE, &sli4->vpd.data)) {
3928 sli4_res_common_get_cntl_attributes_t *attr = sli4->vpd.data.virt;
3929
3930 if (sli_bmbx_command(sli4)) {
3931 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (COMMON_GET_CNTL_ATTRIBUTES)\n");
3932 return -1;
3933 } else if (attr->hdr.status) {
3934 ocs_log_err(sli4->os, "COMMON_GET_CNTL_ATTRIBUTES bad status %#x att'l %#x\n",
3935 attr->hdr.status, attr->hdr.additional_status);
3936 return -1;
3937 }
3938
3939 sli4->config.port_number = attr->port_number;
3940
3941 ocs_memcpy(sli4->config.bios_version_string, attr->bios_version_string,
3942 sizeof(sli4->config.bios_version_string));
3943 } else {
3944 ocs_log_err(sli4->os, "bad COMMON_GET_CNTL_ATTRIBUTES write\n");
3945 return -1;
3946 }
3947
3948 if (ocs_dma_alloc(sli4->os, &get_cntl_addl_data, sizeof(sli4_res_common_get_cntl_addl_attributes_t),
3949 OCS_MIN_DMA_ALIGNMENT)) {
3950 ocs_log_err(sli4->os, "Failed to allocate memory for GET_CNTL_ADDL_ATTR data\n");
3951 } else {
3952 if (sli_cmd_common_get_cntl_addl_attributes(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE,
3953 &get_cntl_addl_data)) {
3954 sli4_res_common_get_cntl_addl_attributes_t *attr = get_cntl_addl_data.virt;
3955
3956 if (sli_bmbx_command(sli4)) {
3957 ocs_log_crit(sli4->os,
3958 "bootstrap mailbox write fail (COMMON_GET_CNTL_ADDL_ATTRIBUTES)\n");
3959 ocs_dma_free(sli4->os, &get_cntl_addl_data);
3960 return -1;
3961 }
3962 if (attr->hdr.status) {
3963 ocs_log_err(sli4->os, "COMMON_GET_CNTL_ADDL_ATTRIBUTES bad status %#x\n",
3964 attr->hdr.status);
3965 ocs_dma_free(sli4->os, &get_cntl_addl_data);
3966 return -1;
3967 }
3968
3969 ocs_memcpy(sli4->config.ipl_name, attr->ipl_file_name, sizeof(sli4->config.ipl_name));
3970
3971 ocs_log_debug(sli4->os, "IPL:%s \n", (char*)sli4->config.ipl_name);
3972 } else {
3973 ocs_log_err(sli4->os, "bad COMMON_GET_CNTL_ADDL_ATTRIBUTES write\n");
3974 ocs_dma_free(sli4->os, &get_cntl_addl_data);
3975 return -1;
3976 }
3977
3978 ocs_dma_free(sli4->os, &get_cntl_addl_data);
3979 }
3980
3981 if (sli_cmd_common_get_port_name(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE)) {
3982 sli4_res_common_get_port_name_t *port_name = (sli4_res_common_get_port_name_t *)(((uint8_t *)sli4->bmbx.virt) +
3983 offsetof(sli4_cmd_sli_config_t, payload.embed));
3984
3985 if (sli_bmbx_command(sli4)) {
3986 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (COMMON_GET_PORT_NAME)\n");
3987 return -1;
3988 }
3989
3990 sli4->config.port_name[0] = port_name->port_name[sli4->config.port_number];
3991 }
3992 sli4->config.port_name[1] = '\0';
3993
3994 if (sli_cmd_read_rev(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE, &sli4->vpd.data)) {
3995 sli4_cmd_read_rev_t *read_rev = sli4->bmbx.virt;
3996
3997 if (sli_bmbx_command(sli4)) {
3998 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (READ_REV)\n");
3999 return -1;
4000 }
4001 if (read_rev->hdr.status) {
4002 ocs_log_err(sli4->os, "READ_REV bad status %#x\n",
4003 read_rev->hdr.status);
4004 return -1;
4005 }
4006
4007 sli4->config.fw_rev[0] = read_rev->first_fw_id;
4008 ocs_memcpy(sli4->config.fw_name[0],read_rev->first_fw_name, sizeof(sli4->config.fw_name[0]));
4009
4010 sli4->config.fw_rev[1] = read_rev->second_fw_id;
4011 ocs_memcpy(sli4->config.fw_name[1],read_rev->second_fw_name, sizeof(sli4->config.fw_name[1]));
4012
4013 sli4->config.hw_rev[0] = read_rev->first_hw_revision;
4014 sli4->config.hw_rev[1] = read_rev->second_hw_revision;
4015 sli4->config.hw_rev[2] = read_rev->third_hw_revision;
4016
4017 ocs_log_debug(sli4->os, "FW1:%s (%08x) / FW2:%s (%08x)\n",
4018 read_rev->first_fw_name, read_rev->first_fw_id,
4019 read_rev->second_fw_name, read_rev->second_fw_id);
4020
4021 ocs_log_debug(sli4->os, "HW1: %08x / HW2: %08x\n", read_rev->first_hw_revision,
4022 read_rev->second_hw_revision);
4023
4024 /* Check that all VPD data was returned */
4025 if (read_rev->returned_vpd_length != read_rev->actual_vpd_length) {
4026 ocs_log_test(sli4->os, "VPD length: available=%d returned=%d actual=%d\n",
4027 read_rev->available_length,
4028 read_rev->returned_vpd_length,
4029 read_rev->actual_vpd_length);
4030 }
4031 sli4->vpd.length = read_rev->returned_vpd_length;
4032 } else {
4033 ocs_log_err(sli4->os, "bad READ_REV write\n");
4034 return -1;
4035 }
4036
4037 if (sli_cmd_read_nvparms(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE)) {
4038 sli4_cmd_read_nvparms_t *read_nvparms = sli4->bmbx.virt;
4039
4040 if (sli_bmbx_command(sli4)) {
4041 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (READ_NVPARMS)\n");
4042 return -1;
4043 }
4044 if (read_nvparms->hdr.status) {
4045 ocs_log_err(sli4->os, "READ_NVPARMS bad status %#x\n",
4046 read_nvparms->hdr.status);
4047 return -1;
4048 }
4049
4050 ocs_memcpy(sli4->config.wwpn, read_nvparms->wwpn, sizeof(sli4->config.wwpn));
4051 ocs_memcpy(sli4->config.wwnn, read_nvparms->wwnn, sizeof(sli4->config.wwnn));
4052
4053 ocs_log_debug(sli4->os, "WWPN %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
4054 sli4->config.wwpn[0],
4055 sli4->config.wwpn[1],
4056 sli4->config.wwpn[2],
4057 sli4->config.wwpn[3],
4058 sli4->config.wwpn[4],
4059 sli4->config.wwpn[5],
4060 sli4->config.wwpn[6],
4061 sli4->config.wwpn[7]);
4062 ocs_log_debug(sli4->os, "WWNN %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
4063 sli4->config.wwnn[0],
4064 sli4->config.wwnn[1],
4065 sli4->config.wwnn[2],
4066 sli4->config.wwnn[3],
4067 sli4->config.wwnn[4],
4068 sli4->config.wwnn[5],
4069 sli4->config.wwnn[6],
4070 sli4->config.wwnn[7]);
4071 } else {
4072 ocs_log_err(sli4->os, "bad READ_NVPARMS write\n");
4073 return -1;
4074 }
4075
4076 return 0;
4077 }
4078
4079 /****************************************************************************
4080 * Public functions
4081 */
4082
4083 /**
4084 * @ingroup sli
4085 * @brief Set up the SLI context.
4086 *
4087 * @param sli4 SLI context.
4088 * @param os Device abstraction.
4089 * @param port_type Protocol type of port (for example, FC and NIC).
4090 *
4091 * @return Returns 0 on success, or a non-zero value on failure.
4092 */
4093 int32_t
sli_setup(sli4_t * sli4,ocs_os_handle_t os,sli4_port_type_e port_type)4094 sli_setup(sli4_t *sli4, ocs_os_handle_t os, sli4_port_type_e port_type)
4095 {
4096 uint32_t sli_intf = UINT32_MAX;
4097 uint32_t pci_class_rev = 0;
4098 uint32_t rev_id = 0;
4099 uint32_t family = 0;
4100 uint32_t i;
4101 sli4_asic_entry_t *asic;
4102
4103 ocs_memset(sli4, 0, sizeof(sli4_t));
4104
4105 sli4->os = os;
4106 sli4->port_type = port_type;
4107
4108 /*
4109 * Read the SLI_INTF register to discover the register layout
4110 * and other capability information
4111 */
4112 sli_intf = ocs_config_read32(os, SLI4_INTF_REG);
4113
4114 if (sli_intf_valid_check(sli_intf)) {
4115 ocs_log_err(os, "SLI_INTF is not valid\n");
4116 return -1;
4117 }
4118
4119 /* driver only support SLI-4 */
4120 sli4->sli_rev = sli_intf_sli_revision(sli_intf);
4121 if (4 != sli4->sli_rev) {
4122 ocs_log_err(os, "Unsupported SLI revision (intf=%#x)\n",
4123 sli_intf);
4124 return -1;
4125 }
4126
4127 sli4->sli_family = sli_intf_sli_family(sli_intf);
4128
4129 sli4->if_type = sli_intf_if_type(sli_intf);
4130
4131 if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type) ||
4132 (SLI4_IF_TYPE_LANCER_G7 == sli4->if_type)) {
4133 ocs_log_debug(os, "status=%#x error1=%#x error2=%#x\n",
4134 sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS),
4135 sli_reg_read(sli4, SLI4_REG_SLIPORT_ERROR1),
4136 sli_reg_read(sli4, SLI4_REG_SLIPORT_ERROR2));
4137 }
4138
4139 /*
4140 * set the ASIC type and revision
4141 */
4142 pci_class_rev = ocs_config_read32(os, SLI4_PCI_CLASS_REVISION);
4143 rev_id = sli_pci_rev_id(pci_class_rev);
4144 family = sli4->sli_family;
4145 if (family == SLI4_FAMILY_CHECK_ASIC_TYPE) {
4146 uint32_t asic_id = ocs_config_read32(os, SLI4_ASIC_ID_REG);
4147 family = sli_asic_gen(asic_id);
4148 }
4149
4150 for (i = 0, asic = sli4_asic_table; i < ARRAY_SIZE(sli4_asic_table); i++, asic++) {
4151 if ((rev_id == asic->rev_id) && (family == asic->family)) {
4152 sli4->asic_type = asic->type;
4153 sli4->asic_rev = asic->rev;
4154 break;
4155 }
4156 }
4157 /* Fail if no matching asic type/rev was found */
4158 if( (sli4->asic_type == 0) || (sli4->asic_rev == 0)) {
4159 ocs_log_err(os, "no matching asic family/rev found: %02x/%02x\n", family, rev_id);
4160 return -1;
4161 }
4162
4163 /*
4164 * The bootstrap mailbox is equivalent to a MQ with a single 256 byte
4165 * entry, a CQ with a single 16 byte entry, and no event queue.
4166 * Alignment must be 16 bytes as the low order address bits in the
4167 * address register are also control / status.
4168 */
4169 if (ocs_dma_alloc(sli4->os, &sli4->bmbx, SLI4_BMBX_SIZE +
4170 sizeof(sli4_mcqe_t), 16)) {
4171 ocs_log_err(os, "bootstrap mailbox allocation failed\n");
4172 return -1;
4173 }
4174
4175 if (sli4->bmbx.phys & SLI4_BMBX_MASK_LO) {
4176 ocs_log_err(os, "bad alignment for bootstrap mailbox\n");
4177 return -1;
4178 }
4179
4180 ocs_log_debug(os, "bmbx v=%p p=0x%x %08x s=%zd\n", sli4->bmbx.virt,
4181 ocs_addr32_hi(sli4->bmbx.phys),
4182 ocs_addr32_lo(sli4->bmbx.phys),
4183 sli4->bmbx.size);
4184
4185 /* TODO 4096 is arbitrary. What should this value actually be? */
4186 if (ocs_dma_alloc(sli4->os, &sli4->vpd.data, 4096/*TODO*/, 4096)) {
4187 /* Note that failure isn't fatal in this specific case */
4188 sli4->vpd.data.size = 0;
4189 ocs_log_test(os, "VPD buffer allocation failed\n");
4190 }
4191
4192 if (sli_fw_init(sli4)) {
4193 ocs_log_err(sli4->os, "FW initialization failed\n");
4194 return -1;
4195 }
4196
4197 /*
4198 * Set one of fcpi(initiator), fcpt(target), fcpc(combined) to true
4199 * in addition to any other desired features
4200 */
4201 sli4->config.features.flag.iaab = TRUE;
4202 sli4->config.features.flag.npiv = TRUE;
4203 sli4->config.features.flag.dif = TRUE;
4204 sli4->config.features.flag.vf = TRUE;
4205 sli4->config.features.flag.fcpc = TRUE;
4206 sli4->config.features.flag.iaar = TRUE;
4207 sli4->config.features.flag.hlm = TRUE;
4208 sli4->config.features.flag.perfh = TRUE;
4209 sli4->config.features.flag.rxseq = TRUE;
4210 sli4->config.features.flag.rxri = TRUE;
4211 sli4->config.features.flag.mrqp = TRUE;
4212
4213 /* use performance hints if available */
4214 if (sli4->config.perf_hint) {
4215 sli4->config.features.flag.perfh = TRUE;
4216 }
4217
4218 if (sli_request_features(sli4, &sli4->config.features, TRUE)) {
4219 return -1;
4220 }
4221
4222 if (sli_get_config(sli4)) {
4223 return -1;
4224 }
4225
4226 return 0;
4227 }
4228
4229 bool
sli_persist_topology_enabled(sli4_t * sli4)4230 sli_persist_topology_enabled(sli4_t *sli4)
4231 {
4232 return (sli4->config.ptv);
4233 }
4234
4235 int32_t
sli_init(sli4_t * sli4)4236 sli_init(sli4_t *sli4)
4237 {
4238
4239 if (sli4->config.has_extents) {
4240 /* TODO COMMON_ALLOC_RESOURCE_EXTENTS */;
4241 ocs_log_test(sli4->os, "XXX need to implement extent allocation\n");
4242 return -1;
4243 }
4244
4245 sli4->config.features.flag.hlm = sli4->config.high_login_mode;
4246 sli4->config.features.flag.rxseq = FALSE;
4247 sli4->config.features.flag.rxri = FALSE;
4248
4249 if (sli_request_features(sli4, &sli4->config.features, FALSE)) {
4250 return -1;
4251 }
4252
4253 return 0;
4254 }
4255
4256 int32_t
sli_reset(sli4_t * sli4)4257 sli_reset(sli4_t *sli4)
4258 {
4259 uint32_t i;
4260
4261 if (sli_fw_init(sli4)) {
4262 ocs_log_crit(sli4->os, "FW initialization failed\n");
4263 return -1;
4264 }
4265
4266 if (sli4->config.extent[0].base) {
4267 ocs_free(sli4->os, sli4->config.extent[0].base, SLI_RSRC_MAX * sizeof(uint32_t));
4268 sli4->config.extent[0].base = NULL;
4269 }
4270
4271 for (i = 0; i < SLI_RSRC_MAX; i++) {
4272 if (sli4->config.extent[i].use_map) {
4273 ocs_bitmap_free(sli4->config.extent[i].use_map);
4274 sli4->config.extent[i].use_map = NULL;
4275 }
4276 sli4->config.extent[i].base = NULL;
4277 }
4278
4279 if (sli_get_config(sli4)) {
4280 return -1;
4281 }
4282
4283 return 0;
4284 }
4285
4286 /**
4287 * @ingroup sli
4288 * @brief Issue a Firmware Reset.
4289 *
4290 * @par Description
4291 * Issues a Firmware Reset to the chip. This reset affects the entire chip,
4292 * so all PCI function on the same PCI bus and device are affected.
4293 * @n @n This type of reset can be used to activate newly downloaded firmware.
4294 * @n @n The driver should be considered to be in an unknown state after this
4295 * reset and should be reloaded.
4296 *
4297 * @param sli4 SLI context.
4298 *
4299 * @return Returns 0 on success, or -1 otherwise.
4300 */
4301
4302 int32_t
sli_fw_reset(sli4_t * sli4)4303 sli_fw_reset(sli4_t *sli4)
4304 {
4305 uint32_t val;
4306 uint32_t ready;
4307
4308 /*
4309 * Firmware must be ready before issuing the reset.
4310 */
4311 ready = sli_wait_for_fw_ready(sli4, SLI4_FW_READY_TIMEOUT_MSEC);
4312 if (!ready) {
4313 ocs_log_crit(sli4->os, "FW status is NOT ready\n");
4314 return -1;
4315 }
4316 switch(sli4->if_type) {
4317 case SLI4_IF_TYPE_BE3_SKH_PF:
4318 /* BE3 / Skyhawk use PCICFG_SOFT_RESET_CSR */
4319 val = ocs_config_read32(sli4->os, SLI4_PCI_SOFT_RESET_CSR);
4320 val |= SLI4_PCI_SOFT_RESET_MASK;
4321 ocs_config_write32(sli4->os, SLI4_PCI_SOFT_RESET_CSR, val);
4322 break;
4323 case SLI4_IF_TYPE_LANCER_FC_ETH:
4324 /* Lancer uses PHYDEV_CONTROL */
4325
4326 val = SLI4_PHYDEV_CONTROL_FRST;
4327 sli_reg_write(sli4, SLI4_REG_PHYSDEV_CONTROL, val);
4328 break;
4329 default:
4330 ocs_log_test(sli4->os, "Unexpected iftype %d\n", sli4->if_type);
4331 return -1;
4332 break;
4333 }
4334
4335 /* wait for the FW to become ready after the reset */
4336 ready = sli_wait_for_fw_ready(sli4, SLI4_FW_READY_TIMEOUT_MSEC);
4337 if (!ready) {
4338 ocs_log_crit(sli4->os, "Failed to become ready after firmware reset\n");
4339 return -1;
4340 }
4341 return 0;
4342 }
4343
4344 /**
4345 * @ingroup sli
4346 * @brief Tear down a SLI context.
4347 *
4348 * @param sli4 SLI context.
4349 *
4350 * @return Returns 0 on success, or non-zero otherwise.
4351 */
4352 int32_t
sli_teardown(sli4_t * sli4)4353 sli_teardown(sli4_t *sli4)
4354 {
4355 uint32_t i;
4356
4357 if (sli4->config.extent[0].base) {
4358 ocs_free(sli4->os, sli4->config.extent[0].base, SLI_RSRC_MAX * sizeof(uint32_t));
4359 sli4->config.extent[0].base = NULL;
4360 }
4361
4362 for (i = 0; i < SLI_RSRC_MAX; i++) {
4363 if (sli4->config.has_extents) {
4364 /* TODO COMMON_DEALLOC_RESOURCE_EXTENTS */;
4365 }
4366
4367 sli4->config.extent[i].base = NULL;
4368
4369 ocs_bitmap_free(sli4->config.extent[i].use_map);
4370 sli4->config.extent[i].use_map = NULL;
4371 }
4372
4373 if (sli_fw_term(sli4)) {
4374 ocs_log_err(sli4->os, "FW deinitialization failed\n");
4375 }
4376
4377 ocs_dma_free(sli4->os, &sli4->vpd.data);
4378 ocs_dma_free(sli4->os, &sli4->bmbx);
4379
4380 return 0;
4381 }
4382
4383 /**
4384 * @ingroup sli
4385 * @brief Register a callback for the given event.
4386 *
4387 * @param sli4 SLI context.
4388 * @param which Event of interest.
4389 * @param func Function to call when the event occurs.
4390 * @param arg Argument passed to the callback function.
4391 *
4392 * @return Returns 0 on success, or non-zero otherwise.
4393 */
4394 int32_t
sli_callback(sli4_t * sli4,sli4_callback_e which,void * func,void * arg)4395 sli_callback(sli4_t *sli4, sli4_callback_e which, void *func, void *arg)
4396 {
4397
4398 if (!sli4 || !func || (which >= SLI4_CB_MAX)) {
4399 ocs_log_err(NULL, "bad parameter sli4=%p which=%#x func=%p\n",
4400 sli4, which, func);
4401 return -1;
4402 }
4403
4404 switch (which) {
4405 case SLI4_CB_LINK:
4406 sli4->link = func;
4407 sli4->link_arg = arg;
4408 break;
4409 case SLI4_CB_FIP:
4410 sli4->fip = func;
4411 sli4->fip_arg = arg;
4412 break;
4413 default:
4414 ocs_log_test(sli4->os, "unknown callback %#x\n", which);
4415 return -1;
4416 }
4417
4418 return 0;
4419 }
4420
4421 /**
4422 * @ingroup sli
4423 * @brief Initialize a queue object.
4424 *
4425 * @par Description
4426 * This initializes the sli4_queue_t object members, including the underlying
4427 * DMA memory.
4428 *
4429 * @param sli4 SLI context.
4430 * @param q Pointer to queue object.
4431 * @param qtype Type of queue to create.
4432 * @param size Size of each entry.
4433 * @param n_entries Number of entries to allocate.
4434 * @param align Starting memory address alignment.
4435 *
4436 * @note Checks if using the existing DMA memory (if any) is possible. If not,
4437 * it frees the existing memory and re-allocates.
4438 *
4439 * @return Returns 0 on success, or non-zero otherwise.
4440 */
4441 int32_t
__sli_queue_init(sli4_t * sli4,sli4_queue_t * q,uint32_t qtype,size_t size,uint32_t n_entries,uint32_t align)4442 __sli_queue_init(sli4_t *sli4, sli4_queue_t *q, uint32_t qtype,
4443 size_t size, uint32_t n_entries, uint32_t align)
4444 {
4445
4446 if ((q->dma.virt == NULL) || (size != q->size) || (n_entries != q->length)) {
4447 if (q->dma.size) {
4448 ocs_dma_free(sli4->os, &q->dma);
4449 }
4450
4451 ocs_memset(q, 0, sizeof(sli4_queue_t));
4452
4453 if (ocs_dma_alloc(sli4->os, &q->dma, size * n_entries, align)) {
4454 ocs_log_err(sli4->os, "%s allocation failed\n", SLI_QNAME[qtype]);
4455 return -1;
4456 }
4457
4458 ocs_memset(q->dma.virt, 0, size * n_entries);
4459
4460 ocs_lock_init(sli4->os, &q->lock, "%s lock[%d:%p]",
4461 SLI_QNAME[qtype], ocs_instance(sli4->os), &q->lock);
4462
4463 q->type = qtype;
4464 q->size = size;
4465 q->length = n_entries;
4466
4467 /* Limit to hwf the queue size per interrupt */
4468 q->proc_limit = n_entries / 2;
4469
4470 if ( (q->type == SLI_QTYPE_EQ) || (q->type == SLI_QTYPE_CQ) ) {
4471 /* For prism, phase will be flipped after a sweep through eq and cq */
4472 q->phase = 1;
4473 }
4474
4475 switch(q->type) {
4476 case SLI_QTYPE_EQ:
4477 q->posted_limit = q->length / 2;
4478 break;
4479 default:
4480 if ((sli4->if_type == SLI4_IF_TYPE_BE3_SKH_PF) ||
4481 (sli4->if_type == SLI4_IF_TYPE_BE3_SKH_VF)) {
4482 /* For Skyhawk, ring the doorbell more often */
4483 q->posted_limit = 8;
4484 } else {
4485 q->posted_limit = 64;
4486 }
4487 break;
4488 }
4489 }
4490
4491 return 0;
4492 }
4493
4494 /**
4495 * @ingroup sli
4496 * @brief Issue the command to create a queue.
4497 *
4498 * @param sli4 SLI context.
4499 * @param q Pointer to queue object.
4500 *
4501 * @return Returns 0 on success, or non-zero otherwise.
4502 */
4503 int32_t
__sli_create_queue(sli4_t * sli4,sli4_queue_t * q)4504 __sli_create_queue(sli4_t *sli4, sli4_queue_t *q)
4505 {
4506 sli4_res_common_create_queue_t *res_q = NULL;
4507
4508 if (sli_bmbx_command(sli4)){
4509 ocs_log_crit(sli4->os, "bootstrap mailbox write fail %s\n",
4510 SLI_QNAME[q->type]);
4511 ocs_dma_free(sli4->os, &q->dma);
4512 return -1;
4513 }
4514 if (sli_res_sli_config(sli4->bmbx.virt)) {
4515 ocs_log_err(sli4->os, "bad status create %s\n", SLI_QNAME[q->type]);
4516 ocs_dma_free(sli4->os, &q->dma);
4517 return -1;
4518 }
4519 res_q = (void *)((uint8_t *)sli4->bmbx.virt +
4520 offsetof(sli4_cmd_sli_config_t, payload));
4521
4522 if (res_q->hdr.status) {
4523 ocs_log_err(sli4->os, "bad create %s status=%#x addl=%#x\n",
4524 SLI_QNAME[q->type],
4525 res_q->hdr.status, res_q->hdr.additional_status);
4526 ocs_dma_free(sli4->os, &q->dma);
4527 return -1;
4528 } else {
4529 q->id = res_q->q_id;
4530 q->doorbell_offset = res_q->db_offset;
4531 q->doorbell_rset = res_q->db_rs;
4532
4533 switch (q->type) {
4534 case SLI_QTYPE_EQ:
4535 /* No doorbell information in response for EQs */
4536 q->doorbell_offset = regmap[SLI4_REG_EQ_DOORBELL][sli4->if_type].off;
4537 q->doorbell_rset = regmap[SLI4_REG_EQ_DOORBELL][sli4->if_type].rset;
4538 break;
4539 case SLI_QTYPE_CQ:
4540 /* No doorbell information in response for CQs */
4541 q->doorbell_offset = regmap[SLI4_REG_CQ_DOORBELL][sli4->if_type].off;
4542 q->doorbell_rset = regmap[SLI4_REG_CQ_DOORBELL][sli4->if_type].rset;
4543 break;
4544 case SLI_QTYPE_MQ:
4545 /* No doorbell information in response for MQs */
4546 q->doorbell_offset = regmap[SLI4_REG_MQ_DOORBELL][sli4->if_type].off;
4547 q->doorbell_rset = regmap[SLI4_REG_MQ_DOORBELL][sli4->if_type].rset;
4548 break;
4549 case SLI_QTYPE_RQ:
4550 /* set the doorbell for non-skyhawks */
4551 if (!sli4->config.dual_ulp_capable) {
4552 q->doorbell_offset = regmap[SLI4_REG_FCOE_RQ_DOORBELL][sli4->if_type].off;
4553 q->doorbell_rset = regmap[SLI4_REG_FCOE_RQ_DOORBELL][sli4->if_type].rset;
4554 }
4555 break;
4556 case SLI_QTYPE_WQ:
4557 /* set the doorbell for non-skyhawks */
4558 if (!sli4->config.dual_ulp_capable) {
4559 q->doorbell_offset = regmap[SLI4_REG_IO_WQ_DOORBELL][sli4->if_type].off;
4560 q->doorbell_rset = regmap[SLI4_REG_IO_WQ_DOORBELL][sli4->if_type].rset;
4561 }
4562 break;
4563 default:
4564 break;
4565 }
4566 }
4567
4568 return 0;
4569 }
4570
4571 /**
4572 * @ingroup sli
4573 * @brief Get queue entry size.
4574 *
4575 * Get queue entry size given queue type.
4576 *
4577 * @param sli4 SLI context
4578 * @param qtype Type for which the entry size is returned.
4579 *
4580 * @return Returns > 0 on success (queue entry size), or a negative value on failure.
4581 */
4582 int32_t
sli_get_queue_entry_size(sli4_t * sli4,uint32_t qtype)4583 sli_get_queue_entry_size(sli4_t *sli4, uint32_t qtype)
4584 {
4585 uint32_t size = 0;
4586
4587 if (!sli4) {
4588 ocs_log_err(NULL, "bad parameter sli4=%p\n", sli4);
4589 return -1;
4590 }
4591
4592 switch (qtype) {
4593 case SLI_QTYPE_EQ:
4594 size = sizeof(uint32_t);
4595 break;
4596 case SLI_QTYPE_CQ:
4597 size = 16;
4598 break;
4599 case SLI_QTYPE_MQ:
4600 size = 256;
4601 break;
4602 case SLI_QTYPE_WQ:
4603 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
4604 size = sli4->config.wqe_size;
4605 } else {
4606 /* TODO */
4607 ocs_log_test(sli4->os, "unsupported queue entry size\n");
4608 return -1;
4609 }
4610 break;
4611 case SLI_QTYPE_RQ:
4612 size = SLI4_FCOE_RQE_SIZE;
4613 break;
4614 default:
4615 ocs_log_test(sli4->os, "unknown queue type %d\n", qtype);
4616 return -1;
4617 }
4618 return size;
4619 }
4620
4621 /**
4622 * @ingroup sli
4623 * @brief Modify the delay timer for all the EQs
4624 *
4625 * @param sli4 SLI context.
4626 * @param eq Array of EQs.
4627 * @param num_eq Count of EQs.
4628 * @param shift Phase shift for staggering interrupts.
4629 * @param delay_mult Delay multiplier for limiting interrupt frequency.
4630 *
4631 * @return Returns 0 on success, or -1 otherwise.
4632 */
4633 int32_t
sli_eq_modify_delay(sli4_t * sli4,sli4_queue_t * eq,uint32_t num_eq,uint32_t shift,uint32_t delay_mult)4634 sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult)
4635 {
4636
4637 sli_cmd_common_modify_eq_delay(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE, eq, num_eq, shift, delay_mult);
4638
4639 if (sli_bmbx_command(sli4)) {
4640 ocs_log_crit(sli4->os, "bootstrap mailbox write fail (MODIFY EQ DELAY)\n");
4641 return -1;
4642 }
4643 if (sli_res_sli_config(sli4->bmbx.virt)) {
4644 ocs_log_err(sli4->os, "bad status MODIFY EQ DELAY\n");
4645 return -1;
4646 }
4647
4648 return 0;
4649 }
4650
4651 /**
4652 * @ingroup sli
4653 * @brief Allocate a queue.
4654 *
4655 * @par Description
4656 * Allocates DMA memory and configures the requested queue type.
4657 *
4658 * @param sli4 SLI context.
4659 * @param qtype Type of queue to create.
4660 * @param q Pointer to the queue object.
4661 * @param n_entries Number of entries to allocate.
4662 * @param assoc Associated queue (that is, the EQ for a CQ, the CQ for a MQ, and so on).
4663 * @param ulp The ULP to bind, which is only used for WQ and RQs
4664 *
4665 * @return Returns 0 on success, or -1 otherwise.
4666 */
4667 int32_t
sli_queue_alloc(sli4_t * sli4,uint32_t qtype,sli4_queue_t * q,uint32_t n_entries,sli4_queue_t * assoc,uint16_t ulp)4668 sli_queue_alloc(sli4_t *sli4, uint32_t qtype, sli4_queue_t *q, uint32_t n_entries,
4669 sli4_queue_t *assoc, uint16_t ulp)
4670 {
4671 int32_t size;
4672 uint32_t align = 0;
4673 sli4_create_q_fn_t create = NULL;
4674
4675 if (!sli4 || !q) {
4676 ocs_log_err(NULL, "bad parameter sli4=%p q=%p\n", sli4, q);
4677 return -1;
4678 }
4679
4680 /* get queue size */
4681 size = sli_get_queue_entry_size(sli4, qtype);
4682 if (size < 0)
4683 return -1;
4684 align = SLI_PAGE_SIZE;
4685
4686 switch (qtype) {
4687 case SLI_QTYPE_EQ:
4688 create = sli_cmd_common_create_eq;
4689 break;
4690 case SLI_QTYPE_CQ:
4691 create = sli_cmd_common_create_cq;
4692 break;
4693 case SLI_QTYPE_MQ:
4694 /* Validate the number of entries */
4695 switch (n_entries) {
4696 case 16:
4697 case 32:
4698 case 64:
4699 case 128:
4700 break;
4701 default:
4702 ocs_log_test(sli4->os, "illegal n_entries value %d for MQ\n", n_entries);
4703 return -1;
4704 }
4705 assoc->u.flag.is_mq = TRUE;
4706 create = sli_cmd_common_create_mq_ext;
4707 break;
4708 case SLI_QTYPE_WQ:
4709 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
4710 if (sli4->if_type == SLI4_IF_TYPE_BE3_SKH_PF) {
4711 create = sli_cmd_fcoe_wq_create;
4712 } else {
4713 create = sli_cmd_fcoe_wq_create_v1;
4714 }
4715 } else {
4716 /* TODO */
4717 ocs_log_test(sli4->os, "unsupported WQ create\n");
4718 return -1;
4719 }
4720 break;
4721 default:
4722 ocs_log_test(sli4->os, "unknown queue type %d\n", qtype);
4723 return -1;
4724 }
4725
4726
4727 if (__sli_queue_init(sli4, q, qtype, size, n_entries, align)) {
4728 ocs_log_err(sli4->os, "%s allocation failed\n", SLI_QNAME[qtype]);
4729 return -1;
4730 }
4731
4732 if (create(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE, &q->dma, assoc ? assoc->id : 0, ulp)) {
4733
4734 if (__sli_create_queue(sli4, q)) {
4735 ocs_log_err(sli4->os, "create %s failed\n", SLI_QNAME[qtype]);
4736 return -1;
4737 }
4738 q->ulp = ulp;
4739 } else {
4740 ocs_log_err(sli4->os, "cannot create %s\n", SLI_QNAME[qtype]);
4741 return -1;
4742 }
4743
4744 return 0;
4745 }
4746
4747
4748 /**
4749 * @ingroup sli
4750 * @brief Allocate a c queue set.
4751 *
4752 * @param sli4 SLI context.
4753 * @param num_cqs to create
4754 * @param qs Pointers to the queue objects.
4755 * @param n_entries Number of entries to allocate per CQ.
4756 * @param eqs Associated event queues
4757 *
4758 * @return Returns 0 on success, or -1 otherwise.
4759 */
4760 int32_t
sli_cq_alloc_set(sli4_t * sli4,sli4_queue_t * qs[],uint32_t num_cqs,uint32_t n_entries,sli4_queue_t * eqs[])4761 sli_cq_alloc_set(sli4_t *sli4, sli4_queue_t *qs[], uint32_t num_cqs,
4762 uint32_t n_entries, sli4_queue_t *eqs[])
4763 {
4764 uint32_t i, offset = 0, page_bytes = 0, payload_size, cmd_size = 0;
4765 uint32_t p = 0, page_size = 0, n_cqe = 0, num_pages_cq;
4766 uintptr_t addr;
4767 ocs_dma_t dma;
4768 sli4_req_common_create_cq_set_v0_t *req = NULL;
4769 sli4_res_common_create_queue_set_t *res = NULL;
4770
4771 if (!sli4) {
4772 ocs_log_err(NULL, "bad parameter sli4=%p\n", sli4);
4773 return -1;
4774 }
4775
4776 /* Align the queue DMA memory */
4777 for (i = 0; i < num_cqs; i++) {
4778 if (__sli_queue_init(sli4, qs[i], SLI_QTYPE_CQ, SLI4_CQE_BYTES,
4779 n_entries, SLI_PAGE_SIZE)) {
4780 ocs_log_err(sli4->os, "Queue init failed.\n");
4781 goto error;
4782 }
4783 }
4784
4785 n_cqe = qs[0]->dma.size / SLI4_CQE_BYTES;
4786 switch (n_cqe) {
4787 case 256:
4788 case 512:
4789 case 1024:
4790 case 2048:
4791 page_size = 1;
4792 break;
4793 case 4096:
4794 page_size = 2;
4795 break;
4796 default:
4797 return -1;
4798 }
4799
4800 page_bytes = page_size * SLI_PAGE_SIZE;
4801 num_pages_cq = sli_page_count(qs[0]->dma.size, page_bytes);
4802 cmd_size = sizeof(sli4_req_common_create_cq_set_v0_t) + (8 * num_pages_cq * num_cqs);
4803 payload_size = max((size_t)cmd_size, sizeof(sli4_res_common_create_queue_set_t));
4804
4805 if (ocs_dma_alloc(sli4->os, &dma, payload_size, SLI_PAGE_SIZE)) {
4806 ocs_log_err(sli4->os, "DMA allocation failed\n");
4807 goto error;
4808 }
4809 ocs_memset(dma.virt, 0, payload_size);
4810
4811 if (sli_cmd_sli_config(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE,
4812 payload_size, &dma) == -1) {
4813 goto error;
4814 }
4815
4816 /* Fill the request structure */
4817
4818 req = (sli4_req_common_create_cq_set_v0_t *)((uint8_t *)dma.virt);
4819 req->hdr.opcode = SLI4_OPC_COMMON_CREATE_CQ_SET;
4820 req->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
4821 req->hdr.version = 0;
4822 req->hdr.request_length = cmd_size - sizeof(sli4_req_hdr_t);
4823 req->page_size = page_size;
4824
4825 req->num_pages = num_pages_cq;
4826 switch (req->num_pages) {
4827 case 1:
4828 req->cqecnt = SLI4_CQ_CNT_256;
4829 break;
4830 case 2:
4831 req->cqecnt = SLI4_CQ_CNT_512;
4832 break;
4833 case 4:
4834 req->cqecnt = SLI4_CQ_CNT_1024;
4835 break;
4836 case 8:
4837 req->cqecnt = SLI4_CQ_CNT_LARGE;
4838 req->cqe_count = n_cqe;
4839 break;
4840 default:
4841 ocs_log_test(sli4->os, "num_pages %d not valid\n", req->num_pages);
4842 goto error;
4843 }
4844
4845 req->evt = TRUE;
4846 req->valid = TRUE;
4847 req->arm = FALSE;
4848 req->num_cq_req = num_cqs;
4849
4850 if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7)
4851 req->autovalid = TRUE;
4852
4853 /* Fill page addresses of all the CQs. */
4854 for (i = 0; i < num_cqs; i++) {
4855 req->eq_id[i] = eqs[i]->id;
4856 for (p = 0, addr = qs[i]->dma.phys; p < req->num_pages; p++, addr += page_bytes) {
4857 req->page_physical_address[offset].low = ocs_addr32_lo(addr);
4858 req->page_physical_address[offset].high = ocs_addr32_hi(addr);
4859 offset++;
4860 }
4861 }
4862
4863 if (sli_bmbx_command(sli4)) {
4864 ocs_log_crit(sli4->os, "bootstrap mailbox write fail CQSet\n");
4865 goto error;
4866 }
4867
4868 res = (void *)((uint8_t *)dma.virt);
4869 if (res->hdr.status) {
4870 ocs_log_err(sli4->os, "bad create CQSet status=%#x addl=%#x\n",
4871 res->hdr.status, res->hdr.additional_status);
4872 goto error;
4873 } else {
4874 /* Check if we got all requested CQs. */
4875 if (res->num_q_allocated != num_cqs) {
4876 ocs_log_crit(sli4->os, "Requested count CQs doesnt match.\n");
4877 goto error;
4878 }
4879
4880 /* Fill the resp cq ids. */
4881 for (i = 0; i < num_cqs; i++) {
4882 qs[i]->id = res->q_id + i;
4883 qs[i]->doorbell_offset = regmap[SLI4_REG_CQ_DOORBELL][sli4->if_type].off;
4884 qs[i]->doorbell_rset = regmap[SLI4_REG_CQ_DOORBELL][sli4->if_type].rset;
4885 }
4886 }
4887
4888 ocs_dma_free(sli4->os, &dma);
4889
4890 return 0;
4891
4892 error:
4893 for (i = 0; i < num_cqs; i++) {
4894 if (qs[i]->dma.size) {
4895 ocs_dma_free(sli4->os, &qs[i]->dma);
4896 }
4897 }
4898
4899 if (dma.size) {
4900 ocs_dma_free(sli4->os, &dma);
4901 }
4902
4903 return -1;
4904 }
4905
4906
4907
4908 /**
4909 * @ingroup sli
4910 * @brief Free a queue.
4911 *
4912 * @par Description
4913 * Frees DMA memory and de-registers the requested queue.
4914 *
4915 * @param sli4 SLI context.
4916 * @param q Pointer to the queue object.
4917 * @param destroy_queues Non-zero if the mailbox commands should be sent to destroy the queues.
4918 * @param free_memory Non-zero if the DMA memory associated with the queue should be freed.
4919 *
4920 * @return Returns 0 on success, or -1 otherwise.
4921 */
4922 int32_t
sli_queue_free(sli4_t * sli4,sli4_queue_t * q,uint32_t destroy_queues,uint32_t free_memory)4923 sli_queue_free(sli4_t *sli4, sli4_queue_t *q, uint32_t destroy_queues, uint32_t free_memory)
4924 {
4925 sli4_destroy_q_fn_t destroy = NULL;
4926 int32_t rc = -1;
4927
4928 if (!sli4 || !q) {
4929 ocs_log_err(NULL, "bad parameter sli4=%p q=%p\n", sli4, q);
4930 return -1;
4931 }
4932
4933 if (destroy_queues) {
4934 switch (q->type) {
4935 case SLI_QTYPE_EQ:
4936 destroy = sli_cmd_common_destroy_eq;
4937 break;
4938 case SLI_QTYPE_CQ:
4939 destroy = sli_cmd_common_destroy_cq;
4940 break;
4941 case SLI_QTYPE_MQ:
4942 destroy = sli_cmd_common_destroy_mq;
4943 break;
4944 case SLI_QTYPE_WQ:
4945 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
4946 destroy = sli_cmd_fcoe_wq_destroy;
4947 } else {
4948 /* TODO */
4949 ocs_log_test(sli4->os, "unsupported WQ destroy\n");
4950 return -1;
4951 }
4952 break;
4953 case SLI_QTYPE_RQ:
4954 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
4955 destroy = sli_cmd_fcoe_rq_destroy;
4956 } else {
4957 /* TODO */
4958 ocs_log_test(sli4->os, "unsupported RQ destroy\n");
4959 return -1;
4960 }
4961 break;
4962 default:
4963 ocs_log_test(sli4->os, "bad queue type %d\n",
4964 q->type);
4965 return -1;
4966 }
4967
4968 /*
4969 * Destroying queues makes BE3 sad (version 0 interface type). Rely
4970 * on COMMON_FUNCTION_RESET to free host allocated queue resources
4971 * inside the SLI Port.
4972 */
4973 if (SLI4_IF_TYPE_BE3_SKH_PF == sli4->if_type) {
4974 destroy = NULL;
4975 }
4976
4977 /* Destroy the queue if the operation is defined */
4978 if (destroy && destroy(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE, q->id)) {
4979 sli4_res_hdr_t *res = NULL;
4980
4981 if (sli_bmbx_command(sli4)){
4982 ocs_log_crit(sli4->os, "bootstrap mailbox write fail destroy %s\n",
4983 SLI_QNAME[q->type]);
4984 } else if (sli_res_sli_config(sli4->bmbx.virt)) {
4985 ocs_log_err(sli4->os, "bad status destroy %s\n", SLI_QNAME[q->type]);
4986 } else {
4987 res = (void *)((uint8_t *)sli4->bmbx.virt +
4988 offsetof(sli4_cmd_sli_config_t, payload));
4989
4990 if (res->status) {
4991 ocs_log_err(sli4->os, "bad destroy %s status=%#x addl=%#x\n",
4992 SLI_QNAME[q->type],
4993 res->status, res->additional_status);
4994 } else {
4995 rc = 0;
4996 }
4997 }
4998 }
4999 }
5000
5001 if (free_memory) {
5002 ocs_lock_free(&q->lock);
5003
5004 if (ocs_dma_free(sli4->os, &q->dma)) {
5005 ocs_log_err(sli4->os, "%s queue ID %d free failed\n",
5006 SLI_QNAME[q->type], q->id);
5007 rc = -1;
5008 }
5009 }
5010
5011 return rc;
5012 }
5013
5014 int32_t
sli_queue_reset(sli4_t * sli4,sli4_queue_t * q)5015 sli_queue_reset(sli4_t *sli4, sli4_queue_t *q)
5016 {
5017
5018 ocs_lock(&q->lock);
5019
5020 q->index = 0;
5021 q->n_posted = 0;
5022
5023 if (SLI_QTYPE_MQ == q->type) {
5024 q->u.r_idx = 0;
5025 }
5026
5027 if (q->dma.virt != NULL) {
5028 ocs_memset(q->dma.virt, 0, (q->size * q->length));
5029 }
5030
5031 ocs_unlock(&q->lock);
5032
5033 return 0;
5034 }
5035
5036 /**
5037 * @ingroup sli
5038 * @brief Check if the given queue is empty.
5039 *
5040 * @par Description
5041 * If the valid bit of the current entry is unset, the queue is empty.
5042 *
5043 * @param sli4 SLI context.
5044 * @param q Pointer to the queue object.
5045 *
5046 * @return Returns TRUE if empty, or FALSE otherwise.
5047 */
5048 int32_t
sli_queue_is_empty(sli4_t * sli4,sli4_queue_t * q)5049 sli_queue_is_empty(sli4_t *sli4, sli4_queue_t *q)
5050 {
5051 int32_t rc = TRUE;
5052 uint8_t *qe = q->dma.virt;
5053
5054 ocs_lock(&q->lock);
5055
5056 ocs_dma_sync(&q->dma, OCS_DMASYNC_POSTREAD);
5057
5058 qe += q->index * q->size;
5059
5060 rc = !sli_queue_entry_is_valid(q, qe, FALSE);
5061
5062 ocs_unlock(&q->lock);
5063
5064 return rc;
5065 }
5066
5067 /**
5068 * @ingroup sli
5069 * @brief Arm an EQ.
5070 *
5071 * @param sli4 SLI context.
5072 * @param q Pointer to queue object.
5073 * @param arm If TRUE, arm the EQ.
5074 *
5075 * @return Returns 0 on success, or non-zero otherwise.
5076 */
5077 int32_t
sli_queue_eq_arm(sli4_t * sli4,sli4_queue_t * q,uint8_t arm)5078 sli_queue_eq_arm(sli4_t *sli4, sli4_queue_t *q, uint8_t arm)
5079 {
5080 uint32_t val = 0;
5081
5082 ocs_lock(&q->lock);
5083 if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7)
5084 val = sli_iftype6_eq_doorbell(q->n_posted, q->id, arm);
5085 else
5086 val = sli_eq_doorbell(q->n_posted, q->id, arm);
5087
5088 ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val);
5089 q->n_posted = 0;
5090 ocs_unlock(&q->lock);
5091
5092 return 0;
5093 }
5094
5095 /**
5096 * @ingroup sli
5097 * @brief Arm a queue.
5098 *
5099 * @param sli4 SLI context.
5100 * @param q Pointer to queue object.
5101 * @param arm If TRUE, arm the queue.
5102 *
5103 * @return Returns 0 on success, or non-zero otherwise.
5104 */
5105 int32_t
sli_queue_arm(sli4_t * sli4,sli4_queue_t * q,uint8_t arm)5106 sli_queue_arm(sli4_t *sli4, sli4_queue_t *q, uint8_t arm)
5107 {
5108 uint32_t val = 0;
5109
5110 ocs_lock(&q->lock);
5111
5112 switch (q->type) {
5113 case SLI_QTYPE_EQ:
5114 if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7)
5115 val = sli_iftype6_eq_doorbell(q->n_posted, q->id, arm);
5116 else
5117 val = sli_eq_doorbell(q->n_posted, q->id, arm);
5118 ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val);
5119 q->n_posted = 0;
5120 break;
5121 case SLI_QTYPE_CQ:
5122 if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7)
5123 val = sli_iftype6_cq_doorbell(q->n_posted, q->id, arm);
5124 else
5125 val = sli_cq_doorbell(q->n_posted, q->id, arm);
5126 ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val);
5127 q->n_posted = 0;
5128 break;
5129 default:
5130 ocs_log_test(sli4->os, "should only be used for EQ/CQ, not %s\n",
5131 SLI_QNAME[q->type]);
5132 }
5133
5134 ocs_unlock(&q->lock);
5135
5136 return 0;
5137 }
5138
5139 /**
5140 * @ingroup sli
5141 * @brief Write an entry to the queue object.
5142 *
5143 * Note: Assumes the q->lock will be locked and released by the caller.
5144 *
5145 * @param sli4 SLI context.
5146 * @param q Pointer to the queue object.
5147 * @param entry Pointer to the entry contents.
5148 *
5149 * @return Returns queue index on success, or negative error value otherwise.
5150 */
5151 int32_t
_sli_queue_write(sli4_t * sli4,sli4_queue_t * q,uint8_t * entry)5152 _sli_queue_write(sli4_t *sli4, sli4_queue_t *q, uint8_t *entry)
5153 {
5154 int32_t rc = 0;
5155 uint8_t *qe = q->dma.virt;
5156 uint32_t qindex;
5157
5158 qindex = q->index;
5159 qe += q->index * q->size;
5160
5161 if (entry) {
5162 if ((SLI_QTYPE_WQ == q->type) && sli4->config.perf_wq_id_association) {
5163 sli_set_wq_id_association(entry, q->id);
5164 }
5165 #if defined(OCS_INCLUDE_DEBUG)
5166 switch (q->type) {
5167 case SLI_QTYPE_WQ: {
5168 ocs_dump32(OCS_DEBUG_ENABLE_WQ_DUMP, sli4->os, "wqe", entry, q->size);
5169 break;
5170
5171 }
5172 case SLI_QTYPE_MQ:
5173 /* Note: we don't really need to dump the whole
5174 * 256 bytes, just do 64 */
5175 ocs_dump32(OCS_DEBUG_ENABLE_MQ_DUMP, sli4->os, "mqe outbound", entry, 64);
5176 break;
5177
5178 default:
5179 break;
5180 }
5181 #endif
5182 ocs_memcpy(qe, entry, q->size);
5183 q->n_posted = 1;
5184 }
5185
5186 ocs_dma_sync(&q->dma, OCS_DMASYNC_PREWRITE);
5187
5188 rc = sli_queue_doorbell(sli4, q);
5189
5190 q->index = (q->index + q->n_posted) & (q->length - 1);
5191 q->n_posted = 0;
5192
5193 if (rc < 0) {
5194 /* failure */
5195 return rc;
5196 } else if (rc > 0) {
5197 /* failure, but we need to return a negative value on failure */
5198 return -rc;
5199 } else {
5200 return qindex;
5201 }
5202 }
5203
5204 /**
5205 * @ingroup sli
5206 * @brief Write an entry to the queue object.
5207 *
5208 * Note: Assumes the q->lock will be locked and released by the caller.
5209 *
5210 * @param sli4 SLI context.
5211 * @param q Pointer to the queue object.
5212 * @param entry Pointer to the entry contents.
5213 *
5214 * @return Returns queue index on success, or negative error value otherwise.
5215 */
5216 int32_t
sli_queue_write(sli4_t * sli4,sli4_queue_t * q,uint8_t * entry)5217 sli_queue_write(sli4_t *sli4, sli4_queue_t *q, uint8_t *entry)
5218 {
5219 int32_t rc;
5220
5221 ocs_lock(&q->lock);
5222 rc = _sli_queue_write(sli4, q, entry);
5223 ocs_unlock(&q->lock);
5224
5225 return rc;
5226 }
5227
5228 /**
5229 * @brief Check if the current queue entry is valid.
5230 *
5231 * @param q Pointer to the queue object.
5232 * @param qe Pointer to the queue entry.
5233 * @param clear Boolean to clear valid bit.
5234 *
5235 * @return Returns TRUE if the entry is valid, or FALSE otherwise.
5236 */
5237 static uint8_t
sli_queue_entry_is_valid(sli4_queue_t * q,uint8_t * qe,uint8_t clear)5238 sli_queue_entry_is_valid(sli4_queue_t *q, uint8_t *qe, uint8_t clear)
5239 {
5240 uint8_t valid = FALSE;
5241 uint8_t valid_bit_set = 0;
5242
5243 switch (q->type) {
5244 case SLI_QTYPE_EQ:
5245 valid = (((sli4_eqe_t *)qe)->vld == q->phase) ? 1 : 0;
5246 if (valid && clear) {
5247 ((sli4_eqe_t *)qe)->vld = 0;
5248 }
5249 break;
5250 case SLI_QTYPE_CQ:
5251 /*
5252 * For both MCQE and WCQE/RCQE, the valid bit
5253 * is bit 31 of dword 3 (0 based)
5254 */
5255 valid_bit_set = (qe[15] & 0x80) != 0;
5256 if (valid_bit_set == q->phase)
5257 valid = 1;
5258
5259 if (valid & clear) {
5260 qe[15] &= ~0x80;
5261 }
5262 break;
5263 case SLI_QTYPE_MQ:
5264 valid = q->index != q->u.r_idx;
5265 break;
5266 case SLI_QTYPE_RQ:
5267 valid = TRUE;
5268 clear = FALSE;
5269 break;
5270 default:
5271 ocs_log_test(NULL, "doesn't handle type=%#x\n", q->type);
5272 }
5273
5274 if (clear) {
5275
5276 ocs_dma_sync(&q->dma, OCS_DMASYNC_PREWRITE);
5277 }
5278
5279 return valid;
5280 }
5281
5282 /**
5283 * @ingroup sli
5284 * @brief Read an entry from the queue object.
5285 *
5286 * @param sli4 SLI context.
5287 * @param q Pointer to the queue object.
5288 * @param entry Destination pointer for the queue entry contents.
5289 *
5290 * @return Returns 0 on success, or non-zero otherwise.
5291 */
5292 int32_t
sli_queue_read(sli4_t * sli4,sli4_queue_t * q,uint8_t * entry)5293 sli_queue_read(sli4_t *sli4, sli4_queue_t *q, uint8_t *entry)
5294 {
5295 int32_t rc = 0;
5296 uint8_t *qe = q->dma.virt;
5297 uint32_t *qindex = NULL;
5298
5299 uint8_t clear = (SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(sli4)) ? FALSE : TRUE;
5300 if (SLI_QTYPE_MQ == q->type) {
5301 qindex = &q->u.r_idx;
5302 } else {
5303 qindex = &q->index;
5304 }
5305
5306 ocs_lock(&q->lock);
5307
5308 ocs_dma_sync(&q->dma, OCS_DMASYNC_POSTREAD);
5309
5310 qe += *qindex * q->size;
5311
5312 if (!sli_queue_entry_is_valid(q, qe, clear)) {
5313 ocs_unlock(&q->lock);
5314 return -1;
5315 }
5316
5317 if (entry) {
5318 ocs_memcpy(entry, qe, q->size);
5319 #if defined(OCS_INCLUDE_DEBUG)
5320 switch(q->type) {
5321 case SLI_QTYPE_CQ:
5322 ocs_dump32(OCS_DEBUG_ENABLE_CQ_DUMP, sli4->os, "cq", entry, q->size);
5323 break;
5324 case SLI_QTYPE_MQ:
5325 ocs_dump32(OCS_DEBUG_ENABLE_MQ_DUMP, sli4->os, "mq Compl", entry, 64);
5326 break;
5327 case SLI_QTYPE_EQ:
5328 ocs_dump32(OCS_DEBUG_ENABLE_EQ_DUMP, sli4->os, "eq Compl", entry, q->size);
5329 break;
5330 default:
5331 break;
5332 }
5333 #endif
5334 }
5335
5336 switch (q->type) {
5337 case SLI_QTYPE_EQ:
5338 case SLI_QTYPE_CQ:
5339 case SLI_QTYPE_MQ:
5340 *qindex = (*qindex + 1) & (q->length - 1);
5341 if (SLI_QTYPE_MQ != q->type) {
5342 q->n_posted++;
5343 /*
5344 * For prism, the phase value will be used to check the validity of eq/cq entries.
5345 * The value toggles after a complete sweep through the queue.
5346 */
5347 if ((SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(sli4)) && (*qindex == 0)) {
5348 q->phase ^= (uint16_t) 0x1;
5349 }
5350 }
5351 break;
5352 default:
5353 /* reads don't update the index */
5354 break;
5355 }
5356
5357 ocs_unlock(&q->lock);
5358
5359 return rc;
5360 }
5361
5362 int32_t
sli_queue_index(sli4_t * sli4,sli4_queue_t * q)5363 sli_queue_index(sli4_t *sli4, sli4_queue_t *q)
5364 {
5365
5366 if (q) {
5367 return q->index;
5368 } else {
5369 return -1;
5370 }
5371 }
5372
5373 int32_t
sli_queue_poke(sli4_t * sli4,sli4_queue_t * q,uint32_t index,uint8_t * entry)5374 sli_queue_poke(sli4_t *sli4, sli4_queue_t *q, uint32_t index, uint8_t *entry)
5375 {
5376 int32_t rc;
5377
5378 ocs_lock(&q->lock);
5379 rc = _sli_queue_poke(sli4, q, index, entry);
5380 ocs_unlock(&q->lock);
5381
5382 return rc;
5383 }
5384
5385 int32_t
_sli_queue_poke(sli4_t * sli4,sli4_queue_t * q,uint32_t index,uint8_t * entry)5386 _sli_queue_poke(sli4_t *sli4, sli4_queue_t *q, uint32_t index, uint8_t *entry)
5387 {
5388 int32_t rc = 0;
5389 uint8_t *qe = q->dma.virt;
5390
5391 if (index >= q->length) {
5392 return -1;
5393 }
5394
5395 qe += index * q->size;
5396
5397 if (entry) {
5398 ocs_memcpy(qe, entry, q->size);
5399 }
5400
5401 ocs_dma_sync(&q->dma, OCS_DMASYNC_PREWRITE);
5402
5403 return rc;
5404 }
5405
5406 /**
5407 * @ingroup sli
5408 * @brief Allocate SLI Port resources.
5409 *
5410 * @par Description
5411 * Allocate port-related resources, such as VFI, RPI, XRI, and so on.
5412 * Resources are modeled using extents, regardless of whether the underlying
5413 * device implements resource extents. If the device does not implement
5414 * extents, the SLI layer models this as a single (albeit large) extent.
5415 *
5416 * @param sli4 SLI context.
5417 * @param rtype Resource type (for example, RPI or XRI)
5418 * @param rid Allocated resource ID.
5419 * @param index Index into the bitmap.
5420 *
5421 * @return Returns 0 on success, or a non-zero value on failure.
5422 */
5423 int32_t
sli_resource_alloc(sli4_t * sli4,sli4_resource_e rtype,uint32_t * rid,uint32_t * index)5424 sli_resource_alloc(sli4_t *sli4, sli4_resource_e rtype, uint32_t *rid, uint32_t *index)
5425 {
5426 int32_t rc = 0;
5427 uint32_t size;
5428 uint32_t extent_idx;
5429 uint32_t item_idx;
5430 int status;
5431
5432 *rid = UINT32_MAX;
5433 *index = UINT32_MAX;
5434
5435 switch (rtype) {
5436 case SLI_RSRC_FCOE_VFI:
5437 case SLI_RSRC_FCOE_VPI:
5438 case SLI_RSRC_FCOE_RPI:
5439 case SLI_RSRC_FCOE_XRI:
5440 status = ocs_bitmap_find(sli4->config.extent[rtype].use_map,
5441 sli4->config.extent[rtype].map_size);
5442 if (status < 0) {
5443 ocs_log_err(sli4->os, "out of resource %d (alloc=%d)\n",
5444 rtype, sli4->config.extent[rtype].n_alloc);
5445 rc = -1;
5446 break;
5447 } else {
5448 *index = status;
5449 }
5450
5451 size = sli4->config.extent[rtype].size;
5452
5453 extent_idx = *index / size;
5454 item_idx = *index % size;
5455
5456 *rid = sli4->config.extent[rtype].base[extent_idx] + item_idx;
5457
5458 sli4->config.extent[rtype].n_alloc++;
5459 break;
5460 default:
5461 rc = -1;
5462 }
5463
5464 return rc;
5465 }
5466
5467 /**
5468 * @ingroup sli
5469 * @brief Free the SLI Port resources.
5470 *
5471 * @par Description
5472 * Free port-related resources, such as VFI, RPI, XRI, and so. See discussion of
5473 * "extent" usage in sli_resource_alloc.
5474 *
5475 * @param sli4 SLI context.
5476 * @param rtype Resource type (for example, RPI or XRI).
5477 * @param rid Allocated resource ID.
5478 *
5479 * @return Returns 0 on success, or a non-zero value on failure.
5480 */
5481 int32_t
sli_resource_free(sli4_t * sli4,sli4_resource_e rtype,uint32_t rid)5482 sli_resource_free(sli4_t *sli4, sli4_resource_e rtype, uint32_t rid)
5483 {
5484 int32_t rc = -1;
5485 uint32_t x;
5486 uint32_t size, *base;
5487
5488 switch (rtype) {
5489 case SLI_RSRC_FCOE_VFI:
5490 case SLI_RSRC_FCOE_VPI:
5491 case SLI_RSRC_FCOE_RPI:
5492 case SLI_RSRC_FCOE_XRI:
5493 /*
5494 * Figure out which extent contains the resource ID. I.e. find
5495 * the extent such that
5496 * extent->base <= resource ID < extent->base + extent->size
5497 */
5498 base = sli4->config.extent[rtype].base;
5499 size = sli4->config.extent[rtype].size;
5500
5501 /*
5502 * In the case of FW reset, this may be cleared but the force_free path will
5503 * still attempt to free the resource. Prevent a NULL pointer access.
5504 */
5505 if (base != NULL) {
5506 for (x = 0; x < sli4->config.extent[rtype].number; x++) {
5507 if ((rid >= base[x]) && (rid < (base[x] + size))) {
5508 rid -= base[x];
5509 ocs_bitmap_clear(sli4->config.extent[rtype].use_map,
5510 (x * size) + rid);
5511 rc = 0;
5512 break;
5513 }
5514 }
5515 }
5516 break;
5517 default:
5518 ;
5519 }
5520
5521 return rc;
5522 }
5523
5524 int32_t
sli_resource_reset(sli4_t * sli4,sli4_resource_e rtype)5525 sli_resource_reset(sli4_t *sli4, sli4_resource_e rtype)
5526 {
5527 int32_t rc = -1;
5528 uint32_t i;
5529
5530 switch (rtype) {
5531 case SLI_RSRC_FCOE_VFI:
5532 case SLI_RSRC_FCOE_VPI:
5533 case SLI_RSRC_FCOE_RPI:
5534 case SLI_RSRC_FCOE_XRI:
5535 for (i = 0; i < sli4->config.extent[rtype].map_size; i++) {
5536 ocs_bitmap_clear(sli4->config.extent[rtype].use_map, i);
5537 }
5538 rc = 0;
5539 break;
5540 default:
5541 ;
5542 }
5543
5544 return rc;
5545 }
5546
5547 /**
5548 * @ingroup sli
5549 * @brief Parse an EQ entry to retrieve the CQ_ID for this event.
5550 *
5551 * @param sli4 SLI context.
5552 * @param buf Pointer to the EQ entry.
5553 * @param cq_id CQ_ID for this entry (only valid on success).
5554 *
5555 * @return
5556 * - 0 if success.
5557 * - < 0 if error.
5558 * - > 0 if firmware detects EQ overflow.
5559 */
5560 int32_t
sli_eq_parse(sli4_t * sli4,uint8_t * buf,uint16_t * cq_id)5561 sli_eq_parse(sli4_t *sli4, uint8_t *buf, uint16_t *cq_id)
5562 {
5563 sli4_eqe_t *eqe = (void *)buf;
5564 int32_t rc = 0;
5565
5566 if (!sli4 || !buf || !cq_id) {
5567 ocs_log_err(NULL, "bad parameters sli4=%p buf=%p cq_id=%p\n",
5568 sli4, buf, cq_id);
5569 return -1;
5570 }
5571
5572 switch (eqe->major_code) {
5573 case SLI4_MAJOR_CODE_STANDARD:
5574 *cq_id = eqe->resource_id;
5575 break;
5576 case SLI4_MAJOR_CODE_SENTINEL:
5577 ocs_log_debug(sli4->os, "sentinel EQE\n");
5578 rc = 1;
5579 break;
5580 default:
5581 ocs_log_test(sli4->os, "Unsupported EQE: major %x minor %x\n",
5582 eqe->major_code, eqe->minor_code);
5583 rc = -1;
5584 }
5585
5586 return rc;
5587 }
5588
5589 /**
5590 * @ingroup sli
5591 * @brief Parse a CQ entry to retrieve the event type and the associated queue.
5592 *
5593 * @param sli4 SLI context.
5594 * @param cq CQ to process.
5595 * @param cqe Pointer to the CQ entry.
5596 * @param etype CQ event type.
5597 * @param q_id Queue ID associated with this completion message
5598 * (that is, MQ_ID, RQ_ID, and so on).
5599 *
5600 * @return
5601 * - 0 if call completed correctly and CQE status is SUCCESS.
5602 * - -1 if call failed (no CQE status).
5603 * - Other value if call completed correctly and return value is a CQE status value.
5604 */
5605 int32_t
sli_cq_parse(sli4_t * sli4,sli4_queue_t * cq,uint8_t * cqe,sli4_qentry_e * etype,uint16_t * q_id)5606 sli_cq_parse(sli4_t *sli4, sli4_queue_t *cq, uint8_t *cqe, sli4_qentry_e *etype,
5607 uint16_t *q_id)
5608 {
5609 int32_t rc = 0;
5610
5611 if (!sli4 || !cq || !cqe || !etype) {
5612 ocs_log_err(NULL, "bad parameters sli4=%p cq=%p cqe=%p etype=%p q_id=%p\n",
5613 sli4, cq, cqe, etype, q_id);
5614 return -1;
5615 }
5616
5617 if (cq->u.flag.is_mq) {
5618 sli4_mcqe_t *mcqe = (void *)cqe;
5619
5620 if (mcqe->ae) {
5621 *etype = SLI_QENTRY_ASYNC;
5622 } else {
5623 *etype = SLI_QENTRY_MQ;
5624 rc = sli_cqe_mq(mcqe);
5625 }
5626 *q_id = -1;
5627 } else if (SLI4_PORT_TYPE_FC == sli4->port_type) {
5628 rc = sli_fc_cqe_parse(sli4, cq, cqe, etype, q_id);
5629 } else {
5630 ocs_log_test(sli4->os, "implement CQE parsing type = %#x\n",
5631 sli4->port_type);
5632 rc = -1;
5633 }
5634
5635 return rc;
5636 }
5637
5638 /**
5639 * @ingroup sli
5640 * @brief Cause chip to enter an unrecoverable error state.
5641 *
5642 * @par Description
5643 * Cause chip to enter an unrecoverable error state. This is
5644 * used when detecting unexpected FW behavior so FW can be
5645 * hwted from the driver as soon as error is detected.
5646 *
5647 * @param sli4 SLI context.
5648 * @param dump Generate dump as part of reset.
5649 *
5650 * @return Returns 0 if call completed correctly, or -1 if call failed (unsupported chip).
5651 */
sli_raise_ue(sli4_t * sli4,uint8_t dump)5652 int32_t sli_raise_ue(sli4_t *sli4, uint8_t dump)
5653 {
5654 #define FDD 2
5655 if (SLI4_IF_TYPE_BE3_SKH_PF == sli_get_if_type(sli4)) {
5656 switch(sli_get_asic_type(sli4)) {
5657 case SLI4_ASIC_TYPE_BE3: {
5658 sli_reg_write(sli4, SLI4_REG_SW_UE_CSR1, 0xffffffff);
5659 sli_reg_write(sli4, SLI4_REG_SW_UE_CSR2, 0);
5660 break;
5661 }
5662 case SLI4_ASIC_TYPE_SKYHAWK: {
5663 uint32_t value;
5664 value = ocs_config_read32(sli4->os, SLI4_SW_UE_REG);
5665 ocs_config_write32(sli4->os, SLI4_SW_UE_REG, (value | (1U << 24)));
5666 break;
5667 }
5668 default:
5669 ocs_log_test(sli4->os, "invalid asic type %d\n", sli_get_asic_type(sli4));
5670 return -1;
5671 }
5672 } else if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(sli4)) ||
5673 (SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(sli4))) {
5674 if (FDD == dump) {
5675 sli_reg_write(sli4, SLI4_REG_SLIPORT_CONTROL, SLI4_SLIPORT_CONTROL_FDD | SLI4_SLIPORT_CONTROL_IP);
5676 } else {
5677 uint32_t value = SLI4_PHYDEV_CONTROL_FRST;
5678 if (dump == 1) {
5679 value |= SLI4_PHYDEV_CONTROL_DD;
5680 }
5681 sli_reg_write(sli4, SLI4_REG_PHYSDEV_CONTROL, value);
5682 }
5683 } else {
5684 ocs_log_test(sli4->os, "invalid iftype=%d\n", sli_get_if_type(sli4));
5685 return -1;
5686 }
5687 return 0;
5688 }
5689
5690 /**
5691 * @ingroup sli
5692 * @brief Read the SLIPORT_STATUS register to check if a dump is present.
5693 *
5694 * @param sli4 SLI context.
5695 *
5696 * @return Returns 1 if the chip is ready, or 0 if the chip is not ready, 2 if fdp is present.
5697 */
sli_dump_is_ready(sli4_t * sli4)5698 int32_t sli_dump_is_ready(sli4_t *sli4)
5699 {
5700 int32_t rc = 0;
5701 uint32_t port_val;
5702 uint32_t bmbx_val;
5703 uint32_t uerr_lo;
5704 uint32_t uerr_hi;
5705 uint32_t uerr_mask_lo;
5706 uint32_t uerr_mask_hi;
5707
5708 if (SLI4_IF_TYPE_BE3_SKH_PF == sli_get_if_type(sli4)) {
5709 /* for iftype=0, dump ready when UE is encountered */
5710 uerr_lo = sli_reg_read(sli4, SLI4_REG_UERR_STATUS_LO);
5711 uerr_hi = sli_reg_read(sli4, SLI4_REG_UERR_STATUS_HI);
5712 uerr_mask_lo = sli_reg_read(sli4, SLI4_REG_UERR_MASK_LO);
5713 uerr_mask_hi = sli_reg_read(sli4, SLI4_REG_UERR_MASK_HI);
5714 if ((uerr_lo & ~uerr_mask_lo) || (uerr_hi & ~uerr_mask_hi)) {
5715 rc = 1;
5716 }
5717
5718 } else if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(sli4)) ||
5719 (SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(sli4))) {
5720 /*
5721 * Ensure that the port is ready AND the mailbox is
5722 * ready before signaling that the dump is ready to go.
5723 */
5724 port_val = sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS);
5725 bmbx_val = sli_reg_read(sli4, SLI4_REG_BMBX);
5726
5727 if ((bmbx_val & SLI4_BMBX_RDY) &&
5728 SLI4_PORT_STATUS_READY(port_val)) {
5729 if(SLI4_PORT_STATUS_DUMP_PRESENT(port_val)) {
5730 rc = 1;
5731 }else if( SLI4_PORT_STATUS_FDP_PRESENT(port_val)) {
5732 rc = 2;
5733 }
5734 }
5735 } else {
5736 ocs_log_test(sli4->os, "invalid iftype=%d\n", sli_get_if_type(sli4));
5737 return -1;
5738 }
5739 return rc;
5740 }
5741
5742 /**
5743 * @ingroup sli
5744 * @brief Read the SLIPORT_STATUS register to check if a dump is present.
5745 *
5746 * @param sli4 SLI context.
5747 *
5748 * @return
5749 * - 0 if call completed correctly and no dump is present.
5750 * - 1 if call completed and dump is present.
5751 * - -1 if call failed (unsupported chip).
5752 */
sli_dump_is_present(sli4_t * sli4)5753 int32_t sli_dump_is_present(sli4_t *sli4)
5754 {
5755 uint32_t val;
5756 uint32_t ready;
5757
5758 if ((SLI4_IF_TYPE_LANCER_FC_ETH != sli_get_if_type(sli4)) &&
5759 (SLI4_IF_TYPE_LANCER_G7 != sli_get_if_type(sli4))) {
5760 ocs_log_test(sli4->os, "Function only supported for I/F type 2");
5761 return -1;
5762 }
5763
5764 /* If the chip is not ready, then there cannot be a dump */
5765 ready = sli_wait_for_fw_ready(sli4, SLI4_INIT_PORT_DELAY_US);
5766 if (!ready) {
5767 return 0;
5768 }
5769
5770 val = sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS);
5771 if (UINT32_MAX == val) {
5772 ocs_log_err(sli4->os, "error reading SLIPORT_STATUS\n");
5773 return -1;
5774 } else {
5775 return ((val & SLI4_PORT_STATUS_DIP) ? 1 : 0);
5776 }
5777 }
5778
5779 /**
5780 * @ingroup sli
5781 * @brief Read the SLIPORT_STATUS register to check if the reset required is set.
5782 *
5783 * @param sli4 SLI context.
5784 *
5785 * @return
5786 * - 0 if call completed correctly and reset is not required.
5787 * - 1 if call completed and reset is required.
5788 * - -1 if call failed.
5789 */
sli_reset_required(sli4_t * sli4)5790 int32_t sli_reset_required(sli4_t *sli4)
5791 {
5792 uint32_t val;
5793
5794 if (SLI4_IF_TYPE_BE3_SKH_PF == sli_get_if_type(sli4)) {
5795 ocs_log_test(sli4->os, "reset required N/A for iftype 0\n");
5796 return 0;
5797 }
5798
5799 val = sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS);
5800 if (UINT32_MAX == val) {
5801 ocs_log_err(sli4->os, "error reading SLIPORT_STATUS\n");
5802 return -1;
5803 } else {
5804 return ((val & SLI4_PORT_STATUS_RN) ? 1 : 0);
5805 }
5806 }
5807
5808 /**
5809 * @ingroup sli
5810 * @brief Read the SLIPORT_SEMAPHORE and SLIPORT_STATUS registers to check if
5811 * the port status indicates that a FW error has occurred.
5812 *
5813 * @param sli4 SLI context.
5814 *
5815 * @return
5816 * - 0 if call completed correctly and no FW error occurred.
5817 * - > 0 which indicates that a FW error has occurred.
5818 * - -1 if call failed.
5819 */
sli_fw_error_status(sli4_t * sli4)5820 int32_t sli_fw_error_status(sli4_t *sli4)
5821 {
5822 uint32_t sliport_semaphore;
5823 int32_t rc = 0;
5824
5825 sliport_semaphore = sli_reg_read(sli4, SLI4_REG_SLIPORT_SEMAPHORE);
5826 if (UINT32_MAX == sliport_semaphore) {
5827 ocs_log_err(sli4->os, "error reading SLIPORT_SEMAPHORE register\n");
5828 return 1;
5829 }
5830 rc = (SLI4_PORT_SEMAPHORE_IN_ERR(sliport_semaphore) ? 1 : 0);
5831
5832 if (rc == 0) {
5833 if (SLI4_IF_TYPE_BE3_SKH_PF == sli4->if_type ||
5834 (SLI4_IF_TYPE_BE3_SKH_VF == sli4->if_type)) {
5835 uint32_t uerr_mask_lo, uerr_mask_hi;
5836 uint32_t uerr_status_lo, uerr_status_hi;
5837
5838 uerr_mask_lo = sli_reg_read(sli4, SLI4_REG_UERR_MASK_LO);
5839 uerr_mask_hi = sli_reg_read(sli4, SLI4_REG_UERR_MASK_HI);
5840 uerr_status_lo = sli_reg_read(sli4, SLI4_REG_UERR_STATUS_LO);
5841 uerr_status_hi = sli_reg_read(sli4, SLI4_REG_UERR_STATUS_HI);
5842 if ((uerr_mask_lo & uerr_status_lo) != 0 ||
5843 (uerr_mask_hi & uerr_status_hi) != 0) {
5844 rc = 1;
5845 }
5846 } else if (SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type ||
5847 SLI4_IF_TYPE_LANCER_G7 == sli4->if_type) {
5848 uint32_t sliport_status;
5849
5850 sliport_status = sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS);
5851 rc = (SLI4_PORT_STATUS_ERROR(sliport_status) ? 1 : 0);
5852 }
5853 }
5854 return rc;
5855 }
5856
5857 /**
5858 * @ingroup sli
5859 * @brief Determine if the chip FW is in a ready state
5860 *
5861 * @param sli4 SLI context.
5862 *
5863 * @return
5864 * - 0 if call completed correctly and FW is not ready.
5865 * - 1 if call completed correctly and FW is ready.
5866 * - -1 if call failed.
5867 */
5868 int32_t
sli_fw_ready(sli4_t * sli4)5869 sli_fw_ready(sli4_t *sli4)
5870 {
5871 uint32_t val;
5872 int32_t rc = -1;
5873
5874 /*
5875 * Is firmware ready for operation? Check needed depends on IF_TYPE
5876 */
5877 if (SLI4_IF_TYPE_BE3_SKH_PF == sli4->if_type ||
5878 SLI4_IF_TYPE_BE3_SKH_VF == sli4->if_type) {
5879 val = sli_reg_read(sli4, SLI4_REG_SLIPORT_SEMAPHORE);
5880 rc = ((SLI4_PORT_SEMAPHORE_STATUS_POST_READY ==
5881 SLI4_PORT_SEMAPHORE_PORT(val)) &&
5882 (!SLI4_PORT_SEMAPHORE_IN_ERR(val)) ? 1 : 0);
5883 } else if (SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type ||
5884 SLI4_IF_TYPE_LANCER_G7 == sli4->if_type) {
5885 val = sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS);
5886 rc = (SLI4_PORT_STATUS_READY(val) ? 1 : 0);
5887 }
5888 return rc;
5889 }
5890
5891 /**
5892 * @ingroup sli
5893 * @brief Determine if the link can be configured
5894 *
5895 * @param sli4 SLI context.
5896 *
5897 * @return
5898 * - 0 if link is not configurable.
5899 * - 1 if link is configurable.
5900 */
sli_link_is_configurable(sli4_t * sli)5901 int32_t sli_link_is_configurable(sli4_t *sli)
5902 {
5903 int32_t rc = 0;
5904 /*
5905 * Link config works on: Skyhawk and Lancer
5906 * Link config does not work on: LancerG6
5907 */
5908
5909 switch (sli_get_asic_type(sli)) {
5910 case SLI4_ASIC_TYPE_SKYHAWK:
5911 case SLI4_ASIC_TYPE_LANCER:
5912 case SLI4_ASIC_TYPE_CORSAIR:
5913 rc = 1;
5914 break;
5915 case SLI4_ASIC_TYPE_LANCERG6:
5916 case SLI4_ASIC_TYPE_LANCERG7:
5917 case SLI4_ASIC_TYPE_BE3:
5918 default:
5919 rc = 0;
5920 break;
5921 }
5922
5923 return rc;
5924
5925 }
5926
5927 /* vim: set noexpandtab textwidth=120: */
5928
5929 /**
5930 * @ingroup sli_fc
5931 * @brief Write an FCOE_WQ_CREATE command.
5932 *
5933 * @param sli4 SLI context.
5934 * @param buf Destination buffer for the command.
5935 * @param size Buffer size, in bytes.
5936 * @param qmem DMA memory for the queue.
5937 * @param cq_id Associated CQ_ID.
5938 * @param ulp The ULP to bind
5939 *
5940 * @note This creates a Version 0 message.
5941 *
5942 * @return Returns the number of bytes written.
5943 */
5944 int32_t
sli_cmd_fcoe_wq_create(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * qmem,uint16_t cq_id,uint16_t ulp)5945 sli_cmd_fcoe_wq_create(sli4_t *sli4, void *buf, size_t size,
5946 ocs_dma_t *qmem, uint16_t cq_id, uint16_t ulp)
5947 {
5948 sli4_req_fcoe_wq_create_t *wq = NULL;
5949 uint32_t sli_config_off = 0;
5950 uint32_t p;
5951 uintptr_t addr;
5952
5953 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
5954 uint32_t payload_size;
5955
5956 /* Payload length must accommodate both request and response */
5957 payload_size = max(sizeof(sli4_req_fcoe_wq_create_t),
5958 sizeof(sli4_res_common_create_queue_t));
5959
5960 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
5961 NULL);
5962 }
5963 wq = (sli4_req_fcoe_wq_create_t *)((uint8_t *)buf + sli_config_off);
5964
5965 wq->hdr.opcode = SLI4_OPC_FCOE_WQ_CREATE;
5966 wq->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
5967 wq->hdr.request_length = sizeof(sli4_req_fcoe_wq_create_t) -
5968 sizeof(sli4_req_hdr_t);
5969 /* valid values for number of pages: 1-4 (sec 4.5.1) */
5970 wq->num_pages = sli_page_count(qmem->size, SLI_PAGE_SIZE);
5971 if (!wq->num_pages || (wq->num_pages > SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES)) {
5972 return 0;
5973 }
5974
5975 wq->cq_id = cq_id;
5976
5977 if (sli4->config.dual_ulp_capable) {
5978 wq->dua = 1;
5979 wq->bqu = 1;
5980 wq->ulp = ulp;
5981 }
5982
5983 for (p = 0, addr = qmem->phys;
5984 p < wq->num_pages;
5985 p++, addr += SLI_PAGE_SIZE) {
5986 wq->page_physical_address[p].low = ocs_addr32_lo(addr);
5987 wq->page_physical_address[p].high = ocs_addr32_hi(addr);
5988 }
5989
5990 return(sli_config_off + sizeof(sli4_req_fcoe_wq_create_t));
5991 }
5992
5993 /**
5994 * @ingroup sli_fc
5995 * @brief Write an FCOE_WQ_CREATE_V1 command.
5996 *
5997 * @param sli4 SLI context.
5998 * @param buf Destination buffer for the command.
5999 * @param size Buffer size, in bytes.
6000 * @param qmem DMA memory for the queue.
6001 * @param cq_id Associated CQ_ID.
6002 * @param ignored This parameter carries the ULP for WQ (ignored for V1)
6003
6004 *
6005 * @return Returns the number of bytes written.
6006 */
6007 int32_t
sli_cmd_fcoe_wq_create_v1(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * qmem,uint16_t cq_id,uint16_t ignored)6008 sli_cmd_fcoe_wq_create_v1(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *qmem,
6009 uint16_t cq_id, uint16_t ignored)
6010 {
6011 sli4_req_fcoe_wq_create_v1_t *wq = NULL;
6012 uint32_t sli_config_off = 0;
6013 uint32_t p;
6014 uintptr_t addr;
6015 uint32_t page_size = 0;
6016 uint32_t page_bytes = 0;
6017 uint32_t n_wqe = 0;
6018
6019 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
6020 uint32_t payload_size;
6021
6022 /* Payload length must accommodate both request and response */
6023 payload_size = max(sizeof(sli4_req_fcoe_wq_create_v1_t),
6024 sizeof(sli4_res_common_create_queue_t));
6025
6026 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
6027 NULL);
6028 }
6029 wq = (sli4_req_fcoe_wq_create_v1_t *)((uint8_t *)buf + sli_config_off);
6030
6031 wq->hdr.opcode = SLI4_OPC_FCOE_WQ_CREATE;
6032 wq->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6033 wq->hdr.request_length = sizeof(sli4_req_fcoe_wq_create_v1_t) -
6034 sizeof(sli4_req_hdr_t);
6035 wq->hdr.version = 1;
6036
6037 n_wqe = qmem->size / sli4->config.wqe_size;
6038
6039 /* This heuristic to determine the page size is simplistic
6040 * but could be made more sophisticated
6041 */
6042 switch (qmem->size) {
6043 case 4096:
6044 case 8192:
6045 case 16384:
6046 case 32768:
6047 page_size = 1;
6048 break;
6049 case 65536:
6050 page_size = 2;
6051 break;
6052 case 131072:
6053 page_size = 4;
6054 break;
6055 case 262144:
6056 page_size = 8;
6057 break;
6058 case 524288:
6059 page_size = 10;
6060 break;
6061 default:
6062 return 0;
6063 }
6064 page_bytes = page_size * SLI_PAGE_SIZE;
6065
6066 /* valid values for number of pages: 1-8 */
6067 wq->num_pages = sli_page_count(qmem->size, page_bytes);
6068 if (!wq->num_pages || (wq->num_pages > SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES)) {
6069 return 0;
6070 }
6071
6072 wq->cq_id = cq_id;
6073
6074 wq->page_size = page_size;
6075
6076 if (sli4->config.wqe_size == SLI4_WQE_EXT_BYTES) {
6077 wq->wqe_size = SLI4_WQE_EXT_SIZE;
6078 } else {
6079 wq->wqe_size = SLI4_WQE_SIZE;
6080 }
6081
6082 wq->wqe_count = n_wqe;
6083
6084 for (p = 0, addr = qmem->phys;
6085 p < wq->num_pages;
6086 p++, addr += page_bytes) {
6087 wq->page_physical_address[p].low = ocs_addr32_lo(addr);
6088 wq->page_physical_address[p].high = ocs_addr32_hi(addr);
6089 }
6090
6091 return(sli_config_off + sizeof(sli4_req_fcoe_wq_create_v1_t));
6092 }
6093
6094 /**
6095 * @ingroup sli_fc
6096 * @brief Write an FCOE_WQ_DESTROY command.
6097 *
6098 * @param sli4 SLI context.
6099 * @param buf Destination buffer for the command.
6100 * @param size Buffer size, in bytes.
6101 * @param wq_id WQ_ID.
6102 *
6103 * @return Returns the number of bytes written.
6104 */
6105 int32_t
sli_cmd_fcoe_wq_destroy(sli4_t * sli4,void * buf,size_t size,uint16_t wq_id)6106 sli_cmd_fcoe_wq_destroy(sli4_t *sli4, void *buf, size_t size, uint16_t wq_id)
6107 {
6108 sli4_req_fcoe_wq_destroy_t *wq = NULL;
6109 uint32_t sli_config_off = 0;
6110
6111 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
6112 uint32_t payload_size;
6113
6114 /* Payload length must accommodate both request and response */
6115 payload_size = max(sizeof(sli4_req_fcoe_wq_destroy_t),
6116 sizeof(sli4_res_hdr_t));
6117
6118 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
6119 NULL);
6120 }
6121 wq = (sli4_req_fcoe_wq_destroy_t *)((uint8_t *)buf + sli_config_off);
6122
6123 wq->hdr.opcode = SLI4_OPC_FCOE_WQ_DESTROY;
6124 wq->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6125 wq->hdr.request_length = sizeof(sli4_req_fcoe_wq_destroy_t) -
6126 sizeof(sli4_req_hdr_t);
6127
6128 wq->wq_id = wq_id;
6129
6130 return(sli_config_off + sizeof(sli4_req_fcoe_wq_destroy_t));
6131 }
6132
6133 /**
6134 * @ingroup sli_fc
6135 * @brief Write an FCOE_POST_SGL_PAGES command.
6136 *
6137 * @param sli4 SLI context.
6138 * @param buf Destination buffer for the command.
6139 * @param size Buffer size, in bytes.
6140 * @param xri starting XRI
6141 * @param xri_count XRI
6142 * @param page0 First SGL memory page.
6143 * @param page1 Second SGL memory page (optional).
6144 * @param dma DMA buffer for non-embedded mailbox command (options)
6145 *
6146 * if non-embedded mbx command is used, dma buffer must be at least (32 + xri_count*16) in length
6147 *
6148 * @return Returns the number of bytes written.
6149 */
6150 int32_t
sli_cmd_fcoe_post_sgl_pages(sli4_t * sli4,void * buf,size_t size,uint16_t xri,uint32_t xri_count,ocs_dma_t * page0[],ocs_dma_t * page1[],ocs_dma_t * dma)6151 sli_cmd_fcoe_post_sgl_pages(sli4_t *sli4, void *buf, size_t size,
6152 uint16_t xri, uint32_t xri_count, ocs_dma_t *page0[], ocs_dma_t *page1[], ocs_dma_t *dma)
6153 {
6154 sli4_req_fcoe_post_sgl_pages_t *post = NULL;
6155 uint32_t sli_config_off = 0;
6156 uint32_t i;
6157
6158 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
6159 uint32_t payload_size;
6160
6161 /* Payload length must accommodate both request and response */
6162 payload_size = max(sizeof(sli4_req_fcoe_post_sgl_pages_t),
6163 sizeof(sli4_res_hdr_t));
6164
6165 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
6166 dma);
6167 }
6168 if (dma) {
6169 post = dma->virt;
6170 ocs_memset(post, 0, dma->size);
6171 } else {
6172 post = (sli4_req_fcoe_post_sgl_pages_t *)((uint8_t *)buf + sli_config_off);
6173 }
6174
6175 post->hdr.opcode = SLI4_OPC_FCOE_POST_SGL_PAGES;
6176 post->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6177 /* payload size calculation
6178 * 4 = xri_start + xri_count
6179 * xri_count = # of XRI's registered
6180 * sizeof(uint64_t) = physical address size
6181 * 2 = # of physical addresses per page set
6182 */
6183 post->hdr.request_length = 4 + (xri_count * (sizeof(uint64_t) * 2));
6184
6185 post->xri_start = xri;
6186 post->xri_count = xri_count;
6187
6188 for (i = 0; i < xri_count; i++) {
6189 post->page_set[i].page0_low = ocs_addr32_lo(page0[i]->phys);
6190 post->page_set[i].page0_high = ocs_addr32_hi(page0[i]->phys);
6191 }
6192
6193 if (page1) {
6194 for (i = 0; i < xri_count; i++) {
6195 post->page_set[i].page1_low = ocs_addr32_lo(page1[i]->phys);
6196 post->page_set[i].page1_high = ocs_addr32_hi(page1[i]->phys);
6197 }
6198 }
6199
6200 return dma ? sli_config_off : (sli_config_off + sizeof(sli4_req_fcoe_post_sgl_pages_t));
6201 }
6202
6203 /**
6204 * @ingroup sli_fc
6205 * @brief Write an FCOE_RQ_CREATE command.
6206 *
6207 * @param sli4 SLI context.
6208 * @param buf Destination buffer for the command.
6209 * @param size Buffer size, in bytes.
6210 * @param qmem DMA memory for the queue.
6211 * @param cq_id Associated CQ_ID.
6212 * @param ulp This parameter carries the ULP for the RQ
6213 * @param buffer_size Buffer size pointed to by each RQE.
6214 *
6215 * @note This creates a Version 0 message.
6216 *
6217 * @return Returns the number of bytes written.
6218 */
6219 int32_t
sli_cmd_fcoe_rq_create(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * qmem,uint16_t cq_id,uint16_t ulp,uint16_t buffer_size)6220 sli_cmd_fcoe_rq_create(sli4_t *sli4, void *buf, size_t size,
6221 ocs_dma_t *qmem, uint16_t cq_id, uint16_t ulp, uint16_t buffer_size)
6222 {
6223 sli4_req_fcoe_rq_create_t *rq = NULL;
6224 uint32_t sli_config_off = 0;
6225 uint32_t p;
6226 uintptr_t addr;
6227
6228 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
6229 uint32_t payload_size;
6230
6231 /* Payload length must accommodate both request and response */
6232 payload_size = max(sizeof(sli4_req_fcoe_rq_create_t),
6233 sizeof(sli4_res_common_create_queue_t));
6234
6235 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
6236 NULL);
6237 }
6238 rq = (sli4_req_fcoe_rq_create_t *)((uint8_t *)buf + sli_config_off);
6239
6240 rq->hdr.opcode = SLI4_OPC_FCOE_RQ_CREATE;
6241 rq->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6242 rq->hdr.request_length = sizeof(sli4_req_fcoe_rq_create_t) -
6243 sizeof(sli4_req_hdr_t);
6244 /* valid values for number of pages: 1-8 (sec 4.5.6) */
6245 rq->num_pages = sli_page_count(qmem->size, SLI_PAGE_SIZE);
6246 if (!rq->num_pages || (rq->num_pages > SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES)) {
6247 ocs_log_test(sli4->os, "num_pages %d not valid\n", rq->num_pages);
6248 return 0;
6249 }
6250
6251 /*
6252 * RQE count is the log base 2 of the total number of entries
6253 */
6254 rq->rqe_count = ocs_lg2(qmem->size / SLI4_FCOE_RQE_SIZE);
6255
6256 if ((buffer_size < SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE) ||
6257 (buffer_size > SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE)) {
6258 ocs_log_err(sli4->os, "buffer_size %d out of range (%d-%d)\n",
6259 buffer_size,
6260 SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE,
6261 SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE);
6262 return -1;
6263 }
6264 rq->buffer_size = buffer_size;
6265
6266 rq->cq_id = cq_id;
6267
6268 if (sli4->config.dual_ulp_capable) {
6269 rq->dua = 1;
6270 rq->bqu = 1;
6271 rq->ulp = ulp;
6272 }
6273
6274 for (p = 0, addr = qmem->phys;
6275 p < rq->num_pages;
6276 p++, addr += SLI_PAGE_SIZE) {
6277 rq->page_physical_address[p].low = ocs_addr32_lo(addr);
6278 rq->page_physical_address[p].high = ocs_addr32_hi(addr);
6279 }
6280
6281 return(sli_config_off + sizeof(sli4_req_fcoe_rq_create_t));
6282 }
6283
6284 /**
6285 * @ingroup sli_fc
6286 * @brief Write an FCOE_RQ_CREATE_V1 command.
6287 *
6288 * @param sli4 SLI context.
6289 * @param buf Destination buffer for the command.
6290 * @param size Buffer size, in bytes.
6291 * @param qmem DMA memory for the queue.
6292 * @param cq_id Associated CQ_ID.
6293 * @param ulp This parameter carries the ULP for RQ (ignored for V1)
6294 * @param buffer_size Buffer size pointed to by each RQE.
6295 *
6296 * @note This creates a Version 0 message
6297 *
6298 * @return Returns the number of bytes written.
6299 */
6300 int32_t
sli_cmd_fcoe_rq_create_v1(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * qmem,uint16_t cq_id,uint16_t ulp,uint16_t buffer_size)6301 sli_cmd_fcoe_rq_create_v1(sli4_t *sli4, void *buf, size_t size,
6302 ocs_dma_t *qmem, uint16_t cq_id, uint16_t ulp,
6303 uint16_t buffer_size)
6304 {
6305 sli4_req_fcoe_rq_create_v1_t *rq = NULL;
6306 uint32_t sli_config_off = 0;
6307 uint32_t p;
6308 uintptr_t addr;
6309
6310 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
6311 uint32_t payload_size;
6312
6313 /* Payload length must accommodate both request and response */
6314 payload_size = max(sizeof(sli4_req_fcoe_rq_create_v1_t),
6315 sizeof(sli4_res_common_create_queue_t));
6316
6317 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
6318 NULL);
6319 }
6320 rq = (sli4_req_fcoe_rq_create_v1_t *)((uint8_t *)buf + sli_config_off);
6321
6322 rq->hdr.opcode = SLI4_OPC_FCOE_RQ_CREATE;
6323 rq->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6324 rq->hdr.request_length = sizeof(sli4_req_fcoe_rq_create_v1_t) -
6325 sizeof(sli4_req_hdr_t);
6326 rq->hdr.version = 1;
6327
6328 /* Disable "no buffer warnings" to avoid Lancer bug */
6329 rq->dnb = TRUE;
6330
6331 /* valid values for number of pages: 1-8 (sec 4.5.6) */
6332 rq->num_pages = sli_page_count(qmem->size, SLI_PAGE_SIZE);
6333 if (!rq->num_pages || (rq->num_pages > SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES)) {
6334 ocs_log_test(sli4->os, "num_pages %d not valid, max %d\n",
6335 rq->num_pages, SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES);
6336 return 0;
6337 }
6338
6339 /*
6340 * RQE count is the total number of entries (note not lg2(# entries))
6341 */
6342 rq->rqe_count = qmem->size / SLI4_FCOE_RQE_SIZE;
6343
6344 rq->rqe_size = SLI4_FCOE_RQE_SIZE_8;
6345
6346 rq->page_size = SLI4_FCOE_RQ_PAGE_SIZE_4096;
6347
6348 if ((buffer_size < sli4->config.rq_min_buf_size) ||
6349 (buffer_size > sli4->config.rq_max_buf_size)) {
6350 ocs_log_err(sli4->os, "buffer_size %d out of range (%d-%d)\n",
6351 buffer_size,
6352 sli4->config.rq_min_buf_size,
6353 sli4->config.rq_max_buf_size);
6354 return -1;
6355 }
6356 rq->buffer_size = buffer_size;
6357
6358 rq->cq_id = cq_id;
6359
6360 for (p = 0, addr = qmem->phys;
6361 p < rq->num_pages;
6362 p++, addr += SLI_PAGE_SIZE) {
6363 rq->page_physical_address[p].low = ocs_addr32_lo(addr);
6364 rq->page_physical_address[p].high = ocs_addr32_hi(addr);
6365 }
6366
6367 return(sli_config_off + sizeof(sli4_req_fcoe_rq_create_v1_t));
6368 }
6369
6370 /**
6371 * @ingroup sli_fc
6372 * @brief Write an FCOE_RQ_DESTROY command.
6373 *
6374 * @param sli4 SLI context.
6375 * @param buf Destination buffer for the command.
6376 * @param size Buffer size, in bytes.
6377 * @param rq_id RQ_ID.
6378 *
6379 * @return Returns the number of bytes written.
6380 */
6381 int32_t
sli_cmd_fcoe_rq_destroy(sli4_t * sli4,void * buf,size_t size,uint16_t rq_id)6382 sli_cmd_fcoe_rq_destroy(sli4_t *sli4, void *buf, size_t size, uint16_t rq_id)
6383 {
6384 sli4_req_fcoe_rq_destroy_t *rq = NULL;
6385 uint32_t sli_config_off = 0;
6386
6387 if (SLI4_PORT_TYPE_FC == sli4->port_type) {
6388 uint32_t payload_size;
6389
6390 /* Payload length must accommodate both request and response */
6391 payload_size = max(sizeof(sli4_req_fcoe_rq_destroy_t),
6392 sizeof(sli4_res_hdr_t));
6393
6394 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size,
6395 NULL);
6396 }
6397 rq = (sli4_req_fcoe_rq_destroy_t *)((uint8_t *)buf + sli_config_off);
6398
6399 rq->hdr.opcode = SLI4_OPC_FCOE_RQ_DESTROY;
6400 rq->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6401 rq->hdr.request_length = sizeof(sli4_req_fcoe_rq_destroy_t) -
6402 sizeof(sli4_req_hdr_t);
6403
6404 rq->rq_id = rq_id;
6405
6406 return(sli_config_off + sizeof(sli4_req_fcoe_rq_destroy_t));
6407 }
6408
6409 /**
6410 * @ingroup sli_fc
6411 * @brief Write an FCOE_READ_FCF_TABLE command.
6412 *
6413 * @note
6414 * The response of this command exceeds the size of an embedded
6415 * command and requires an external buffer with DMA capability to hold the results.
6416 * The caller should allocate the ocs_dma_t structure / memory.
6417 *
6418 * @param sli4 SLI context.
6419 * @param buf Destination buffer for the command.
6420 * @param size Buffer size, in bytes.
6421 * @param dma Pointer to DMA memory structure. This is allocated by the caller.
6422 * @param index FCF table index to retrieve.
6423 *
6424 * @return Returns the number of bytes written.
6425 */
6426 int32_t
sli_cmd_fcoe_read_fcf_table(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma,uint16_t index)6427 sli_cmd_fcoe_read_fcf_table(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *dma, uint16_t index)
6428 {
6429 sli4_req_fcoe_read_fcf_table_t *read_fcf = NULL;
6430
6431 if (SLI4_PORT_TYPE_FC != sli4->port_type) {
6432 ocs_log_test(sli4->os, "FCOE_READ_FCF_TABLE only supported on FC\n");
6433 return -1;
6434 }
6435
6436 read_fcf = dma->virt;
6437
6438 ocs_memset(read_fcf, 0, sizeof(sli4_req_fcoe_read_fcf_table_t));
6439
6440 read_fcf->hdr.opcode = SLI4_OPC_FCOE_READ_FCF_TABLE;
6441 read_fcf->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6442 read_fcf->hdr.request_length = dma->size -
6443 sizeof(sli4_req_fcoe_read_fcf_table_t);
6444 read_fcf->fcf_index = index;
6445
6446 return sli_cmd_sli_config(sli4, buf, size, 0, dma);
6447 }
6448
6449 /**
6450 * @ingroup sli_fc
6451 * @brief Write an FCOE_POST_HDR_TEMPLATES command.
6452 *
6453 * @param sli4 SLI context.
6454 * @param buf Destination buffer for the command.
6455 * @param size Buffer size, in bytes.
6456 * @param dma Pointer to DMA memory structure. This is allocated by the caller.
6457 * @param rpi Starting RPI index for the header templates.
6458 * @param payload_dma Pointer to DMA memory used to hold larger descriptor counts.
6459 *
6460 * @return Returns the number of bytes written.
6461 */
6462 int32_t
sli_cmd_fcoe_post_hdr_templates(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * dma,uint16_t rpi,ocs_dma_t * payload_dma)6463 sli_cmd_fcoe_post_hdr_templates(sli4_t *sli4, void *buf, size_t size,
6464 ocs_dma_t *dma, uint16_t rpi, ocs_dma_t *payload_dma)
6465 {
6466 sli4_req_fcoe_post_hdr_templates_t *template = NULL;
6467 uint32_t sli_config_off = 0;
6468 uintptr_t phys = 0;
6469 uint32_t i = 0;
6470 uint32_t page_count;
6471 uint32_t payload_size;
6472
6473 page_count = sli_page_count(dma->size, SLI_PAGE_SIZE);
6474
6475 payload_size = sizeof(sli4_req_fcoe_post_hdr_templates_t) +
6476 page_count * sizeof(sli4_physical_page_descriptor_t);
6477
6478 if (page_count > 16) {
6479 /* We can't fit more than 16 descriptors into an embedded mailbox
6480 command, it has to be non-embedded */
6481 if (ocs_dma_alloc(sli4->os, payload_dma, payload_size, 4)) {
6482 ocs_log_err(sli4->os, "mailbox payload memory allocation fail\n");
6483 return 0;
6484 }
6485 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size, payload_dma);
6486 template = (sli4_req_fcoe_post_hdr_templates_t *)payload_dma->virt;
6487 } else {
6488 sli_config_off = sli_cmd_sli_config(sli4, buf, size, payload_size, NULL);
6489 template = (sli4_req_fcoe_post_hdr_templates_t *)((uint8_t *)buf + sli_config_off);
6490 }
6491
6492 if (UINT16_MAX == rpi) {
6493 rpi = sli4->config.extent[SLI_RSRC_FCOE_RPI].base[0];
6494 }
6495
6496 template->hdr.opcode = SLI4_OPC_FCOE_POST_HDR_TEMPLATES;
6497 template->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6498 template->hdr.request_length = sizeof(sli4_req_fcoe_post_hdr_templates_t) -
6499 sizeof(sli4_req_hdr_t);
6500
6501 template->rpi_offset = rpi;
6502 template->page_count = page_count;
6503 phys = dma->phys;
6504 for (i = 0; i < template->page_count; i++) {
6505 template->page_descriptor[i].low = ocs_addr32_lo(phys);
6506 template->page_descriptor[i].high = ocs_addr32_hi(phys);
6507
6508 phys += SLI_PAGE_SIZE;
6509 }
6510
6511 return(sli_config_off + payload_size);
6512 }
6513
6514 int32_t
sli_cmd_fcoe_rediscover_fcf(sli4_t * sli4,void * buf,size_t size,uint16_t index)6515 sli_cmd_fcoe_rediscover_fcf(sli4_t *sli4, void *buf, size_t size, uint16_t index)
6516 {
6517 sli4_req_fcoe_rediscover_fcf_t *redisc = NULL;
6518 uint32_t sli_config_off = 0;
6519
6520 sli_config_off = sli_cmd_sli_config(sli4, buf, size,
6521 sizeof(sli4_req_fcoe_rediscover_fcf_t),
6522 NULL);
6523
6524 redisc = (sli4_req_fcoe_rediscover_fcf_t *)((uint8_t *)buf + sli_config_off);
6525
6526 redisc->hdr.opcode = SLI4_OPC_FCOE_REDISCOVER_FCF;
6527 redisc->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
6528 redisc->hdr.request_length = sizeof(sli4_req_fcoe_rediscover_fcf_t) -
6529 sizeof(sli4_req_hdr_t);
6530
6531 if (index == UINT16_MAX) {
6532 redisc->fcf_count = 0;
6533 } else {
6534 redisc->fcf_count = 1;
6535 redisc->fcf_index[0] = index;
6536 }
6537
6538 return(sli_config_off + sizeof(sli4_req_fcoe_rediscover_fcf_t));
6539 }
6540
6541 /**
6542 * @ingroup sli_fc
6543 * @brief Write an ABORT_WQE work queue entry.
6544 *
6545 * @param sli4 SLI context.
6546 * @param buf Destination buffer for the WQE.
6547 * @param size Buffer size, in bytes.
6548 * @param type Abort type, such as XRI, abort tag, and request tag.
6549 * @param send_abts Boolean to cause the hardware to automatically generate an ABTS.
6550 * @param ids ID of IOs to abort.
6551 * @param mask Mask applied to the ID values to abort.
6552 * @param tag Tag value associated with this abort.
6553 * @param cq_id The id of the completion queue where the WQE response is sent.
6554 * @param dnrx When set to 1, this field indicates that the SLI Port must not return the associated XRI to the SLI
6555 * Port's optimized write XRI pool.
6556 *
6557 * @return Returns 0 on success, or a non-zero value on failure.
6558 */
6559 int32_t
sli_abort_wqe(sli4_t * sli4,void * buf,size_t size,sli4_abort_type_e type,uint32_t send_abts,uint32_t ids,uint32_t mask,uint16_t tag,uint16_t cq_id)6560 sli_abort_wqe(sli4_t *sli4, void *buf, size_t size, sli4_abort_type_e type, uint32_t send_abts,
6561 uint32_t ids, uint32_t mask, uint16_t tag, uint16_t cq_id)
6562 {
6563 sli4_abort_wqe_t *abort = buf;
6564
6565 ocs_memset(buf, 0, size);
6566
6567 switch (type) {
6568 case SLI_ABORT_XRI:
6569 abort->criteria = SLI4_ABORT_CRITERIA_XRI_TAG;
6570 if (mask) {
6571 ocs_log_warn(sli4->os, "warning non-zero mask %#x when aborting XRI %#x\n", mask, ids);
6572 mask = 0;
6573 }
6574 break;
6575 case SLI_ABORT_ABORT_ID:
6576 abort->criteria = SLI4_ABORT_CRITERIA_ABORT_TAG;
6577 break;
6578 case SLI_ABORT_REQUEST_ID:
6579 abort->criteria = SLI4_ABORT_CRITERIA_REQUEST_TAG;
6580 break;
6581 default:
6582 ocs_log_test(sli4->os, "unsupported type %#x\n", type);
6583 return -1;
6584 }
6585
6586 abort->ia = send_abts ? 0 : 1;
6587
6588 /* Suppress ABTS retries */
6589 abort->ir = 1;
6590
6591 abort->t_mask = mask;
6592 abort->t_tag = ids;
6593 abort->command = SLI4_WQE_ABORT;
6594 abort->request_tag = tag;
6595 abort->qosd = TRUE;
6596 abort->cq_id = cq_id;
6597 abort->cmd_type = SLI4_CMD_ABORT_WQE;
6598
6599 return 0;
6600 }
6601
6602 /**
6603 * @ingroup sli_fc
6604 * @brief Write an ELS_REQUEST64_WQE work queue entry.
6605 *
6606 * @param sli4 SLI context.
6607 * @param buf Destination buffer for the WQE.
6608 * @param size Buffer size, in bytes.
6609 * @param sgl DMA memory for the ELS request.
6610 * @param req_type ELS request type.
6611 * @param req_len Length of ELS request in bytes.
6612 * @param max_rsp_len Max length of ELS response in bytes.
6613 * @param timeout Time, in seconds, before an IO times out. Zero means 2 * R_A_TOV.
6614 * @param xri XRI for this exchange.
6615 * @param tag IO tag value.
6616 * @param cq_id The id of the completion queue where the WQE response is sent.
6617 * @param rnode Destination of ELS request (that is, the remote node).
6618 *
6619 * @return Returns 0 on success, or a non-zero value on failure.
6620 */
6621 int32_t
sli_els_request64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint8_t req_type,uint32_t req_len,uint32_t max_rsp_len,uint8_t timeout,uint16_t xri,uint16_t tag,uint16_t cq_id,ocs_remote_node_t * rnode)6622 sli_els_request64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl, uint8_t req_type,
6623 uint32_t req_len, uint32_t max_rsp_len, uint8_t timeout,
6624 uint16_t xri, uint16_t tag, uint16_t cq_id, ocs_remote_node_t *rnode)
6625 {
6626 sli4_els_request64_wqe_t *els = buf;
6627 sli4_sge_t *sge = sgl->virt;
6628 uint8_t is_fabric = FALSE;
6629
6630 ocs_memset(buf, 0, size);
6631
6632 if (sli4->config.sgl_pre_registered) {
6633 els->xbl = FALSE;
6634
6635 els->dbde = TRUE;
6636 els->els_request_payload.bde_type = SLI4_BDE_TYPE_BDE_64;
6637
6638 els->els_request_payload.buffer_length = req_len;
6639 els->els_request_payload.u.data.buffer_address_low = sge[0].buffer_address_low;
6640 els->els_request_payload.u.data.buffer_address_high = sge[0].buffer_address_high;
6641 } else {
6642 els->xbl = TRUE;
6643
6644 els->els_request_payload.bde_type = SLI4_BDE_TYPE_BLP;
6645
6646 els->els_request_payload.buffer_length = 2 * sizeof(sli4_sge_t);
6647 els->els_request_payload.u.blp.sgl_segment_address_low = ocs_addr32_lo(sgl->phys);
6648 els->els_request_payload.u.blp.sgl_segment_address_high = ocs_addr32_hi(sgl->phys);
6649 }
6650
6651 els->els_request_payload_length = req_len;
6652 els->max_response_payload_length = max_rsp_len;
6653
6654 els->xri_tag = xri;
6655 els->timer = timeout;
6656 els->class = SLI4_ELS_REQUEST64_CLASS_3;
6657
6658 els->command = SLI4_WQE_ELS_REQUEST64;
6659
6660 els->request_tag = tag;
6661
6662 if (rnode->node_group) {
6663 els->hlm = TRUE;
6664 els->remote_id = rnode->fc_id & 0x00ffffff;
6665 }
6666
6667 els->iod = SLI4_ELS_REQUEST64_DIR_READ;
6668
6669 els->qosd = TRUE;
6670
6671 /* figure out the ELS_ID value from the request buffer */
6672
6673 switch (req_type) {
6674 case FC_ELS_CMD_LOGO:
6675 els->els_id = SLI4_ELS_REQUEST64_LOGO;
6676 if (rnode->attached) {
6677 els->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
6678 els->context_tag = rnode->indicator;
6679 } else {
6680 els->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
6681 els->context_tag = rnode->sport->indicator;
6682 }
6683 if (FC_ADDR_FABRIC == rnode->fc_id) {
6684 is_fabric = TRUE;
6685 }
6686 break;
6687 case FC_ELS_CMD_FDISC:
6688 if (FC_ADDR_FABRIC == rnode->fc_id) {
6689 is_fabric = TRUE;
6690 }
6691 if (0 == rnode->sport->fc_id) {
6692 els->els_id = SLI4_ELS_REQUEST64_FDISC;
6693 is_fabric = TRUE;
6694 } else {
6695 els->els_id = SLI4_ELS_REQUEST64_OTHER;
6696 }
6697 els->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
6698 els->context_tag = rnode->sport->indicator;
6699 els->sp = TRUE;
6700 break;
6701 case FC_ELS_CMD_FLOGI:
6702 els->els_id = SLI4_ELS_REQUEST64_FLOGIN;
6703 is_fabric = TRUE;
6704 if (SLI4_IF_TYPE_BE3_SKH_PF == sli4->if_type) {
6705 if (!rnode->sport->domain) {
6706 ocs_log_test(sli4->os, "invalid domain handle\n");
6707 return -1;
6708 }
6709 /*
6710 * IF_TYPE 0 skips INIT_VFI/INIT_VPI and therefore must use the
6711 * FCFI here
6712 */
6713 els->ct = SLI4_ELS_REQUEST64_CONTEXT_FCFI;
6714 els->context_tag = rnode->sport->domain->fcf_indicator;
6715 els->sp = TRUE;
6716 } else {
6717 els->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
6718 els->context_tag = rnode->sport->indicator;
6719
6720 /*
6721 * Set SP here ... we haven't done a REG_VPI yet
6722 * TODO: need to maybe not set this when we have
6723 * completed VFI/VPI registrations ...
6724 *
6725 * Use the FC_ID of the SPORT if it has been allocated, otherwise
6726 * use an S_ID of zero.
6727 */
6728 els->sp = TRUE;
6729 if (rnode->sport->fc_id != UINT32_MAX) {
6730 els->sid = rnode->sport->fc_id;
6731 }
6732 }
6733 break;
6734 case FC_ELS_CMD_PLOGI:
6735 els->els_id = SLI4_ELS_REQUEST64_PLOGI;
6736 els->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
6737 els->context_tag = rnode->sport->indicator;
6738 break;
6739 case FC_ELS_CMD_SCR:
6740 els->els_id = SLI4_ELS_REQUEST64_OTHER;
6741 els->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
6742 els->context_tag = rnode->sport->indicator;
6743 break;
6744 default:
6745 els->els_id = SLI4_ELS_REQUEST64_OTHER;
6746 if (rnode->attached) {
6747 els->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
6748 els->context_tag = rnode->indicator;
6749 } else {
6750 els->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
6751 els->context_tag = rnode->sport->indicator;
6752 }
6753 break;
6754 }
6755
6756 if (is_fabric) {
6757 els->cmd_type = SLI4_ELS_REQUEST64_CMD_FABRIC;
6758 } else {
6759 els->cmd_type = SLI4_ELS_REQUEST64_CMD_NON_FABRIC;
6760 }
6761
6762 els->cq_id = cq_id;
6763
6764 if (SLI4_ELS_REQUEST64_CONTEXT_RPI != els->ct) {
6765 els->remote_id = rnode->fc_id;
6766 }
6767 if (SLI4_ELS_REQUEST64_CONTEXT_VPI == els->ct) {
6768 els->temporary_rpi = rnode->indicator;
6769 }
6770
6771 return 0;
6772 }
6773
6774
6775 /**
6776 * @ingroup sli_fc
6777 * @brief Write an FCP_ICMND64_WQE work queue entry.
6778 *
6779 * @param sli4 SLI context.
6780 * @param buf Destination buffer for the WQE.
6781 * @param size Buffer size, in bytes.
6782 * @param sgl DMA memory for the scatter gather list.
6783 * @param xri XRI for this exchange.
6784 * @param tag IO tag value.
6785 * @param cq_id The id of the completion queue where the WQE response is sent.
6786 * @param rpi remote node indicator (RPI)
6787 * @param rnode Destination request (that is, the remote node).
6788 * @param timeout Time, in seconds, before an IO times out. Zero means no timeout.
6789 *
6790 * @return Returns 0 on success, or a non-zero value on failure.
6791 */
6792 int32_t
sli_fcp_icmnd64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint16_t xri,uint16_t tag,uint16_t cq_id,uint32_t rpi,ocs_remote_node_t * rnode,uint8_t timeout)6793 sli_fcp_icmnd64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl,
6794 uint16_t xri, uint16_t tag, uint16_t cq_id,
6795 uint32_t rpi, ocs_remote_node_t *rnode, uint8_t timeout)
6796 {
6797 sli4_fcp_icmnd64_wqe_t *icmnd = buf;
6798 sli4_sge_t *sge = NULL;
6799
6800 ocs_memset(buf, 0, size);
6801
6802 if (!sgl || !sgl->virt) {
6803 ocs_log_err(sli4->os, "bad parameter sgl=%p virt=%p\n",
6804 sgl, sgl ? sgl->virt : NULL);
6805 return -1;
6806 }
6807 sge = sgl->virt;
6808
6809 if (sli4->config.sgl_pre_registered) {
6810 icmnd->xbl = FALSE;
6811
6812 icmnd->dbde = TRUE;
6813 icmnd->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
6814
6815 icmnd->bde.buffer_length = sge[0].buffer_length;
6816 icmnd->bde.u.data.buffer_address_low = sge[0].buffer_address_low;
6817 icmnd->bde.u.data.buffer_address_high = sge[0].buffer_address_high;
6818 } else {
6819 icmnd->xbl = TRUE;
6820
6821 icmnd->bde.bde_type = SLI4_BDE_TYPE_BLP;
6822
6823 icmnd->bde.buffer_length = sgl->size;
6824 icmnd->bde.u.blp.sgl_segment_address_low = ocs_addr32_lo(sgl->phys);
6825 icmnd->bde.u.blp.sgl_segment_address_high = ocs_addr32_hi(sgl->phys);
6826 }
6827
6828 icmnd->payload_offset_length = sge[0].buffer_length + sge[1].buffer_length;
6829 icmnd->xri_tag = xri;
6830 icmnd->context_tag = rpi;
6831 icmnd->timer = timeout;
6832
6833 icmnd->pu = 2; /* WQE word 4 contains read transfer length */
6834 icmnd->class = SLI4_ELS_REQUEST64_CLASS_3;
6835 icmnd->command = SLI4_WQE_FCP_ICMND64;
6836 icmnd->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
6837
6838 icmnd->abort_tag = xri;
6839
6840 icmnd->request_tag = tag;
6841 icmnd->len_loc = 3;
6842 if (rnode->node_group) {
6843 icmnd->hlm = TRUE;
6844 icmnd->remote_n_port_id = rnode->fc_id & 0x00ffffff;
6845 }
6846 if (((ocs_node_t *)rnode->node)->fcp2device) {
6847 icmnd->erp = TRUE;
6848 }
6849 icmnd->cmd_type = SLI4_CMD_FCP_ICMND64_WQE;
6850 icmnd->cq_id = cq_id;
6851
6852 return 0;
6853 }
6854
6855 /**
6856 * @ingroup sli_fc
6857 * @brief Write an FCP_IREAD64_WQE work queue entry.
6858 *
6859 * @param sli4 SLI context.
6860 * @param buf Destination buffer for the WQE.
6861 * @param size Buffer size, in bytes.
6862 * @param sgl DMA memory for the scatter gather list.
6863 * @param first_data_sge Index of first data sge (used if perf hints are enabled)
6864 * @param xfer_len Data transfer length.
6865 * @param xri XRI for this exchange.
6866 * @param tag IO tag value.
6867 * @param cq_id The id of the completion queue where the WQE response is sent.
6868 * @param rpi remote node indicator (RPI)
6869 * @param rnode Destination request (i.e. remote node).
6870 * @param dif T10 DIF operation, or 0 to disable.
6871 * @param bs T10 DIF block size, or 0 if DIF is disabled.
6872 * @param timeout Time, in seconds, before an IO times out. Zero means no timeout.
6873 *
6874 * @return Returns 0 on success, or a non-zero value on failure.
6875 */
6876 int32_t
sli_fcp_iread64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint32_t first_data_sge,uint32_t xfer_len,uint16_t xri,uint16_t tag,uint16_t cq_id,uint32_t rpi,ocs_remote_node_t * rnode,uint8_t dif,uint8_t bs,uint8_t timeout)6877 sli_fcp_iread64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl, uint32_t first_data_sge,
6878 uint32_t xfer_len, uint16_t xri, uint16_t tag, uint16_t cq_id,
6879 uint32_t rpi, ocs_remote_node_t *rnode,
6880 uint8_t dif, uint8_t bs, uint8_t timeout)
6881 {
6882 sli4_fcp_iread64_wqe_t *iread = buf;
6883 sli4_sge_t *sge = NULL;
6884
6885 ocs_memset(buf, 0, size);
6886
6887 if (!sgl || !sgl->virt) {
6888 ocs_log_err(sli4->os, "bad parameter sgl=%p virt=%p\n",
6889 sgl, sgl ? sgl->virt : NULL);
6890 return -1;
6891 }
6892 sge = sgl->virt;
6893
6894 if (sli4->config.sgl_pre_registered) {
6895 iread->xbl = FALSE;
6896
6897 iread->dbde = TRUE;
6898 iread->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
6899
6900 iread->bde.buffer_length = sge[0].buffer_length;
6901 iread->bde.u.data.buffer_address_low = sge[0].buffer_address_low;
6902 iread->bde.u.data.buffer_address_high = sge[0].buffer_address_high;
6903 } else {
6904 iread->xbl = TRUE;
6905
6906 iread->bde.bde_type = SLI4_BDE_TYPE_BLP;
6907
6908 iread->bde.buffer_length = sgl->size;
6909 iread->bde.u.blp.sgl_segment_address_low = ocs_addr32_lo(sgl->phys);
6910 iread->bde.u.blp.sgl_segment_address_high = ocs_addr32_hi(sgl->phys);
6911
6912 /* fill out fcp_cmnd buffer len and change resp buffer to be of type
6913 * "skip" (note: response will still be written to sge[1] if necessary) */
6914 iread->fcp_cmd_buffer_length = sge[0].buffer_length;
6915 sge[1].sge_type = SLI4_SGE_TYPE_SKIP;
6916 }
6917
6918 iread->payload_offset_length = sge[0].buffer_length + sge[1].buffer_length;
6919 iread->total_transfer_length = xfer_len;
6920
6921 iread->xri_tag = xri;
6922 iread->context_tag = rpi;
6923
6924 iread->timer = timeout;
6925
6926 iread->pu = 2; /* WQE word 4 contains read transfer length */
6927 iread->class = SLI4_ELS_REQUEST64_CLASS_3;
6928 iread->command = SLI4_WQE_FCP_IREAD64;
6929 iread->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
6930 iread->dif = dif;
6931 iread->bs = bs;
6932
6933 iread->abort_tag = xri;
6934
6935 iread->request_tag = tag;
6936 iread->len_loc = 3;
6937 if (rnode->node_group) {
6938 iread->hlm = TRUE;
6939 iread->remote_n_port_id = rnode->fc_id & 0x00ffffff;
6940 }
6941 if (((ocs_node_t *)rnode->node)->fcp2device) {
6942 iread->erp = TRUE;
6943 }
6944 iread->iod = 1;
6945 iread->cmd_type = SLI4_CMD_FCP_IREAD64_WQE;
6946 iread->cq_id = cq_id;
6947
6948 if (sli4->config.perf_hint) {
6949 iread->first_data_bde.bde_type = SLI4_BDE_TYPE_BDE_64;
6950 iread->first_data_bde.buffer_length = sge[first_data_sge].buffer_length;
6951 iread->first_data_bde.u.data.buffer_address_low = sge[first_data_sge].buffer_address_low;
6952 iread->first_data_bde.u.data.buffer_address_high = sge[first_data_sge].buffer_address_high;
6953 }
6954
6955 return 0;
6956 }
6957
6958
6959 /**
6960 * @ingroup sli_fc
6961 * @brief Write an FCP_IWRITE64_WQE work queue entry.
6962 *
6963 * @param sli4 SLI context.
6964 * @param buf Destination buffer for the WQE.
6965 * @param size Buffer size, in bytes.
6966 * @param sgl DMA memory for the scatter gather list.
6967 * @param first_data_sge Index of first data sge (used if perf hints are enabled)
6968 * @param xfer_len Data transfer length.
6969 * @param first_burst The number of first burst bytes
6970 * @param xri XRI for this exchange.
6971 * @param tag IO tag value.
6972 * @param cq_id The id of the completion queue where the WQE response is sent.
6973 * @param rpi remote node indicator (RPI)
6974 * @param rnode Destination request (i.e. remote node)
6975 * @param dif T10 DIF operation, or 0 to disable
6976 * @param bs T10 DIF block size, or 0 if DIF is disabled
6977 * @param timeout Time, in seconds, before an IO times out. Zero means no timeout.
6978 *
6979 * @return Returns 0 on success, or a non-zero value on failure.
6980 */
6981 int32_t
sli_fcp_iwrite64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint32_t first_data_sge,uint32_t xfer_len,uint32_t first_burst,uint16_t xri,uint16_t tag,uint16_t cq_id,uint32_t rpi,ocs_remote_node_t * rnode,uint8_t dif,uint8_t bs,uint8_t timeout)6982 sli_fcp_iwrite64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl, uint32_t first_data_sge,
6983 uint32_t xfer_len, uint32_t first_burst, uint16_t xri, uint16_t tag, uint16_t cq_id,
6984 uint32_t rpi, ocs_remote_node_t *rnode,
6985 uint8_t dif, uint8_t bs, uint8_t timeout)
6986 {
6987 sli4_fcp_iwrite64_wqe_t *iwrite = buf;
6988 sli4_sge_t *sge = NULL;
6989
6990 ocs_memset(buf, 0, size);
6991
6992 if (!sgl || !sgl->virt) {
6993 ocs_log_err(sli4->os, "bad parameter sgl=%p virt=%p\n",
6994 sgl, sgl ? sgl->virt : NULL);
6995 return -1;
6996 }
6997 sge = sgl->virt;
6998
6999 if (sli4->config.sgl_pre_registered) {
7000 iwrite->xbl = FALSE;
7001
7002 iwrite->dbde = TRUE;
7003 iwrite->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7004
7005 iwrite->bde.buffer_length = sge[0].buffer_length;
7006 iwrite->bde.u.data.buffer_address_low = sge[0].buffer_address_low;
7007 iwrite->bde.u.data.buffer_address_high = sge[0].buffer_address_high;
7008 } else {
7009 iwrite->xbl = TRUE;
7010
7011 iwrite->bde.bde_type = SLI4_BDE_TYPE_BLP;
7012
7013 iwrite->bde.buffer_length = sgl->size;
7014 iwrite->bde.u.blp.sgl_segment_address_low = ocs_addr32_lo(sgl->phys);
7015 iwrite->bde.u.blp.sgl_segment_address_high = ocs_addr32_hi(sgl->phys);
7016
7017 /* fill out fcp_cmnd buffer len and change resp buffer to be of type
7018 * "skip" (note: response will still be written to sge[1] if necessary) */
7019 iwrite->fcp_cmd_buffer_length = sge[0].buffer_length;
7020 sge[1].sge_type = SLI4_SGE_TYPE_SKIP;
7021 }
7022
7023 iwrite->payload_offset_length = sge[0].buffer_length + sge[1].buffer_length;
7024 iwrite->total_transfer_length = xfer_len;
7025 iwrite->initial_transfer_length = MIN(xfer_len, first_burst);
7026
7027 iwrite->xri_tag = xri;
7028 iwrite->context_tag = rpi;
7029
7030 iwrite->timer = timeout;
7031
7032 iwrite->pu = 2; /* WQE word 4 contains read transfer length */
7033 iwrite->class = SLI4_ELS_REQUEST64_CLASS_3;
7034 iwrite->command = SLI4_WQE_FCP_IWRITE64;
7035 iwrite->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
7036 iwrite->dif = dif;
7037 iwrite->bs = bs;
7038
7039 iwrite->abort_tag = xri;
7040
7041 iwrite->request_tag = tag;
7042 iwrite->len_loc = 3;
7043 if (rnode->node_group) {
7044 iwrite->hlm = TRUE;
7045 iwrite->remote_n_port_id = rnode->fc_id & 0x00ffffff;
7046 }
7047 if (((ocs_node_t *)rnode->node)->fcp2device) {
7048 iwrite->erp = TRUE;
7049 }
7050 iwrite->cmd_type = SLI4_CMD_FCP_IWRITE64_WQE;
7051 iwrite->cq_id = cq_id;
7052
7053 if (sli4->config.perf_hint) {
7054 iwrite->first_data_bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7055 iwrite->first_data_bde.buffer_length = sge[first_data_sge].buffer_length;
7056 iwrite->first_data_bde.u.data.buffer_address_low = sge[first_data_sge].buffer_address_low;
7057 iwrite->first_data_bde.u.data.buffer_address_high = sge[first_data_sge].buffer_address_high;
7058 }
7059
7060 return 0;
7061 }
7062
7063 /**
7064 * @ingroup sli_fc
7065 * @brief Write an FCP_TRECEIVE64_WQE work queue entry.
7066 *
7067 * @param sli4 SLI context.
7068 * @param buf Destination buffer for the WQE.
7069 * @param size Buffer size, in bytes.
7070 * @param sgl DMA memory for the Scatter-Gather List.
7071 * @param first_data_sge Index of first data sge (used if perf hints are enabled)
7072 * @param relative_off Relative offset of the IO (if any).
7073 * @param xfer_len Data transfer length.
7074 * @param xri XRI for this exchange.
7075 * @param tag IO tag value.
7076 * @param xid OX_ID for the exchange.
7077 * @param cq_id The id of the completion queue where the WQE response is sent.
7078 * @param rpi remote node indicator (RPI)
7079 * @param rnode Destination request (i.e. remote node).
7080 * @param flags Optional attributes, including:
7081 * - ACTIVE - IO is already active.
7082 * - AUTO RSP - Automatically generate a good FCP_RSP.
7083 * @param dif T10 DIF operation, or 0 to disable.
7084 * @param bs T10 DIF block size, or 0 if DIF is disabled.
7085 * @param csctl value of csctl field.
7086 * @param app_id value for VM application header.
7087 *
7088 * @return Returns 0 on success, or a non-zero value on failure.
7089 */
7090 int32_t
sli_fcp_treceive64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint32_t first_data_sge,uint32_t relative_off,uint32_t xfer_len,uint16_t xri,uint16_t tag,uint16_t cq_id,uint16_t xid,uint32_t rpi,ocs_remote_node_t * rnode,uint32_t flags,uint8_t dif,uint8_t bs,uint8_t csctl,uint32_t app_id)7091 sli_fcp_treceive64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl, uint32_t first_data_sge,
7092 uint32_t relative_off, uint32_t xfer_len, uint16_t xri, uint16_t tag, uint16_t cq_id,
7093 uint16_t xid, uint32_t rpi, ocs_remote_node_t *rnode, uint32_t flags, uint8_t dif, uint8_t bs,
7094 uint8_t csctl, uint32_t app_id)
7095 {
7096 sli4_fcp_treceive64_wqe_t *trecv = buf;
7097 sli4_fcp_128byte_wqe_t *trecv_128 = buf;
7098 sli4_sge_t *sge = NULL;
7099
7100 ocs_memset(buf, 0, size);
7101
7102 if (!sgl || !sgl->virt) {
7103 ocs_log_err(sli4->os, "bad parameter sgl=%p virt=%p\n",
7104 sgl, sgl ? sgl->virt : NULL);
7105 return -1;
7106 }
7107 sge = sgl->virt;
7108
7109 if (sli4->config.sgl_pre_registered) {
7110 trecv->xbl = FALSE;
7111
7112 trecv->dbde = TRUE;
7113 trecv->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7114
7115 trecv->bde.buffer_length = sge[0].buffer_length;
7116 trecv->bde.u.data.buffer_address_low = sge[0].buffer_address_low;
7117 trecv->bde.u.data.buffer_address_high = sge[0].buffer_address_high;
7118
7119 trecv->payload_offset_length = sge[0].buffer_length;
7120 } else {
7121 trecv->xbl = TRUE;
7122
7123 /* if data is a single physical address, use a BDE */
7124 if (!dif && (xfer_len <= sge[2].buffer_length)) {
7125 trecv->dbde = TRUE;
7126 trecv->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7127
7128 trecv->bde.buffer_length = sge[2].buffer_length;
7129 trecv->bde.u.data.buffer_address_low = sge[2].buffer_address_low;
7130 trecv->bde.u.data.buffer_address_high = sge[2].buffer_address_high;
7131 } else {
7132 trecv->bde.bde_type = SLI4_BDE_TYPE_BLP;
7133 trecv->bde.buffer_length = sgl->size;
7134 trecv->bde.u.blp.sgl_segment_address_low = ocs_addr32_lo(sgl->phys);
7135 trecv->bde.u.blp.sgl_segment_address_high = ocs_addr32_hi(sgl->phys);
7136 }
7137 }
7138
7139 trecv->relative_offset = relative_off;
7140
7141 if (flags & SLI4_IO_CONTINUATION) {
7142 trecv->xc = TRUE;
7143 }
7144 trecv->xri_tag = xri;
7145
7146 trecv->context_tag = rpi;
7147
7148 trecv->pu = TRUE; /* WQE uses relative offset */
7149
7150 if (flags & SLI4_IO_AUTO_GOOD_RESPONSE) {
7151 trecv->ar = TRUE;
7152 }
7153
7154 trecv->command = SLI4_WQE_FCP_TRECEIVE64;
7155 trecv->class = SLI4_ELS_REQUEST64_CLASS_3;
7156 trecv->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
7157 trecv->dif = dif;
7158 trecv->bs = bs;
7159
7160 trecv->remote_xid = xid;
7161
7162 trecv->request_tag = tag;
7163
7164 trecv->iod = 1;
7165
7166 trecv->len_loc = 0x2;
7167
7168 if (rnode->node_group) {
7169 trecv->hlm = TRUE;
7170 trecv->dword5.dword = rnode->fc_id & 0x00ffffff;
7171 }
7172
7173 trecv->cmd_type = SLI4_CMD_FCP_TRECEIVE64_WQE;
7174
7175 trecv->cq_id = cq_id;
7176
7177 trecv->fcp_data_receive_length = xfer_len;
7178
7179 if (sli4->config.perf_hint) {
7180 trecv->first_data_bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7181 trecv->first_data_bde.buffer_length = sge[first_data_sge].buffer_length;
7182 trecv->first_data_bde.u.data.buffer_address_low = sge[first_data_sge].buffer_address_low;
7183 trecv->first_data_bde.u.data.buffer_address_high = sge[first_data_sge].buffer_address_high;
7184 }
7185
7186 /* The upper 7 bits of csctl is the priority */
7187 if (csctl & SLI4_MASK_CCP) {
7188 trecv->ccpe = 1;
7189 trecv->ccp = (csctl & SLI4_MASK_CCP);
7190 }
7191
7192 if (app_id && (sli4->config.wqe_size == SLI4_WQE_EXT_BYTES) && !trecv->eat) {
7193 trecv->app_id_valid = 1;
7194 trecv->wqes = 1;
7195 trecv_128->dw[31] = app_id;
7196 }
7197 return 0;
7198 }
7199
7200 /**
7201 * @ingroup sli_fc
7202 * @brief Write an FCP_CONT_TRECEIVE64_WQE work queue entry.
7203 *
7204 * @param sli4 SLI context.
7205 * @param buf Destination buffer for the WQE.
7206 * @param size Buffer size, in bytes.
7207 * @param sgl DMA memory for the Scatter-Gather List.
7208 * @param first_data_sge Index of first data sge (used if perf hints are enabled)
7209 * @param relative_off Relative offset of the IO (if any).
7210 * @param xfer_len Data transfer length.
7211 * @param xri XRI for this exchange.
7212 * @param sec_xri Secondary XRI for this exchange. (BZ 161832 workaround)
7213 * @param tag IO tag value.
7214 * @param xid OX_ID for the exchange.
7215 * @param cq_id The id of the completion queue where the WQE response is sent.
7216 * @param rpi remote node indicator (RPI)
7217 * @param rnode Destination request (i.e. remote node).
7218 * @param flags Optional attributes, including:
7219 * - ACTIVE - IO is already active.
7220 * - AUTO RSP - Automatically generate a good FCP_RSP.
7221 * @param dif T10 DIF operation, or 0 to disable.
7222 * @param bs T10 DIF block size, or 0 if DIF is disabled.
7223 * @param csctl value of csctl field.
7224 * @param app_id value for VM application header.
7225 *
7226 * @return Returns 0 on success, or a non-zero value on failure.
7227 */
7228 int32_t
sli_fcp_cont_treceive64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint32_t first_data_sge,uint32_t relative_off,uint32_t xfer_len,uint16_t xri,uint16_t sec_xri,uint16_t tag,uint16_t cq_id,uint16_t xid,uint32_t rpi,ocs_remote_node_t * rnode,uint32_t flags,uint8_t dif,uint8_t bs,uint8_t csctl,uint32_t app_id)7229 sli_fcp_cont_treceive64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl, uint32_t first_data_sge,
7230 uint32_t relative_off, uint32_t xfer_len, uint16_t xri, uint16_t sec_xri, uint16_t tag,
7231 uint16_t cq_id, uint16_t xid, uint32_t rpi, ocs_remote_node_t *rnode, uint32_t flags,
7232 uint8_t dif, uint8_t bs, uint8_t csctl, uint32_t app_id)
7233 {
7234 int32_t rc;
7235
7236 rc = sli_fcp_treceive64_wqe(sli4, buf, size, sgl, first_data_sge, relative_off, xfer_len, xri, tag,
7237 cq_id, xid, rpi, rnode, flags, dif, bs, csctl, app_id);
7238 if (rc == 0) {
7239 sli4_fcp_treceive64_wqe_t *trecv = buf;
7240
7241 trecv->command = SLI4_WQE_FCP_CONT_TRECEIVE64;
7242 trecv->dword5.sec_xri_tag = sec_xri;
7243 }
7244 return rc;
7245 }
7246
7247 /**
7248 * @ingroup sli_fc
7249 * @brief Write an FCP_TRSP64_WQE work queue entry.
7250 *
7251 * @param sli4 SLI context.
7252 * @param buf Destination buffer for the WQE.
7253 * @param size Buffer size, in bytes.
7254 * @param sgl DMA memory for the Scatter-Gather List.
7255 * @param rsp_len Response data length.
7256 * @param xri XRI for this exchange.
7257 * @param tag IO tag value.
7258 * @param cq_id The id of the completion queue where the WQE response is sent.
7259 * @param xid OX_ID for the exchange.
7260 * @param rpi remote node indicator (RPI)
7261 * @param rnode Destination request (i.e. remote node).
7262 * @param flags Optional attributes, including:
7263 * - ACTIVE - IO is already active
7264 * - AUTO RSP - Automatically generate a good FCP_RSP.
7265 * @param csctl value of csctl field.
7266 * @param port_owned 0/1 to indicate if the XRI is port owned (used to set XBL=0)
7267 * @param app_id value for VM application header.
7268 *
7269 * @return Returns 0 on success, or a non-zero value on failure.
7270 */
7271 int32_t
sli_fcp_trsp64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint32_t rsp_len,uint16_t xri,uint16_t tag,uint16_t cq_id,uint16_t xid,uint32_t rpi,ocs_remote_node_t * rnode,uint32_t flags,uint8_t csctl,uint8_t port_owned,uint32_t app_id)7272 sli_fcp_trsp64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl, uint32_t rsp_len,
7273 uint16_t xri, uint16_t tag, uint16_t cq_id, uint16_t xid, uint32_t rpi, ocs_remote_node_t *rnode,
7274 uint32_t flags, uint8_t csctl, uint8_t port_owned, uint32_t app_id)
7275 {
7276 sli4_fcp_trsp64_wqe_t *trsp = buf;
7277 sli4_fcp_128byte_wqe_t *trsp_128 = buf;
7278
7279 ocs_memset(buf, 0, size);
7280
7281 if (flags & SLI4_IO_AUTO_GOOD_RESPONSE) {
7282 trsp->ag = TRUE;
7283 /*
7284 * The SLI-4 documentation states that the BDE is ignored when
7285 * using auto-good response, but, at least for IF_TYPE 0 devices,
7286 * this does not appear to be true.
7287 */
7288 if (SLI4_IF_TYPE_BE3_SKH_PF == sli4->if_type) {
7289 trsp->bde.buffer_length = 12; /* byte size of RSP */
7290 }
7291 } else {
7292 sli4_sge_t *sge = sgl->virt;
7293
7294 if (sli4->config.sgl_pre_registered || port_owned) {
7295 trsp->dbde = TRUE;
7296 } else {
7297 trsp->xbl = TRUE;
7298 }
7299
7300 trsp->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7301 trsp->bde.buffer_length = sge[0].buffer_length;
7302 trsp->bde.u.data.buffer_address_low = sge[0].buffer_address_low;
7303 trsp->bde.u.data.buffer_address_high = sge[0].buffer_address_high;
7304
7305 trsp->fcp_response_length = rsp_len;
7306 }
7307
7308 if (flags & SLI4_IO_CONTINUATION) {
7309 trsp->xc = TRUE;
7310 }
7311
7312 if (rnode->node_group) {
7313 trsp->hlm = TRUE;
7314 trsp->dword5 = rnode->fc_id & 0x00ffffff;
7315 }
7316
7317 trsp->xri_tag = xri;
7318 trsp->rpi = rpi;
7319
7320 trsp->command = SLI4_WQE_FCP_TRSP64;
7321 trsp->class = SLI4_ELS_REQUEST64_CLASS_3;
7322
7323 trsp->remote_xid = xid;
7324 trsp->request_tag = tag;
7325 trsp->dnrx = ((flags & SLI4_IO_DNRX) == 0 ? 0 : 1);
7326 trsp->len_loc = 0x1;
7327 trsp->cq_id = cq_id;
7328 trsp->cmd_type = SLI4_CMD_FCP_TRSP64_WQE;
7329
7330 /* The upper 7 bits of csctl is the priority */
7331 if (csctl & SLI4_MASK_CCP) {
7332 trsp->ccpe = 1;
7333 trsp->ccp = (csctl & SLI4_MASK_CCP);
7334 }
7335
7336 if (app_id && (sli4->config.wqe_size == SLI4_WQE_EXT_BYTES) && !trsp->eat) {
7337 trsp->app_id_valid = 1;
7338 trsp->wqes = 1;
7339 trsp_128->dw[31] = app_id;
7340 }
7341 return 0;
7342 }
7343
7344 /**
7345 * @ingroup sli_fc
7346 * @brief Write an FCP_TSEND64_WQE work queue entry.
7347 *
7348 * @param sli4 SLI context.
7349 * @param buf Destination buffer for the WQE.
7350 * @param size Buffer size, in bytes.
7351 * @param sgl DMA memory for the scatter gather list.
7352 * @param first_data_sge Index of first data sge (used if perf hints are enabled)
7353 * @param relative_off Relative offset of the IO (if any).
7354 * @param xfer_len Data transfer length.
7355 * @param xri XRI for this exchange.
7356 * @param tag IO tag value.
7357 * @param cq_id The id of the completion queue where the WQE response is sent.
7358 * @param xid OX_ID for the exchange.
7359 * @param rpi remote node indicator (RPI)
7360 * @param rnode Destination request (i.e. remote node).
7361 * @param flags Optional attributes, including:
7362 * - ACTIVE - IO is already active.
7363 * - AUTO RSP - Automatically generate a good FCP_RSP.
7364 * @param dif T10 DIF operation, or 0 to disable.
7365 * @param bs T10 DIF block size, or 0 if DIF is disabled.
7366 * @param csctl value of csctl field.
7367 * @param app_id value for VM application header.
7368 *
7369 * @return Returns 0 on success, or a non-zero value on failure.
7370 */
7371 int32_t
sli_fcp_tsend64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint32_t first_data_sge,uint32_t relative_off,uint32_t xfer_len,uint16_t xri,uint16_t tag,uint16_t cq_id,uint16_t xid,uint32_t rpi,ocs_remote_node_t * rnode,uint32_t flags,uint8_t dif,uint8_t bs,uint8_t csctl,uint32_t app_id)7372 sli_fcp_tsend64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl, uint32_t first_data_sge,
7373 uint32_t relative_off, uint32_t xfer_len,
7374 uint16_t xri, uint16_t tag, uint16_t cq_id, uint16_t xid, uint32_t rpi, ocs_remote_node_t *rnode,
7375 uint32_t flags, uint8_t dif, uint8_t bs, uint8_t csctl, uint32_t app_id)
7376 {
7377 sli4_fcp_tsend64_wqe_t *tsend = buf;
7378 sli4_fcp_128byte_wqe_t *tsend_128 = buf;
7379 sli4_sge_t *sge = NULL;
7380
7381 ocs_memset(buf, 0, size);
7382
7383 if (!sgl || !sgl->virt) {
7384 ocs_log_err(sli4->os, "bad parameter sgl=%p virt=%p\n",
7385 sgl, sgl ? sgl->virt : NULL);
7386 return -1;
7387 }
7388 sge = sgl->virt;
7389
7390 if (sli4->config.sgl_pre_registered) {
7391 tsend->xbl = FALSE;
7392
7393 tsend->dbde = TRUE;
7394 tsend->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7395
7396 /* TSEND64_WQE specifies first two SGE are skipped
7397 * (i.e. 3rd is valid) */
7398 tsend->bde.buffer_length = sge[2].buffer_length;
7399 tsend->bde.u.data.buffer_address_low = sge[2].buffer_address_low;
7400 tsend->bde.u.data.buffer_address_high = sge[2].buffer_address_high;
7401 } else {
7402 tsend->xbl = TRUE;
7403
7404 /* if data is a single physical address, use a BDE */
7405 if (!dif && (xfer_len <= sge[2].buffer_length)) {
7406 tsend->dbde = TRUE;
7407 tsend->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7408 /* TSEND64_WQE specifies first two SGE are skipped
7409 * (i.e. 3rd is valid) */
7410 tsend->bde.buffer_length = sge[2].buffer_length;
7411 tsend->bde.u.data.buffer_address_low = sge[2].buffer_address_low;
7412 tsend->bde.u.data.buffer_address_high = sge[2].buffer_address_high;
7413 } else {
7414 tsend->bde.bde_type = SLI4_BDE_TYPE_BLP;
7415 tsend->bde.buffer_length = sgl->size;
7416 tsend->bde.u.blp.sgl_segment_address_low = ocs_addr32_lo(sgl->phys);
7417 tsend->bde.u.blp.sgl_segment_address_high = ocs_addr32_hi(sgl->phys);
7418 }
7419 }
7420
7421 tsend->relative_offset = relative_off;
7422
7423 if (flags & SLI4_IO_CONTINUATION) {
7424 tsend->xc = TRUE;
7425 }
7426 tsend->xri_tag = xri;
7427
7428 tsend->rpi = rpi;
7429
7430 tsend->pu = TRUE; /* WQE uses relative offset */
7431
7432 if (flags & SLI4_IO_AUTO_GOOD_RESPONSE) {
7433 tsend->ar = TRUE;
7434 }
7435
7436 tsend->command = SLI4_WQE_FCP_TSEND64;
7437 tsend->class = SLI4_ELS_REQUEST64_CLASS_3;
7438 tsend->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
7439 tsend->dif = dif;
7440 tsend->bs = bs;
7441
7442 tsend->remote_xid = xid;
7443
7444 tsend->request_tag = tag;
7445
7446 tsend->len_loc = 0x2;
7447
7448 if (rnode->node_group) {
7449 tsend->hlm = TRUE;
7450 tsend->dword5 = rnode->fc_id & 0x00ffffff;
7451 }
7452
7453 tsend->cq_id = cq_id;
7454
7455 tsend->cmd_type = SLI4_CMD_FCP_TSEND64_WQE;
7456
7457 tsend->fcp_data_transmit_length = xfer_len;
7458
7459 if (sli4->config.perf_hint) {
7460 tsend->first_data_bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7461 tsend->first_data_bde.buffer_length = sge[first_data_sge].buffer_length;
7462 tsend->first_data_bde.u.data.buffer_address_low = sge[first_data_sge].buffer_address_low;
7463 tsend->first_data_bde.u.data.buffer_address_high = sge[first_data_sge].buffer_address_high;
7464 }
7465
7466 /* The upper 7 bits of csctl is the priority */
7467 if (csctl & SLI4_MASK_CCP) {
7468 tsend->ccpe = 1;
7469 tsend->ccp = (csctl & SLI4_MASK_CCP);
7470 }
7471
7472 if (app_id && (sli4->config.wqe_size == SLI4_WQE_EXT_BYTES) && !tsend->eat) {
7473 tsend->app_id_valid = 1;
7474 tsend->wqes = 1;
7475 tsend_128->dw[31] = app_id;
7476 }
7477 return 0;
7478 }
7479
7480 /**
7481 * @ingroup sli_fc
7482 * @brief Write a GEN_REQUEST64 work queue entry.
7483 *
7484 * @note This WQE is only used to send FC-CT commands.
7485 *
7486 * @param sli4 SLI context.
7487 * @param buf Destination buffer for the WQE.
7488 * @param size Buffer size, in bytes.
7489 * @param sgl DMA memory for the request.
7490 * @param req_len Length of request.
7491 * @param max_rsp_len Max length of response.
7492 * @param timeout Time, in seconds, before an IO times out. Zero means infinite.
7493 * @param xri XRI for this exchange.
7494 * @param tag IO tag value.
7495 * @param cq_id The id of the completion queue where the WQE response is sent.
7496 * @param rnode Destination of request (that is, the remote node).
7497 * @param r_ctl R_CTL value for sequence.
7498 * @param type TYPE value for sequence.
7499 * @param df_ctl DF_CTL value for sequence.
7500 *
7501 * @return Returns 0 on success, or a non-zero value on failure.
7502 */
7503 int32_t
sli_gen_request64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * sgl,uint32_t req_len,uint32_t max_rsp_len,uint8_t timeout,uint16_t xri,uint16_t tag,uint16_t cq_id,ocs_remote_node_t * rnode,uint8_t r_ctl,uint8_t type,uint8_t df_ctl)7504 sli_gen_request64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *sgl,
7505 uint32_t req_len, uint32_t max_rsp_len, uint8_t timeout,
7506 uint16_t xri, uint16_t tag, uint16_t cq_id, ocs_remote_node_t *rnode,
7507 uint8_t r_ctl, uint8_t type, uint8_t df_ctl)
7508 {
7509 sli4_gen_request64_wqe_t *gen = buf;
7510 sli4_sge_t *sge = NULL;
7511
7512 ocs_memset(buf, 0, size);
7513
7514 if (!sgl || !sgl->virt) {
7515 ocs_log_err(sli4->os, "bad parameter sgl=%p virt=%p\n",
7516 sgl, sgl ? sgl->virt : NULL);
7517 return -1;
7518 }
7519 sge = sgl->virt;
7520
7521 if (sli4->config.sgl_pre_registered) {
7522 gen->xbl = FALSE;
7523
7524 gen->dbde = TRUE;
7525 gen->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7526
7527 gen->bde.buffer_length = req_len;
7528 gen->bde.u.data.buffer_address_low = sge[0].buffer_address_low;
7529 gen->bde.u.data.buffer_address_high = sge[0].buffer_address_high;
7530 } else {
7531 gen->xbl = TRUE;
7532
7533 gen->bde.bde_type = SLI4_BDE_TYPE_BLP;
7534
7535 gen->bde.buffer_length = 2 * sizeof(sli4_sge_t);
7536 gen->bde.u.blp.sgl_segment_address_low = ocs_addr32_lo(sgl->phys);
7537 gen->bde.u.blp.sgl_segment_address_high = ocs_addr32_hi(sgl->phys);
7538 }
7539
7540 gen->request_payload_length = req_len;
7541 gen->max_response_payload_length = max_rsp_len;
7542
7543 gen->df_ctl = df_ctl;
7544 gen->type = type;
7545 gen->r_ctl = r_ctl;
7546
7547 gen->xri_tag = xri;
7548
7549 gen->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
7550 gen->context_tag = rnode->indicator;
7551
7552 gen->class = SLI4_ELS_REQUEST64_CLASS_3;
7553
7554 gen->command = SLI4_WQE_GEN_REQUEST64;
7555
7556 gen->timer = timeout;
7557
7558 gen->request_tag = tag;
7559
7560 gen->iod = SLI4_ELS_REQUEST64_DIR_READ;
7561
7562 gen->qosd = TRUE;
7563
7564 if (rnode->node_group) {
7565 gen->hlm = TRUE;
7566 gen->remote_n_port_id = rnode->fc_id & 0x00ffffff;
7567 }
7568
7569 gen->cmd_type = SLI4_CMD_GEN_REQUEST64_WQE;
7570
7571 gen->cq_id = cq_id;
7572
7573 return 0;
7574 }
7575
7576 /**
7577 * @ingroup sli_fc
7578 * @brief Write a SEND_FRAME work queue entry
7579 *
7580 * @param sli4 SLI context.
7581 * @param buf Destination buffer for the WQE.
7582 * @param size Buffer size, in bytes.
7583 * @param sof Start of frame value
7584 * @param eof End of frame value
7585 * @param hdr Pointer to FC header data
7586 * @param payload DMA memory for the payload.
7587 * @param req_len Length of payload.
7588 * @param timeout Time, in seconds, before an IO times out. Zero means infinite.
7589 * @param xri XRI for this exchange.
7590 * @param req_tag IO tag value.
7591 *
7592 * @return Returns 0 on success, or a non-zero value on failure.
7593 */
7594 int32_t
sli_send_frame_wqe(sli4_t * sli4,void * buf,size_t size,uint8_t sof,uint8_t eof,uint32_t * hdr,ocs_dma_t * payload,uint32_t req_len,uint8_t timeout,uint16_t xri,uint16_t req_tag)7595 sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr,
7596 ocs_dma_t *payload, uint32_t req_len, uint8_t timeout,
7597 uint16_t xri, uint16_t req_tag)
7598 {
7599 sli4_send_frame_wqe_t *sf = buf;
7600
7601 ocs_memset(buf, 0, size);
7602
7603 sf->dbde = TRUE;
7604 sf->bde.buffer_length = req_len;
7605 sf->bde.u.data.buffer_address_low = ocs_addr32_lo(payload->phys);
7606 sf->bde.u.data.buffer_address_high = ocs_addr32_hi(payload->phys);
7607
7608 /* Copy FC header */
7609 sf->fc_header_0_1[0] = hdr[0];
7610 sf->fc_header_0_1[1] = hdr[1];
7611 sf->fc_header_2_5[0] = hdr[2];
7612 sf->fc_header_2_5[1] = hdr[3];
7613 sf->fc_header_2_5[2] = hdr[4];
7614 sf->fc_header_2_5[3] = hdr[5];
7615
7616 sf->frame_length = req_len;
7617
7618 sf->xri_tag = xri;
7619 sf->pu = 0;
7620 sf->context_tag = 0;
7621
7622
7623 sf->ct = 0;
7624 sf->command = SLI4_WQE_SEND_FRAME;
7625 sf->class = SLI4_ELS_REQUEST64_CLASS_3;
7626 sf->timer = timeout;
7627
7628 sf->request_tag = req_tag;
7629 sf->eof = eof;
7630 sf->sof = sof;
7631
7632 sf->qosd = 0;
7633 sf->lenloc = 1;
7634 sf->xc = 0;
7635
7636 sf->xbl = 1;
7637
7638 sf->cmd_type = SLI4_CMD_SEND_FRAME_WQE;
7639 sf->cq_id = 0xffff;
7640
7641 return 0;
7642 }
7643
7644 /**
7645 * @ingroup sli_fc
7646 * @brief Write a XMIT_SEQUENCE64 work queue entry.
7647 *
7648 * This WQE is used to send FC-CT response frames.
7649 *
7650 * @note This API implements a restricted use for this WQE, a TODO: would
7651 * include passing in sequence initiative, and full SGL's
7652 *
7653 * @param sli4 SLI context.
7654 * @param buf Destination buffer for the WQE.
7655 * @param size Buffer size, in bytes.
7656 * @param payload DMA memory for the request.
7657 * @param payload_len Length of request.
7658 * @param timeout Time, in seconds, before an IO times out. Zero means infinite.
7659 * @param ox_id originator exchange ID
7660 * @param xri XRI for this exchange.
7661 * @param tag IO tag value.
7662 * @param rnode Destination of request (that is, the remote node).
7663 * @param r_ctl R_CTL value for sequence.
7664 * @param type TYPE value for sequence.
7665 * @param df_ctl DF_CTL value for sequence.
7666 *
7667 * @return Returns 0 on success, or a non-zero value on failure.
7668 */
7669 int32_t
sli_xmit_sequence64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * payload,uint32_t payload_len,uint8_t timeout,uint16_t ox_id,uint16_t xri,uint16_t tag,ocs_remote_node_t * rnode,uint8_t r_ctl,uint8_t type,uint8_t df_ctl)7670 sli_xmit_sequence64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *payload,
7671 uint32_t payload_len, uint8_t timeout, uint16_t ox_id,
7672 uint16_t xri, uint16_t tag, ocs_remote_node_t *rnode,
7673 uint8_t r_ctl, uint8_t type, uint8_t df_ctl)
7674 {
7675 sli4_xmit_sequence64_wqe_t *xmit = buf;
7676
7677 ocs_memset(buf, 0, size);
7678
7679 if ((payload == NULL) || (payload->virt == NULL)) {
7680 ocs_log_err(sli4->os, "bad parameter sgl=%p virt=%p\n",
7681 payload, payload ? payload->virt : NULL);
7682 return -1;
7683 }
7684
7685 if (sli4->config.sgl_pre_registered) {
7686 xmit->dbde = TRUE;
7687 } else {
7688 xmit->xbl = TRUE;
7689 }
7690
7691 xmit->bde.bde_type = SLI4_BDE_TYPE_BDE_64;
7692 xmit->bde.buffer_length = payload_len;
7693 xmit->bde.u.data.buffer_address_low = ocs_addr32_lo(payload->phys);
7694 xmit->bde.u.data.buffer_address_high = ocs_addr32_hi(payload->phys);
7695 xmit->sequence_payload_len = payload_len;
7696
7697 xmit->remote_n_port_id = rnode->fc_id & 0x00ffffff;
7698
7699 xmit->relative_offset = 0;
7700
7701 xmit->si = 0; /* sequence initiative - this matches what is seen from
7702 * FC switches in response to FCGS commands */
7703 xmit->ft = 0; /* force transmit */
7704 xmit->xo = 0; /* exchange responder */
7705 xmit->ls = 1; /* last in seqence */
7706 xmit->df_ctl = df_ctl;
7707 xmit->type = type;
7708 xmit->r_ctl = r_ctl;
7709
7710 xmit->xri_tag = xri;
7711 xmit->context_tag = rnode->indicator;
7712
7713 xmit->dif = 0;
7714 xmit->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
7715 xmit->bs = 0;
7716
7717 xmit->command = SLI4_WQE_XMIT_SEQUENCE64;
7718 xmit->class = SLI4_ELS_REQUEST64_CLASS_3;
7719 xmit->pu = 0;
7720 xmit->timer = timeout;
7721
7722 xmit->abort_tag = 0;
7723 xmit->request_tag = tag;
7724 xmit->remote_xid = ox_id;
7725
7726 xmit->iod = SLI4_ELS_REQUEST64_DIR_READ;
7727
7728 if (rnode->node_group) {
7729 xmit->hlm = TRUE;
7730 xmit->remote_n_port_id = rnode->fc_id & 0x00ffffff;
7731 }
7732
7733 xmit->cmd_type = SLI4_CMD_XMIT_SEQUENCE64_WQE;
7734
7735 xmit->len_loc = 2;
7736
7737 xmit->cq_id = 0xFFFF;
7738
7739 return 0;
7740 }
7741
7742 /**
7743 * @ingroup sli_fc
7744 * @brief Write a REQUEUE_XRI_WQE work queue entry.
7745 *
7746 * @param sli4 SLI context.
7747 * @param buf Destination buffer for the WQE.
7748 * @param size Buffer size, in bytes.
7749 * @param xri XRI for this exchange.
7750 * @param tag IO tag value.
7751 * @param cq_id The id of the completion queue where the WQE response is sent.
7752 *
7753 * @return Returns 0 on success, or a non-zero value on failure.
7754 */
7755 int32_t
sli_requeue_xri_wqe(sli4_t * sli4,void * buf,size_t size,uint16_t xri,uint16_t tag,uint16_t cq_id)7756 sli_requeue_xri_wqe(sli4_t *sli4, void *buf, size_t size, uint16_t xri, uint16_t tag, uint16_t cq_id)
7757 {
7758 sli4_requeue_xri_wqe_t *requeue = buf;
7759
7760 ocs_memset(buf, 0, size);
7761
7762 requeue->command = SLI4_WQE_REQUEUE_XRI;
7763 requeue->xri_tag = xri;
7764 requeue->request_tag = tag;
7765 requeue->xc = 1;
7766 requeue->qosd = 1;
7767 requeue->cq_id = cq_id;
7768 requeue->cmd_type = SLI4_CMD_REQUEUE_XRI_WQE;
7769 return 0;
7770 }
7771
7772 int32_t
sli_xmit_bcast64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * payload,uint32_t payload_len,uint8_t timeout,uint16_t xri,uint16_t tag,uint16_t cq_id,ocs_remote_node_t * rnode,uint8_t r_ctl,uint8_t type,uint8_t df_ctl)7773 sli_xmit_bcast64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *payload,
7774 uint32_t payload_len, uint8_t timeout, uint16_t xri, uint16_t tag,
7775 uint16_t cq_id, ocs_remote_node_t *rnode,
7776 uint8_t r_ctl, uint8_t type, uint8_t df_ctl)
7777 {
7778 sli4_xmit_bcast64_wqe_t *bcast = buf;
7779
7780 /* Command requires a temporary RPI (i.e. unused remote node) */
7781 if (rnode->attached) {
7782 ocs_log_test(sli4->os, "remote node %d in use\n", rnode->indicator);
7783 return -1;
7784 }
7785
7786 ocs_memset(buf, 0, size);
7787
7788 bcast->dbde = TRUE;
7789 bcast->sequence_payload.bde_type = SLI4_BDE_TYPE_BDE_64;
7790 bcast->sequence_payload.buffer_length = payload_len;
7791 bcast->sequence_payload.u.data.buffer_address_low = ocs_addr32_lo(payload->phys);
7792 bcast->sequence_payload.u.data.buffer_address_high = ocs_addr32_hi(payload->phys);
7793
7794 bcast->sequence_payload_length = payload_len;
7795
7796 bcast->df_ctl = df_ctl;
7797 bcast->type = type;
7798 bcast->r_ctl = r_ctl;
7799
7800 bcast->xri_tag = xri;
7801
7802 bcast->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
7803 bcast->context_tag = rnode->sport->indicator;
7804
7805 bcast->class = SLI4_ELS_REQUEST64_CLASS_3;
7806
7807 bcast->command = SLI4_WQE_XMIT_BCAST64;
7808
7809 bcast->timer = timeout;
7810
7811 bcast->request_tag = tag;
7812
7813 bcast->temporary_rpi = rnode->indicator;
7814
7815 bcast->len_loc = 0x1;
7816
7817 bcast->iod = SLI4_ELS_REQUEST64_DIR_WRITE;
7818
7819 bcast->cmd_type = SLI4_CMD_XMIT_BCAST64_WQE;
7820
7821 bcast->cq_id = cq_id;
7822
7823 return 0;
7824 }
7825
7826 /**
7827 * @ingroup sli_fc
7828 * @brief Write an XMIT_BLS_RSP64_WQE work queue entry.
7829 *
7830 * @param sli4 SLI context.
7831 * @param buf Destination buffer for the WQE.
7832 * @param size Buffer size, in bytes.
7833 * @param payload Contents of the BLS payload to be sent.
7834 * @param xri XRI for this exchange.
7835 * @param tag IO tag value.
7836 * @param cq_id The id of the completion queue where the WQE response is sent.
7837 * @param rnode Destination of request (that is, the remote node).
7838 * @param s_id Source ID to use in the response. If UINT32_MAX, use SLI Port's ID.
7839 *
7840 * @return Returns 0 on success, or a non-zero value on failure.
7841 */
7842 int32_t
sli_xmit_bls_rsp64_wqe(sli4_t * sli4,void * buf,size_t size,sli_bls_payload_t * payload,uint16_t xri,uint16_t tag,uint16_t cq_id,ocs_remote_node_t * rnode,uint32_t s_id)7843 sli_xmit_bls_rsp64_wqe(sli4_t *sli4, void *buf, size_t size, sli_bls_payload_t *payload,
7844 uint16_t xri, uint16_t tag, uint16_t cq_id, ocs_remote_node_t *rnode, uint32_t s_id)
7845 {
7846 sli4_xmit_bls_rsp_wqe_t *bls = buf;
7847
7848 /*
7849 * Callers can either specify RPI or S_ID, but not both
7850 */
7851 if (rnode->attached && (s_id != UINT32_MAX)) {
7852 ocs_log_test(sli4->os, "S_ID specified for attached remote node %d\n",
7853 rnode->indicator);
7854 return -1;
7855 }
7856
7857 ocs_memset(buf, 0, size);
7858
7859 if (SLI_BLS_ACC == payload->type) {
7860 bls->payload_word0 = (payload->u.acc.seq_id_last << 16) |
7861 (payload->u.acc.seq_id_validity << 24);
7862 bls->high_seq_cnt = payload->u.acc.high_seq_cnt;
7863 bls->low_seq_cnt = payload->u.acc.low_seq_cnt;
7864 } else if (SLI_BLS_RJT == payload->type) {
7865 bls->payload_word0 = *((uint32_t *)&payload->u.rjt);
7866 bls->ar = TRUE;
7867 } else {
7868 ocs_log_test(sli4->os, "bad BLS type %#x\n",
7869 payload->type);
7870 return -1;
7871 }
7872
7873 bls->ox_id = payload->ox_id;
7874 bls->rx_id = payload->rx_id;
7875
7876 if (rnode->attached) {
7877 bls->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
7878 bls->context_tag = rnode->indicator;
7879 } else {
7880 bls->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
7881 bls->context_tag = rnode->sport->indicator;
7882
7883 if (UINT32_MAX != s_id) {
7884 bls->local_n_port_id = s_id & 0x00ffffff;
7885 } else {
7886 bls->local_n_port_id = rnode->sport->fc_id & 0x00ffffff;
7887 }
7888 bls->remote_id = rnode->fc_id & 0x00ffffff;
7889
7890 bls->temporary_rpi = rnode->indicator;
7891 }
7892
7893 bls->xri_tag = xri;
7894
7895 bls->class = SLI4_ELS_REQUEST64_CLASS_3;
7896
7897 bls->command = SLI4_WQE_XMIT_BLS_RSP;
7898
7899 bls->request_tag = tag;
7900
7901 bls->qosd = TRUE;
7902
7903 if (rnode->node_group) {
7904 bls->hlm = TRUE;
7905 bls->remote_id = rnode->fc_id & 0x00ffffff;
7906 }
7907
7908 bls->cq_id = cq_id;
7909
7910 bls->cmd_type = SLI4_CMD_XMIT_BLS_RSP64_WQE;
7911
7912 return 0;
7913 }
7914
7915 /**
7916 * @ingroup sli_fc
7917 * @brief Write a XMIT_ELS_RSP64_WQE work queue entry.
7918 *
7919 * @param sli4 SLI context.
7920 * @param buf Destination buffer for the WQE.
7921 * @param size Buffer size, in bytes.
7922 * @param rsp DMA memory for the ELS response.
7923 * @param rsp_len Length of ELS response, in bytes.
7924 * @param xri XRI for this exchange.
7925 * @param tag IO tag value.
7926 * @param cq_id The id of the completion queue where the WQE response is sent.
7927 * @param ox_id OX_ID of the exchange containing the request.
7928 * @param rnode Destination of the ELS response (that is, the remote node).
7929 * @param flags Optional attributes, including:
7930 * - SLI4_IO_CONTINUATION - IO is already active.
7931 * @param s_id S_ID used for special responses.
7932 *
7933 * @return Returns 0 on success, or a non-zero value on failure.
7934 */
7935 int32_t
sli_xmit_els_rsp64_wqe(sli4_t * sli4,void * buf,size_t size,ocs_dma_t * rsp,uint32_t rsp_len,uint16_t xri,uint16_t tag,uint16_t cq_id,uint16_t ox_id,ocs_remote_node_t * rnode,uint32_t flags,uint32_t s_id)7936 sli_xmit_els_rsp64_wqe(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *rsp,
7937 uint32_t rsp_len, uint16_t xri, uint16_t tag, uint16_t cq_id,
7938 uint16_t ox_id, ocs_remote_node_t *rnode, uint32_t flags, uint32_t s_id)
7939 {
7940 sli4_xmit_els_rsp64_wqe_t *els = buf;
7941
7942 ocs_memset(buf, 0, size);
7943
7944 if (sli4->config.sgl_pre_registered) {
7945 els->dbde = TRUE;
7946 } else {
7947 els->xbl = TRUE;
7948 }
7949
7950 els->els_response_payload.bde_type = SLI4_BDE_TYPE_BDE_64;
7951 els->els_response_payload.buffer_length = rsp_len;
7952 els->els_response_payload.u.data.buffer_address_low = ocs_addr32_lo(rsp->phys);
7953 els->els_response_payload.u.data.buffer_address_high = ocs_addr32_hi(rsp->phys);
7954
7955 els->els_response_payload_length = rsp_len;
7956
7957 els->xri_tag = xri;
7958
7959 els->class = SLI4_ELS_REQUEST64_CLASS_3;
7960
7961 els->command = SLI4_WQE_ELS_RSP64;
7962
7963 els->request_tag = tag;
7964
7965 els->ox_id = ox_id;
7966
7967 els->iod = SLI4_ELS_REQUEST64_DIR_WRITE;
7968
7969 els->qosd = TRUE;
7970
7971 if (flags & SLI4_IO_CONTINUATION) {
7972 els->xc = TRUE;
7973 }
7974
7975 if (rnode->attached) {
7976 els->ct = SLI4_ELS_REQUEST64_CONTEXT_RPI;
7977 els->context_tag = rnode->indicator;
7978 } else {
7979 els->ct = SLI4_ELS_REQUEST64_CONTEXT_VPI;
7980 els->context_tag = rnode->sport->indicator;
7981 els->remote_id = rnode->fc_id & 0x00ffffff;
7982 els->temporary_rpi = rnode->indicator;
7983 if (UINT32_MAX != s_id) {
7984 els->sp = TRUE;
7985 els->s_id = s_id & 0x00ffffff;
7986 }
7987 }
7988
7989 if (rnode->node_group) {
7990 els->hlm = TRUE;
7991 els->remote_id = rnode->fc_id & 0x00ffffff;
7992 }
7993
7994 els->cmd_type = SLI4_ELS_REQUEST64_CMD_GEN;
7995
7996 els->cq_id = cq_id;
7997
7998 return 0;
7999 }
8000
8001 /**
8002 * @ingroup sli_fc
8003 * @brief Process an asynchronous Link State event entry.
8004 *
8005 * @par Description
8006 * Parses Asynchronous Completion Queue Entry (ACQE),
8007 * creates an abstracted event, and calls registered callback functions.
8008 *
8009 * @param sli4 SLI context.
8010 * @param acqe Pointer to the ACQE.
8011 *
8012 * @return Returns 0 on success, or a non-zero value on failure.
8013 */
8014 int32_t
sli_fc_process_link_state(sli4_t * sli4,void * acqe)8015 sli_fc_process_link_state(sli4_t *sli4, void *acqe)
8016 {
8017 sli4_link_state_t *link_state = acqe;
8018 sli4_link_event_t event = { 0 };
8019 int32_t rc = 0;
8020
8021 if (!sli4->link) {
8022 /* bail if there is no callback */
8023 return 0;
8024 }
8025
8026 if (SLI4_LINK_TYPE_ETHERNET == link_state->link_type) {
8027 event.topology = SLI_LINK_TOPO_NPORT;
8028 event.medium = SLI_LINK_MEDIUM_ETHERNET;
8029 } else {
8030 /* TODO is this supported for anything other than FCoE? */
8031 ocs_log_test(sli4->os, "unsupported link type %#x\n",
8032 link_state->link_type);
8033 event.topology = SLI_LINK_TOPO_MAX;
8034 event.medium = SLI_LINK_MEDIUM_MAX;
8035 rc = -1;
8036 }
8037
8038 switch (link_state->port_link_status) {
8039 case SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN:
8040 case SLI4_PORT_LINK_STATUS_LOGICAL_DOWN:
8041 event.status = SLI_LINK_STATUS_DOWN;
8042 break;
8043 case SLI4_PORT_LINK_STATUS_PHYSICAL_UP:
8044 case SLI4_PORT_LINK_STATUS_LOGICAL_UP:
8045 event.status = SLI_LINK_STATUS_UP;
8046 break;
8047 default:
8048 ocs_log_test(sli4->os, "unsupported link status %#x\n",
8049 link_state->port_link_status);
8050 event.status = SLI_LINK_STATUS_MAX;
8051 rc = -1;
8052 }
8053
8054 switch (link_state->port_speed) {
8055 case 0:
8056 event.speed = 0;
8057 break;
8058 case 1:
8059 event.speed = 10;
8060 break;
8061 case 2:
8062 event.speed = 100;
8063 break;
8064 case 3:
8065 event.speed = 1000;
8066 break;
8067 case 4:
8068 event.speed = 10000;
8069 break;
8070 case 5:
8071 event.speed = 20000;
8072 break;
8073 case 6:
8074 event.speed = 25000;
8075 break;
8076 case 7:
8077 event.speed = 40000;
8078 break;
8079 case 8:
8080 event.speed = 100000;
8081 break;
8082 default:
8083 ocs_log_test(sli4->os, "unsupported port_speed %#x\n",
8084 link_state->port_speed);
8085 rc = -1;
8086 }
8087
8088 sli4->link(sli4->link_arg, (void *)&event);
8089
8090 return rc;
8091 }
8092
8093 /**
8094 * @ingroup sli_fc
8095 * @brief Process an asynchronous Link Attention event entry.
8096 *
8097 * @par Description
8098 * Parses Asynchronous Completion Queue Entry (ACQE),
8099 * creates an abstracted event, and calls the registered callback functions.
8100 *
8101 * @param sli4 SLI context.
8102 * @param acqe Pointer to the ACQE.
8103 *
8104 * @todo XXX all events return LINK_UP.
8105 *
8106 * @return Returns 0 on success, or a non-zero value on failure.
8107 */
8108 int32_t
sli_fc_process_link_attention(sli4_t * sli4,void * acqe)8109 sli_fc_process_link_attention(sli4_t *sli4, void *acqe)
8110 {
8111 sli4_link_attention_t *link_attn = acqe;
8112 sli4_link_event_t event = { 0 };
8113
8114 ocs_log_debug(sli4->os, "link_number=%d attn_type=%#x topology=%#x port_speed=%#x "
8115 "port_fault=%#x shared_link_status=%#x logical_link_speed=%#x "
8116 "event_tag=%#x\n", link_attn->link_number, link_attn->attn_type,
8117 link_attn->topology, link_attn->port_speed, link_attn->port_fault,
8118 link_attn->shared_link_status, link_attn->logical_link_speed,
8119 link_attn->event_tag);
8120
8121 if (!sli4->link) {
8122 return 0;
8123 }
8124
8125 event.medium = SLI_LINK_MEDIUM_FC;
8126
8127 switch (link_attn->attn_type) {
8128 case SLI4_LINK_ATTN_TYPE_LINK_UP:
8129 event.status = SLI_LINK_STATUS_UP;
8130 break;
8131 case SLI4_LINK_ATTN_TYPE_LINK_DOWN:
8132 event.status = SLI_LINK_STATUS_DOWN;
8133 break;
8134 case SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA:
8135 ocs_log_debug(sli4->os, "attn_type: no hard alpa\n");
8136 event.status = SLI_LINK_STATUS_NO_ALPA;
8137 break;
8138 default:
8139 ocs_log_test(sli4->os, "attn_type: unknown\n");
8140 break;
8141 }
8142
8143 switch (link_attn->event_type) {
8144 case SLI4_FC_EVENT_LINK_ATTENTION:
8145 break;
8146 case SLI4_FC_EVENT_SHARED_LINK_ATTENTION:
8147 ocs_log_debug(sli4->os, "event_type: FC shared link event \n");
8148 break;
8149 default:
8150 ocs_log_test(sli4->os, "event_type: unknown\n");
8151 break;
8152 }
8153
8154 switch (link_attn->topology) {
8155 case SLI4_LINK_ATTN_P2P:
8156 event.topology = SLI_LINK_TOPO_NPORT;
8157 break;
8158 case SLI4_LINK_ATTN_FC_AL:
8159 event.topology = SLI_LINK_TOPO_LOOP;
8160 break;
8161 case SLI4_LINK_ATTN_INTERNAL_LOOPBACK:
8162 ocs_log_debug(sli4->os, "topology Internal loopback\n");
8163 event.topology = SLI_LINK_TOPO_LOOPBACK_INTERNAL;
8164 break;
8165 case SLI4_LINK_ATTN_SERDES_LOOPBACK:
8166 ocs_log_debug(sli4->os, "topology serdes loopback\n");
8167 event.topology = SLI_LINK_TOPO_LOOPBACK_EXTERNAL;
8168 break;
8169 default:
8170 ocs_log_test(sli4->os, "topology: unknown\n");
8171 break;
8172 }
8173
8174 event.speed = link_attn->port_speed * 1000;
8175
8176 sli4->link(sli4->link_arg, (void *)&event);
8177
8178 return 0;
8179 }
8180
8181 /**
8182 * @ingroup sli_fc
8183 * @brief Parse an FC/FCoE work queue CQ entry.
8184 *
8185 * @param sli4 SLI context.
8186 * @param cq CQ to process.
8187 * @param cqe Pointer to the CQ entry.
8188 * @param etype CQ event type.
8189 * @param r_id Resource ID associated with this completion message (such as the IO tag).
8190 *
8191 * @return Returns 0 on success, or a non-zero value on failure.
8192 */
8193 int32_t
sli_fc_cqe_parse(sli4_t * sli4,sli4_queue_t * cq,uint8_t * cqe,sli4_qentry_e * etype,uint16_t * r_id)8194 sli_fc_cqe_parse(sli4_t *sli4, sli4_queue_t *cq, uint8_t *cqe, sli4_qentry_e *etype,
8195 uint16_t *r_id)
8196 {
8197 uint8_t code = cqe[SLI4_CQE_CODE_OFFSET];
8198 int32_t rc = -1;
8199
8200 switch (code) {
8201 case SLI4_CQE_CODE_WORK_REQUEST_COMPLETION:
8202 {
8203 sli4_fc_wcqe_t *wcqe = (void *)cqe;
8204
8205 *etype = SLI_QENTRY_WQ;
8206 *r_id = wcqe->request_tag;
8207 rc = wcqe->status;
8208
8209 /* Flag errors except for FCP_RSP_FAILURE */
8210 if (rc && (rc != SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE)) {
8211
8212 ocs_log_test(sli4->os, "WCQE: status=%#x hw_status=%#x tag=%#x w1=%#x w2=%#x xb=%d\n",
8213 wcqe->status, wcqe->hw_status,
8214 wcqe->request_tag, wcqe->wqe_specific_1,
8215 wcqe->wqe_specific_2, wcqe->xb);
8216 ocs_log_test(sli4->os, " %08X %08X %08X %08X\n", ((uint32_t*) cqe)[0], ((uint32_t*) cqe)[1],
8217 ((uint32_t*) cqe)[2], ((uint32_t*) cqe)[3]);
8218 }
8219
8220 /* TODO: need to pass additional status back out of here as well
8221 * as status (could overload rc as status/addlstatus are only 8 bits each)
8222 */
8223
8224 break;
8225 }
8226 case SLI4_CQE_CODE_RQ_ASYNC:
8227 {
8228 sli4_fc_async_rcqe_t *rcqe = (void *)cqe;
8229
8230 *etype = SLI_QENTRY_RQ;
8231 *r_id = rcqe->rq_id;
8232 rc = rcqe->status;
8233 break;
8234 }
8235 case SLI4_CQE_CODE_RQ_ASYNC_V1:
8236 {
8237 sli4_fc_async_rcqe_v1_t *rcqe = (void *)cqe;
8238
8239 *etype = SLI_QENTRY_RQ;
8240 *r_id = rcqe->rq_id;
8241 rc = rcqe->status;
8242 break;
8243 }
8244 case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD:
8245 {
8246 sli4_fc_optimized_write_cmd_cqe_t *optcqe = (void *)cqe;
8247
8248 *etype = SLI_QENTRY_OPT_WRITE_CMD;
8249 *r_id = optcqe->rq_id;
8250 rc = optcqe->status;
8251 break;
8252 }
8253 case SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA:
8254 {
8255 sli4_fc_optimized_write_data_cqe_t *dcqe = (void *)cqe;
8256
8257 *etype = SLI_QENTRY_OPT_WRITE_DATA;
8258 *r_id = dcqe->xri;
8259 rc = dcqe->status;
8260
8261 /* Flag errors */
8262 if (rc != SLI4_FC_WCQE_STATUS_SUCCESS) {
8263 ocs_log_test(sli4->os, "Optimized DATA CQE: status=%#x hw_status=%#x xri=%#x dpl=%#x w3=%#x xb=%d\n",
8264 dcqe->status, dcqe->hw_status,
8265 dcqe->xri, dcqe->total_data_placed,
8266 ((uint32_t*) cqe)[3], dcqe->xb);
8267 }
8268 break;
8269 }
8270 case SLI4_CQE_CODE_RQ_COALESCING:
8271 {
8272 sli4_fc_coalescing_rcqe_t *rcqe = (void *)cqe;
8273
8274 *etype = SLI_QENTRY_RQ;
8275 *r_id = rcqe->rq_id;
8276 rc = rcqe->status;
8277 break;
8278 }
8279 case SLI4_CQE_CODE_XRI_ABORTED:
8280 {
8281 sli4_fc_xri_aborted_cqe_t *xa = (void *)cqe;
8282
8283 *etype = SLI_QENTRY_XABT;
8284 *r_id = xa->xri;
8285 rc = 0;
8286 break;
8287 }
8288 case SLI4_CQE_CODE_RELEASE_WQE: {
8289 sli4_fc_wqec_t *wqec = (void*) cqe;
8290
8291 *etype = SLI_QENTRY_WQ_RELEASE;
8292 *r_id = wqec->wq_id;
8293 rc = 0;
8294 break;
8295 }
8296 default:
8297 ocs_log_test(sli4->os, "CQE completion code %d not handled\n", code);
8298 *etype = SLI_QENTRY_MAX;
8299 *r_id = UINT16_MAX;
8300 }
8301
8302 return rc;
8303 }
8304
8305 /**
8306 * @ingroup sli_fc
8307 * @brief Return the ELS/CT response length.
8308 *
8309 * @param sli4 SLI context.
8310 * @param cqe Pointer to the CQ entry.
8311 *
8312 * @return Returns the length, in bytes.
8313 */
8314 uint32_t
sli_fc_response_length(sli4_t * sli4,uint8_t * cqe)8315 sli_fc_response_length(sli4_t *sli4, uint8_t *cqe)
8316 {
8317 sli4_fc_wcqe_t *wcqe = (void *)cqe;
8318
8319 return wcqe->wqe_specific_1;
8320 }
8321
8322 /**
8323 * @ingroup sli_fc
8324 * @brief Return the FCP IO length.
8325 *
8326 * @param sli4 SLI context.
8327 * @param cqe Pointer to the CQ entry.
8328 *
8329 * @return Returns the length, in bytes.
8330 */
8331 uint32_t
sli_fc_io_length(sli4_t * sli4,uint8_t * cqe)8332 sli_fc_io_length(sli4_t *sli4, uint8_t *cqe)
8333 {
8334 sli4_fc_wcqe_t *wcqe = (void *)cqe;
8335
8336 return wcqe->wqe_specific_1;
8337 }
8338
8339 /**
8340 * @ingroup sli_fc
8341 * @brief Retrieve the D_ID from the completion.
8342 *
8343 * @param sli4 SLI context.
8344 * @param cqe Pointer to the CQ entry.
8345 * @param d_id Pointer where the D_ID is written.
8346 *
8347 * @return Returns 0 on success, or a non-zero value on failure.
8348 */
8349 int32_t
sli_fc_els_did(sli4_t * sli4,uint8_t * cqe,uint32_t * d_id)8350 sli_fc_els_did(sli4_t *sli4, uint8_t *cqe, uint32_t *d_id)
8351 {
8352 sli4_fc_wcqe_t *wcqe = (void *)cqe;
8353
8354 *d_id = 0;
8355
8356 if (wcqe->status) {
8357 return -1;
8358 } else {
8359 *d_id = wcqe->wqe_specific_2 & 0x00ffffff;
8360 return 0;
8361 }
8362 }
8363
8364 uint32_t
sli_fc_ext_status(sli4_t * sli4,uint8_t * cqe)8365 sli_fc_ext_status(sli4_t *sli4, uint8_t *cqe)
8366 {
8367 sli4_fc_wcqe_t *wcqe = (void *)cqe;
8368 uint32_t mask;
8369
8370 switch (wcqe->status) {
8371 case SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE:
8372 mask = UINT32_MAX;
8373 break;
8374 case SLI4_FC_WCQE_STATUS_LOCAL_REJECT:
8375 case SLI4_FC_WCQE_STATUS_CMD_REJECT:
8376 mask = 0xff;
8377 break;
8378 case SLI4_FC_WCQE_STATUS_NPORT_RJT:
8379 case SLI4_FC_WCQE_STATUS_FABRIC_RJT:
8380 case SLI4_FC_WCQE_STATUS_NPORT_BSY:
8381 case SLI4_FC_WCQE_STATUS_FABRIC_BSY:
8382 case SLI4_FC_WCQE_STATUS_LS_RJT:
8383 mask = UINT32_MAX;
8384 break;
8385 case SLI4_FC_WCQE_STATUS_DI_ERROR:
8386 mask = UINT32_MAX;
8387 break;
8388 default:
8389 mask = 0;
8390 }
8391
8392 return wcqe->wqe_specific_2 & mask;
8393 }
8394
8395 /**
8396 * @ingroup sli_fc
8397 * @brief Retrieve the RQ index from the completion.
8398 *
8399 * @param sli4 SLI context.
8400 * @param cqe Pointer to the CQ entry.
8401 * @param rq_id Pointer where the rq_id is written.
8402 * @param index Pointer where the index is written.
8403 *
8404 * @return Returns 0 on success, or a non-zero value on failure.
8405 */
8406 int32_t
sli_fc_rqe_rqid_and_index(sli4_t * sli4,uint8_t * cqe,uint16_t * rq_id,uint32_t * index)8407 sli_fc_rqe_rqid_and_index(sli4_t *sli4, uint8_t *cqe, uint16_t *rq_id, uint32_t *index)
8408 {
8409 sli4_fc_async_rcqe_t *rcqe = (void *)cqe;
8410 sli4_fc_async_rcqe_v1_t *rcqe_v1 = (void *)cqe;
8411 int32_t rc = -1;
8412 uint8_t code = 0;
8413
8414 *rq_id = 0;
8415 *index = UINT32_MAX;
8416
8417 code = cqe[SLI4_CQE_CODE_OFFSET];
8418
8419 if (code == SLI4_CQE_CODE_RQ_ASYNC) {
8420 *rq_id = rcqe->rq_id;
8421 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) {
8422 *index = rcqe->rq_element_index;
8423 rc = 0;
8424 } else {
8425 *index = rcqe->rq_element_index;
8426 rc = rcqe->status;
8427 ocs_log_test(sli4->os, "status=%02x (%s) rq_id=%d, index=%x pdpl=%x sof=%02x eof=%02x hdpl=%x\n",
8428 rcqe->status, sli_fc_get_status_string(rcqe->status), rcqe->rq_id,
8429 rcqe->rq_element_index, rcqe->payload_data_placement_length, rcqe->sof_byte,
8430 rcqe->eof_byte, rcqe->header_data_placement_length);
8431 }
8432 } else if (code == SLI4_CQE_CODE_RQ_ASYNC_V1) {
8433 *rq_id = rcqe_v1->rq_id;
8434 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe_v1->status) {
8435 *index = rcqe_v1->rq_element_index;
8436 rc = 0;
8437 } else {
8438 *index = rcqe_v1->rq_element_index;
8439 rc = rcqe_v1->status;
8440 ocs_log_test(sli4->os, "status=%02x (%s) rq_id=%d, index=%x pdpl=%x sof=%02x eof=%02x hdpl=%x\n",
8441 rcqe_v1->status, sli_fc_get_status_string(rcqe_v1->status),
8442 rcqe_v1->rq_id, rcqe_v1->rq_element_index,
8443 rcqe_v1->payload_data_placement_length, rcqe_v1->sof_byte,
8444 rcqe_v1->eof_byte, rcqe_v1->header_data_placement_length);
8445 }
8446 } else if (code == SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD) {
8447 sli4_fc_optimized_write_cmd_cqe_t *optcqe = (void *)cqe;
8448
8449 *rq_id = optcqe->rq_id;
8450 if (SLI4_FC_ASYNC_RQ_SUCCESS == optcqe->status) {
8451 *index = optcqe->rq_element_index;
8452 rc = 0;
8453 } else {
8454 *index = optcqe->rq_element_index;
8455 rc = optcqe->status;
8456 ocs_log_test(sli4->os, "status=%02x (%s) rq_id=%d, index=%x pdpl=%x hdpl=%x oox=%d agxr=%d xri=0x%x rpi=0x%x\n",
8457 optcqe->status, sli_fc_get_status_string(optcqe->status), optcqe->rq_id,
8458 optcqe->rq_element_index, optcqe->payload_data_placement_length,
8459 optcqe->header_data_placement_length, optcqe->oox, optcqe->agxr, optcqe->xri,
8460 optcqe->rpi);
8461 }
8462 } else if (code == SLI4_CQE_CODE_RQ_COALESCING) {
8463 sli4_fc_coalescing_rcqe_t *rcqe = (void *)cqe;
8464
8465 *rq_id = rcqe->rq_id;
8466 if (SLI4_FC_COALESCE_RQ_SUCCESS == rcqe->status) {
8467 *index = rcqe->rq_element_index;
8468 rc = 0;
8469 } else {
8470 *index = UINT32_MAX;
8471 rc = rcqe->status;
8472
8473 ocs_log_test(sli4->os, "status=%02x (%s) rq_id=%d, index=%x rq_id=%#x sdpl=%x\n",
8474 rcqe->status, sli_fc_get_status_string(rcqe->status), rcqe->rq_id,
8475 rcqe->rq_element_index, rcqe->rq_id, rcqe->sequence_reporting_placement_length);
8476 }
8477 } else {
8478 *index = UINT32_MAX;
8479
8480 rc = rcqe->status;
8481
8482 ocs_log_debug(sli4->os, "status=%02x rq_id=%d, index=%x pdpl=%x sof=%02x eof=%02x hdpl=%x\n",
8483 rcqe->status, rcqe->rq_id, rcqe->rq_element_index, rcqe->payload_data_placement_length,
8484 rcqe->sof_byte, rcqe->eof_byte, rcqe->header_data_placement_length);
8485 }
8486
8487 return rc;
8488 }
8489
8490 /**
8491 * @ingroup sli_fc
8492 * @brief Process an asynchronous FCoE event entry.
8493 *
8494 * @par Description
8495 * Parses Asynchronous Completion Queue Entry (ACQE),
8496 * creates an abstracted event, and calls the registered callback functions.
8497 *
8498 * @param sli4 SLI context.
8499 * @param acqe Pointer to the ACQE.
8500 *
8501 * @return Returns 0 on success, or a non-zero value on failure.
8502 */
8503 int32_t
sli_fc_process_fcoe(sli4_t * sli4,void * acqe)8504 sli_fc_process_fcoe(sli4_t *sli4, void *acqe)
8505 {
8506 sli4_fcoe_fip_t *fcoe = acqe;
8507 sli4_fip_event_t event = { 0 };
8508 uint32_t mask = UINT32_MAX;
8509
8510 ocs_log_debug(sli4->os, "ACQE FCoE FIP type=%02x count=%d tag=%#x\n",
8511 fcoe->event_type,
8512 fcoe->fcf_count,
8513 fcoe->event_tag);
8514
8515 if (!sli4->fip) {
8516 return 0;
8517 }
8518
8519 event.type = fcoe->event_type;
8520 event.index = UINT32_MAX;
8521
8522 switch (fcoe->event_type) {
8523 case SLI4_FCOE_FIP_FCF_DISCOVERED:
8524 ocs_log_debug(sli4->os, "FCF Discovered index=%d\n", fcoe->event_information);
8525 break;
8526 case SLI4_FCOE_FIP_FCF_TABLE_FULL:
8527 ocs_log_debug(sli4->os, "FCF Table Full\n");
8528 mask = 0;
8529 break;
8530 case SLI4_FCOE_FIP_FCF_DEAD:
8531 ocs_log_debug(sli4->os, "FCF Dead/Gone index=%d\n", fcoe->event_information);
8532 break;
8533 case SLI4_FCOE_FIP_FCF_CLEAR_VLINK:
8534 mask = UINT16_MAX;
8535 ocs_log_debug(sli4->os, "Clear VLINK Received VPI=%#x\n", fcoe->event_information & mask);
8536 break;
8537 case SLI4_FCOE_FIP_FCF_MODIFIED:
8538 ocs_log_debug(sli4->os, "FCF Modified\n");
8539 break;
8540 default:
8541 ocs_log_test(sli4->os, "bad FCoE type %#x", fcoe->event_type);
8542 mask = 0;
8543 }
8544
8545 if (mask != 0) {
8546 event.index = fcoe->event_information & mask;
8547 }
8548
8549 sli4->fip(sli4->fip_arg, &event);
8550
8551 return 0;
8552 }
8553
8554 /**
8555 * @ingroup sli_fc
8556 * @brief Allocate a receive queue.
8557 *
8558 * @par Description
8559 * Allocates DMA memory and configures the requested queue type.
8560 *
8561 * @param sli4 SLI context.
8562 * @param q Pointer to the queue object for the header.
8563 * @param n_entries Number of entries to allocate.
8564 * @param buffer_size buffer size for the queue.
8565 * @param cq Associated CQ.
8566 * @param ulp The ULP to bind
8567 * @param is_hdr Used to validate the rq_id and set the type of queue
8568 *
8569 * @return Returns 0 on success, or -1 on failure.
8570 */
8571 int32_t
sli_fc_rq_alloc(sli4_t * sli4,sli4_queue_t * q,uint32_t n_entries,uint32_t buffer_size,sli4_queue_t * cq,uint16_t ulp,uint8_t is_hdr)8572 sli_fc_rq_alloc(sli4_t *sli4, sli4_queue_t *q,
8573 uint32_t n_entries, uint32_t buffer_size,
8574 sli4_queue_t *cq, uint16_t ulp, uint8_t is_hdr)
8575 {
8576 int32_t (*rq_create)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
8577
8578 if ((sli4 == NULL) || (q == NULL)) {
8579 void *os = sli4 != NULL ? sli4->os : NULL;
8580
8581 ocs_log_err(os, "bad parameter sli4=%p q=%p\n", sli4, q);
8582 return -1;
8583 }
8584
8585 if (__sli_queue_init(sli4, q, SLI_QTYPE_RQ, SLI4_FCOE_RQE_SIZE,
8586 n_entries, SLI_PAGE_SIZE)) {
8587 return -1;
8588 }
8589
8590 if (sli4->if_type == SLI4_IF_TYPE_BE3_SKH_PF) {
8591 rq_create = sli_cmd_fcoe_rq_create;
8592 } else {
8593 rq_create = sli_cmd_fcoe_rq_create_v1;
8594 }
8595
8596 if (rq_create(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE, &q->dma,
8597 cq->id, ulp, buffer_size)) {
8598 if (__sli_create_queue(sli4, q)) {
8599 ocs_dma_free(sli4->os, &q->dma);
8600 return -1;
8601 }
8602 if (is_hdr && q->id & 1) {
8603 ocs_log_test(sli4->os, "bad header RQ_ID %d\n", q->id);
8604 ocs_dma_free(sli4->os, &q->dma);
8605 return -1;
8606 } else if (!is_hdr && (q->id & 1) == 0) {
8607 ocs_log_test(sli4->os, "bad data RQ_ID %d\n", q->id);
8608 ocs_dma_free(sli4->os, &q->dma);
8609 return -1;
8610 }
8611 } else {
8612 return -1;
8613 }
8614 q->u.flag.is_hdr = is_hdr;
8615 if (SLI4_IF_TYPE_BE3_SKH_PF == sli4->if_type) {
8616 q->u.flag.rq_batch = TRUE;
8617 }
8618 return 0;
8619 }
8620
8621
8622 /**
8623 * @ingroup sli_fc
8624 * @brief Allocate a receive queue set.
8625 *
8626 * @param sli4 SLI context.
8627 * @param num_rq_pairs to create
8628 * @param qs Pointers to the queue objects for both header and data.
8629 * Length of this arrays should be 2 * num_rq_pairs
8630 * @param base_cq_id. Assumes base_cq_id : (base_cq_id + num_rq_pairs) cqs as allotted.
8631 * @param n_entries number of entries in each RQ queue.
8632 * @param header_buffer_size
8633 * @param payload_buffer_size
8634 * @param ulp The ULP to bind
8635 *
8636 * @return Returns 0 on success, or -1 on failure.
8637 */
8638 int32_t
sli_fc_rq_set_alloc(sli4_t * sli4,uint32_t num_rq_pairs,sli4_queue_t * qs[],uint32_t base_cq_id,uint32_t n_entries,uint32_t header_buffer_size,uint32_t payload_buffer_size,uint16_t ulp)8639 sli_fc_rq_set_alloc(sli4_t *sli4, uint32_t num_rq_pairs,
8640 sli4_queue_t *qs[], uint32_t base_cq_id,
8641 uint32_t n_entries, uint32_t header_buffer_size,
8642 uint32_t payload_buffer_size, uint16_t ulp)
8643 {
8644 uint32_t i, p, offset = 0;
8645 uint32_t payload_size, total_page_count = 0;
8646 uintptr_t addr;
8647 ocs_dma_t dma;
8648 sli4_res_common_create_queue_set_t *rsp = NULL;
8649 sli4_req_fcoe_rq_create_v2_t *req = NULL;
8650
8651 for (i = 0; i < (num_rq_pairs * 2); i++) {
8652 if (__sli_queue_init(sli4, qs[i], SLI_QTYPE_RQ, SLI4_FCOE_RQE_SIZE,
8653 n_entries, SLI_PAGE_SIZE)) {
8654 goto error;
8655 }
8656 }
8657
8658 total_page_count = sli_page_count(qs[0]->dma.size, SLI_PAGE_SIZE) * num_rq_pairs * 2;
8659
8660 /* Payload length must accommodate both request and response */
8661 payload_size = max((sizeof(sli4_req_fcoe_rq_create_v1_t) + (8 * total_page_count)),
8662 sizeof(sli4_res_common_create_queue_set_t));
8663
8664 if (ocs_dma_alloc(sli4->os, &dma, payload_size, SLI_PAGE_SIZE)) {
8665 ocs_log_err(sli4->os, "DMA allocation failed\n");
8666 goto error;
8667 }
8668 ocs_memset(dma.virt, 0, payload_size);
8669
8670 if (sli_cmd_sli_config(sli4, sli4->bmbx.virt, SLI4_BMBX_SIZE,
8671 payload_size, &dma) == -1) {
8672 goto error;
8673 }
8674 req = (sli4_req_fcoe_rq_create_v2_t *)((uint8_t *)dma.virt);
8675
8676 /* Fill Header fields */
8677 req->hdr.opcode = SLI4_OPC_FCOE_RQ_CREATE;
8678 req->hdr.subsystem = SLI4_SUBSYSTEM_FCFCOE;
8679 req->hdr.version = 2;
8680 req->hdr.request_length = sizeof(sli4_req_fcoe_rq_create_v2_t) - sizeof(sli4_req_hdr_t)
8681 + (8 * total_page_count);
8682
8683 /* Fill Payload fields */
8684 req->dnb = TRUE;
8685 req->num_pages = sli_page_count(qs[0]->dma.size, SLI_PAGE_SIZE);
8686 req->rqe_count = qs[0]->dma.size / SLI4_FCOE_RQE_SIZE;
8687 req->rqe_size = SLI4_FCOE_RQE_SIZE_8;
8688 req->page_size = SLI4_FCOE_RQ_PAGE_SIZE_4096;
8689 req->rq_count = num_rq_pairs * 2;
8690 req->base_cq_id = base_cq_id;
8691 req->hdr_buffer_size = header_buffer_size;
8692 req->payload_buffer_size = payload_buffer_size;
8693
8694 for (i = 0; i < (num_rq_pairs * 2); i++) {
8695 for (p = 0, addr = qs[i]->dma.phys; p < req->num_pages; p++, addr += SLI_PAGE_SIZE) {
8696 req->page_physical_address[offset].low = ocs_addr32_lo(addr);
8697 req->page_physical_address[offset].high = ocs_addr32_hi(addr);
8698 offset++;
8699 }
8700 }
8701
8702 if (sli_bmbx_command(sli4)){
8703 ocs_log_crit(sli4->os, "bootstrap mailbox write failed RQSet\n");
8704 goto error;
8705 }
8706
8707
8708 rsp = (void *)((uint8_t *)dma.virt);
8709 if (rsp->hdr.status) {
8710 ocs_log_err(sli4->os, "bad create RQSet status=%#x addl=%#x\n",
8711 rsp->hdr.status, rsp->hdr.additional_status);
8712 goto error;
8713 } else {
8714 for (i = 0; i < (num_rq_pairs * 2); i++) {
8715 qs[i]->id = i + rsp->q_id;
8716 if ((qs[i]->id & 1) == 0) {
8717 qs[i]->u.flag.is_hdr = TRUE;
8718 } else {
8719 qs[i]->u.flag.is_hdr = FALSE;
8720 }
8721 qs[i]->doorbell_offset = regmap[SLI4_REG_FCOE_RQ_DOORBELL][sli4->if_type].off;
8722 qs[i]->doorbell_rset = regmap[SLI4_REG_FCOE_RQ_DOORBELL][sli4->if_type].rset;
8723 }
8724 }
8725
8726 ocs_dma_free(sli4->os, &dma);
8727
8728 return 0;
8729
8730 error:
8731 for (i = 0; i < (num_rq_pairs * 2); i++) {
8732 if (qs[i]->dma.size) {
8733 ocs_dma_free(sli4->os, &qs[i]->dma);
8734 }
8735 }
8736
8737 if (dma.size) {
8738 ocs_dma_free(sli4->os, &dma);
8739 }
8740
8741 return -1;
8742 }
8743
8744 /**
8745 * @ingroup sli_fc
8746 * @brief Get the RPI resource requirements.
8747 *
8748 * @param sli4 SLI context.
8749 * @param n_rpi Number of RPIs desired.
8750 *
8751 * @return Returns the number of bytes needed. This value may be zero.
8752 */
8753 uint32_t
sli_fc_get_rpi_requirements(sli4_t * sli4,uint32_t n_rpi)8754 sli_fc_get_rpi_requirements(sli4_t *sli4, uint32_t n_rpi)
8755 {
8756 uint32_t bytes = 0;
8757
8758 /* Check if header templates needed */
8759 if (sli4->config.hdr_template_req) {
8760 /* round up to a page */
8761 bytes = SLI_ROUND_PAGE(n_rpi * SLI4_FCOE_HDR_TEMPLATE_SIZE);
8762 }
8763
8764 return bytes;
8765 }
8766
8767 /**
8768 * @ingroup sli_fc
8769 * @brief Return a text string corresponding to a CQE status value
8770 *
8771 * @param status Status value
8772 *
8773 * @return Returns corresponding string, otherwise "unknown"
8774 */
8775 const char *
sli_fc_get_status_string(uint32_t status)8776 sli_fc_get_status_string(uint32_t status)
8777 {
8778 static struct {
8779 uint32_t code;
8780 const char *label;
8781 } lookup[] = {
8782 {SLI4_FC_WCQE_STATUS_SUCCESS, "SUCCESS"},
8783 {SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE, "FCP_RSP_FAILURE"},
8784 {SLI4_FC_WCQE_STATUS_REMOTE_STOP, "REMOTE_STOP"},
8785 {SLI4_FC_WCQE_STATUS_LOCAL_REJECT, "LOCAL_REJECT"},
8786 {SLI4_FC_WCQE_STATUS_NPORT_RJT, "NPORT_RJT"},
8787 {SLI4_FC_WCQE_STATUS_FABRIC_RJT, "FABRIC_RJT"},
8788 {SLI4_FC_WCQE_STATUS_NPORT_BSY, "NPORT_BSY"},
8789 {SLI4_FC_WCQE_STATUS_FABRIC_BSY, "FABRIC_BSY"},
8790 {SLI4_FC_WCQE_STATUS_LS_RJT, "LS_RJT"},
8791 {SLI4_FC_WCQE_STATUS_CMD_REJECT, "CMD_REJECT"},
8792 {SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK, "FCP_TGT_LENCHECK"},
8793 {SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED, "BUF_LEN_EXCEEDED"},
8794 {SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED, "RQ_INSUFF_BUF_NEEDED"},
8795 {SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC, "RQ_INSUFF_FRM_DESC"},
8796 {SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE, "RQ_DMA_FAILURE"},
8797 {SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE, "FCP_RSP_TRUNCATE"},
8798 {SLI4_FC_WCQE_STATUS_DI_ERROR, "DI_ERROR"},
8799 {SLI4_FC_WCQE_STATUS_BA_RJT, "BA_RJT"},
8800 {SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED, "RQ_INSUFF_XRI_NEEDED"},
8801 {SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC, "INSUFF_XRI_DISC"},
8802 {SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT, "RX_ERROR_DETECT"},
8803 {SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST, "RX_ABORT_REQUEST"},
8804 };
8805 uint32_t i;
8806
8807 for (i = 0; i < ARRAY_SIZE(lookup); i++) {
8808 if (status == lookup[i].code) {
8809 return lookup[i].label;
8810 }
8811 }
8812 return "unknown";
8813 }
8814