1 /*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 /*
34 * the Sonics Silicon Backplane driver.
35 */
36
37 #include "opt_siba.h"
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/kernel.h>
44 #include <sys/endian.h>
45 #include <sys/errno.h>
46 #include <sys/lock.h>
47 #include <sys/mutex.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <sys/bus.h>
51 #include <sys/rman.h>
52 #include <sys/socket.h>
53
54 #include <net/if.h>
55 #include <net/if_media.h>
56 #include <net/if_arp.h>
57
58 #include <dev/pci/pcivar.h>
59 #include <dev/pci/pcireg.h>
60
61 #include <dev/siba/siba_ids.h>
62 #include <dev/siba/sibareg.h>
63 #include <dev/siba/sibavar.h>
64
65 enum {
66 SIBA_DEBUG_SCAN = 0x00000001, /* scan */
67 SIBA_DEBUG_PMU = 0x00000002, /* PMU */
68 SIBA_DEBUG_PLL = 0x00000004, /* PLL */
69 SIBA_DEBUG_SWITCHCORE = 0x00000008, /* switching core */
70 SIBA_DEBUG_SPROM = 0x00000010, /* SPROM */
71 SIBA_DEBUG_CORE = 0x00000020, /* handling cores */
72 SIBA_DEBUG_DMA = 0x00000040, /* DMA bits */
73 SIBA_DEBUG_ANY = 0xffffffff
74 };
75
76 #ifdef SIBA_DEBUG
77 #define DPRINTF(siba, m, ...) do { \
78 if (siba->siba_debug & (m)) \
79 device_printf(siba->siba_dev, __VA_ARGS__); \
80 } while (0)
81 #else
82 #define DPRINTF(siba, m, ...) do { (void) siba; } while (0)
83 #endif
84
85 #define N(a) (sizeof(a) / sizeof(a[0]))
86
87 static void siba_pci_gpio(struct siba_softc *, uint32_t, int);
88 static void siba_scan(struct siba_softc *);
89 static int siba_switchcore(struct siba_softc *, uint8_t);
90 static int siba_pci_switchcore_sub(struct siba_softc *, uint8_t);
91 static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t);
92 static uint16_t siba_dev2chipid(struct siba_softc *);
93 static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t);
94 static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t);
95 static void siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t);
96 static void siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t);
97 static void siba_cc_clock(struct siba_cc *,
98 enum siba_clock);
99 static void siba_cc_pmu_init(struct siba_cc *);
100 static void siba_cc_power_init(struct siba_cc *);
101 static void siba_cc_powerup_delay(struct siba_cc *);
102 static int siba_cc_clockfreq(struct siba_cc *, int);
103 static void siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t);
104 static void siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t);
105 static enum siba_clksrc siba_cc_clksrc(struct siba_cc *);
106 static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t);
107 static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t);
108 static void siba_cc_pll_write(struct siba_cc *, uint32_t,
109 uint32_t);
110 static const struct siba_cc_pmu0_plltab *
111 siba_cc_pmu0_plltab_findentry(uint32_t);
112 static int siba_pci_sprom(struct siba_softc *, struct siba_sprom *);
113 static int siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t);
114 static int sprom_check_crc(const uint16_t *, size_t);
115 static uint8_t siba_crc8(uint8_t, uint8_t);
116 static void siba_sprom_r123(struct siba_sprom *, const uint16_t *);
117 static void siba_sprom_r45(struct siba_sprom *, const uint16_t *);
118 static void siba_sprom_r8(struct siba_sprom *, const uint16_t *);
119 static int8_t siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t,
120 uint16_t);
121 static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *);
122 static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t);
123 static void siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t);
124 static uint32_t siba_pcie_read(struct siba_pci *, uint32_t);
125 static void siba_pcie_write(struct siba_pci *, uint32_t, uint32_t);
126 static void siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t,
127 uint16_t);
128 static void siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t,
129 uint16_t);
130 static void siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t,
131 uint16_t);
132 static void siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t,
133 uint16_t);
134 static void siba_pci_write_multi_1(struct siba_dev_softc *, const void *,
135 size_t, uint16_t);
136 static void siba_pci_write_multi_2(struct siba_dev_softc *, const void *,
137 size_t, uint16_t);
138 static void siba_pci_write_multi_4(struct siba_dev_softc *, const void *,
139 size_t, uint16_t);
140 static const char *siba_core_name(uint16_t);
141 static void siba_pcicore_init(struct siba_pci *);
142 static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t);
143 static void siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t);
144 static void siba_powerup_sub(struct siba_softc *, int);
145 static int siba_powerdown_sub(struct siba_softc *);
146 static int siba_dev_isup_sub(struct siba_dev_softc *);
147 static void siba_dev_up_sub(struct siba_dev_softc *, uint32_t);
148 static void siba_dev_down_sub(struct siba_dev_softc *, uint32_t);
149 int siba_core_attach(struct siba_softc *);
150 int siba_core_detach(struct siba_softc *);
151 int siba_core_suspend(struct siba_softc *);
152 int siba_core_resume(struct siba_softc *);
153 uint8_t siba_getncores(device_t, uint16_t);
154
155 static const struct siba_bus_ops siba_pci_ops = {
156 .read_2 = siba_pci_read_2,
157 .read_4 = siba_pci_read_4,
158 .write_2 = siba_pci_write_2,
159 .write_4 = siba_pci_write_4,
160 .read_multi_1 = siba_pci_read_multi_1,
161 .read_multi_2 = siba_pci_read_multi_2,
162 .read_multi_4 = siba_pci_read_multi_4,
163 .write_multi_1 = siba_pci_write_multi_1,
164 .write_multi_2 = siba_pci_write_multi_2,
165 .write_multi_4 = siba_pci_write_multi_4,
166 };
167
168 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] =
169 SIBA_CC_PMU_4325_RES_UPDOWN;
170 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] =
171 SIBA_CC_PMU_4325_RES_DEPEND;
172 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] =
173 SIBA_CC_PMU_4328_RES_UPDOWN;
174 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] =
175 SIBA_CC_PMU_4328_RES_DEPEND;
176 static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] =
177 SIBA_CC_PMU0_PLLTAB_ENTRY;
178 static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] =
179 SIBA_CC_PMU1_PLLTAB_ENTRY;
180
181 int
siba_core_attach(struct siba_softc * siba)182 siba_core_attach(struct siba_softc *siba)
183 {
184 struct siba_cc *scc;
185 int error;
186
187 KASSERT(siba->siba_type == SIBA_TYPE_PCI,
188 ("unsupported BUS type (%#x)", siba->siba_type));
189
190 siba->siba_ops = &siba_pci_ops;
191
192 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
193 siba_scan(siba);
194
195 /* XXX init PCI or PCMCIA host devices */
196
197 siba_powerup_sub(siba, 0);
198
199 /* init ChipCommon */
200 scc = &siba->siba_cc;
201 if (scc->scc_dev != NULL) {
202 siba_cc_pmu_init(scc);
203 siba_cc_power_init(scc);
204 siba_cc_clock(scc, SIBA_CLOCK_FAST);
205 siba_cc_powerup_delay(scc);
206 }
207
208 error = siba_pci_sprom(siba, &siba->siba_sprom);
209 if (error) {
210 siba_powerdown_sub(siba);
211 return (error);
212 }
213
214 siba_pcicore_init(&siba->siba_pci);
215 siba_powerdown_sub(siba);
216
217 return (bus_generic_attach(siba->siba_dev));
218 }
219
220 int
siba_core_detach(struct siba_softc * siba)221 siba_core_detach(struct siba_softc *siba)
222 {
223 /* detach & delete all children */
224 device_delete_children(siba->siba_dev);
225 return (0);
226 }
227
228 static void
siba_pci_gpio(struct siba_softc * siba,uint32_t what,int on)229 siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on)
230 {
231 uint32_t in, out;
232 uint16_t status;
233
234 if (siba->siba_type != SIBA_TYPE_PCI)
235 return;
236
237 out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4);
238 if (on == 0) {
239 if (what & SIBA_GPIO_PLL)
240 out |= SIBA_GPIO_PLL;
241 if (what & SIBA_GPIO_CRYSTAL)
242 out &= ~SIBA_GPIO_CRYSTAL;
243 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
244 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN,
245 pci_read_config(siba->siba_dev,
246 SIBA_GPIO_OUT_EN, 4) | what, 4);
247 return;
248 }
249
250 in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4);
251 if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) {
252 if (what & SIBA_GPIO_CRYSTAL) {
253 out |= SIBA_GPIO_CRYSTAL;
254 if (what & SIBA_GPIO_PLL)
255 out |= SIBA_GPIO_PLL;
256 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
257 pci_write_config(siba->siba_dev,
258 SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev,
259 SIBA_GPIO_OUT_EN, 4) | what, 4);
260 DELAY(1000);
261 }
262 if (what & SIBA_GPIO_PLL) {
263 out &= ~SIBA_GPIO_PLL;
264 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
265 DELAY(5000);
266 }
267 }
268
269 status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2);
270 status &= ~PCIM_STATUS_STABORT;
271 pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2);
272 }
273
274 static void
siba_scan(struct siba_softc * siba)275 siba_scan(struct siba_softc *siba)
276 {
277 struct siba_dev_softc *sd;
278 uint32_t idhi, tmp;
279 device_t child;
280 int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0,
281 n_pci = 0;
282
283 KASSERT(siba->siba_type == SIBA_TYPE_PCI,
284 ("unsupported BUS type (%#x)", siba->siba_type));
285
286 siba->siba_ndevs = 0;
287 error = siba_switchcore(siba, 0); /* need the first core */
288 if (error)
289 return;
290
291 idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH);
292 if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) {
293 tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID);
294 siba->siba_chipid = SIBA_CC_ID(tmp);
295 siba->siba_chiprev = SIBA_CC_REV(tmp);
296 siba->siba_chippkg = SIBA_CC_PKG(tmp);
297 if (SIBA_IDHIGH_REV(idhi) >= 4)
298 siba->siba_ndevs = SIBA_CC_NCORES(tmp);
299 siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0,
300 SIBA_CC_CAPS);
301 } else {
302 if (siba->siba_type == SIBA_TYPE_PCI) {
303 siba->siba_chipid = siba_dev2chipid(siba);
304 siba->siba_chiprev = pci_read_config(siba->siba_dev,
305 PCIR_REVID, 2);
306 siba->siba_chippkg = 0;
307 } else {
308 siba->siba_chipid = 0x4710;
309 siba->siba_chiprev = 0;
310 siba->siba_chippkg = 0;
311 }
312 }
313 if (siba->siba_ndevs == 0)
314 siba->siba_ndevs = siba_getncores(siba->siba_dev,
315 siba->siba_chipid);
316 if (siba->siba_ndevs > SIBA_MAX_CORES) {
317 device_printf(siba->siba_dev,
318 "too many siba cores (max %d %d)\n",
319 SIBA_MAX_CORES, siba->siba_ndevs);
320 return;
321 }
322
323 /* looking basic information about each cores/devices */
324 for (i = 0; i < siba->siba_ndevs; i++) {
325 error = siba_switchcore(siba, i);
326 if (error)
327 return;
328 sd = &(siba->siba_devs[dev_i]);
329 idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH);
330 sd->sd_bus = siba;
331 sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi);
332 sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi);
333 sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi);
334 sd->sd_ops = siba->siba_ops;
335 sd->sd_coreidx = i;
336
337 DPRINTF(siba, SIBA_DEBUG_SCAN,
338 "core %d (%s) found (cc %#x rev %#x vendor %#x)\n",
339 i, siba_core_name(sd->sd_id.sd_device),
340 sd->sd_id.sd_device, sd->sd_id.sd_rev,
341 sd->sd_id.sd_vendor);
342
343 switch (sd->sd_id.sd_device) {
344 case SIBA_DEVID_CHIPCOMMON:
345 n_cc++;
346 if (n_cc > 1) {
347 device_printf(siba->siba_dev,
348 "warn: multiple ChipCommon\n");
349 break;
350 }
351 siba->siba_cc.scc_dev = sd;
352 break;
353 case SIBA_DEVID_80211:
354 n_80211++;
355 if (n_80211 > 1) {
356 device_printf(siba->siba_dev,
357 "warn: multiple 802.11 core\n");
358 continue;
359 }
360 break;
361 case SIBA_DEVID_PCI:
362 case SIBA_DEVID_PCIE:
363 n_pci++;
364 error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS,
365 &base);
366 is_pcie = (error == 0) ? 1 : 0;
367
368 if (n_pci > 1) {
369 device_printf(siba->siba_dev,
370 "warn: multiple PCI(E) cores\n");
371 break;
372 }
373 if (sd->sd_id.sd_device == SIBA_DEVID_PCI &&
374 is_pcie == 1)
375 continue;
376 if (sd->sd_id.sd_device == SIBA_DEVID_PCIE &&
377 is_pcie == 0)
378 continue;
379 siba->siba_pci.spc_dev = sd;
380 break;
381 case SIBA_DEVID_MODEM:
382 case SIBA_DEVID_PCMCIA:
383 break;
384 default:
385 device_printf(siba->siba_dev,
386 "unsupported coreid (%s)\n",
387 siba_core_name(sd->sd_id.sd_device));
388 break;
389 }
390 dev_i++;
391
392 child = device_add_child(siba->siba_dev, NULL, -1);
393 if (child == NULL) {
394 device_printf(siba->siba_dev, "child attach failed\n");
395 continue;
396 }
397
398 device_set_ivars(child, sd);
399 }
400 siba->siba_ndevs = dev_i;
401 }
402
403 static int
siba_switchcore(struct siba_softc * siba,uint8_t idx)404 siba_switchcore(struct siba_softc *siba, uint8_t idx)
405 {
406
407 switch (siba->siba_type) {
408 case SIBA_TYPE_PCI:
409 return (siba_pci_switchcore_sub(siba, idx));
410 default:
411 KASSERT(0 == 1,
412 ("%s: unsupported bustype %#x", __func__,
413 siba->siba_type));
414 }
415 return (0);
416 }
417
418 static int
siba_pci_switchcore_sub(struct siba_softc * siba,uint8_t idx)419 siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx)
420 {
421 #define RETRY_MAX 50
422 int i;
423 uint32_t dir;
424
425 dir = SIBA_REGWIN(idx);
426
427 for (i = 0; i < RETRY_MAX; i++) {
428 pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4);
429 if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir)
430 return (0);
431 DELAY(10);
432 }
433 DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "%s: idx %d, failed\n", __func__, idx);
434 return (ENODEV);
435 #undef RETRY_MAX
436 }
437
438 static int
siba_pci_switchcore(struct siba_softc * siba,struct siba_dev_softc * sd)439 siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd)
440 {
441 int error;
442
443 DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n",
444 siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx);
445
446 error = siba_pci_switchcore_sub(siba, sd->sd_coreidx);
447 if (error == 0)
448 siba->siba_curdev = sd;
449
450 return (error);
451 }
452
453 static uint32_t
siba_scan_read_4(struct siba_softc * siba,uint8_t coreidx,uint16_t offset)454 siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx,
455 uint16_t offset)
456 {
457
458 (void)coreidx;
459 KASSERT(siba->siba_type == SIBA_TYPE_PCI,
460 ("unsupported BUS type (%#x)", siba->siba_type));
461
462 return (SIBA_READ_4(siba, offset));
463 }
464
465 static uint16_t
siba_dev2chipid(struct siba_softc * siba)466 siba_dev2chipid(struct siba_softc *siba)
467 {
468 uint16_t chipid = 0;
469
470 switch (siba->siba_pci_did) {
471 case 0x4301:
472 chipid = 0x4301;
473 break;
474 case 0x4305:
475 case 0x4306:
476 case 0x4307:
477 chipid = 0x4307;
478 break;
479 case 0x4403:
480 chipid = 0x4402;
481 break;
482 case 0x4610:
483 case 0x4611:
484 case 0x4612:
485 case 0x4613:
486 case 0x4614:
487 case 0x4615:
488 chipid = 0x4610;
489 break;
490 case 0x4710:
491 case 0x4711:
492 case 0x4712:
493 case 0x4713:
494 case 0x4714:
495 case 0x4715:
496 chipid = 0x4710;
497 break;
498 case 0x4320:
499 case 0x4321:
500 case 0x4322:
501 case 0x4323:
502 case 0x4324:
503 case 0x4325:
504 chipid = 0x4309;
505 break;
506 case PCI_DEVICE_ID_BCM4401:
507 case PCI_DEVICE_ID_BCM4401B0:
508 case PCI_DEVICE_ID_BCM4401B1:
509 chipid = 0x4401;
510 break;
511 default:
512 device_printf(siba->siba_dev, "unknown PCI did (%d)\n",
513 siba->siba_pci_did);
514 }
515
516 return (chipid);
517 }
518
519 /*
520 * Earlier ChipCommon revisions have hardcoded number of cores
521 * present dependent on the ChipCommon ID.
522 */
523 uint8_t
siba_getncores(device_t dev,uint16_t chipid)524 siba_getncores(device_t dev, uint16_t chipid)
525 {
526 switch (chipid) {
527 case 0x4401:
528 case 0x4402:
529 return (3);
530 case 0x4301:
531 case 0x4307:
532 return (5);
533 case 0x4306:
534 return (6);
535 case SIBA_CCID_SENTRY5:
536 return (7);
537 case 0x4310:
538 return (8);
539 case SIBA_CCID_BCM4710:
540 case 0x4610:
541 case SIBA_CCID_BCM4704:
542 return (9);
543 default:
544 device_printf(dev, "unknown the chipset ID %#x\n", chipid);
545 }
546
547 return (1);
548 }
549
550 static const char *
siba_core_name(uint16_t coreid)551 siba_core_name(uint16_t coreid)
552 {
553
554 switch (coreid) {
555 case SIBA_DEVID_CHIPCOMMON:
556 return ("ChipCommon");
557 case SIBA_DEVID_ILINE20:
558 return ("ILine 20");
559 case SIBA_DEVID_SDRAM:
560 return ("SDRAM");
561 case SIBA_DEVID_PCI:
562 return ("PCI");
563 case SIBA_DEVID_MIPS:
564 return ("MIPS");
565 case SIBA_DEVID_ETHERNET:
566 return ("Fast Ethernet");
567 case SIBA_DEVID_MODEM:
568 return ("Modem");
569 case SIBA_DEVID_USB11_HOSTDEV:
570 return ("USB 1.1 Hostdev");
571 case SIBA_DEVID_ADSL:
572 return ("ADSL");
573 case SIBA_DEVID_ILINE100:
574 return ("ILine 100");
575 case SIBA_DEVID_IPSEC:
576 return ("IPSEC");
577 case SIBA_DEVID_PCMCIA:
578 return ("PCMCIA");
579 case SIBA_DEVID_INTERNAL_MEM:
580 return ("Internal Memory");
581 case SIBA_DEVID_SDRAMDDR:
582 return ("MEMC SDRAM");
583 case SIBA_DEVID_EXTIF:
584 return ("EXTIF");
585 case SIBA_DEVID_80211:
586 return ("IEEE 802.11");
587 case SIBA_DEVID_MIPS_3302:
588 return ("MIPS 3302");
589 case SIBA_DEVID_USB11_HOST:
590 return ("USB 1.1 Host");
591 case SIBA_DEVID_USB11_DEV:
592 return ("USB 1.1 Device");
593 case SIBA_DEVID_USB20_HOST:
594 return ("USB 2.0 Host");
595 case SIBA_DEVID_USB20_DEV:
596 return ("USB 2.0 Device");
597 case SIBA_DEVID_SDIO_HOST:
598 return ("SDIO Host");
599 case SIBA_DEVID_ROBOSWITCH:
600 return ("Roboswitch");
601 case SIBA_DEVID_PARA_ATA:
602 return ("PATA");
603 case SIBA_DEVID_SATA_XORDMA:
604 return ("SATA XOR-DMA");
605 case SIBA_DEVID_ETHERNET_GBIT:
606 return ("GBit Ethernet");
607 case SIBA_DEVID_PCIE:
608 return ("PCI-Express");
609 case SIBA_DEVID_MIMO_PHY:
610 return ("MIMO PHY");
611 case SIBA_DEVID_SRAM_CTRLR:
612 return ("SRAM Controller");
613 case SIBA_DEVID_MINI_MACPHY:
614 return ("Mini MACPHY");
615 case SIBA_DEVID_ARM_1176:
616 return ("ARM 1176");
617 case SIBA_DEVID_ARM_7TDMI:
618 return ("ARM 7TDMI");
619 }
620 return ("unknown");
621 }
622
623 static uint16_t
siba_pci_read_2(struct siba_dev_softc * sd,uint16_t offset)624 siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset)
625 {
626 struct siba_softc *siba = sd->sd_bus;
627
628 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
629 return (0xffff);
630
631 return (SIBA_READ_2(siba, offset));
632 }
633
634 static uint32_t
siba_pci_read_4(struct siba_dev_softc * sd,uint16_t offset)635 siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset)
636 {
637 struct siba_softc *siba = sd->sd_bus;
638
639 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
640 return (0xffff);
641
642 return (SIBA_READ_4(siba, offset));
643 }
644
645 static void
siba_pci_write_2(struct siba_dev_softc * sd,uint16_t offset,uint16_t value)646 siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value)
647 {
648 struct siba_softc *siba = sd->sd_bus;
649
650 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
651 return;
652
653 SIBA_WRITE_2(siba, offset, value);
654 }
655
656 static void
siba_pci_write_4(struct siba_dev_softc * sd,uint16_t offset,uint32_t value)657 siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
658 {
659 struct siba_softc *siba = sd->sd_bus;
660
661 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
662 return;
663
664 SIBA_WRITE_4(siba, offset, value);
665 }
666
667 static void
siba_pci_read_multi_1(struct siba_dev_softc * sd,void * buffer,size_t count,uint16_t offset)668 siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count,
669 uint16_t offset)
670 {
671 struct siba_softc *siba = sd->sd_bus;
672
673 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
674 memset(buffer, 0xff, count);
675 return;
676 }
677
678 SIBA_READ_MULTI_1(siba, offset, buffer, count);
679 }
680
681 static void
siba_pci_read_multi_2(struct siba_dev_softc * sd,void * buffer,size_t count,uint16_t offset)682 siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count,
683 uint16_t offset)
684 {
685 struct siba_softc *siba = sd->sd_bus;
686
687 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
688 memset(buffer, 0xff, count);
689 return;
690 }
691
692 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
693 SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1);
694 }
695
696 static void
siba_pci_read_multi_4(struct siba_dev_softc * sd,void * buffer,size_t count,uint16_t offset)697 siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count,
698 uint16_t offset)
699 {
700 struct siba_softc *siba = sd->sd_bus;
701
702 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
703 memset(buffer, 0xff, count);
704 return;
705 }
706
707 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
708 SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2);
709 }
710
711 static void
siba_pci_write_multi_1(struct siba_dev_softc * sd,const void * buffer,size_t count,uint16_t offset)712 siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer,
713 size_t count, uint16_t offset)
714 {
715 struct siba_softc *siba = sd->sd_bus;
716
717 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
718 return;
719
720 SIBA_WRITE_MULTI_1(siba, offset, buffer, count);
721 }
722
723 static void
siba_pci_write_multi_2(struct siba_dev_softc * sd,const void * buffer,size_t count,uint16_t offset)724 siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer,
725 size_t count, uint16_t offset)
726 {
727 struct siba_softc *siba = sd->sd_bus;
728
729 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
730 return;
731
732 KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
733 SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1);
734 }
735
736 static void
siba_pci_write_multi_4(struct siba_dev_softc * sd,const void * buffer,size_t count,uint16_t offset)737 siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer,
738 size_t count, uint16_t offset)
739 {
740 struct siba_softc *siba = sd->sd_bus;
741
742 if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
743 return;
744
745 KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
746 SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2);
747 }
748
749 void
siba_powerup(device_t dev,int dynamic)750 siba_powerup(device_t dev, int dynamic)
751 {
752 struct siba_dev_softc *sd = device_get_ivars(dev);
753 struct siba_softc *siba = sd->sd_bus;
754
755 siba_powerup_sub(siba, dynamic);
756 }
757
758 static void
siba_powerup_sub(struct siba_softc * siba,int dynamic)759 siba_powerup_sub(struct siba_softc *siba, int dynamic)
760 {
761
762 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
763 siba_cc_clock(&siba->siba_cc,
764 (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST);
765 }
766
767 static void
siba_cc_clock(struct siba_cc * scc,enum siba_clock clock)768 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock)
769 {
770 struct siba_dev_softc *sd = scc->scc_dev;
771 struct siba_softc *siba;
772 uint32_t tmp;
773
774 if (sd == NULL)
775 return;
776 siba = sd->sd_bus;
777
778 /*
779 * PMU controls clockmode; separate function is needed
780 */
781 if (scc->scc_caps & SIBA_CC_CAPS_PMU)
782 return;
783
784 /*
785 * chipcommon < r6 (no dynamic clock control)
786 * chipcommon >= r10 (unknown)
787 */
788 if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 ||
789 (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
790 return;
791
792 switch (clock) {
793 case SIBA_CLOCK_DYNAMIC:
794 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) &
795 ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW |
796 SIBA_CC_CLKSLOW_IPLL);
797 if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL)
798 tmp |= SIBA_CC_CLKSLOW_ENXTAL;
799 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp);
800 if (tmp & SIBA_CC_CLKSLOW_ENXTAL)
801 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0);
802 break;
803 case SIBA_CLOCK_SLOW:
804 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
805 SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
806 SIBA_CC_CLKSLOW_FSLOW);
807 break;
808 case SIBA_CLOCK_FAST:
809 /* crystal on */
810 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1);
811 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
812 (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
813 SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW);
814 break;
815 default:
816 KASSERT(0 == 1,
817 ("%s: unsupported clock %#x", __func__, clock));
818 }
819 }
820
821 uint16_t
siba_read_2(device_t dev,uint16_t offset)822 siba_read_2(device_t dev, uint16_t offset)
823 {
824 struct siba_dev_softc *sd = device_get_ivars(dev);
825
826 return (sd->sd_ops->read_2(sd, offset));
827 }
828
829 uint32_t
siba_read_4(device_t dev,uint16_t offset)830 siba_read_4(device_t dev, uint16_t offset)
831 {
832 struct siba_dev_softc *sd = device_get_ivars(dev);
833
834 return (siba_read_4_sub(sd, offset));
835 }
836
837 static uint32_t
siba_read_4_sub(struct siba_dev_softc * sd,uint16_t offset)838 siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset)
839 {
840
841 return (sd->sd_ops->read_4(sd, offset));
842 }
843
844 void
siba_write_2(device_t dev,uint16_t offset,uint16_t value)845 siba_write_2(device_t dev, uint16_t offset, uint16_t value)
846 {
847 struct siba_dev_softc *sd = device_get_ivars(dev);
848
849 sd->sd_ops->write_2(sd, offset, value);
850 }
851
852 void
siba_write_4(device_t dev,uint16_t offset,uint32_t value)853 siba_write_4(device_t dev, uint16_t offset, uint32_t value)
854 {
855 struct siba_dev_softc *sd = device_get_ivars(dev);
856
857 return (siba_write_4_sub(sd, offset, value));
858 }
859
860 static void
siba_write_4_sub(struct siba_dev_softc * sd,uint16_t offset,uint32_t value)861 siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
862 {
863
864 sd->sd_ops->write_4(sd, offset, value);
865 }
866
867 void
siba_read_multi_1(device_t dev,void * buffer,size_t count,uint16_t offset)868 siba_read_multi_1(device_t dev, void *buffer, size_t count,
869 uint16_t offset)
870 {
871 struct siba_dev_softc *sd = device_get_ivars(dev);
872
873 sd->sd_ops->read_multi_1(sd, buffer, count, offset);
874 }
875
876 void
siba_read_multi_2(device_t dev,void * buffer,size_t count,uint16_t offset)877 siba_read_multi_2(device_t dev, void *buffer, size_t count,
878 uint16_t offset)
879 {
880 struct siba_dev_softc *sd = device_get_ivars(dev);
881
882 sd->sd_ops->read_multi_2(sd, buffer, count, offset);
883 }
884
885 void
siba_read_multi_4(device_t dev,void * buffer,size_t count,uint16_t offset)886 siba_read_multi_4(device_t dev, void *buffer, size_t count,
887 uint16_t offset)
888 {
889 struct siba_dev_softc *sd = device_get_ivars(dev);
890
891 sd->sd_ops->read_multi_4(sd, buffer, count, offset);
892 }
893
894 void
siba_write_multi_1(device_t dev,const void * buffer,size_t count,uint16_t offset)895 siba_write_multi_1(device_t dev, const void *buffer, size_t count,
896 uint16_t offset)
897 {
898 struct siba_dev_softc *sd = device_get_ivars(dev);
899
900 sd->sd_ops->write_multi_1(sd, buffer, count, offset);
901 }
902
903 void
siba_write_multi_2(device_t dev,const void * buffer,size_t count,uint16_t offset)904 siba_write_multi_2(device_t dev, const void *buffer, size_t count,
905 uint16_t offset)
906 {
907 struct siba_dev_softc *sd = device_get_ivars(dev);
908
909 sd->sd_ops->write_multi_2(sd, buffer, count, offset);
910 }
911
912 void
siba_write_multi_4(device_t dev,const void * buffer,size_t count,uint16_t offset)913 siba_write_multi_4(device_t dev, const void *buffer, size_t count,
914 uint16_t offset)
915 {
916 struct siba_dev_softc *sd = device_get_ivars(dev);
917
918 sd->sd_ops->write_multi_4(sd, buffer, count, offset);
919 }
920
921 static void
siba_cc_pmu_init(struct siba_cc * scc)922 siba_cc_pmu_init(struct siba_cc *scc)
923 {
924 const struct siba_cc_pmu_res_updown *updown = NULL;
925 const struct siba_cc_pmu_res_depend *depend = NULL;
926 struct siba_dev_softc *sd = scc->scc_dev;
927 struct siba_softc *siba = sd->sd_bus;
928 uint32_t min = 0, max = 0, pmucap;
929 unsigned int i, updown_size, depend_size;
930
931 if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0)
932 return;
933
934 pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS);
935 scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV);
936
937 DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n",
938 scc->scc_pmu.rev, pmucap);
939
940 #if 0
941 if (scc->scc_pmu.rev >= 1) {
942 if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325)
943 SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL,
944 ~SIBA_CC_PMUCTL_NOILP);
945 else
946 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL,
947 SIBA_CC_PMUCTL_NOILP);
948 }
949 #endif
950 if (scc->scc_pmu.rev == 1) {
951 SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, ~SIBA_CC_PMUCTL_NOILP);
952 } else {
953 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_NOILP);
954 }
955
956 /* initialize PLL & PMU resources */
957 switch (siba->siba_chipid) {
958 case 0x4312:
959 siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
960 /* use the default: min = 0xcbb max = 0x7ffff */
961 break;
962 case 0x4322:
963 if (scc->scc_pmu.rev == 2) {
964 DPRINTF(siba, SIBA_DEBUG_PMU, "%s: chipid 0x4322; PLLing\n",
965 __func__);
966 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, 0x0000000a);
967 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, 0x380005c0);
968 }
969 /* use the default: min = 0xcbb max = 0x7ffff */
970 break;
971 case 43222:
972 break;
973 case 0x4325:
974 siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
975
976 updown = siba_cc_pmu_4325_updown;
977 updown_size = N(siba_cc_pmu_4325_updown);
978 depend = siba_cc_pmu_4325_depend;
979 depend_size = N(siba_cc_pmu_4325_depend);
980
981 min = (1 << SIBA_CC_PMU_4325_BURST) |
982 (1 << SIBA_CC_PMU_4325_LN);
983 if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) &
984 SIBA_CC_CHST_4325_PMUTOP_2B)
985 min |= (1 << SIBA_CC_PMU_4325_CLBURST);
986 max = 0xfffff;
987 break;
988 case 0x4328:
989 siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
990
991 updown = siba_cc_pmu_4328_updown;
992 updown_size = N(siba_cc_pmu_4328_updown);
993 depend = siba_cc_pmu_4328_depend;
994 depend_size = N(siba_cc_pmu_4328_depend);
995
996 min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) |
997 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) |
998 (1 << SIBA_CC_PMU_4328_CRYSTAL_EN);
999
1000 max = 0xfffff;
1001 break;
1002 case 0x5354:
1003 siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
1004
1005 max = 0xfffff;
1006 break;
1007 default:
1008 device_printf(siba->siba_dev,
1009 "unknown chipid %#x for PLL & PMU init\n",
1010 siba->siba_chipid);
1011 }
1012
1013 if (updown) {
1014 for (i = 0; i < updown_size; i++) {
1015 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
1016 updown[i].res);
1017 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM,
1018 updown[i].updown);
1019 }
1020 }
1021 if (depend) {
1022 for (i = 0; i < depend_size; i++) {
1023 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
1024 depend[i].res);
1025 switch (depend[i].task) {
1026 case SIBA_CC_PMU_DEP_SET:
1027 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK,
1028 depend[i].depend);
1029 break;
1030 case SIBA_CC_PMU_DEP_ADD:
1031 SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK,
1032 depend[i].depend);
1033 break;
1034 case SIBA_CC_PMU_DEP_REMOVE:
1035 SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK,
1036 ~(depend[i].depend));
1037 break;
1038 default:
1039 KASSERT(0 == 1,
1040 ("%s:%d: assertion failed",
1041 __func__, __LINE__));
1042 }
1043 }
1044 }
1045
1046 if (min)
1047 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min);
1048 if (max)
1049 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max);
1050 }
1051
1052 static void
siba_cc_power_init(struct siba_cc * scc)1053 siba_cc_power_init(struct siba_cc *scc)
1054 {
1055 struct siba_softc *siba = scc->scc_dev->sd_bus;
1056 int maxfreq;
1057
1058 if (siba->siba_chipid == 0x4321) {
1059 if (siba->siba_chiprev == 0)
1060 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4);
1061 else if (siba->siba_chiprev == 1)
1062 SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4);
1063 }
1064
1065 if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
1066 return;
1067
1068 if (scc->scc_dev->sd_id.sd_rev >= 10)
1069 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL,
1070 (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) &
1071 0xffff) | 0x40000);
1072 else {
1073 maxfreq = siba_cc_clockfreq(scc, 1);
1074 SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY,
1075 (maxfreq * 150 + 999999) / 1000000);
1076 SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY,
1077 (maxfreq * 15 + 999999) / 1000000);
1078 }
1079 }
1080
1081 static void
siba_cc_powerup_delay(struct siba_cc * scc)1082 siba_cc_powerup_delay(struct siba_cc *scc)
1083 {
1084 struct siba_softc *siba = scc->scc_dev->sd_bus;
1085 int min;
1086
1087 if (siba->siba_type != SIBA_TYPE_PCI)
1088 return;
1089
1090 if (scc->scc_caps & SIBA_CC_CAPS_PMU) {
1091 if ((siba->siba_chipid == 0x4312) ||
1092 (siba->siba_chipid == 0x4322) ||
1093 (siba->siba_chipid == 0x4328)) {
1094 scc->scc_powerup_delay = 7000;
1095 } else {
1096 /* 0x4325 is marked as TODO */
1097 scc->scc_powerup_delay = 15000;
1098 }
1099 return;
1100 }
1101
1102 if (!(scc->scc_caps & SIBA_CC_CAPS_PWCTL))
1103 return;
1104
1105 min = siba_cc_clockfreq(scc, 0);
1106 scc->scc_powerup_delay =
1107 howmany((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000,
1108 min);
1109 }
1110
1111 static int
siba_cc_clockfreq(struct siba_cc * scc,int max)1112 siba_cc_clockfreq(struct siba_cc *scc, int max)
1113 {
1114 enum siba_clksrc src;
1115 int div = 1, limit = 0;
1116
1117 src = siba_cc_clksrc(scc);
1118 if (scc->scc_dev->sd_id.sd_rev < 6) {
1119 div = (src == SIBA_CC_CLKSRC_PCI) ? 64 :
1120 (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1;
1121 KASSERT(div != 1,
1122 ("%s: unknown clock %d", __func__, src));
1123 } else if (scc->scc_dev->sd_id.sd_rev < 10) {
1124 switch (src) {
1125 case SIBA_CC_CLKSRC_CRYSTAL:
1126 case SIBA_CC_CLKSRC_PCI:
1127 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) +
1128 1) * 4;
1129 break;
1130 case SIBA_CC_CLKSRC_LOWPW:
1131 break;
1132 }
1133 } else
1134 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4;
1135
1136 switch (src) {
1137 case SIBA_CC_CLKSRC_CRYSTAL:
1138 limit = (max) ? 20200000 : 19800000;
1139 break;
1140 case SIBA_CC_CLKSRC_LOWPW:
1141 limit = (max) ? 43000 : 25000;
1142 break;
1143 case SIBA_CC_CLKSRC_PCI:
1144 limit = (max) ? 34000000 : 25000000;
1145 break;
1146 }
1147
1148 return (limit / div);
1149 }
1150
1151 static void
siba_cc_pmu1_pll0_init(struct siba_cc * scc,uint32_t freq)1152 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq)
1153 {
1154 struct siba_dev_softc *sd = scc->scc_dev;
1155 struct siba_softc *siba = sd->sd_bus;
1156 const struct siba_cc_pmu1_plltab *e = NULL;
1157 uint32_t bufsth = 0, pll, pmu;
1158 unsigned int i;
1159
1160 KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__));
1161 if (siba->siba_chipid == 0x4312) {
1162 scc->scc_pmu.freq = 20000;
1163 return;
1164 }
1165
1166 e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ);
1167 KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__));
1168 scc->scc_pmu.freq = e->freq;
1169
1170 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1171 if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf)
1172 return;
1173
1174 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
1175 (e->freq / 1000), (e->freq % 1000));
1176
1177 /* turn PLL off */
1178 switch (siba->siba_chipid) {
1179 case 0x4325:
1180 bufsth = 0x222222;
1181 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1182 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
1183 (1 << SIBA_CC_PMU_4325_HT)));
1184 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1185 ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
1186 (1 << SIBA_CC_PMU_4325_HT)));
1187 break;
1188 default:
1189 KASSERT(0 == 1,
1190 ("%s:%d: assertion failed", __func__, __LINE__));
1191 }
1192 for (i = 0; i < 1500; i++) {
1193 if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) &
1194 SIBA_CC_CLKCTLSTATUS_HT))
1195 break;
1196 DELAY(10);
1197 }
1198 if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT)
1199 device_printf(siba->siba_dev, "failed to turn PLL off!\n");
1200
1201 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0);
1202 pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV);
1203 pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV;
1204 pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV;
1205 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll);
1206
1207 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2);
1208 pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE);
1209 pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT;
1210 pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE;
1211 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll);
1212
1213 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3);
1214 pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC;
1215 pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC;
1216 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll);
1217
1218 if (bufsth) {
1219 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5);
1220 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV;
1221 pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV;
1222 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll);
1223 }
1224
1225 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1226 pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF);
1227 pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) &
1228 SIBA_CC_PMUCTL_ILP;
1229 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
1230 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1231 }
1232
1233 static void
siba_cc_pmu0_pll0_init(struct siba_cc * scc,uint32_t xtalfreq)1234 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq)
1235 {
1236 struct siba_dev_softc *sd = scc->scc_dev;
1237 struct siba_softc *siba = sd->sd_bus;
1238 const struct siba_cc_pmu0_plltab *e = NULL;
1239 uint32_t pmu, tmp, pll;
1240 unsigned int i;
1241
1242 if ((siba->siba_chipid == 0x5354) && !xtalfreq)
1243 xtalfreq = 25000;
1244 if (xtalfreq)
1245 e = siba_cc_pmu0_plltab_findentry(xtalfreq);
1246 if (!e)
1247 e = siba_cc_pmu0_plltab_findentry(
1248 SIBA_CC_PMU0_DEFAULT_XTALFREQ);
1249 KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__));
1250 xtalfreq = e->freq;
1251 scc->scc_pmu.freq = e->freq;
1252
1253 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1254 if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf)
1255 return;
1256
1257 DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
1258 (xtalfreq / 1000), (xtalfreq % 1000));
1259
1260 KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354,
1261 ("%s:%d: fail", __func__, __LINE__));
1262
1263 switch (siba->siba_chipid) {
1264 case 0x4328:
1265 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1266 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
1267 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1268 ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
1269 break;
1270 case 0x5354:
1271 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1272 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
1273 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1274 ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
1275 break;
1276 }
1277 for (i = 1500; i; i--) {
1278 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1279 if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT))
1280 break;
1281 DELAY(10);
1282 }
1283 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1284 if (tmp & SIBA_CC_CLKCTLSTATUS_HT)
1285 device_printf(siba->siba_dev, "failed to turn PLL off!\n");
1286
1287 /* set PDIV */
1288 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0);
1289 if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ)
1290 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK;
1291 else
1292 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK;
1293 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll);
1294
1295 /* set WILD */
1296 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1);
1297 pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK |
1298 SIBA_CC_PMU0_PLL1_FMSK);
1299 pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK;
1300 pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK;
1301 if (e->wb_frac == 0)
1302 pll |= SIBA_CC_PMU0_PLL1_STOPMOD;
1303 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll);
1304
1305 /* set WILD */
1306 pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2);
1307 pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI;
1308 pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI;
1309 siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll);
1310
1311 /* set freq and divisor. */
1312 pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1313 pmu &= ~SIBA_CC_PMUCTL_ILP;
1314 pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP;
1315 pmu &= ~SIBA_CC_PMUCTL_XF;
1316 pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
1317 SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1318 }
1319
1320 static enum siba_clksrc
siba_cc_clksrc(struct siba_cc * scc)1321 siba_cc_clksrc(struct siba_cc *scc)
1322 {
1323 struct siba_dev_softc *sd = scc->scc_dev;
1324 struct siba_softc *siba = sd->sd_bus;
1325
1326 if (sd->sd_id.sd_rev < 6) {
1327 if (siba->siba_type == SIBA_TYPE_PCI) {
1328 if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) &
1329 0x10)
1330 return (SIBA_CC_CLKSRC_PCI);
1331 return (SIBA_CC_CLKSRC_CRYSTAL);
1332 }
1333 if (siba->siba_type == SIBA_TYPE_SSB ||
1334 siba->siba_type == SIBA_TYPE_PCMCIA)
1335 return (SIBA_CC_CLKSRC_CRYSTAL);
1336 }
1337 if (sd->sd_id.sd_rev < 10) {
1338 switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) {
1339 case 0:
1340 return (SIBA_CC_CLKSRC_LOWPW);
1341 case 1:
1342 return (SIBA_CC_CLKSRC_CRYSTAL);
1343 case 2:
1344 return (SIBA_CC_CLKSRC_PCI);
1345 default:
1346 break;
1347 }
1348 }
1349
1350 return (SIBA_CC_CLKSRC_CRYSTAL);
1351 }
1352
1353 static const struct siba_cc_pmu1_plltab *
siba_cc_pmu1_plltab_find(uint32_t crystalfreq)1354 siba_cc_pmu1_plltab_find(uint32_t crystalfreq)
1355 {
1356 const struct siba_cc_pmu1_plltab *e;
1357 unsigned int i;
1358
1359 for (i = 0; i < N(siba_cc_pmu1_plltab); i++) {
1360 e = &siba_cc_pmu1_plltab[i];
1361 if (crystalfreq == e->freq)
1362 return (e);
1363 }
1364
1365 return (NULL);
1366 }
1367
1368 static uint32_t
siba_cc_pll_read(struct siba_cc * scc,uint32_t offset)1369 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset)
1370 {
1371
1372 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1373 return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA));
1374 }
1375
1376 static void
siba_cc_pll_write(struct siba_cc * scc,uint32_t offset,uint32_t value)1377 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value)
1378 {
1379
1380 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1381 SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value);
1382 }
1383
1384 static const struct siba_cc_pmu0_plltab *
siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq)1385 siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq)
1386 {
1387 const struct siba_cc_pmu0_plltab *e;
1388 unsigned int i;
1389
1390 for (i = 0; i < N(siba_cc_pmu0_plltab); i++) {
1391 e = &siba_cc_pmu0_plltab[i];
1392 if (e->freq == crystalfreq)
1393 return (e);
1394 }
1395
1396 return (NULL);
1397 }
1398
1399 static int
siba_pci_sprom(struct siba_softc * siba,struct siba_sprom * sprom)1400 siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom)
1401 {
1402 int error = ENOMEM;
1403 uint16_t *buf;
1404
1405 buf = malloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t),
1406 M_DEVBUF, M_NOWAIT | M_ZERO);
1407 if (buf == NULL)
1408 return (ENOMEM);
1409 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123);
1410 error = sprom_check_crc(buf, siba->siba_spromsize);
1411 if (error) {
1412 free(buf, M_DEVBUF);
1413 buf = malloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t),
1414 M_DEVBUF, M_NOWAIT | M_ZERO);
1415 if (buf == NULL)
1416 return (ENOMEM);
1417 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4);
1418 error = sprom_check_crc(buf, siba->siba_spromsize);
1419 if (error)
1420 device_printf(siba->siba_dev, "warn: bad SPROM CRC\n");
1421 }
1422
1423 bzero(sprom, sizeof(*sprom));
1424
1425 sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF;
1426 DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n",
1427 sprom->rev);
1428 memset(sprom->mac_eth, 0xff, 6);
1429 memset(sprom->mac_80211a, 0xff, 6);
1430 if ((siba->siba_chipid & 0xff00) == 0x4400) {
1431 sprom->rev = 1;
1432 siba_sprom_r123(sprom, buf);
1433 } else if (siba->siba_chipid == 0x4321) {
1434 sprom->rev = 4;
1435 siba_sprom_r45(sprom, buf);
1436 } else {
1437 switch (sprom->rev) {
1438 case 1:
1439 case 2:
1440 case 3:
1441 siba_sprom_r123(sprom, buf);
1442 break;
1443 case 4:
1444 case 5:
1445 siba_sprom_r45(sprom, buf);
1446 break;
1447 case 8:
1448 siba_sprom_r8(sprom, buf);
1449 break;
1450 default:
1451 device_printf(siba->siba_dev,
1452 "unknown SPROM revision %d.\n", sprom->rev);
1453 siba_sprom_r123(sprom, buf);
1454 }
1455 }
1456
1457 if (sprom->bf_lo == 0xffff)
1458 sprom->bf_lo = 0;
1459 if (sprom->bf_hi == 0xffff)
1460 sprom->bf_hi = 0;
1461
1462 free(buf, M_DEVBUF);
1463 return (error);
1464 }
1465
1466 static int
siba_sprom_read(struct siba_softc * siba,uint16_t * sprom,uint16_t len)1467 siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len)
1468 {
1469 int i;
1470
1471 for (i = 0; i < len; i++)
1472 sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2));
1473
1474 siba->siba_spromsize = len;
1475 return (0);
1476 }
1477
1478 static int
sprom_check_crc(const uint16_t * sprom,size_t size)1479 sprom_check_crc(const uint16_t *sprom, size_t size)
1480 {
1481 int word;
1482 uint8_t crc0, crc1 = 0xff;
1483
1484 crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8;
1485 for (word = 0; word < size - 1; word++) {
1486 crc1 = siba_crc8(crc1, sprom[word] & 0x00ff);
1487 crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8);
1488 }
1489 crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff);
1490 crc1 ^= 0xff;
1491
1492 return ((crc0 != crc1) ? EPROTO : 0);
1493 }
1494
1495 static uint8_t
siba_crc8(uint8_t crc,uint8_t data)1496 siba_crc8(uint8_t crc, uint8_t data)
1497 {
1498 static const uint8_t ct[] = {
1499 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b,
1500 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21,
1501 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff,
1502 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5,
1503 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14,
1504 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e,
1505 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80,
1506 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca,
1507 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95,
1508 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf,
1509 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01,
1510 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b,
1511 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea,
1512 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0,
1513 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e,
1514 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34,
1515 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0,
1516 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a,
1517 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54,
1518 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e,
1519 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf,
1520 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5,
1521 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b,
1522 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61,
1523 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e,
1524 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74,
1525 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa,
1526 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0,
1527 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41,
1528 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b,
1529 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5,
1530 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f,
1531 };
1532 return (ct[crc ^ data]);
1533 }
1534
1535 #define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
1536 #define SIBA_OFFSET(offset) \
1537 (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t))
1538 #define SIBA_SHIFTOUT_SUB(__x, __mask) \
1539 (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask))
1540 #define SIBA_SHIFTOUT(_var, _offset, _mask) \
1541 out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask))
1542 #define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift) \
1543 out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 | \
1544 in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift))
1545
1546 static void
siba_sprom_r123(struct siba_sprom * out,const uint16_t * in)1547 siba_sprom_r123(struct siba_sprom *out, const uint16_t *in)
1548 {
1549 int i;
1550 uint16_t v;
1551 int8_t gain;
1552 uint16_t loc[3];
1553
1554 if (out->rev == 3)
1555 loc[0] = SIBA_SPROM3_MAC_80211BG;
1556 else {
1557 loc[0] = SIBA_SPROM1_MAC_80211BG;
1558 loc[1] = SIBA_SPROM1_MAC_ETH;
1559 loc[2] = SIBA_SPROM1_MAC_80211A;
1560 }
1561 for (i = 0; i < 3; i++) {
1562 v = in[SIBA_OFFSET(loc[0]) + i];
1563 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1564 }
1565 if (out->rev < 3) {
1566 for (i = 0; i < 3; i++) {
1567 v = in[SIBA_OFFSET(loc[1]) + i];
1568 *(((uint16_t *)out->mac_eth) + i) = htobe16(v);
1569 }
1570 for (i = 0; i < 3; i++) {
1571 v = in[SIBA_OFFSET(loc[2]) + i];
1572 *(((uint16_t *)out->mac_80211a) + i) = htobe16(v);
1573 }
1574 }
1575 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY,
1576 SIBA_SPROM1_ETHPHY_MII_ETH0);
1577 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY,
1578 SIBA_SPROM1_ETHPHY_MII_ETH1);
1579 SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY,
1580 SIBA_SPROM1_ETHPHY_MDIO_ETH0);
1581 SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY,
1582 SIBA_SPROM1_ETHPHY_MDIO_ETH1);
1583 SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV);
1584 SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO,
1585 SIBA_SPROM1_BOARDINFO_CCODE);
1586 SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA);
1587 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO,
1588 SIBA_SPROM1_BOARDINFO_ANTBG);
1589 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff);
1590 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff);
1591 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff);
1592 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff);
1593 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff);
1594 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff);
1595 SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0);
1596 SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1);
1597 SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2);
1598 SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3);
1599
1600 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A);
1601 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG);
1602 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A);
1603 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG);
1604 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff);
1605 if (out->rev >= 2)
1606 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff);
1607
1608 /* antenna gain */
1609 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0);
1610 out->again.ghz24.a0 = out->again.ghz24.a1 = gain;
1611 out->again.ghz24.a2 = out->again.ghz24.a3 = gain;
1612 gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8);
1613 out->again.ghz5.a0 = out->again.ghz5.a1 = gain;
1614 out->again.ghz5.a2 = out->again.ghz5.a3 = gain;
1615 }
1616
1617 static void
siba_sprom_r458(struct siba_sprom * out,const uint16_t * in)1618 siba_sprom_r458(struct siba_sprom *out, const uint16_t *in)
1619 {
1620
1621 SIBA_SHIFTOUT(txpid2g[0], SIBA_SPROM4_TXPID2G01,
1622 SIBA_SPROM4_TXPID2G0);
1623 SIBA_SHIFTOUT(txpid2g[1], SIBA_SPROM4_TXPID2G01,
1624 SIBA_SPROM4_TXPID2G1);
1625 SIBA_SHIFTOUT(txpid2g[2], SIBA_SPROM4_TXPID2G23,
1626 SIBA_SPROM4_TXPID2G2);
1627 SIBA_SHIFTOUT(txpid2g[3], SIBA_SPROM4_TXPID2G23,
1628 SIBA_SPROM4_TXPID2G3);
1629
1630 SIBA_SHIFTOUT(txpid5gl[0], SIBA_SPROM4_TXPID5GL01,
1631 SIBA_SPROM4_TXPID5GL0);
1632 SIBA_SHIFTOUT(txpid5gl[1], SIBA_SPROM4_TXPID5GL01,
1633 SIBA_SPROM4_TXPID5GL1);
1634 SIBA_SHIFTOUT(txpid5gl[2], SIBA_SPROM4_TXPID5GL23,
1635 SIBA_SPROM4_TXPID5GL2);
1636 SIBA_SHIFTOUT(txpid5gl[3], SIBA_SPROM4_TXPID5GL23,
1637 SIBA_SPROM4_TXPID5GL3);
1638
1639 SIBA_SHIFTOUT(txpid5g[0], SIBA_SPROM4_TXPID5G01,
1640 SIBA_SPROM4_TXPID5G0);
1641 SIBA_SHIFTOUT(txpid5g[1], SIBA_SPROM4_TXPID5G01,
1642 SIBA_SPROM4_TXPID5G1);
1643 SIBA_SHIFTOUT(txpid5g[2], SIBA_SPROM4_TXPID5G23,
1644 SIBA_SPROM4_TXPID5G2);
1645 SIBA_SHIFTOUT(txpid5g[3], SIBA_SPROM4_TXPID5G23,
1646 SIBA_SPROM4_TXPID5G3);
1647
1648 SIBA_SHIFTOUT(txpid5gh[0], SIBA_SPROM4_TXPID5GH01,
1649 SIBA_SPROM4_TXPID5GH0);
1650 SIBA_SHIFTOUT(txpid5gh[1], SIBA_SPROM4_TXPID5GH01,
1651 SIBA_SPROM4_TXPID5GH1);
1652 SIBA_SHIFTOUT(txpid5gh[2], SIBA_SPROM4_TXPID5GH23,
1653 SIBA_SPROM4_TXPID5GH2);
1654 SIBA_SHIFTOUT(txpid5gh[3], SIBA_SPROM4_TXPID5GH23,
1655 SIBA_SPROM4_TXPID5GH3);
1656 }
1657
1658 static void
siba_sprom_r45(struct siba_sprom * out,const uint16_t * in)1659 siba_sprom_r45(struct siba_sprom *out, const uint16_t *in)
1660 {
1661 int i;
1662 uint16_t v;
1663 uint16_t mac_80211bg_offset;
1664 const uint16_t pwr_info_offset[] = {
1665 SIBA_SPROM4_PWR_INFO_CORE0, SIBA_SPROM4_PWR_INFO_CORE1,
1666 SIBA_SPROM4_PWR_INFO_CORE2, SIBA_SPROM4_PWR_INFO_CORE3
1667 };
1668
1669 if (out->rev == 4)
1670 mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG;
1671 else
1672 mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG;
1673 for (i = 0; i < 3; i++) {
1674 v = in[SIBA_OFFSET(mac_80211bg_offset) + i];
1675 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1676 }
1677 SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A);
1678 SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A);
1679 if (out->rev == 4) {
1680 SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff);
1681 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff);
1682 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff);
1683 } else {
1684 SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff);
1685 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff);
1686 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff);
1687 }
1688 SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A);
1689 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG);
1690 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK);
1691 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG);
1692 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK);
1693 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A);
1694 if (out->rev == 4) {
1695 SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0);
1696 SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1);
1697 SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2);
1698 SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3);
1699 } else {
1700 SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0);
1701 SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1);
1702 SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2);
1703 SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3);
1704 }
1705
1706 /* antenna gain */
1707 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0);
1708 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1);
1709 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2);
1710 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3);
1711 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
1712
1713 /* Extract core power info */
1714 for (i = 0; i < nitems(pwr_info_offset); i++) {
1715 uint16_t o = pwr_info_offset[i];
1716
1717 SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI,
1718 SIBA_SPROM4_2G_ITSSI);
1719 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI,
1720 SIBA_SPROM4_2G_MAXP);
1721
1722 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SPROM4_2G_PA_0, ~0);
1723 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SPROM4_2G_PA_1, ~0);
1724 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SPROM4_2G_PA_2, ~0);
1725 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[3], o + SIBA_SPROM4_2G_PA_3, ~0);
1726
1727 SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI,
1728 SIBA_SPROM4_5G_ITSSI);
1729 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI,
1730 SIBA_SPROM4_5G_MAXP);
1731 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM4_5GHL_MAXP,
1732 SIBA_SPROM4_5GH_MAXP);
1733 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM4_5GHL_MAXP,
1734 SIBA_SPROM4_5GL_MAXP);
1735
1736 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SPROM4_5GL_PA_0, ~0);
1737 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SPROM4_5GL_PA_1, ~0);
1738 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SPROM4_5GL_PA_2, ~0);
1739 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[3], o + SIBA_SPROM4_5GL_PA_3, ~0);
1740 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SPROM4_5G_PA_0, ~0);
1741 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SPROM4_5G_PA_1, ~0);
1742 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SPROM4_5G_PA_2, ~0);
1743 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[3], o + SIBA_SPROM4_5G_PA_3, ~0);
1744 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SPROM4_5GH_PA_0, ~0);
1745 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SPROM4_5GH_PA_1, ~0);
1746 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SPROM4_5GH_PA_2, ~0);
1747 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[3], o + SIBA_SPROM4_5GH_PA_3, ~0);
1748 }
1749
1750 siba_sprom_r458(out, in);
1751 }
1752
1753 static void
siba_sprom_r8(struct siba_sprom * out,const uint16_t * in)1754 siba_sprom_r8(struct siba_sprom *out, const uint16_t *in)
1755 {
1756 int i;
1757 uint16_t v;
1758 uint16_t pwr_info_offset[] = {
1759 SIBA_SROM8_PWR_INFO_CORE0, SIBA_SROM8_PWR_INFO_CORE1,
1760 SIBA_SROM8_PWR_INFO_CORE2, SIBA_SROM8_PWR_INFO_CORE3
1761 };
1762
1763 for (i = 0; i < 3; i++) {
1764 v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i];
1765 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1766 }
1767 SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff);
1768 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff);
1769 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff);
1770 SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff);
1771 SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff);
1772 SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A);
1773 SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG);
1774 SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK);
1775 SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG);
1776 SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK);
1777 SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A);
1778 SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL,
1779 SIBA_SPROM8_MAXP_AH_MASK);
1780 SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL,
1781 SIBA_SPROM8_MAXP_AL_MASK);
1782 SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0);
1783 SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1);
1784 SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2);
1785 SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3);
1786 SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G);
1787 SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G);
1788 SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL);
1789 SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH);
1790 SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G);
1791 SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G);
1792
1793 SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G);
1794 SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G);
1795 SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G);
1796 SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G);
1797 SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G);
1798 SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G);
1799 SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G);
1800 SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G);
1801
1802 SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff);
1803 SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff);
1804 SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff);
1805 SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff);
1806 SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff);
1807 SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff);
1808 SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff);
1809 SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff);
1810 SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff);
1811 SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff);
1812 SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff);
1813 SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff);
1814 SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff);
1815
1816 SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0);
1817 SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0);
1818 SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0);
1819 SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0);
1820
1821 /* antenna gain */
1822 SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0);
1823 SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1);
1824 SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2);
1825 SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3);
1826 bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
1827
1828 /* FEM */
1829 SIBA_SHIFTOUT(fem.ghz2.tssipos, SIBA_SPROM8_FEM2G,
1830 SIBA_SROM8_FEM_TSSIPOS);
1831 SIBA_SHIFTOUT(fem.ghz2.extpa_gain, SIBA_SPROM8_FEM2G,
1832 SIBA_SROM8_FEM_EXTPA_GAIN);
1833 SIBA_SHIFTOUT(fem.ghz2.pdet_range, SIBA_SPROM8_FEM2G,
1834 SIBA_SROM8_FEM_PDET_RANGE);
1835 SIBA_SHIFTOUT(fem.ghz2.tr_iso, SIBA_SPROM8_FEM2G,
1836 SIBA_SROM8_FEM_TR_ISO);
1837 SIBA_SHIFTOUT(fem.ghz2.antswlut, SIBA_SPROM8_FEM2G,
1838 SIBA_SROM8_FEM_ANTSWLUT);
1839
1840 SIBA_SHIFTOUT(fem.ghz5.tssipos, SIBA_SPROM8_FEM5G,
1841 SIBA_SROM8_FEM_TSSIPOS);
1842 SIBA_SHIFTOUT(fem.ghz5.extpa_gain, SIBA_SPROM8_FEM5G,
1843 SIBA_SROM8_FEM_EXTPA_GAIN);
1844 SIBA_SHIFTOUT(fem.ghz5.pdet_range, SIBA_SPROM8_FEM5G,
1845 SIBA_SROM8_FEM_PDET_RANGE);
1846 SIBA_SHIFTOUT(fem.ghz5.tr_iso, SIBA_SPROM8_FEM5G,
1847 SIBA_SROM8_FEM_TR_ISO);
1848 SIBA_SHIFTOUT(fem.ghz5.antswlut, SIBA_SPROM8_FEM5G,
1849 SIBA_SROM8_FEM_ANTSWLUT);
1850
1851 /* Extract cores power info info */
1852 for (i = 0; i < nitems(pwr_info_offset); i++) {
1853 uint16_t o = pwr_info_offset[i];
1854 SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SROM8_2G_MAXP_ITSSI,
1855 SIBA_SPROM8_2G_ITSSI);
1856 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SROM8_2G_MAXP_ITSSI,
1857 SIBA_SPROM8_2G_MAXP);
1858
1859 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SROM8_2G_PA_0, ~0);
1860 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SROM8_2G_PA_1, ~0);
1861 SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SROM8_2G_PA_2, ~0);
1862
1863 SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SROM8_5G_MAXP_ITSSI,
1864 SIBA_SPROM8_5G_ITSSI);
1865 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SROM8_5G_MAXP_ITSSI,
1866 SIBA_SPROM8_5G_MAXP);
1867 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM8_5GHL_MAXP,
1868 SIBA_SPROM8_5GH_MAXP);
1869 SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM8_5GHL_MAXP,
1870 SIBA_SPROM8_5GL_MAXP);
1871
1872 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SROM8_5GL_PA_0, ~0);
1873 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SROM8_5GL_PA_1, ~0);
1874 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SROM8_5GL_PA_2, ~0);
1875 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SROM8_5G_PA_0, ~0);
1876 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SROM8_5G_PA_1, ~0);
1877 SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SROM8_5G_PA_2, ~0);
1878 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SROM8_5GH_PA_0, ~0);
1879 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SROM8_5GH_PA_1, ~0);
1880 SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SROM8_5GH_PA_2, ~0);
1881 }
1882
1883 SIBA_SHIFTOUT(cddpo, SIBA_SPROM8_CDDPO, ~0);
1884 SIBA_SHIFTOUT(stbcpo, SIBA_SPROM8_STBCPO, ~0);
1885
1886 siba_sprom_r458(out, in);
1887 }
1888
1889 static int8_t
siba_sprom_r123_antgain(uint8_t sprom_revision,const uint16_t * in,uint16_t mask,uint16_t shift)1890 siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in,
1891 uint16_t mask, uint16_t shift)
1892 {
1893 uint16_t v;
1894 uint8_t gain;
1895
1896 v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)];
1897 gain = (v & mask) >> shift;
1898 gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 :
1899 ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2);
1900
1901 return ((int8_t)gain);
1902 }
1903
1904 #undef SIBA_LOWEST_SET_BIT
1905 #undef SIBA_OFFSET
1906 #undef SIBA_SHIFTOUT_SUB
1907 #undef SIBA_SHIFTOUT
1908
1909 int
siba_powerdown(device_t dev)1910 siba_powerdown(device_t dev)
1911 {
1912 struct siba_dev_softc *sd = device_get_ivars(dev);
1913 struct siba_softc *siba = sd->sd_bus;
1914
1915 return (siba_powerdown_sub(siba));
1916 }
1917
1918 static int
siba_powerdown_sub(struct siba_softc * siba)1919 siba_powerdown_sub(struct siba_softc *siba)
1920 {
1921 struct siba_cc *scc;
1922
1923 if (siba->siba_type == SIBA_TYPE_SSB)
1924 return (0);
1925
1926 scc = &siba->siba_cc;
1927 if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5)
1928 return (0);
1929 siba_cc_clock(scc, SIBA_CLOCK_SLOW);
1930 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
1931 return (0);
1932 }
1933
1934 static void
siba_pcicore_init(struct siba_pci * spc)1935 siba_pcicore_init(struct siba_pci *spc)
1936 {
1937 struct siba_dev_softc *sd = spc->spc_dev;
1938
1939 if (sd == NULL)
1940 return;
1941
1942 if (!siba_dev_isup_sub(sd))
1943 siba_dev_up_sub(sd, 0);
1944
1945 KASSERT(spc->spc_hostmode == 0,
1946 ("%s:%d: hostmode", __func__, __LINE__));
1947 /* disable PCI interrupt */
1948 siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0);
1949 }
1950
1951 int
siba_dev_isup(device_t dev)1952 siba_dev_isup(device_t dev)
1953 {
1954 struct siba_dev_softc *sd = device_get_ivars(dev);
1955
1956 return (siba_dev_isup_sub(sd));
1957 }
1958
1959 static int
siba_dev_isup_sub(struct siba_dev_softc * sd)1960 siba_dev_isup_sub(struct siba_dev_softc *sd)
1961 {
1962 uint32_t reject, val;
1963
1964 reject = siba_tmslow_reject_bitmask(sd);
1965 val = siba_read_4_sub(sd, SIBA_TGSLOW);
1966 val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject;
1967
1968 return (val == SIBA_TGSLOW_CLOCK);
1969 }
1970
1971 void
siba_dev_up(device_t dev,uint32_t flags)1972 siba_dev_up(device_t dev, uint32_t flags)
1973 {
1974 struct siba_dev_softc *sd = device_get_ivars(dev);
1975
1976 siba_dev_up_sub(sd, flags);
1977 }
1978
1979 static void
siba_dev_up_sub(struct siba_dev_softc * sd,uint32_t flags)1980 siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags)
1981 {
1982 uint32_t val;
1983
1984 siba_dev_down_sub(sd, flags);
1985 siba_write_4_sub(sd, SIBA_TGSLOW,
1986 SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
1987 siba_read_4_sub(sd, SIBA_TGSLOW);
1988 DELAY(1);
1989
1990 if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR)
1991 siba_write_4_sub(sd, SIBA_TGSHIGH, 0);
1992
1993 val = siba_read_4_sub(sd, SIBA_IAS);
1994 if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) {
1995 val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT);
1996 siba_write_4_sub(sd, SIBA_IAS, val);
1997 }
1998
1999 siba_write_4_sub(sd, SIBA_TGSLOW,
2000 SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
2001 siba_read_4_sub(sd, SIBA_TGSLOW);
2002 DELAY(1);
2003
2004 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags);
2005 siba_read_4_sub(sd, SIBA_TGSLOW);
2006 DELAY(1);
2007 }
2008
2009 static uint32_t
siba_tmslow_reject_bitmask(struct siba_dev_softc * sd)2010 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd)
2011 {
2012 uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV;
2013
2014 switch (rev) {
2015 case SIBA_IDLOW_SSBREV_22:
2016 return (SIBA_TGSLOW_REJECT_22);
2017 case SIBA_IDLOW_SSBREV_23:
2018 return (SIBA_TGSLOW_REJECT_23);
2019 case SIBA_IDLOW_SSBREV_24:
2020 case SIBA_IDLOW_SSBREV_25:
2021 case SIBA_IDLOW_SSBREV_26:
2022 case SIBA_IDLOW_SSBREV_27:
2023 return (SIBA_TGSLOW_REJECT_23);
2024 default:
2025 KASSERT(0 == 1,
2026 ("%s:%d: unknown backplane rev %#x\n",
2027 __func__, __LINE__, rev));
2028 }
2029 return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23);
2030 }
2031
2032 void
siba_dev_down(device_t dev,uint32_t flags)2033 siba_dev_down(device_t dev, uint32_t flags)
2034 {
2035 struct siba_dev_softc *sd = device_get_ivars(dev);
2036
2037 siba_dev_down_sub(sd, flags);
2038 }
2039
2040 static void
siba_dev_down_sub(struct siba_dev_softc * sd,uint32_t flags)2041 siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags)
2042 {
2043 struct siba_softc *siba = sd->sd_bus;
2044 uint32_t reject, val;
2045 int i;
2046
2047 if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET)
2048 return;
2049
2050 reject = siba_tmslow_reject_bitmask(sd);
2051 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK);
2052
2053 for (i = 0; i < 1000; i++) {
2054 val = siba_read_4_sub(sd, SIBA_TGSLOW);
2055 if (val & reject)
2056 break;
2057 DELAY(10);
2058 }
2059 if ((val & reject) == 0) {
2060 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
2061 reject, SIBA_TGSLOW);
2062 }
2063 for (i = 0; i < 1000; i++) {
2064 val = siba_read_4_sub(sd, SIBA_TGSHIGH);
2065 if (!(val & SIBA_TGSHIGH_BUSY))
2066 break;
2067 DELAY(10);
2068 }
2069 if ((val & SIBA_TGSHIGH_BUSY) != 0) {
2070 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
2071 SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH);
2072 }
2073
2074 siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK |
2075 reject | SIBA_TGSLOW_RESET | flags);
2076 siba_read_4_sub(sd, SIBA_TGSLOW);
2077 DELAY(1);
2078 siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags);
2079 siba_read_4_sub(sd, SIBA_TGSLOW);
2080 DELAY(1);
2081 }
2082
2083 static void
siba_pcicore_setup(struct siba_pci * spc,struct siba_dev_softc * sd)2084 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd)
2085 {
2086 struct siba_dev_softc *psd = spc->spc_dev;
2087 struct siba_softc *siba = psd->sd_bus;
2088 uint32_t tmp;
2089
2090 if (psd->sd_id.sd_device == SIBA_DEVID_PCI) {
2091 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2,
2092 siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) |
2093 SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST);
2094
2095 if (psd->sd_id.sd_rev < 5) {
2096 tmp = siba_read_4_sub(psd, SIBA_IMCFGLO);
2097 tmp &= ~SIBA_IMCFGLO_SERTO;
2098 tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO;
2099 tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */;
2100 siba_write_4_sub(psd, SIBA_IMCFGLO, tmp);
2101
2102 /* broadcast value */
2103 sd = (siba->siba_cc.scc_dev != NULL) ?
2104 siba->siba_cc.scc_dev : siba->siba_pci.spc_dev;
2105 if (sd != NULL) {
2106 siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR,
2107 0xfd8);
2108 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR);
2109 siba_write_4_sub(sd,
2110 SIBA_PCICORE_BCAST_DATA, 0);
2111 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA);
2112 }
2113 } else if (psd->sd_id.sd_rev >= 11) {
2114 tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2);
2115 tmp |= SIBA_PCICORE_SBTOPCI_MRM;
2116 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp);
2117 }
2118 } else {
2119 KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE"));
2120 if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1))
2121 siba_pcie_write(spc, 0x4,
2122 siba_pcie_read(spc, 0x4) | 0x8);
2123 if (psd->sd_id.sd_rev == 0) {
2124 siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */
2125 siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */
2126 siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */
2127 } else if (psd->sd_id.sd_rev == 1)
2128 siba_pcie_write(spc, 0x100,
2129 siba_pcie_read(spc, 0x100) | 0x40);
2130 }
2131 spc->spc_inited = 1;
2132 }
2133
2134 void
siba_pcicore_intr(device_t dev)2135 siba_pcicore_intr(device_t dev)
2136 {
2137 struct siba_dev_softc *sd = device_get_ivars(dev);
2138 struct siba_softc *siba = sd->sd_bus;
2139 struct siba_pci *spc = &siba->siba_pci;
2140 struct siba_dev_softc *psd = spc->spc_dev;
2141 uint32_t tmp;
2142
2143 if (siba->siba_type != SIBA_TYPE_PCI || !psd)
2144 return;
2145
2146 KASSERT(siba == psd->sd_bus, ("different pointers"));
2147
2148 /* enable interrupts */
2149 if (siba->siba_dev != NULL &&
2150 (psd->sd_id.sd_rev >= 6 ||
2151 psd->sd_id.sd_device == SIBA_DEVID_PCIE)) {
2152 tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4);
2153 tmp |= (1 << sd->sd_coreidx) << 8;
2154 pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4);
2155 } else {
2156 tmp = siba_read_4_sub(sd, SIBA_TPS);
2157 tmp &= SIBA_TPS_BPFLAG;
2158 siba_write_4_sub(psd, SIBA_INTR_MASK,
2159 siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp));
2160 }
2161
2162 /* setup PCIcore */
2163 if (spc->spc_inited == 0)
2164 siba_pcicore_setup(spc, sd);
2165 }
2166
2167 static uint32_t
siba_pcicore_read_4(struct siba_pci * spc,uint16_t offset)2168 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset)
2169 {
2170
2171 return (siba_read_4_sub(spc->spc_dev, offset));
2172 }
2173
2174 static void
siba_pcicore_write_4(struct siba_pci * spc,uint16_t offset,uint32_t value)2175 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value)
2176 {
2177
2178 siba_write_4_sub(spc->spc_dev, offset, value);
2179 }
2180
2181 static uint32_t
siba_pcie_read(struct siba_pci * spc,uint32_t address)2182 siba_pcie_read(struct siba_pci *spc, uint32_t address)
2183 {
2184
2185 siba_pcicore_write_4(spc, 0x130, address);
2186 return (siba_pcicore_read_4(spc, 0x134));
2187 }
2188
2189 static void
siba_pcie_write(struct siba_pci * spc,uint32_t address,uint32_t data)2190 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data)
2191 {
2192
2193 siba_pcicore_write_4(spc, 0x130, address);
2194 siba_pcicore_write_4(spc, 0x134, data);
2195 }
2196
2197 static void
siba_pcie_mdio_write(struct siba_pci * spc,uint8_t device,uint8_t address,uint16_t data)2198 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address,
2199 uint16_t data)
2200 {
2201 int i;
2202
2203 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2);
2204 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA,
2205 (1 << 30) | (1 << 28) |
2206 ((uint32_t)device << 22) | ((uint32_t)address << 18) |
2207 (1 << 17) | data);
2208 DELAY(10);
2209 for (i = 0; i < 10; i++) {
2210 if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100)
2211 break;
2212 DELAY(1000);
2213 }
2214 siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0);
2215 }
2216
2217 uint32_t
siba_dma_translation(device_t dev)2218 siba_dma_translation(device_t dev)
2219 {
2220 #ifdef INVARIANTS
2221 struct siba_dev_softc *sd = device_get_ivars(dev);
2222 struct siba_softc *siba = sd->sd_bus;
2223
2224 KASSERT(siba->siba_type == SIBA_TYPE_PCI,
2225 ("unsupported bustype %d\n", siba->siba_type));
2226 #endif
2227
2228 /* Default */
2229 return (SIBA_PCI_DMA);
2230 }
2231
2232 void
siba_barrier(device_t dev,int flags)2233 siba_barrier(device_t dev, int flags)
2234 {
2235 struct siba_dev_softc *sd = device_get_ivars(dev);
2236 struct siba_softc *siba = sd->sd_bus;
2237
2238 SIBA_BARRIER(siba, flags);
2239 }
2240
2241 static void
siba_cc_suspend(struct siba_cc * scc)2242 siba_cc_suspend(struct siba_cc *scc)
2243 {
2244
2245 siba_cc_clock(scc, SIBA_CLOCK_SLOW);
2246 }
2247
2248 static void
siba_cc_resume(struct siba_cc * scc)2249 siba_cc_resume(struct siba_cc *scc)
2250 {
2251
2252 siba_cc_power_init(scc);
2253 siba_cc_clock(scc, SIBA_CLOCK_FAST);
2254 }
2255
2256 int
siba_core_suspend(struct siba_softc * siba)2257 siba_core_suspend(struct siba_softc *siba)
2258 {
2259
2260 siba_cc_suspend(&siba->siba_cc);
2261 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
2262 return (0);
2263 }
2264
2265 int
siba_core_resume(struct siba_softc * siba)2266 siba_core_resume(struct siba_softc *siba)
2267 {
2268
2269 siba->siba_pci.spc_inited = 0;
2270 siba->siba_curdev = NULL;
2271
2272 siba_powerup_sub(siba, 0);
2273 /* XXX setup H/W for PCMCIA??? */
2274 siba_cc_resume(&siba->siba_cc);
2275 siba_powerdown_sub(siba);
2276
2277 return (0);
2278 }
2279
2280 static void
siba_cc_regctl_setmask(struct siba_cc * cc,uint32_t offset,uint32_t mask,uint32_t set)2281 siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask,
2282 uint32_t set)
2283 {
2284
2285 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
2286 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset);
2287 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
2288 SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA,
2289 (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set);
2290 SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA);
2291 }
2292
2293 void
siba_cc_pmu_set_ldovolt(device_t dev,int id,uint32_t volt)2294 siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt)
2295 {
2296 struct siba_dev_softc *sd = device_get_ivars(dev);
2297 struct siba_softc *siba = sd->sd_bus;
2298 struct siba_cc *scc = &siba->siba_cc;
2299 uint32_t *p = NULL, info[5][3] = {
2300 { 2, 25, 0xf },
2301 { 3, 1, 0xf },
2302 { 3, 9, 0xf },
2303 { 3, 17, 0x3f },
2304 { 0, 21, 0x3f }
2305 };
2306
2307 if (siba->siba_chipid == 0x4312) {
2308 if (id != SIBA_LDO_PAREF)
2309 return;
2310 p = info[4];
2311 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2312 (volt & p[2]) << p[1]);
2313 return;
2314 }
2315 if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) {
2316 switch (id) {
2317 case SIBA_LDO_PAREF:
2318 p = info[3];
2319 break;
2320 case SIBA_LDO_VOLT1:
2321 p = info[0];
2322 break;
2323 case SIBA_LDO_VOLT2:
2324 p = info[1];
2325 break;
2326 case SIBA_LDO_VOLT3:
2327 p = info[2];
2328 break;
2329 default:
2330 KASSERT(0 == 1,
2331 ("%s: unsupported voltage ID %#x", __func__, id));
2332 return;
2333 }
2334 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2335 (volt & p[2]) << p[1]);
2336 }
2337 }
2338
2339 void
siba_cc_pmu_set_ldoparef(device_t dev,uint8_t on)2340 siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on)
2341 {
2342 struct siba_dev_softc *sd = device_get_ivars(dev);
2343 struct siba_softc *siba = sd->sd_bus;
2344 struct siba_cc *scc = &siba->siba_cc;
2345 int ldo;
2346
2347 ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF :
2348 ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF :
2349 ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1)));
2350 if (ldo == -1)
2351 return;
2352
2353 if (on)
2354 SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo);
2355 else
2356 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo));
2357 SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES);
2358 }
2359
2360 int
siba_read_sprom(device_t dev,device_t child,int which,uintptr_t * result)2361 siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result)
2362 {
2363 struct siba_dev_softc *sd = device_get_ivars(child);
2364 struct siba_softc *siba = sd->sd_bus;
2365
2366 switch (which) {
2367 case SIBA_SPROMVAR_REV:
2368 *result = siba->siba_sprom.rev;
2369 break;
2370 case SIBA_SPROMVAR_MAC_80211BG:
2371 *((uint8_t **) result) = siba->siba_sprom.mac_80211bg;
2372 break;
2373 case SIBA_SPROMVAR_MAC_ETH:
2374 *((uint8_t **) result) = siba->siba_sprom.mac_eth;
2375 break;
2376 case SIBA_SPROMVAR_MAC_80211A:
2377 *((uint8_t **) result) = siba->siba_sprom.mac_80211a;
2378 break;
2379 case SIBA_SPROMVAR_MII_ETH0:
2380 *result = siba->siba_sprom.mii_eth0;
2381 break;
2382 case SIBA_SPROMVAR_MII_ETH1:
2383 *result = siba->siba_sprom.mii_eth1;
2384 break;
2385 case SIBA_SPROMVAR_MDIO_ETH0:
2386 *result = siba->siba_sprom.mdio_eth0;
2387 break;
2388 case SIBA_SPROMVAR_MDIO_ETH1:
2389 *result = siba->siba_sprom.mdio_eth1;
2390 break;
2391 case SIBA_SPROMVAR_BREV:
2392 *result = siba->siba_sprom.brev;
2393 break;
2394 case SIBA_SPROMVAR_CCODE:
2395 *result = siba->siba_sprom.ccode;
2396 break;
2397 case SIBA_SPROMVAR_ANT_A:
2398 *result = siba->siba_sprom.ant_a;
2399 break;
2400 case SIBA_SPROMVAR_ANT_BG:
2401 *result = siba->siba_sprom.ant_bg;
2402 break;
2403 case SIBA_SPROMVAR_PA0B0:
2404 *result = siba->siba_sprom.pa0b0;
2405 break;
2406 case SIBA_SPROMVAR_PA0B1:
2407 *result = siba->siba_sprom.pa0b1;
2408 break;
2409 case SIBA_SPROMVAR_PA0B2:
2410 *result = siba->siba_sprom.pa0b2;
2411 break;
2412 case SIBA_SPROMVAR_PA1B0:
2413 *result = siba->siba_sprom.pa1b0;
2414 break;
2415 case SIBA_SPROMVAR_PA1B1:
2416 *result = siba->siba_sprom.pa1b1;
2417 break;
2418 case SIBA_SPROMVAR_PA1B2:
2419 *result = siba->siba_sprom.pa1b2;
2420 break;
2421 case SIBA_SPROMVAR_PA1LOB0:
2422 *result = siba->siba_sprom.pa1lob0;
2423 break;
2424 case SIBA_SPROMVAR_PA1LOB1:
2425 *result = siba->siba_sprom.pa1lob1;
2426 break;
2427 case SIBA_SPROMVAR_PA1LOB2:
2428 *result = siba->siba_sprom.pa1lob2;
2429 break;
2430 case SIBA_SPROMVAR_PA1HIB0:
2431 *result = siba->siba_sprom.pa1hib0;
2432 break;
2433 case SIBA_SPROMVAR_PA1HIB1:
2434 *result = siba->siba_sprom.pa1hib1;
2435 break;
2436 case SIBA_SPROMVAR_PA1HIB2:
2437 *result = siba->siba_sprom.pa1hib2;
2438 break;
2439 case SIBA_SPROMVAR_GPIO0:
2440 *result = siba->siba_sprom.gpio0;
2441 break;
2442 case SIBA_SPROMVAR_GPIO1:
2443 *result = siba->siba_sprom.gpio1;
2444 break;
2445 case SIBA_SPROMVAR_GPIO2:
2446 *result = siba->siba_sprom.gpio2;
2447 break;
2448 case SIBA_SPROMVAR_GPIO3:
2449 *result = siba->siba_sprom.gpio3;
2450 break;
2451 case SIBA_SPROMVAR_MAXPWR_AL:
2452 *result = siba->siba_sprom.maxpwr_al;
2453 break;
2454 case SIBA_SPROMVAR_MAXPWR_A:
2455 *result = siba->siba_sprom.maxpwr_a;
2456 break;
2457 case SIBA_SPROMVAR_MAXPWR_AH:
2458 *result = siba->siba_sprom.maxpwr_ah;
2459 break;
2460 case SIBA_SPROMVAR_MAXPWR_BG:
2461 *result = siba->siba_sprom.maxpwr_bg;
2462 break;
2463 case SIBA_SPROMVAR_RXPO2G:
2464 *result = siba->siba_sprom.rxpo2g;
2465 break;
2466 case SIBA_SPROMVAR_RXPO5G:
2467 *result = siba->siba_sprom.rxpo5g;
2468 break;
2469 case SIBA_SPROMVAR_TSSI_A:
2470 *result = siba->siba_sprom.tssi_a;
2471 break;
2472 case SIBA_SPROMVAR_TSSI_BG:
2473 *result = siba->siba_sprom.tssi_bg;
2474 break;
2475 case SIBA_SPROMVAR_TRI2G:
2476 *result = siba->siba_sprom.tri2g;
2477 break;
2478 case SIBA_SPROMVAR_TRI5GL:
2479 *result = siba->siba_sprom.tri5gl;
2480 break;
2481 case SIBA_SPROMVAR_TRI5G:
2482 *result = siba->siba_sprom.tri5g;
2483 break;
2484 case SIBA_SPROMVAR_TRI5GH:
2485 *result = siba->siba_sprom.tri5gh;
2486 break;
2487 case SIBA_SPROMVAR_RSSISAV2G:
2488 *result = siba->siba_sprom.rssisav2g;
2489 break;
2490 case SIBA_SPROMVAR_RSSISMC2G:
2491 *result = siba->siba_sprom.rssismc2g;
2492 break;
2493 case SIBA_SPROMVAR_RSSISMF2G:
2494 *result = siba->siba_sprom.rssismf2g;
2495 break;
2496 case SIBA_SPROMVAR_BXA2G:
2497 *result = siba->siba_sprom.bxa2g;
2498 break;
2499 case SIBA_SPROMVAR_RSSISAV5G:
2500 *result = siba->siba_sprom.rssisav5g;
2501 break;
2502 case SIBA_SPROMVAR_RSSISMC5G:
2503 *result = siba->siba_sprom.rssismc5g;
2504 break;
2505 case SIBA_SPROMVAR_RSSISMF5G:
2506 *result = siba->siba_sprom.rssismf5g;
2507 break;
2508 case SIBA_SPROMVAR_BXA5G:
2509 *result = siba->siba_sprom.bxa5g;
2510 break;
2511 case SIBA_SPROMVAR_CCK2GPO:
2512 *result = siba->siba_sprom.cck2gpo;
2513 break;
2514 case SIBA_SPROMVAR_OFDM2GPO:
2515 *result = siba->siba_sprom.ofdm2gpo;
2516 break;
2517 case SIBA_SPROMVAR_OFDM5GLPO:
2518 *result = siba->siba_sprom.ofdm5glpo;
2519 break;
2520 case SIBA_SPROMVAR_OFDM5GPO:
2521 *result = siba->siba_sprom.ofdm5gpo;
2522 break;
2523 case SIBA_SPROMVAR_OFDM5GHPO:
2524 *result = siba->siba_sprom.ofdm5ghpo;
2525 break;
2526 case SIBA_SPROMVAR_BF_LO:
2527 *result = siba->siba_sprom.bf_lo;
2528 break;
2529 case SIBA_SPROMVAR_BF_HI:
2530 *result = siba->siba_sprom.bf_hi;
2531 break;
2532 case SIBA_SPROMVAR_BF2_LO:
2533 *result = siba->siba_sprom.bf2_lo;
2534 break;
2535 case SIBA_SPROMVAR_BF2_HI:
2536 *result = siba->siba_sprom.bf2_hi;
2537 break;
2538 case SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS:
2539 *result = siba->siba_sprom.fem.ghz2.tssipos;
2540 break;
2541 case SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN:
2542 *result = siba->siba_sprom.fem.ghz2.extpa_gain;
2543 break;
2544 case SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE:
2545 *result = siba->siba_sprom.fem.ghz2.pdet_range;
2546 break;
2547 case SIBA_SPROMVAR_FEM_2GHZ_TR_ISO:
2548 *result = siba->siba_sprom.fem.ghz2.tr_iso;
2549 break;
2550 case SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT:
2551 *result = siba->siba_sprom.fem.ghz2.antswlut;
2552 break;
2553 case SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS:
2554 *result = siba->siba_sprom.fem.ghz5.tssipos;
2555 break;
2556 case SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN:
2557 *result = siba->siba_sprom.fem.ghz5.extpa_gain;
2558 break;
2559 case SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE:
2560 *result = siba->siba_sprom.fem.ghz5.pdet_range;
2561 break;
2562 case SIBA_SPROMVAR_FEM_5GHZ_TR_ISO:
2563 *result = siba->siba_sprom.fem.ghz5.tr_iso;
2564 break;
2565 case SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT:
2566 *result = siba->siba_sprom.fem.ghz5.antswlut;
2567 break;
2568 case SIBA_SPROMVAR_TXPID_2G_0:
2569 *result = siba->siba_sprom.txpid2g[0];
2570 break;
2571 case SIBA_SPROMVAR_TXPID_2G_1:
2572 *result = siba->siba_sprom.txpid2g[1];
2573 break;
2574 case SIBA_SPROMVAR_TXPID_2G_2:
2575 *result = siba->siba_sprom.txpid2g[2];
2576 break;
2577 case SIBA_SPROMVAR_TXPID_2G_3:
2578 *result = siba->siba_sprom.txpid2g[3];
2579 break;
2580 case SIBA_SPROMVAR_TXPID_5GL_0:
2581 *result = siba->siba_sprom.txpid5gl[0];
2582 break;
2583 case SIBA_SPROMVAR_TXPID_5GL_1:
2584 *result = siba->siba_sprom.txpid5gl[1];
2585 break;
2586 case SIBA_SPROMVAR_TXPID_5GL_2:
2587 *result = siba->siba_sprom.txpid5gl[2];
2588 break;
2589 case SIBA_SPROMVAR_TXPID_5GL_3:
2590 *result = siba->siba_sprom.txpid5gl[3];
2591 break;
2592 case SIBA_SPROMVAR_TXPID_5G_0:
2593 *result = siba->siba_sprom.txpid5g[0];
2594 break;
2595 case SIBA_SPROMVAR_TXPID_5G_1:
2596 *result = siba->siba_sprom.txpid5g[1];
2597 break;
2598 case SIBA_SPROMVAR_TXPID_5G_2:
2599 *result = siba->siba_sprom.txpid5g[2];
2600 break;
2601 case SIBA_SPROMVAR_TXPID_5G_3:
2602 *result = siba->siba_sprom.txpid5g[3];
2603 break;
2604 case SIBA_SPROMVAR_TXPID_5GH_0:
2605 *result = siba->siba_sprom.txpid5gh[0];
2606 break;
2607 case SIBA_SPROMVAR_TXPID_5GH_1:
2608 *result = siba->siba_sprom.txpid5gh[1];
2609 break;
2610 case SIBA_SPROMVAR_TXPID_5GH_2:
2611 *result = siba->siba_sprom.txpid5gh[2];
2612 break;
2613 case SIBA_SPROMVAR_TXPID_5GH_3:
2614 *result = siba->siba_sprom.txpid5gh[3];
2615 break;
2616 case SIBA_SPROMVAR_STBCPO:
2617 *result = siba->siba_sprom.stbcpo;
2618 break;
2619 case SIBA_SPROMVAR_CDDPO:
2620 *result = siba->siba_sprom.cddpo;
2621 break;
2622 default:
2623 return (ENOENT);
2624 }
2625 return (0);
2626 }
2627
2628 int
siba_write_sprom(device_t dev,device_t child,int which,uintptr_t value)2629 siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value)
2630 {
2631 struct siba_dev_softc *sd = device_get_ivars(child);
2632 struct siba_softc *siba = sd->sd_bus;
2633
2634 switch (which) {
2635 case SIBA_SPROMVAR_REV:
2636 siba->siba_sprom.rev = value;
2637 break;
2638 case SIBA_SPROMVAR_MII_ETH0:
2639 siba->siba_sprom.mii_eth0 = value;
2640 break;
2641 case SIBA_SPROMVAR_MII_ETH1:
2642 siba->siba_sprom.mii_eth1 = value;
2643 break;
2644 case SIBA_SPROMVAR_MDIO_ETH0:
2645 siba->siba_sprom.mdio_eth0 = value;
2646 break;
2647 case SIBA_SPROMVAR_MDIO_ETH1:
2648 siba->siba_sprom.mdio_eth1 = value;
2649 break;
2650 case SIBA_SPROMVAR_BREV:
2651 siba->siba_sprom.brev = value;
2652 break;
2653 case SIBA_SPROMVAR_CCODE:
2654 siba->siba_sprom.ccode = value;
2655 break;
2656 case SIBA_SPROMVAR_ANT_A:
2657 siba->siba_sprom.ant_a = value;
2658 break;
2659 case SIBA_SPROMVAR_ANT_BG:
2660 siba->siba_sprom.ant_bg = value;
2661 break;
2662 case SIBA_SPROMVAR_PA0B0:
2663 siba->siba_sprom.pa0b0 = value;
2664 break;
2665 case SIBA_SPROMVAR_PA0B1:
2666 siba->siba_sprom.pa0b1 = value;
2667 break;
2668 case SIBA_SPROMVAR_PA0B2:
2669 siba->siba_sprom.pa0b2 = value;
2670 break;
2671 case SIBA_SPROMVAR_PA1B0:
2672 siba->siba_sprom.pa1b0 = value;
2673 break;
2674 case SIBA_SPROMVAR_PA1B1:
2675 siba->siba_sprom.pa1b1 = value;
2676 break;
2677 case SIBA_SPROMVAR_PA1B2:
2678 siba->siba_sprom.pa1b2 = value;
2679 break;
2680 case SIBA_SPROMVAR_PA1LOB0:
2681 siba->siba_sprom.pa1lob0 = value;
2682 break;
2683 case SIBA_SPROMVAR_PA1LOB1:
2684 siba->siba_sprom.pa1lob1 = value;
2685 break;
2686 case SIBA_SPROMVAR_PA1LOB2:
2687 siba->siba_sprom.pa1lob2 = value;
2688 break;
2689 case SIBA_SPROMVAR_PA1HIB0:
2690 siba->siba_sprom.pa1hib0 = value;
2691 break;
2692 case SIBA_SPROMVAR_PA1HIB1:
2693 siba->siba_sprom.pa1hib1 = value;
2694 break;
2695 case SIBA_SPROMVAR_PA1HIB2:
2696 siba->siba_sprom.pa1hib2 = value;
2697 break;
2698 case SIBA_SPROMVAR_GPIO0:
2699 siba->siba_sprom.gpio0 = value;
2700 break;
2701 case SIBA_SPROMVAR_GPIO1:
2702 siba->siba_sprom.gpio1 = value;
2703 break;
2704 case SIBA_SPROMVAR_GPIO2:
2705 siba->siba_sprom.gpio2 = value;
2706 break;
2707 case SIBA_SPROMVAR_GPIO3:
2708 siba->siba_sprom.gpio3 = value;
2709 break;
2710 case SIBA_SPROMVAR_MAXPWR_AL:
2711 siba->siba_sprom.maxpwr_al = value;
2712 break;
2713 case SIBA_SPROMVAR_MAXPWR_A:
2714 siba->siba_sprom.maxpwr_a = value;
2715 break;
2716 case SIBA_SPROMVAR_MAXPWR_AH:
2717 siba->siba_sprom.maxpwr_ah = value;
2718 break;
2719 case SIBA_SPROMVAR_MAXPWR_BG:
2720 siba->siba_sprom.maxpwr_bg = value;
2721 break;
2722 case SIBA_SPROMVAR_RXPO2G:
2723 siba->siba_sprom.rxpo2g = value;
2724 break;
2725 case SIBA_SPROMVAR_RXPO5G:
2726 siba->siba_sprom.rxpo5g = value;
2727 break;
2728 case SIBA_SPROMVAR_TSSI_A:
2729 siba->siba_sprom.tssi_a = value;
2730 break;
2731 case SIBA_SPROMVAR_TSSI_BG:
2732 siba->siba_sprom.tssi_bg = value;
2733 break;
2734 case SIBA_SPROMVAR_TRI2G:
2735 siba->siba_sprom.tri2g = value;
2736 break;
2737 case SIBA_SPROMVAR_TRI5GL:
2738 siba->siba_sprom.tri5gl = value;
2739 break;
2740 case SIBA_SPROMVAR_TRI5G:
2741 siba->siba_sprom.tri5g = value;
2742 break;
2743 case SIBA_SPROMVAR_TRI5GH:
2744 siba->siba_sprom.tri5gh = value;
2745 break;
2746 case SIBA_SPROMVAR_RSSISAV2G:
2747 siba->siba_sprom.rssisav2g = value;
2748 break;
2749 case SIBA_SPROMVAR_RSSISMC2G:
2750 siba->siba_sprom.rssismc2g = value;
2751 break;
2752 case SIBA_SPROMVAR_RSSISMF2G:
2753 siba->siba_sprom.rssismf2g = value;
2754 break;
2755 case SIBA_SPROMVAR_BXA2G:
2756 siba->siba_sprom.bxa2g = value;
2757 break;
2758 case SIBA_SPROMVAR_RSSISAV5G:
2759 siba->siba_sprom.rssisav5g = value;
2760 break;
2761 case SIBA_SPROMVAR_RSSISMC5G:
2762 siba->siba_sprom.rssismc5g = value;
2763 break;
2764 case SIBA_SPROMVAR_RSSISMF5G:
2765 siba->siba_sprom.rssismf5g = value;
2766 break;
2767 case SIBA_SPROMVAR_BXA5G:
2768 siba->siba_sprom.bxa5g = value;
2769 break;
2770 case SIBA_SPROMVAR_CCK2GPO:
2771 siba->siba_sprom.cck2gpo = value;
2772 break;
2773 case SIBA_SPROMVAR_OFDM2GPO:
2774 siba->siba_sprom.ofdm2gpo = value;
2775 break;
2776 case SIBA_SPROMVAR_OFDM5GLPO:
2777 siba->siba_sprom.ofdm5glpo = value;
2778 break;
2779 case SIBA_SPROMVAR_OFDM5GPO:
2780 siba->siba_sprom.ofdm5gpo = value;
2781 break;
2782 case SIBA_SPROMVAR_OFDM5GHPO:
2783 siba->siba_sprom.ofdm5ghpo = value;
2784 break;
2785 case SIBA_SPROMVAR_BF_LO:
2786 siba->siba_sprom.bf_lo = value;
2787 break;
2788 case SIBA_SPROMVAR_BF_HI:
2789 siba->siba_sprom.bf_hi = value;
2790 break;
2791 case SIBA_SPROMVAR_BF2_LO:
2792 siba->siba_sprom.bf2_lo = value;
2793 break;
2794 case SIBA_SPROMVAR_BF2_HI:
2795 siba->siba_sprom.bf2_hi = value;
2796 break;
2797 default:
2798 return (ENOENT);
2799 }
2800 return (0);
2801 }
2802
2803 #define SIBA_GPIOCTL 0x06c
2804
2805 uint32_t
siba_gpio_get(device_t dev)2806 siba_gpio_get(device_t dev)
2807 {
2808 struct siba_dev_softc *sd = device_get_ivars(dev);
2809 struct siba_softc *siba = sd->sd_bus;
2810 struct siba_dev_softc *gpiodev, *pcidev = NULL;
2811
2812 pcidev = siba->siba_pci.spc_dev;
2813 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
2814 if (!gpiodev)
2815 return (-1);
2816 return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL));
2817 }
2818
2819 void
siba_gpio_set(device_t dev,uint32_t value)2820 siba_gpio_set(device_t dev, uint32_t value)
2821 {
2822 struct siba_dev_softc *sd = device_get_ivars(dev);
2823 struct siba_softc *siba = sd->sd_bus;
2824 struct siba_dev_softc *gpiodev, *pcidev = NULL;
2825
2826 pcidev = siba->siba_pci.spc_dev;
2827 gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
2828 if (!gpiodev)
2829 return;
2830 siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value);
2831 }
2832
2833 void
siba_fix_imcfglobug(device_t dev)2834 siba_fix_imcfglobug(device_t dev)
2835 {
2836 struct siba_dev_softc *sd = device_get_ivars(dev);
2837 struct siba_softc *siba = sd->sd_bus;
2838 uint32_t tmp;
2839
2840 if (siba->siba_pci.spc_dev == NULL)
2841 return;
2842 if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI ||
2843 siba->siba_pci.spc_dev->sd_id.sd_rev > 5)
2844 return;
2845
2846 tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) &
2847 ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO);
2848 switch (siba->siba_type) {
2849 case SIBA_TYPE_PCI:
2850 case SIBA_TYPE_PCMCIA:
2851 tmp |= 0x32;
2852 break;
2853 case SIBA_TYPE_SSB:
2854 tmp |= 0x53;
2855 break;
2856 }
2857 siba_write_4_sub(sd, SIBA_IMCFGLO, tmp);
2858 }
2859
2860 int
siba_sprom_get_core_power_info(device_t dev,int core,struct siba_sprom_core_pwr_info * c)2861 siba_sprom_get_core_power_info(device_t dev, int core,
2862 struct siba_sprom_core_pwr_info *c)
2863 {
2864 struct siba_dev_softc *sd = device_get_ivars(dev);
2865 struct siba_softc *siba = sd->sd_bus;
2866
2867 if (core < 0 || core > 3) {
2868 return (EINVAL);
2869 }
2870 memcpy(c, &siba->siba_sprom.core_pwr_info[core], sizeof(*c));
2871 return (0);
2872 }
2873
2874 int
siba_sprom_get_mcs2gpo(device_t dev,uint16_t * c)2875 siba_sprom_get_mcs2gpo(device_t dev, uint16_t *c)
2876 {
2877 struct siba_dev_softc *sd = device_get_ivars(dev);
2878 struct siba_softc *siba = sd->sd_bus;
2879
2880 memcpy(c, &siba->siba_sprom.mcs2gpo, sizeof(uint16_t) * 8);
2881 return (0);
2882 }
2883
2884 int
siba_sprom_get_mcs5glpo(device_t dev,uint16_t * c)2885 siba_sprom_get_mcs5glpo(device_t dev, uint16_t *c)
2886 {
2887 struct siba_dev_softc *sd = device_get_ivars(dev);
2888 struct siba_softc *siba = sd->sd_bus;
2889
2890 memcpy(c, &siba->siba_sprom.mcs5glpo, sizeof(uint16_t) * 8);
2891 return (0);
2892 }
2893
2894 int
siba_sprom_get_mcs5gpo(device_t dev,uint16_t * c)2895 siba_sprom_get_mcs5gpo(device_t dev, uint16_t *c)
2896 {
2897 struct siba_dev_softc *sd = device_get_ivars(dev);
2898 struct siba_softc *siba = sd->sd_bus;
2899
2900 memcpy(c, &siba->siba_sprom.mcs5gpo, sizeof(uint16_t) * 8);
2901 return (0);
2902 }
2903
2904 int
siba_sprom_get_mcs5ghpo(device_t dev,uint16_t * c)2905 siba_sprom_get_mcs5ghpo(device_t dev, uint16_t *c)
2906 {
2907 struct siba_dev_softc *sd = device_get_ivars(dev);
2908 struct siba_softc *siba = sd->sd_bus;
2909
2910 memcpy(c, &siba->siba_sprom.mcs5ghpo, sizeof(uint16_t) * 8);
2911 return (0);
2912 }
2913
2914 void
siba_pmu_spuravoid_pllupdate(device_t dev,int spur_avoid)2915 siba_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid)
2916 {
2917 struct siba_dev_softc *sd = device_get_ivars(dev);
2918 struct siba_softc *siba = sd->sd_bus;
2919 struct siba_cc *scc;
2920
2921 scc = &siba->siba_cc;
2922
2923 if (scc->scc_dev == NULL) {
2924 device_printf(dev, "%s: called; no pmu\n", __func__);
2925 return;
2926 }
2927
2928 switch (siba_get_chipid(dev)) {
2929 case 0x4322:
2930 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100070);
2931 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x1014140a);
2932 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888854);
2933 if (spur_avoid == 1)
2934 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05201828);
2935 else
2936 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05001828);
2937 break;
2938 case 43222:
2939 if (spur_avoid == 1) {
2940 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11500008);
2941 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0C000C06);
2942 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x0F600a08);
2943 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000);
2944 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x2001E920);
2945 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888815);
2946 } else {
2947 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100008);
2948 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0c000c06);
2949 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x03000a08);
2950 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000);
2951 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x200005c0);
2952 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888855);
2953 }
2954 break;
2955 default:
2956 device_printf(dev,
2957 "%s: unknown spur avoidance settings for chip 0x%04x\n",
2958 __func__,
2959 siba_get_chipid(dev));
2960 return;
2961 }
2962
2963 /* Both chips above use the same update */
2964 SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_PLL_UPD);
2965 }
2966
2967 void
siba_cc_set32(device_t dev,uint32_t reg,uint32_t val)2968 siba_cc_set32(device_t dev, uint32_t reg, uint32_t val)
2969 {
2970 struct siba_dev_softc *sd = device_get_ivars(dev);
2971 struct siba_softc *siba = sd->sd_bus;
2972 struct siba_cc *scc;
2973
2974 scc = &siba->siba_cc;
2975
2976 if (scc->scc_dev == NULL) {
2977 device_printf(dev, "%s: called; no pmu\n", __func__);
2978 return;
2979 }
2980
2981 SIBA_CC_SET32(scc, reg, val);
2982 }
2983
2984 void
siba_cc_mask32(device_t dev,uint32_t reg,uint32_t mask)2985 siba_cc_mask32(device_t dev, uint32_t reg, uint32_t mask)
2986 {
2987 struct siba_dev_softc *sd = device_get_ivars(dev);
2988 struct siba_softc *siba = sd->sd_bus;
2989 struct siba_cc *scc;
2990
2991 scc = &siba->siba_cc;
2992
2993 if (scc->scc_dev == NULL) {
2994 device_printf(dev, "%s: called; no pmu\n", __func__);
2995 return;
2996 }
2997
2998 SIBA_CC_MASK32(scc, reg, mask);
2999 }
3000
3001 uint32_t
siba_cc_read32(device_t dev,uint32_t reg)3002 siba_cc_read32(device_t dev, uint32_t reg)
3003 {
3004 struct siba_dev_softc *sd = device_get_ivars(dev);
3005 struct siba_softc *siba = sd->sd_bus;
3006 struct siba_cc *scc;
3007
3008 scc = &siba->siba_cc;
3009
3010 if (scc->scc_dev == NULL) {
3011 device_printf(dev, "%s: called; no pmu\n", __func__);
3012 return 0xffffffff;
3013 }
3014
3015 return SIBA_CC_READ32(scc, reg);
3016 }
3017
3018 void
siba_cc_write32(device_t dev,uint32_t reg,uint32_t val)3019 siba_cc_write32(device_t dev, uint32_t reg, uint32_t val)
3020 {
3021 struct siba_dev_softc *sd = device_get_ivars(dev);
3022 struct siba_softc *siba = sd->sd_bus;
3023 struct siba_cc *scc;
3024
3025 scc = &siba->siba_cc;
3026
3027 if (scc->scc_dev == NULL) {
3028 device_printf(dev, "%s: called; no pmu\n", __func__);
3029 return;
3030 }
3031
3032 SIBA_CC_WRITE32(scc, reg, val);
3033 }
3034
3035