1 /* $OpenBSD: aic7xxxvar.h,v 1.19 2004/04/12 22:12:32 jmc Exp $ */ 2 /* 3 * Core definitions and data structures shareable across OS platforms. 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2001 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: aic7xxxvar.h,v 1.19 2004/04/12 22:12:32 jmc Exp $ 42 * 43 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.h,v 1.44 2003/01/20 20:44:55 gibbs Exp $ 44 */ 45 /* 46 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 47 */ 48 49 #ifndef _AIC7XXXVAR_H_ 50 #define _AIC7XXXVAR_H_ 51 52 #undef AHC_DEBUG 53 54 /* Register Definitions */ 55 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 56 57 #include <dev/ic/aic7xxx_cam.h> 58 59 #define AIC_OP_OR 0x0 60 #define AIC_OP_AND 0x1 61 #define AIC_OP_XOR 0x2 62 #define AIC_OP_ADD 0x3 63 #define AIC_OP_ADC 0x4 64 #define AIC_OP_ROL 0x5 65 #define AIC_OP_BMOV 0x6 66 67 #define AIC_OP_JMP 0x8 68 #define AIC_OP_JC 0x9 69 #define AIC_OP_JNC 0xa 70 #define AIC_OP_CALL 0xb 71 #define AIC_OP_JNE 0xc 72 #define AIC_OP_JNZ 0xd 73 #define AIC_OP_JE 0xe 74 #define AIC_OP_JZ 0xf 75 76 /* Pseudo Ops */ 77 #define AIC_OP_SHL 0x10 78 #define AIC_OP_SHR 0x20 79 #define AIC_OP_ROR 0x30 80 81 /************************* Forward Declarations *******************************/ 82 struct ahc_platform_data; 83 struct scb_platform_data; 84 struct seeprom_descriptor; 85 86 /****************************** Useful Macros *********************************/ 87 #ifndef MAX 88 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 89 #endif 90 91 #ifndef MIN 92 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 93 #endif 94 95 #ifndef TRUE 96 #define TRUE 1 97 #endif 98 #ifndef FALSE 99 #define FALSE 0 100 #endif 101 102 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 103 104 #define ALL_CHANNELS '\0' 105 #define ALL_TARGETS_MASK 0xFFFF 106 #define INITIATOR_WILDCARD (~0) 107 108 #define SCSIID_TARGET(ahc, scsiid) \ 109 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 110 >> TID_SHIFT) 111 #define SCSIID_OUR_ID(scsiid) \ 112 ((scsiid) & OID) 113 #define SCSIID_CHANNEL(ahc, scsiid) \ 114 ((((ahc)->features & AHC_TWIN) != 0) \ 115 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 116 : 'A') 117 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 118 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 119 #define SCB_GET_OUR_ID(scb) \ 120 SCSIID_OUR_ID((scb)->hscb->scsiid) 121 #define SCB_GET_TARGET(ahc, scb) \ 122 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 123 #define SCB_GET_CHANNEL(ahc, scb) \ 124 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 125 #define SCB_GET_LUN(scb) \ 126 ((scb)->hscb->lun) 127 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 128 (SCB_GET_TARGET(ahc, scb)) 129 #define SCB_GET_TARGET_MASK(ahc, scb) \ 130 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 131 #ifdef AHC_DEBUG 132 #define SCB_IS_SILENT(scb) \ 133 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 134 && (((scb)->flags & SCB_SILENT) != 0)) 135 #else 136 #define SCB_IS_SILENT(scb) \ 137 (((scb)->flags & SCB_SILENT) != 0) 138 #endif 139 #define TCL_TARGET_OFFSET(tcl) \ 140 ((((tcl) >> 4) & TID) >> 4) 141 #define TCL_LUN(tcl) \ 142 (tcl & (AHC_NUM_LUNS - 1)) 143 #define BUILD_TCL(scsiid, lun) \ 144 ((lun) | (((scsiid) & TID) << 4)) 145 146 #ifndef AHC_TARGET_MODE 147 #undef AHC_TMODE_ENABLE 148 #define AHC_TMODE_ENABLE 0 149 #endif 150 151 /**************************** Driver Constants ********************************/ 152 /* 153 * The maximum number of supported targets. 154 */ 155 #define AHC_NUM_TARGETS 16 156 157 /* 158 * The maximum number of supported luns. 159 * The identify message only supports 64 luns in SPI3. 160 * You can have 2^64 luns when information unit transfers are enabled, 161 * but it is doubtful this driver will ever support IUTs. 162 */ 163 #define AHC_NUM_LUNS 64 164 165 /* 166 * The maximum transfer per S/G segment. 167 * Limited by MAXPHYS or a 24-bit counter. 168 */ 169 #define AHC_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff) 170 171 /* 172 * The maximum amount of SCB storage in hardware on a controller. 173 * This value represents an upper bound. Controllers vary in the number 174 * they actually support. 175 */ 176 #define AHC_SCB_MAX 255 177 178 /* 179 * The maximum number of concurrent transactions supported per driver instance. 180 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 181 * the space for SCBs on the host adapter varies by model, the driver will 182 * page the SCBs between host and controller memory as needed. We are limited 183 * to 253 because: 184 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 185 * 2) We reserve one value, 255, to represent the invalid element. 186 * 3) Our input queue scheme requires one SCB to always be reserved 187 * in advance of queuing any SCBs. This takes us down to 254. 188 * 4) To handle our output queue correctly on machines that only 189 * support 32bit stores, we must clear the array 4 bytes at a 190 * time. To avoid colliding with a DMA write from the sequencer, 191 * we must be sure that 4 slots are empty when we write to clear 192 * the queue. This reduces us to 253 SCBs: 1 that just completed 193 * and the known three additional empty slots in the queue that 194 * precede it. 195 */ 196 #define AHC_MAX_QUEUE 253 197 198 /* 199 * The maximum amount of SCB storage we allocate in host memory. This 200 * number should reflect the 1 additional SCB we require to handle our 201 * qinfifo mechanism. 202 */ 203 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 204 205 /* 206 * Ring Buffer of incoming target commands. 207 * We allocate 256 to simplify the logic in the sequencer 208 * by using the natural wrap point of an 8bit counter. 209 */ 210 #define AHC_TMODE_CMDS 256 211 212 /* Reset line assertion time in us */ 213 #define AHC_BUSRESET_DELAY 25 214 215 /******************* Chip Characteristics/Operating Settings *****************/ 216 /* 217 * Chip Type 218 * The chip order is from least sophisticated to most sophisticated. 219 */ 220 typedef enum { 221 AHC_NONE = 0x0000, 222 AHC_CHIPID_MASK = 0x00FF, 223 AHC_AIC7770 = 0x0001, 224 AHC_AIC7850 = 0x0002, 225 AHC_AIC7855 = 0x0003, 226 AHC_AIC7859 = 0x0004, 227 AHC_AIC7860 = 0x0005, 228 AHC_AIC7870 = 0x0006, 229 AHC_AIC7880 = 0x0007, 230 AHC_AIC7895 = 0x0008, 231 AHC_AIC7895C = 0x0009, 232 AHC_AIC7890 = 0x000a, 233 AHC_AIC7896 = 0x000b, 234 AHC_AIC7892 = 0x000c, 235 AHC_AIC7899 = 0x000d, 236 AHC_VL = 0x0100, /* Bus type VL */ 237 AHC_EISA = 0x0200, /* Bus type EISA */ 238 AHC_PCI = 0x0400, /* Bus type PCI */ 239 AHC_BUS_MASK = 0x0F00 240 } ahc_chip; 241 242 /* 243 * Features available in each chip type. 244 */ 245 typedef enum { 246 AHC_FENONE = 0x00000, 247 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 248 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 249 AHC_WIDE = 0x00004, /* Wide Channel */ 250 AHC_TWIN = 0x00008, /* Twin Channel */ 251 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 252 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 253 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 254 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 255 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 256 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 257 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 258 AHC_DT = 0x00800, /* Double Transition transfers */ 259 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 260 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 261 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 262 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 263 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 264 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 265 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 266 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 267 AHC_AIC7770_FE = AHC_FENONE, 268 /* 269 * The real 7850 does not support Ultra modes, but there are 270 * several cards that use the generic 7850 PCI ID even though 271 * they are using an Ultra capable chip (7859/7860). We start 272 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 273 * register to determine if the capability is really present. 274 */ 275 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 276 AHC_AIC7860_FE = AHC_AIC7850_FE, 277 AHC_AIC7870_FE = AHC_TARGETMODE, 278 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 279 /* 280 * Although we have space for both the initiator and 281 * target roles on ULTRA2 chips, we currently disable 282 * the initiator role to allow multi-scsi-id target mode 283 * configurations. We can only respond on the same SCSI 284 * ID as our initiator role if we allow initiator operation. 285 * At some point, we should add a configuration knob to 286 * allow both roles to be loaded. 287 */ 288 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 289 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 290 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 291 |AHC_TARGETMODE, 292 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 293 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 294 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 295 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 296 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 297 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 298 } ahc_feature; 299 300 /* 301 * Bugs in the silicon that we work around in software. 302 */ 303 typedef enum { 304 AHC_BUGNONE = 0x00, 305 /* 306 * On all chips prior to the U2 product line, 307 * the WIDEODD S/G segment feature does not 308 * work during scsi->HostBus transfers. 309 */ 310 AHC_TMODE_WIDEODD_BUG = 0x01, 311 /* 312 * On the aic7890/91 Rev 0 chips, the autoflush 313 * feature does not work. A manual flush of 314 * the DMA FIFO is required. 315 */ 316 AHC_AUTOFLUSH_BUG = 0x02, 317 /* 318 * On many chips, cacheline streaming does not work. 319 */ 320 AHC_CACHETHEN_BUG = 0x04, 321 /* 322 * On the aic7896/97 chips, cacheline 323 * streaming must be enabled. 324 */ 325 AHC_CACHETHEN_DIS_BUG = 0x08, 326 /* 327 * PCI 2.1 Retry failure on non-empty data fifo. 328 */ 329 AHC_PCI_2_1_RETRY_BUG = 0x10, 330 /* 331 * Controller does not handle cacheline residuals 332 * properly on S/G segments if PCI MWI instructions 333 * are allowed. 334 */ 335 AHC_PCI_MWI_BUG = 0x20, 336 /* 337 * An SCB upload using the SCB channel's 338 * auto array entry copy feature may 339 * corrupt data. This appears to only 340 * occur on 66MHz systems. 341 */ 342 AHC_SCBCHAN_UPLOAD_BUG = 0x40 343 } ahc_bug; 344 345 /* 346 * Configuration specific settings. 347 * The driver determines these settings by probing the 348 * chip/controller's configuration. 349 */ 350 typedef enum { 351 AHC_FNONE = 0x000, 352 AHC_PRIMARY_CHANNEL = 0x003, /* 353 * The channel that should 354 * be probed first. 355 */ 356 AHC_USEDEFAULTS = 0x004, /* 357 * For cards without an seeprom 358 * or a BIOS to initialize the chip's 359 * SRAM, we use the default target 360 * settings. 361 */ 362 AHC_SEQUENCER_DEBUG = 0x008, 363 AHC_SHARED_SRAM = 0x010, 364 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 365 AHC_RESET_BUS_A = 0x040, 366 AHC_RESET_BUS_B = 0x080, 367 AHC_EXTENDED_TRANS_A = 0x100, 368 AHC_EXTENDED_TRANS_B = 0x200, 369 AHC_TERM_ENB_A = 0x400, 370 AHC_TERM_ENB_B = 0x800, 371 AHC_INITIATORROLE = 0x1000, /* 372 * Allow initiator operations on 373 * this controller. 374 */ 375 AHC_TARGETROLE = 0x2000, /* 376 * Allow target operations on this 377 * controller. 378 */ 379 AHC_NEWEEPROM_FMT = 0x4000, 380 AHC_RESOURCE_SHORTAGE = 0x8000, 381 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 382 AHC_INT50_SPEEDFLEX = 0x20000, /* 383 * Internal 50pin connector 384 * sits behind an aic3860 385 */ 386 AHC_SCB_BTT = 0x40000, /* 387 * The busy targets table is 388 * stored in SCB space rather 389 * than SRAM. 390 */ 391 AHC_BIOS_ENABLED = 0x80000, 392 AHC_ALL_INTERRUPTS = 0x100000, 393 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 394 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 395 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 396 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 397 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 398 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 399 AHC_DISABLE_PCI_PERR = 0x10000000 400 } ahc_flag; 401 402 /************************* Hardware SCB Definition ***************************/ 403 404 /* 405 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 406 * consists of a "hardware SCB" mirroring the fields available on the card 407 * and additional information the kernel stores for each transaction. 408 * 409 * To minimize space utilization, a portion of the hardware scb stores 410 * different data during different portions of a SCSI transaction. 411 * As initialized by the host driver for the initiator role, this area 412 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 413 * the cdb has been presented to the target, this area serves to store 414 * residual transfer information and the SCSI status byte. 415 * For the target role, the contents of this area do not change, but 416 * still serve a different purpose than for the initiator role. See 417 * struct target_data for details. 418 */ 419 420 /* 421 * Status information embedded in the shared portion of 422 * an SCB after passing the cdb to the target. The kernel 423 * driver will only read this data for transactions that 424 * complete abnormally (non-zero status byte). 425 */ 426 struct status_pkt { 427 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 428 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 429 uint8_t scsi_status; /* Standard SCSI status byte */ 430 }; 431 432 /* 433 * Target mode version of the shared data SCB segment. 434 */ 435 struct target_data { 436 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 437 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 438 uint8_t scsi_status; /* SCSI status to give to initiator */ 439 uint8_t target_phases; /* Bitmap of phases to execute */ 440 uint8_t data_phase; /* Data-In or Data-Out */ 441 uint8_t initiator_tag; /* Initiator's transaction tag */ 442 }; 443 444 struct hardware_scb { 445 /*0*/ union { 446 /* 447 * If the cdb is 12 bytes or less, we embed it directly 448 * in the SCB. For longer cdbs, we embed the address 449 * of the cdb payload as seen by the chip and a DMA 450 * is used to pull it in. 451 */ 452 uint8_t cdb[12]; 453 uint32_t cdb_ptr; 454 struct status_pkt status; 455 struct target_data tdata; 456 } shared_data; 457 /* 458 * A word about residuals. 459 * The scb is presented to the sequencer with the dataptr and datacnt 460 * fields initialized to the contents of the first S/G element to 461 * transfer. The sgptr field is initialized to the bus address for 462 * the S/G element that follows the first in the in core S/G array 463 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 464 * S/G entry for this transfer (single S/G element transfer with the 465 * first elements address and length preloaded in the dataptr/datacnt 466 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 467 * The SG_FULL_RESID flag ensures that the residual will be correctly 468 * noted even if no data transfers occur. Once the data phase is entered, 469 * the residual sgptr and datacnt are loaded from the sgptr and the 470 * datacnt fields. After each S/G element's dataptr and length are 471 * loaded into the hardware, the residual sgptr is advanced. After 472 * each S/G element is expired, its datacnt field is checked to see 473 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 474 * residual sg ptr and the transfer is considered complete. If the 475 * sequencer determines that there is a residual in the transfer, it 476 * will set the SG_RESID_VALID flag in sgptr and DMA the scb back into 477 * host memory. To summarize: 478 * 479 * Sequencer: 480 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 481 * or residual_sgptr does not have SG_LIST_NULL set. 482 * 483 * o We are transfering the last segment if residual_datacnt has 484 * the SG_LAST_SEG flag set. 485 * 486 * Host: 487 * o A residual has occurred if a completed scb has the 488 * SG_RESID_VALID flag set. 489 * 490 * o residual_sgptr and sgptr refer to the "next" sg entry 491 * and so may point beyond the last valid sg entry for the 492 * transfer. 493 */ 494 /*12*/ uint32_t dataptr; 495 /*16*/ uint32_t datacnt; /* 496 * Byte 3 (numbered from 0) of 497 * the datacnt is really the 498 * 4th byte in that data address. 499 */ 500 /*20*/ uint32_t sgptr; 501 #define SG_PTR_MASK 0xFFFFFFF8 502 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 503 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 504 /*26*/ uint8_t lun; 505 /*27*/ uint8_t tag; /* 506 * Index into our kernel SCB array. 507 * Also used as the tag for tagged I/O 508 */ 509 /*28*/ uint8_t cdb_len; 510 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 511 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 512 /*31*/ uint8_t next; /* 513 * Used for threading SCBs in the 514 * "Waiting for Selection" and 515 * "Disconnected SCB" lists down 516 * in the sequencer. 517 */ 518 /*32*/ uint8_t cdb32[32]; /* 519 * CDB storage for cdbs of size 520 * 13->32. We store them here 521 * because hardware scbs are 522 * allocated from DMA safe 523 * memory so we are guaranteed 524 * the controller can access 525 * this data. 526 */ 527 }; 528 529 /************************ Kernel SCB Definitions ******************************/ 530 /* 531 * Some fields of the SCB are OS dependent. Here we collect the 532 * definitions for elements that all OS platforms need to include 533 * in there SCB definition. 534 */ 535 536 /* 537 * Definition of a scatter/gather element as transferred to the controller. 538 * The aic7xxx chips only support a 24bit length. We use the top byte of 539 * the length to store additional address bits and a flag to indicate 540 * that a given segment terminates the transfer. This gives us an 541 * addressable range of 512GB on machines with 64bit PCI or with chips 542 * that can support dual address cycles on 32bit PCI busses. 543 */ 544 struct ahc_dma_seg { 545 uint32_t addr; 546 uint32_t len; 547 #define AHC_DMA_LAST_SEG 0x80000000 548 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 549 #define AHC_SG_LEN_MASK 0x00FFFFFF 550 }; 551 552 struct sg_map_node { 553 bus_dmamap_t sg_dmamap; 554 bus_addr_t sg_physaddr; 555 bus_dma_segment_t sg_dmasegs; 556 int sg_nseg; 557 struct ahc_dma_seg* sg_vaddr; 558 SLIST_ENTRY(sg_map_node) links; 559 }; 560 561 struct ahc_pci_busdata { 562 pci_chipset_tag_t pc; 563 pcitag_t tag; 564 u_int dev; 565 u_int func; 566 pcireg_t class; 567 }; 568 569 /* 570 * The current state of this SCB. 571 */ 572 typedef enum { 573 SCB_FREE = 0x0000, 574 SCB_REQUEUE = 0x0001, 575 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 576 * Another device was active 577 * during the first timeout for 578 * this SCB so we gave ourselves 579 * an additional timeout period 580 * in case it was hogging the 581 * bus. 582 */ 583 SCB_DEVICE_RESET = 0x0004, 584 SCB_SENSE = 0x0008, 585 SCB_CDB32_PTR = 0x0010, 586 SCB_RECOVERY_SCB = 0x0020, 587 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 588 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 589 SCB_ABORT = 0x0100, 590 SCB_UNTAGGEDQ = 0x0200, 591 SCB_ACTIVE = 0x0400, 592 SCB_TARGET_IMMEDIATE = 0x0800, 593 SCB_TRANSMISSION_ERROR = 0x1000,/* 594 * We detected a parity or CRC 595 * error that has effected the 596 * payload of the command. This 597 * flag is checked when normal 598 * status is returned to catch 599 * the case of a target not 600 * responding to our attempt 601 * to report the error. 602 */ 603 SCB_TARGET_SCB = 0x2000, 604 SCB_SILENT = 0x4000,/* 605 * Be quiet about transmission type 606 * errors. They are expected and we 607 * don't want to upset the user. This 608 * flag is typically used during DV. 609 */ 610 SCB_FREEZE_QUEUE = 0x8000 611 } scb_flag; 612 613 struct scb { 614 struct hardware_scb *hscb; 615 union { 616 SLIST_ENTRY(scb) sle; 617 TAILQ_ENTRY(scb) tqe; 618 } links; 619 LIST_ENTRY(scb) pending_links; 620 621 struct scsipi_xfer *xs; 622 struct ahc_softc *ahc_softc; 623 scb_flag flags; 624 #ifndef __linux__ 625 bus_dmamap_t dmamap; 626 #endif 627 struct scb_platform_data *platform_data; 628 struct sg_map_node *sg_map; 629 struct ahc_dma_seg *sg_list; 630 bus_addr_t sg_list_phys; 631 u_int sg_count;/* How full ahc_dma_seg is */ 632 }; 633 634 struct scb_data { 635 SLIST_HEAD(, scb) free_scbs; /* 636 * Pool of SCBs ready to be assigned 637 * commands to execute. 638 */ 639 struct scb *scbindex[256]; /* 640 * Mapping from tag to SCB. 641 * As tag identifiers are an 642 * 8bit value, we provide space 643 * for all possible tag values. 644 * Any lookups to entries at or 645 * above AHC_SCB_MAX_ALLOC will 646 * always fail. 647 */ 648 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 649 struct scb *scbarray; /* Array of kernel SCBs */ 650 struct scsipi_sense_data *sense; /* Per SCB sense data */ 651 652 /* 653 * "Bus" addresses of our data structures. 654 */ 655 bus_dmamap_t hscb_dmamap; 656 bus_addr_t hscb_busaddr; 657 bus_dma_segment_t hscb_seg; 658 int hscb_nseg; 659 int hscb_size; 660 661 bus_dmamap_t sense_dmamap; 662 bus_addr_t sense_busaddr; 663 bus_dma_segment_t sense_seg; 664 int sense_nseg; 665 int sense_size; 666 667 SLIST_HEAD(, sg_map_node) sg_maps; 668 uint8_t numscbs; 669 uint8_t maxhscbs; /* Number of SCBs on the card */ 670 uint8_t init_level; /* 671 * How far we've initialized 672 * this structure. 673 */ 674 }; 675 676 /************************ Target Mode Definitions *****************************/ 677 678 /* 679 * Connection desciptor for select-in requests in target mode. 680 */ 681 struct target_cmd { 682 uint8_t scsiid; /* Our ID and the initiator's ID */ 683 uint8_t identify; /* Identify message */ 684 uint8_t bytes[22]; /* 685 * Bytes contains any additional message 686 * bytes terminated by 0xFF. The remainder 687 * is the cdb to execute. 688 */ 689 uint8_t cmd_valid; /* 690 * When a command is complete, the firmware 691 * will set cmd_valid to all bits set. 692 * After the host has seen the command, 693 * the bits are cleared. This allows us 694 * to just peek at host memory to determine 695 * if more work is complete. cmd_valid is on 696 * an 8 byte boundary to simplify setting 697 * it on aic7880 hardware which only has 698 * limited direct access to the DMA FIFO. 699 */ 700 uint8_t pad[7]; 701 }; 702 703 /* 704 * Number of events we can buffer up if we run out 705 * of immediate notify ccbs. 706 */ 707 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 708 struct ahc_tmode_event { 709 uint8_t initiator_id; 710 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 711 #define EVENT_TYPE_BUS_RESET 0xFF 712 uint8_t event_arg; 713 }; 714 715 /* 716 * Per enabled lun target mode state. 717 * As this state is directly influenced by the host OS'es target mode 718 * environment, we let the OS module define it. Forward declare the 719 * structure here so we can store arrays of them, etc. in OS neutral 720 * data structures. 721 */ 722 #ifdef AHC_TARGET_MODE 723 struct ahc_tmode_lstate { 724 #if 0 725 struct cam_path *path; 726 struct ccb_hdr_slist accept_tios; 727 struct ccb_hdr_slist immed_notifies; 728 #endif 729 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 730 uint8_t event_r_idx; 731 uint8_t event_w_idx; 732 }; 733 #else 734 struct ahc_tmode_lstate; 735 #endif 736 737 /******************** Transfer Negotiation Datastructures *********************/ 738 #define AHC_TRANS_CUR 0x01 /* Modify current negotiation status */ 739 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 740 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 741 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 742 743 #define AHC_WIDTH_UNKNOWN 0xFF 744 #define AHC_PERIOD_UNKNOWN 0xFF 745 #define AHC_OFFSET_UNKNOWN 0x0 746 #define AHC_PPR_OPTS_UNKNOWN 0xFF 747 748 /* 749 * Transfer Negotiation Information. 750 */ 751 struct ahc_transinfo { 752 uint8_t protocol_version; /* SCSI Revision level */ 753 uint8_t transport_version; /* SPI Revision level */ 754 uint8_t width; /* Bus width */ 755 uint8_t period; /* Sync rate factor */ 756 uint8_t offset; /* Sync offset */ 757 uint8_t ppr_options; /* Parallel Protocol Request options */ 758 }; 759 760 /* 761 * Per-initiator current, goal and user transfer negotiation information. */ 762 struct ahc_initiator_tinfo { 763 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 764 struct ahc_transinfo curr; 765 struct ahc_transinfo goal; 766 struct ahc_transinfo user; 767 }; 768 769 /* 770 * Per enabled target ID state. 771 * Pointers to lun target state as well as sync/wide negotiation information 772 * for each initiator<->target mapping. For the initiator role we pretend 773 * that we are the target and the targets are the initiators since the 774 * negotiation is the same regardless of role. 775 */ 776 struct ahc_tmode_tstate { 777 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 778 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 779 780 /* 781 * Per initiator state bitmasks. 782 */ 783 uint16_t auto_negotiate;/* Auto Negotiation Required */ 784 uint16_t ultraenb; /* Using ultra sync rate */ 785 uint16_t discenable; /* Disconnection allowed */ 786 uint16_t tagenable; /* Tagged Queuing allowed */ 787 }; 788 789 /* 790 * Data structure for our table of allowed synchronous transfer rates. 791 */ 792 struct ahc_syncrate { 793 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 794 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 795 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 796 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 797 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 798 uint8_t period; /* Period to send to SCSI target */ 799 char *rate; 800 }; 801 802 /* Safe and valid period for async negotiations. */ 803 #define AHC_ASYNC_XFER_PERIOD 0x45 804 #define AHC_ULTRA2_XFER_PERIOD 0x0a 805 806 /* 807 * Indexes into our table of syncronous transfer rates. 808 */ 809 #define AHC_SYNCRATE_DT 0 810 #define AHC_SYNCRATE_ULTRA2 1 811 #define AHC_SYNCRATE_ULTRA 3 812 #define AHC_SYNCRATE_FAST 6 813 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 814 #define AHC_SYNCRATE_MIN 13 815 816 /***************************** Lookup Tables **********************************/ 817 /* 818 * Phase -> name and message out response 819 * to parity errors in each phase table. 820 */ 821 struct ahc_phase_table_entry { 822 uint8_t phase; 823 uint8_t mesg_out; /* Message response to parity errors */ 824 char *phasemsg; 825 }; 826 827 /************************** Serial EEPROM Format ******************************/ 828 829 struct seeprom_config { 830 /* 831 * Per SCSI ID Configuration Flags 832 */ 833 uint16_t device_flags[16]; /* words 0-15 */ 834 #define CFXFER 0x0007 /* synchronous transfer rate */ 835 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 836 #define CFDISC 0x0010 /* enable disconnection */ 837 #define CFWIDEB 0x0020 /* wide bus device */ 838 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 839 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 840 #define CFSTART 0x0100 /* send start unit SCSI command */ 841 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 842 #define CFRNFOUND 0x0400 /* report even if not found */ 843 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 844 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 845 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 846 847 /* 848 * BIOS Control Bits 849 */ 850 uint16_t bios_control; /* word 16 */ 851 #define CFSUPREM 0x0001 /* support all removable drives */ 852 #define CFSUPREMB 0x0002 /* support removable boot drives */ 853 #define CFBIOSEN 0x0004 /* BIOS enabled */ 854 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 855 #define CFSM2DRV 0x0010 /* support more than two drives */ 856 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 857 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 858 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 859 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 860 #define CFEXTEND 0x0080 /* extended translation enabled */ 861 #define CFSCAMEN 0x0100 /* SCAM enable */ 862 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 863 #define CFMSG_VERBOSE 0x0000 864 #define CFMSG_SILENT 0x0200 865 #define CFMSG_DIAG 0x0400 866 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 867 /* UNUSED 0xff00 */ 868 869 /* 870 * Host Adapter Control Bits 871 */ 872 uint16_t adapter_control; /* word 17 */ 873 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 874 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 875 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 876 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 877 #define CFSTERM 0x0004 /* SCSI low byte termination */ 878 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 879 #define CFSPARITY 0x0010 /* SCSI parity */ 880 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 881 #define CFMULTILUN 0x0020 882 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 883 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 884 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 885 #define CFBOOTCHANSHIFT 8 886 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 887 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 888 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 889 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 890 891 /* 892 * Bus Release Time, Host Adapter ID 893 */ 894 uint16_t brtime_id; /* word 18 */ 895 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 896 /* UNUSED 0x00f0 */ 897 #define CFBRTIME 0xff00 /* bus release time */ 898 899 /* 900 * Maximum targets 901 */ 902 uint16_t max_targets; /* word 19 */ 903 #define CFMAXTARG 0x00ff /* maximum targets */ 904 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 905 #define CFBOOTID 0xf000 /* Target to boot from */ 906 uint16_t res_1[10]; /* words 20-29 */ 907 uint16_t signature; /* Signature == 0x250 */ 908 #define CFSIGNATURE 0x250 909 #define CFSIGNATURE2 0x300 910 uint16_t checksum; /* word 31 */ 911 }; 912 913 /**************************** Message Buffer *********************************/ 914 typedef enum { 915 MSG_TYPE_NONE = 0x00, 916 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 917 MSG_TYPE_INITIATOR_MSGIN = 0x02, 918 MSG_TYPE_TARGET_MSGOUT = 0x03, 919 MSG_TYPE_TARGET_MSGIN = 0x04 920 } ahc_msg_type; 921 922 typedef enum { 923 MSGLOOP_IN_PROG, 924 MSGLOOP_MSGCOMPLETE, 925 MSGLOOP_TERMINATED 926 } msg_loop_stat; 927 928 /*********************** Software Configuration Structure *********************/ 929 TAILQ_HEAD(scb_tailq, scb); 930 931 struct ahc_suspend_channel_state { 932 uint8_t scsiseq; 933 uint8_t sxfrctl0; 934 uint8_t sxfrctl1; 935 uint8_t simode0; 936 uint8_t simode1; 937 uint8_t seltimer; 938 uint8_t seqctl; 939 }; 940 941 struct ahc_suspend_state { 942 struct ahc_suspend_channel_state channel[2]; 943 uint8_t optionmode; 944 uint8_t dscommand0; 945 uint8_t dspcistatus; 946 /* hsmailbox */ 947 uint8_t crccontrol1; 948 uint8_t scbbaddr; 949 /* Host and sequencer SCB counts */ 950 uint8_t dff_thrsh; 951 uint8_t *scratch_ram; 952 uint8_t *btt; 953 }; 954 955 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 956 typedef void ahc_callback_t (void *); 957 958 struct ahc_softc { 959 struct device sc_dev; 960 961 struct scsipi_channel sc_channel; 962 struct scsipi_channel sc_channel_b; 963 struct device * sc_child; 964 struct device * sc_child_b; 965 struct scsipi_adapter sc_adapter; 966 967 bus_space_tag_t tag; 968 bus_space_handle_t bsh; 969 970 #ifndef __linux__ 971 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 972 #endif 973 struct scb_data *scb_data; 974 975 struct scb *next_queued_scb; 976 977 /* 978 * SCBs that have been sent to the controller 979 */ 980 LIST_HEAD(, scb) pending_scbs; 981 982 /* 983 * Counting lock for deferring the release of additional 984 * untagged transactions from the untagged_queues. When 985 * the lock is decremented to 0, all queues in the 986 * untagged_queues array are run. 987 */ 988 u_int untagged_queue_lock; 989 990 /* 991 * Per-target queue of untagged-transactions. The 992 * transaction at the head of the queue is the 993 * currently pending untagged transaction for the 994 * target. The driver only allows a single untagged 995 * transaction per target. 996 */ 997 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 998 999 /* 1000 * Platform specific data. 1001 */ 1002 struct ahc_platform_data *platform_data; 1003 1004 /* 1005 * Platform specific device information. 1006 */ 1007 ahc_dev_softc_t dev_softc; 1008 1009 /* 1010 * Bus specific device information. 1011 */ 1012 ahc_bus_intr_t bus_intr; 1013 1014 /* 1015 * Target mode related state kept on a per enabled lun basis. 1016 * Targets that are not enabled will have null entries. 1017 * As an initiator, we keep one target entry for our initiator 1018 * ID to store our sync/wide transfer settings. 1019 */ 1020 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 1021 1022 char inited_target[AHC_NUM_TARGETS]; 1023 1024 /* 1025 * The black hole device responsible for handling requests for 1026 * disabled luns on enabled targets. 1027 */ 1028 struct ahc_tmode_lstate *black_hole; 1029 1030 /* 1031 * Device instance currently on the bus awaiting a continue TIO 1032 * for a command that was not given the disconnect priviledge. 1033 */ 1034 struct ahc_tmode_lstate *pending_device; 1035 1036 /* 1037 * Card characteristics 1038 */ 1039 ahc_chip chip; 1040 ahc_feature features; 1041 ahc_bug bugs; 1042 ahc_flag flags; 1043 struct seeprom_config *seep_config; 1044 1045 /* Values to store in the SEQCTL register for pause and unpause */ 1046 uint8_t unpause; 1047 uint8_t pause; 1048 1049 /* Command Queues */ 1050 uint8_t qoutfifonext; 1051 uint8_t qinfifonext; 1052 uint8_t *qoutfifo; 1053 uint8_t *qinfifo; 1054 1055 /* Critical Section Data */ 1056 struct cs *critical_sections; 1057 u_int num_critical_sections; 1058 1059 /* Links for chaining softcs */ 1060 TAILQ_ENTRY(ahc_softc) links; 1061 1062 /* Channel Names ('A', 'B', etc.) */ 1063 char channel; 1064 1065 /* Initiator Bus ID */ 1066 uint8_t our_id; 1067 uint8_t our_id_b; 1068 1069 /* 1070 * PCI error detection. 1071 */ 1072 int unsolicited_ints; 1073 1074 /* 1075 * Target incoming command FIFO. 1076 */ 1077 struct target_cmd *targetcmds; 1078 uint8_t tqinfifonext; 1079 1080 /* 1081 * Incoming and outgoing message handling. 1082 */ 1083 uint8_t send_msg_perror; 1084 ahc_msg_type msg_type; 1085 uint8_t msgout_buf[12];/* Message we are sending */ 1086 uint8_t msgin_buf[12];/* Message we are receiving */ 1087 u_int msgout_len; /* Length of message to send */ 1088 u_int msgout_index; /* Current index in msgout */ 1089 u_int msgin_index; /* Current index in msgin */ 1090 1091 /* Interrupt routine */ 1092 void *ih; 1093 1094 /* 1095 * Mapping information for data structures shared 1096 * between the sequencer and kernel. 1097 */ 1098 bus_dma_tag_t parent_dmat; 1099 bus_dmamap_t shared_data_dmamap; 1100 bus_addr_t shared_data_busaddr; 1101 1102 bus_dma_segment_t shared_data_seg; 1103 int shared_data_nseg; 1104 int shared_data_size; 1105 int sc_dmaflags; 1106 1107 /* 1108 * Bus address of the one byte buffer used to 1109 * work-around a DMA bug for chips <= aic7880 1110 * in target mode. 1111 */ 1112 bus_addr_t dma_bug_buf; 1113 1114 /* Information saved through suspend/resume cycles */ 1115 struct ahc_suspend_state suspend_state; 1116 1117 /* Number of enabled target mode device on this card */ 1118 u_int enabled_luns; 1119 1120 /* Initialization level of this data structure */ 1121 u_int init_level; 1122 1123 /* PCI cacheline size. */ 1124 u_int pci_cachesize; 1125 1126 u_int stack_size; 1127 1128 /* Per-Unit descriptive information */ 1129 char *name; 1130 int unit; 1131 1132 /* Selection Timer settings */ 1133 int seltime; 1134 int seltime_b; 1135 1136 uint16_t user_discenable;/* Disconnection allowed */ 1137 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1138 1139 struct ahc_pci_busdata *bd; 1140 1141 void *shutdown_hook; 1142 }; 1143 1144 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1145 extern struct ahc_softc_tailq ahc_tailq; 1146 1147 /************************ Active Device Information ***************************/ 1148 typedef enum { 1149 ROLE_UNKNOWN, 1150 ROLE_INITIATOR, 1151 ROLE_TARGET 1152 } role_t; 1153 1154 struct ahc_devinfo { 1155 int our_scsiid; 1156 int target_offset; 1157 uint16_t target_mask; 1158 u_int target; 1159 u_int lun; 1160 char channel; 1161 role_t role; /* 1162 * Only guaranteed to be correct if not 1163 * in the busfree state. 1164 */ 1165 }; 1166 1167 /****************************** PCI Structures ********************************/ 1168 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1169 1170 struct ahc_pci_identity { 1171 uint64_t full_id; 1172 uint64_t id_mask; 1173 ahc_device_setup_t *setup; 1174 }; 1175 extern struct ahc_pci_identity ahc_pci_ident_table []; 1176 extern const u_int ahc_num_pci_devs; 1177 1178 /***************************** VL/EISA Declarations ***************************/ 1179 struct aic7770_identity { 1180 uint32_t full_id; 1181 uint32_t id_mask; 1182 char *name; 1183 ahc_device_setup_t *setup; 1184 }; 1185 extern struct aic7770_identity aic7770_ident_table []; 1186 extern const int ahc_num_aic7770_devs; 1187 1188 #define AHC_EISA_SLOT_OFFSET 0xc00 1189 #define AHC_EISA_IOSIZE 0x100 1190 1191 /*************************** Function Declarations ****************************/ 1192 /******************************************************************************/ 1193 u_int ahc_index_busy_tcl(struct ahc_softc *, u_int); 1194 void ahc_unbusy_tcl(struct ahc_softc *, u_int); 1195 void ahc_busy_tcl(struct ahc_softc *, u_int, u_int); 1196 1197 /***************************** PCI Front End *********************************/ 1198 const struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t, u_int); 1199 int ahc_pci_config(struct ahc_softc *, 1200 struct ahc_pci_identity *); 1201 int ahc_pci_test_register_access(struct ahc_softc *); 1202 1203 /*************************** EISA/VL Front End ********************************/ 1204 struct aic7770_identity *aic7770_find_device(uint32_t); 1205 int aic7770_config(struct ahc_softc *, 1206 struct aic7770_identity *, u_int); 1207 1208 /************************** SCB and SCB queue management **********************/ 1209 int ahc_probe_scbs(struct ahc_softc *); 1210 void ahc_run_untagged_queues(struct ahc_softc *); 1211 void ahc_run_untagged_queue(struct ahc_softc *, struct scb_tailq *); 1212 void ahc_qinfifo_requeue_tail(struct ahc_softc *, struct scb *); 1213 int ahc_match_scb(struct ahc_softc *, struct scb *, 1214 int, char, int, u_int, role_t); 1215 1216 /****************************** Initialization ********************************/ 1217 int ahc_softc_init(struct ahc_softc *); 1218 void ahc_controller_info(struct ahc_softc *, char *, size_t); 1219 int ahc_init(struct ahc_softc *); 1220 void ahc_intr_enable(struct ahc_softc *, int); 1221 void ahc_pause_and_flushwork(struct ahc_softc *); 1222 int ahc_suspend(struct ahc_softc *); 1223 int ahc_resume(struct ahc_softc *); 1224 void ahc_softc_insert(struct ahc_softc *); 1225 struct ahc_softc *ahc_find_softc(struct ahc_softc *); 1226 void ahc_set_unit(struct ahc_softc *, int); 1227 void ahc_set_name(struct ahc_softc *, char *); 1228 void ahc_alloc_scbs(struct ahc_softc *); 1229 void ahc_free(struct ahc_softc *); 1230 int ahc_reset(struct ahc_softc *); 1231 void ahc_shutdown(void *); 1232 1233 /*************************** Interrupt Services *******************************/ 1234 void ahc_pci_intr(struct ahc_softc *); 1235 void ahc_clear_intstat(struct ahc_softc *); 1236 void ahc_run_qoutfifo(struct ahc_softc *); 1237 #ifdef AHC_TARGET_MODE 1238 void ahc_run_tqinfifo(struct ahc_softc *, int); 1239 #endif 1240 void ahc_handle_brkadrint(struct ahc_softc *); 1241 void ahc_handle_seqint(struct ahc_softc *, u_int); 1242 void ahc_handle_scsiint(struct ahc_softc *, u_int); 1243 void ahc_clear_critical_section(struct ahc_softc *); 1244 1245 /***************************** Error Recovery *********************************/ 1246 typedef enum { 1247 SEARCH_COMPLETE, 1248 SEARCH_COUNT, 1249 SEARCH_REMOVE 1250 } ahc_search_action; 1251 int ahc_search_qinfifo(struct ahc_softc *, int, char, 1252 int, u_int, role_t, uint32_t, ahc_search_action); 1253 int ahc_search_untagged_queues(struct ahc_softc *, 1254 struct scsipi_xfer *, int, char, int, uint32_t, 1255 ahc_search_action); 1256 int ahc_search_disc_list(struct ahc_softc *, int, char, 1257 int, u_int, int, int, int); 1258 void ahc_freeze_devq(struct ahc_softc *, struct scb *); 1259 int ahc_reset_channel(struct ahc_softc *, char, int); 1260 int ahc_abort_scbs(struct ahc_softc *, int, char, int, 1261 u_int, role_t, uint32_t); 1262 void ahc_restart(struct ahc_softc *); 1263 void ahc_calc_residual(struct ahc_softc *, struct scb *); 1264 /*************************** Utility Functions ********************************/ 1265 struct ahc_phase_table_entry* 1266 ahc_lookup_phase_entry(int); 1267 void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, 1268 u_int, char, role_t); 1269 /************************** Transfer Negotiation ******************************/ 1270 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *, u_int *, 1271 u_int *, u_int); 1272 u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 1273 void ahc_validate_offset(struct ahc_softc *, 1274 struct ahc_initiator_tinfo *, struct ahc_syncrate *, 1275 u_int *, int, role_t); 1276 void ahc_validate_width(struct ahc_softc *, 1277 struct ahc_initiator_tinfo *, u_int *, role_t); 1278 /* 1279 * Negotiation types. These are used to qualify if we should renegotiate 1280 * even if our goal and current transport parameters are identical. 1281 */ 1282 typedef enum { 1283 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1284 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1285 AHC_NEG_ALWAYS /* Renegotiate even if goal is async. */ 1286 } ahc_neg_type; 1287 int ahc_update_neg_request(struct ahc_softc *, 1288 struct ahc_devinfo *, struct ahc_tmode_tstate *, 1289 struct ahc_initiator_tinfo*, ahc_neg_type); 1290 void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 1291 u_int, u_int, int); 1292 void ahc_set_syncrate(struct ahc_softc *, 1293 struct ahc_devinfo *, struct ahc_syncrate *, 1294 u_int, u_int, u_int, u_int, int); 1295 void ahc_scb_devinfo(struct ahc_softc *, 1296 struct ahc_devinfo *, struct scb *); 1297 1298 typedef enum { 1299 AHC_QUEUE_NONE, 1300 AHC_QUEUE_BASIC, 1301 AHC_QUEUE_TAGGED 1302 } ahc_queue_alg; 1303 1304 void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 1305 ahc_queue_alg); 1306 1307 /**************************** Target Mode *************************************/ 1308 #ifdef AHC_TARGET_MODE 1309 void ahc_send_lstate_events(struct ahc_softc *, 1310 struct ahc_tmode_lstate *); 1311 void ahc_handle_en_lun(struct ahc_softc *, struct scsipi_xfer *); 1312 cam_status ahc_find_tmode_devs(struct ahc_softc *, 1313 struct ahc_tmode_tstate **, struct ahc_tmode_lstate **, 1314 int); 1315 #ifndef AHC_TMODE_ENABLE 1316 #define AHC_TMODE_ENABLE 0 1317 #endif 1318 #endif 1319 /******************************* Debug ***************************************/ 1320 #ifdef AHC_DEBUG 1321 extern uint32_t ahc_debug; 1322 #define AHC_SHOW_MISC 0x0001 1323 #define AHC_SHOW_SENSE 0x0002 1324 #define AHC_DUMP_SEEPROM 0x0004 1325 #define AHC_SHOW_TERMCTL 0x0008 1326 #define AHC_SHOW_MEMORY 0x0010 1327 #define AHC_SHOW_MESSAGES 0x0020 1328 #define AHC_SHOW_DV 0x0040 1329 #define AHC_SHOW_SELTO 0x0080 1330 #define AHC_SHOW_CMDS 0x0100 1331 #define AHC_SHOW_QFULL 0x0200 1332 #define AHC_SHOW_QUEUE 0x0400 1333 #define AHC_SHOW_TQIN 0x0800 1334 #define AHC_SHOW_MASKED_ERRORS 0x1000 1335 #define AHC_DEBUG_SEQUENCER 0x2000 1336 #endif 1337 void ahc_print_scb(struct scb *); 1338 void ahc_print_devinfo(struct ahc_softc *, 1339 struct ahc_devinfo *); 1340 void ahc_dump_card_state(struct ahc_softc *); 1341 int ahc_print_register(ahc_reg_parse_entry_t *, u_int, 1342 const char *, u_int, u_int, u_int *, u_int); 1343 /******************************* SEEPROM *************************************/ 1344 int ahc_acquire_seeprom(struct ahc_softc *, 1345 struct seeprom_descriptor *); 1346 void ahc_release_seeprom(struct seeprom_descriptor *); 1347 1348 void ahc_check_extport(struct ahc_softc *, u_int *); 1349 #endif /* _AIC7XXXVAR_H_ */ 1350