1 /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause AND BSD-4-Clause
5 *
6 * Copyright (c) 2002-2004 Juli Mallett. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29 /*
30 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
40 * 3. All advertising materials mentioning features or use of this software
41 * must display the following acknowledgement:
42 * This product includes software developed by Per Fogelstrom.
43 * 4. The name of the author may not be used to endorse or promote products
44 * derived from this software without specific prior written permission
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 *
57 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
58 */
59
60 #ifndef _MACHINE_CPUFUNC_H_
61 #define _MACHINE_CPUFUNC_H_
62
63 #include <sys/types.h>
64 #include <machine/cpuregs.h>
65
66 /*
67 * These functions are required by user-land atomi ops
68 */
69
70 static __inline void
mips_barrier(void)71 mips_barrier(void)
72 {
73 #if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM)
74 __compiler_membar();
75 #else
76 __asm __volatile (".set noreorder\n\t"
77 "nop\n\t"
78 "nop\n\t"
79 "nop\n\t"
80 "nop\n\t"
81 "nop\n\t"
82 "nop\n\t"
83 "nop\n\t"
84 "nop\n\t"
85 ".set reorder\n\t"
86 : : : "memory");
87 #endif
88 }
89
90 static __inline void
mips_cp0_sync(void)91 mips_cp0_sync(void)
92 {
93 __asm __volatile (__XSTRING(COP0_SYNC));
94 }
95
96 static __inline void
mips_wbflush(void)97 mips_wbflush(void)
98 {
99 #if defined(CPU_CNMIPS)
100 __asm __volatile (".set noreorder\n\t"
101 "syncw\n\t"
102 ".set reorder\n"
103 : : : "memory");
104 #else
105 __asm __volatile ("sync" : : : "memory");
106 mips_barrier();
107 #endif
108 }
109
110 static __inline void
breakpoint(void)111 breakpoint(void)
112 {
113 __asm __volatile ("break");
114 }
115
116 #ifdef _KERNEL
117 /*
118 * XXX
119 * It would be nice to add variants that read/write register_t, to avoid some
120 * ABI checks.
121 */
122 #if defined(__mips_n32) || defined(__mips_n64)
123 #define MIPS_RW64_COP0(n,r) \
124 static __inline uint64_t \
125 mips_rd_ ## n (void) \
126 { \
127 uint64_t v0; \
128 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
129 : [v0] "=&r"(v0)); \
130 mips_barrier(); \
131 return (v0); \
132 } \
133 static __inline void \
134 mips_wr_ ## n (uint64_t a0) \
135 { \
136 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
137 __XSTRING(COP0_SYNC)";" \
138 "nop;" \
139 "nop;" \
140 : \
141 : [a0] "r"(a0)); \
142 mips_barrier(); \
143 } struct __hack
144
145 #define MIPS_RW64_COP0_SEL(n,r,s) \
146 static __inline uint64_t \
147 mips_rd_ ## n(void) \
148 { \
149 uint64_t v0; \
150 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
151 : [v0] "=&r"(v0)); \
152 mips_barrier(); \
153 return (v0); \
154 } \
155 static __inline void \
156 mips_wr_ ## n(uint64_t a0) \
157 { \
158 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
159 __XSTRING(COP0_SYNC)";" \
160 : \
161 : [a0] "r"(a0)); \
162 mips_barrier(); \
163 } struct __hack
164
165 #if defined(__mips_n64)
166 MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC);
167 MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
168 MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
169 MIPS_RW64_COP0_SEL(userlocal, MIPS_COP_0_USERLOCAL, 2);
170 #ifdef CPU_CNMIPS
171 MIPS_RW64_COP0_SEL(cvmcount, MIPS_COP_0_COUNT, 6);
172 MIPS_RW64_COP0_SEL(cvmctl, MIPS_COP_0_COUNT, 7);
173 MIPS_RW64_COP0_SEL(cvmmemctl, MIPS_COP_0_COMPARE, 7);
174 MIPS_RW64_COP0_SEL(icache_err, MIPS_COP_0_CACHE_ERR, 0);
175 MIPS_RW64_COP0_SEL(dcache_err, MIPS_COP_0_CACHE_ERR, 1);
176 #endif
177 #endif
178 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
179 MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
180 MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
181 #endif
182 MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
183
184 #undef MIPS_RW64_COP0
185 #undef MIPS_RW64_COP0_SEL
186 #endif
187
188 #define MIPS_RW32_COP0(n,r) \
189 static __inline uint32_t \
190 mips_rd_ ## n (void) \
191 { \
192 uint32_t v0; \
193 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
194 : [v0] "=&r"(v0)); \
195 mips_barrier(); \
196 return (v0); \
197 } \
198 static __inline void \
199 mips_wr_ ## n (uint32_t a0) \
200 { \
201 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
202 __XSTRING(COP0_SYNC)";" \
203 "nop;" \
204 "nop;" \
205 : \
206 : [a0] "r"(a0)); \
207 mips_barrier(); \
208 } struct __hack
209
210 #define MIPS_RW32_COP0_SEL(n,r,s) \
211 static __inline uint32_t \
212 mips_rd_ ## n(void) \
213 { \
214 uint32_t v0; \
215 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
216 : [v0] "=&r"(v0)); \
217 mips_barrier(); \
218 return (v0); \
219 } \
220 static __inline void \
221 mips_wr_ ## n(uint32_t a0) \
222 { \
223 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
224 __XSTRING(COP0_SYNC)";" \
225 "nop;" \
226 "nop;" \
227 : \
228 : [a0] "r"(a0)); \
229 mips_barrier(); \
230 } struct __hack
231
232 #ifdef CPU_CNMIPS
mips_sync_icache(void)233 static __inline void mips_sync_icache (void)
234 {
235 __asm __volatile (
236 ".set push\n"
237 ".set mips64\n"
238 ".word 0x041f0000\n" /* xxx ICACHE */
239 "nop\n"
240 ".set pop\n"
241 : : );
242 }
243 #endif
244
245 MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE);
246 MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG);
247 MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
248 MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
249 MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
250 #ifdef CPU_CNMIPS
251 MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
252 #endif
253 #ifdef BERI_LARGE_TLB
254 MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
255 #endif
256 #if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
257 MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
258 #endif
259 #if defined(CPU_NLM) || defined(CPU_MIPS1004K) || defined (CPU_MIPS74K) || \
260 defined(CPU_MIPS24K)
261 MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
262 #endif
263 MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
264 MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX);
265 MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
266 MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
267 #if !defined(__mips_n64)
268 MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
269 #endif
270 MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
271 MIPS_RW32_COP0_SEL(cmgcrbase, 15, 3);
272
273 /* XXX: Some of these registers are specific to MIPS32. */
274 #if !defined(__mips_n64)
275 MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
276 MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
277 MIPS_RW32_COP0_SEL(userlocal, MIPS_COP_0_USERLOCAL, 2);
278 #endif
279 #ifdef CPU_NLM
280 MIPS_RW32_COP0_SEL(pagegrain, MIPS_COP_0_TLB_PG_MASK, 1);
281 #endif
282 #if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
283 MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
284 MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
285 #endif
286 MIPS_RW32_COP0(prid, MIPS_COP_0_PRID);
287 MIPS_RW32_COP0_SEL(cinfo, MIPS_COP_0_PRID, 6);
288 MIPS_RW32_COP0_SEL(tinfo, MIPS_COP_0_PRID, 7);
289 /* XXX 64-bit? */
290 MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
291
292 #if defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \
293 defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \
294 defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \
295 defined(CPU_PROAPTIV)
296 /* MIPS32/64 r2 intctl */
297 MIPS_RW32_COP0_SEL(intctl, MIPS_COP_0_INTCTL, 1);
298 #endif
299
300 #ifdef CPU_XBURST
301 MIPS_RW32_COP0_SEL(xburst_mbox0, MIPS_COP_0_XBURST_MBOX, 0);
302 MIPS_RW32_COP0_SEL(xburst_mbox1, MIPS_COP_0_XBURST_MBOX, 1);
303 MIPS_RW32_COP0_SEL(xburst_core_ctl, MIPS_COP_0_XBURST_C12, 2);
304 MIPS_RW32_COP0_SEL(xburst_core_sts, MIPS_COP_0_XBURST_C12, 3);
305 MIPS_RW32_COP0_SEL(xburst_reim, MIPS_COP_0_XBURST_C12, 4);
306 #endif
307 MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
308 MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
309 MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
310 MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
311 MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
312 MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
313 MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
314 MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
315
316 MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
317 MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
318 MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
319 MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
320 MIPS_RW32_COP0(hwrena, MIPS_COP_0_HWRENA);
321
322 #undef MIPS_RW32_COP0
323 #undef MIPS_RW32_COP0_SEL
324
325 static __inline register_t
intr_disable(void)326 intr_disable(void)
327 {
328 register_t s;
329
330 s = mips_rd_status();
331 mips_wr_status(s & ~MIPS_SR_INT_IE);
332
333 return (s & MIPS_SR_INT_IE);
334 }
335
336 static __inline register_t
intr_enable(void)337 intr_enable(void)
338 {
339 register_t s;
340
341 s = mips_rd_status();
342 mips_wr_status(s | MIPS_SR_INT_IE);
343
344 return (s);
345 }
346
347 static __inline void
intr_restore(register_t ie)348 intr_restore(register_t ie)
349 {
350 if (ie == MIPS_SR_INT_IE) {
351 intr_enable();
352 }
353 }
354
355 static __inline uint32_t
set_intr_mask(uint32_t mask)356 set_intr_mask(uint32_t mask)
357 {
358 uint32_t ostatus;
359
360 ostatus = mips_rd_status();
361 mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
362 mips_wr_status(mask);
363 return (ostatus);
364 }
365
366 static __inline uint32_t
get_intr_mask(void)367 get_intr_mask(void)
368 {
369
370 return (mips_rd_status() & MIPS_SR_INT_MASK);
371 }
372
373 #endif /* _KERNEL */
374
375 #define readb(va) (*(volatile uint8_t *) (va))
376 #define readw(va) (*(volatile uint16_t *) (va))
377 #define readl(va) (*(volatile uint32_t *) (va))
378 #if !defined(__mips_o32)
379 #define readq(a) (*(volatile uint64_t *)(a))
380 #endif
381
382 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
383 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
384 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
385 #if !defined(__mips_o32)
386 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
387 #endif
388
389 #endif /* !_MACHINE_CPUFUNC_H_ */
390