1 /*-
2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/callout.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
39 #include <sys/rman.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
42
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/stdarg.h>
46
47 #include <dev/mmc/bridge.h>
48 #include <dev/mmc/mmcreg.h>
49 #include <dev/mmc/mmcbrvar.h>
50
51 #include "mmcbr_if.h"
52 #include "sdhci.h"
53 #include "sdhci_if.h"
54
55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
56
57 static int sdhci_debug;
58 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
59 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level");
60
61 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
62 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
63 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
64 #define RD_MULTI_4(slot, off, ptr, count) \
65 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
66
67 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
68 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
69 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
70 #define WR_MULTI_4(slot, off, ptr, count) \
71 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
72
73 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
74 static void sdhci_start(struct sdhci_slot *slot);
75 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
76
77 static void sdhci_card_task(void *, int);
78
79 /* helper routines */
80 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
81 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
82 #define SDHCI_LOCK_INIT(_slot) \
83 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
84 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
85 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
86 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
87
88 #define SDHCI_DEFAULT_MAX_FREQ 50
89
90 #define SDHCI_200_MAX_DIVIDER 256
91 #define SDHCI_300_MAX_DIVIDER 2046
92
93 static void
sdhci_getaddr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)94 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
95 {
96 if (error != 0) {
97 printf("getaddr: error %d\n", error);
98 return;
99 }
100 *(bus_addr_t *)arg = segs[0].ds_addr;
101 }
102
103 static int
slot_printf(struct sdhci_slot * slot,const char * fmt,...)104 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
105 {
106 va_list ap;
107 int retval;
108
109 retval = printf("%s-slot%d: ",
110 device_get_nameunit(slot->bus), slot->num);
111
112 va_start(ap, fmt);
113 retval += vprintf(fmt, ap);
114 va_end(ap);
115 return (retval);
116 }
117
118 static void
sdhci_dumpregs(struct sdhci_slot * slot)119 sdhci_dumpregs(struct sdhci_slot *slot)
120 {
121 slot_printf(slot,
122 "============== REGISTER DUMP ==============\n");
123
124 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
125 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
126 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
127 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
128 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
129 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
130 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
131 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
132 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
133 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
134 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
135 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
136 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
137 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
138 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
139 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
140 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
141 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
142 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
143 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
144
145 slot_printf(slot,
146 "===========================================\n");
147 }
148
149 static void
sdhci_reset(struct sdhci_slot * slot,uint8_t mask)150 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
151 {
152 int timeout;
153
154 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
155 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
156 SDHCI_CARD_PRESENT))
157 return;
158 }
159
160 /* Some controllers need this kick or reset won't work. */
161 if ((mask & SDHCI_RESET_ALL) == 0 &&
162 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
163 uint32_t clock;
164
165 /* This is to force an update */
166 clock = slot->clock;
167 slot->clock = 0;
168 sdhci_set_clock(slot, clock);
169 }
170
171 if (mask & SDHCI_RESET_ALL) {
172 slot->clock = 0;
173 slot->power = 0;
174 }
175
176 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
177
178 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
179 /*
180 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
181 * specification. The reset bit has internal propagation delay,
182 * so a fast read after write returns 0 even if reset process is
183 * in progress. The workaround is to poll for 1 before polling
184 * for 0. In the worst case, if we miss seeing it asserted the
185 * time we spent waiting is enough to ensure the reset finishes.
186 */
187 timeout = 10000;
188 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
189 if (timeout <= 0)
190 break;
191 timeout--;
192 DELAY(1);
193 }
194 }
195
196 /* Wait max 100 ms */
197 timeout = 10000;
198 /* Controller clears the bits when it's done */
199 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
200 if (timeout <= 0) {
201 slot_printf(slot, "Reset 0x%x never completed.\n",
202 mask);
203 sdhci_dumpregs(slot);
204 return;
205 }
206 timeout--;
207 DELAY(10);
208 }
209 }
210
211 static void
sdhci_init(struct sdhci_slot * slot)212 sdhci_init(struct sdhci_slot *slot)
213 {
214
215 sdhci_reset(slot, SDHCI_RESET_ALL);
216
217 /* Enable interrupts. */
218 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
219 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
220 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
221 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
222 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
223 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
224 SDHCI_INT_ACMD12ERR;
225 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
226 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
227 }
228
229 static void
sdhci_set_clock(struct sdhci_slot * slot,uint32_t clock)230 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
231 {
232 uint32_t res;
233 uint16_t clk;
234 uint16_t div;
235 int timeout;
236
237 if (clock == slot->clock)
238 return;
239 slot->clock = clock;
240
241 /* Turn off the clock. */
242 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
243 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
244 /* If no clock requested - left it so. */
245 if (clock == 0)
246 return;
247
248 /* Recalculate timeout clock frequency based on the new sd clock. */
249 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
250 slot->timeout_clk = slot->clock / 1000;
251
252 if (slot->version < SDHCI_SPEC_300) {
253 /* Looking for highest freq <= clock. */
254 res = slot->max_clk;
255 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
256 if (res <= clock)
257 break;
258 res >>= 1;
259 }
260 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
261 div >>= 1;
262 }
263 else {
264 /* Version 3.0 divisors are multiples of two up to 1023*2 */
265 if (clock >= slot->max_clk)
266 div = 0;
267 else {
268 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
269 if ((slot->max_clk / div) <= clock)
270 break;
271 }
272 }
273 div >>= 1;
274 }
275
276 if (bootverbose || sdhci_debug)
277 slot_printf(slot, "Divider %d for freq %d (max %d)\n",
278 div, clock, slot->max_clk);
279
280 /* Now we have got divider, set it. */
281 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
282 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
283 << SDHCI_DIVIDER_HI_SHIFT;
284
285 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
286 /* Enable clock. */
287 clk |= SDHCI_CLOCK_INT_EN;
288 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
289 /* Wait up to 10 ms until it stabilize. */
290 timeout = 10;
291 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
292 & SDHCI_CLOCK_INT_STABLE)) {
293 if (timeout == 0) {
294 slot_printf(slot,
295 "Internal clock never stabilised.\n");
296 sdhci_dumpregs(slot);
297 return;
298 }
299 timeout--;
300 DELAY(1000);
301 }
302 /* Pass clock signal to the bus. */
303 clk |= SDHCI_CLOCK_CARD_EN;
304 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
305 }
306
307 static void
sdhci_set_power(struct sdhci_slot * slot,u_char power)308 sdhci_set_power(struct sdhci_slot *slot, u_char power)
309 {
310 uint8_t pwr;
311
312 if (slot->power == power)
313 return;
314
315 slot->power = power;
316
317 /* Turn off the power. */
318 pwr = 0;
319 WR1(slot, SDHCI_POWER_CONTROL, pwr);
320 /* If power down requested - left it so. */
321 if (power == 0)
322 return;
323 /* Set voltage. */
324 switch (1 << power) {
325 case MMC_OCR_LOW_VOLTAGE:
326 pwr |= SDHCI_POWER_180;
327 break;
328 case MMC_OCR_290_300:
329 case MMC_OCR_300_310:
330 pwr |= SDHCI_POWER_300;
331 break;
332 case MMC_OCR_320_330:
333 case MMC_OCR_330_340:
334 pwr |= SDHCI_POWER_330;
335 break;
336 }
337 WR1(slot, SDHCI_POWER_CONTROL, pwr);
338 /* Turn on the power. */
339 pwr |= SDHCI_POWER_ON;
340 WR1(slot, SDHCI_POWER_CONTROL, pwr);
341 }
342
343 static void
sdhci_read_block_pio(struct sdhci_slot * slot)344 sdhci_read_block_pio(struct sdhci_slot *slot)
345 {
346 uint32_t data;
347 char *buffer;
348 size_t left;
349
350 buffer = slot->curcmd->data->data;
351 buffer += slot->offset;
352 /* Transfer one block at a time. */
353 left = min(512, slot->curcmd->data->len - slot->offset);
354 slot->offset += left;
355
356 /* If we are too fast, broken controllers return zeroes. */
357 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
358 DELAY(10);
359 /* Handle unaligned and aligned buffer cases. */
360 if ((intptr_t)buffer & 3) {
361 while (left > 3) {
362 data = RD4(slot, SDHCI_BUFFER);
363 buffer[0] = data;
364 buffer[1] = (data >> 8);
365 buffer[2] = (data >> 16);
366 buffer[3] = (data >> 24);
367 buffer += 4;
368 left -= 4;
369 }
370 } else {
371 RD_MULTI_4(slot, SDHCI_BUFFER,
372 (uint32_t *)buffer, left >> 2);
373 left &= 3;
374 }
375 /* Handle uneven size case. */
376 if (left > 0) {
377 data = RD4(slot, SDHCI_BUFFER);
378 while (left > 0) {
379 *(buffer++) = data;
380 data >>= 8;
381 left--;
382 }
383 }
384 }
385
386 static void
sdhci_write_block_pio(struct sdhci_slot * slot)387 sdhci_write_block_pio(struct sdhci_slot *slot)
388 {
389 uint32_t data = 0;
390 char *buffer;
391 size_t left;
392
393 buffer = slot->curcmd->data->data;
394 buffer += slot->offset;
395 /* Transfer one block at a time. */
396 left = min(512, slot->curcmd->data->len - slot->offset);
397 slot->offset += left;
398
399 /* Handle unaligned and aligned buffer cases. */
400 if ((intptr_t)buffer & 3) {
401 while (left > 3) {
402 data = buffer[0] +
403 (buffer[1] << 8) +
404 (buffer[2] << 16) +
405 (buffer[3] << 24);
406 left -= 4;
407 buffer += 4;
408 WR4(slot, SDHCI_BUFFER, data);
409 }
410 } else {
411 WR_MULTI_4(slot, SDHCI_BUFFER,
412 (uint32_t *)buffer, left >> 2);
413 left &= 3;
414 }
415 /* Handle uneven size case. */
416 if (left > 0) {
417 while (left > 0) {
418 data <<= 8;
419 data += *(buffer++);
420 left--;
421 }
422 WR4(slot, SDHCI_BUFFER, data);
423 }
424 }
425
426 static void
sdhci_transfer_pio(struct sdhci_slot * slot)427 sdhci_transfer_pio(struct sdhci_slot *slot)
428 {
429
430 /* Read as many blocks as possible. */
431 if (slot->curcmd->data->flags & MMC_DATA_READ) {
432 while (RD4(slot, SDHCI_PRESENT_STATE) &
433 SDHCI_DATA_AVAILABLE) {
434 sdhci_read_block_pio(slot);
435 if (slot->offset >= slot->curcmd->data->len)
436 break;
437 }
438 } else {
439 while (RD4(slot, SDHCI_PRESENT_STATE) &
440 SDHCI_SPACE_AVAILABLE) {
441 sdhci_write_block_pio(slot);
442 if (slot->offset >= slot->curcmd->data->len)
443 break;
444 }
445 }
446 }
447
448 static void
sdhci_card_delay(void * arg)449 sdhci_card_delay(void *arg)
450 {
451 struct sdhci_slot *slot = arg;
452
453 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
454 }
455
456 static void
sdhci_card_task(void * arg,int pending)457 sdhci_card_task(void *arg, int pending)
458 {
459 struct sdhci_slot *slot = arg;
460
461 SDHCI_LOCK(slot);
462 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
463 if (slot->dev == NULL) {
464 /* If card is present - attach mmc bus. */
465 slot->dev = device_add_child(slot->bus, "mmc", -1);
466 device_set_ivars(slot->dev, slot);
467 SDHCI_UNLOCK(slot);
468 device_probe_and_attach(slot->dev);
469 } else
470 SDHCI_UNLOCK(slot);
471 } else {
472 if (slot->dev != NULL) {
473 /* If no card present - detach mmc bus. */
474 device_t d = slot->dev;
475 slot->dev = NULL;
476 SDHCI_UNLOCK(slot);
477 device_delete_child(slot->bus, d);
478 } else
479 SDHCI_UNLOCK(slot);
480 }
481 }
482
483 int
sdhci_init_slot(device_t dev,struct sdhci_slot * slot,int num)484 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
485 {
486 uint32_t caps, freq;
487 int err;
488
489 SDHCI_LOCK_INIT(slot);
490 slot->num = num;
491 slot->bus = dev;
492
493 /* Allocate DMA tag. */
494 err = bus_dma_tag_create(bus_get_dma_tag(dev),
495 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
496 BUS_SPACE_MAXADDR, NULL, NULL,
497 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
498 BUS_DMA_ALLOCNOW, NULL, NULL,
499 &slot->dmatag);
500 if (err != 0) {
501 device_printf(dev, "Can't create DMA tag\n");
502 SDHCI_LOCK_DESTROY(slot);
503 return (err);
504 }
505 /* Allocate DMA memory. */
506 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
507 BUS_DMA_NOWAIT, &slot->dmamap);
508 if (err != 0) {
509 device_printf(dev, "Can't alloc DMA memory\n");
510 SDHCI_LOCK_DESTROY(slot);
511 return (err);
512 }
513 /* Map the memory. */
514 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
515 (void *)slot->dmamem, DMA_BLOCK_SIZE,
516 sdhci_getaddr, &slot->paddr, 0);
517 if (err != 0 || slot->paddr == 0) {
518 device_printf(dev, "Can't load DMA memory\n");
519 SDHCI_LOCK_DESTROY(slot);
520 if(err)
521 return (err);
522 else
523 return (EFAULT);
524 }
525
526 /* Initialize slot. */
527 sdhci_init(slot);
528 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
529 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
530 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
531 caps = slot->caps;
532 else
533 caps = RD4(slot, SDHCI_CAPABILITIES);
534 /* Calculate base clock frequency. */
535 if (slot->version >= SDHCI_SPEC_300)
536 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
537 SDHCI_CLOCK_BASE_SHIFT;
538 else
539 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
540 SDHCI_CLOCK_BASE_SHIFT;
541 if (freq != 0)
542 slot->max_clk = freq * 1000000;
543 /*
544 * If the frequency wasn't in the capabilities and the hardware driver
545 * hasn't already set max_clk we're probably not going to work right
546 * with an assumption, so complain about it.
547 */
548 if (slot->max_clk == 0) {
549 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
550 device_printf(dev, "Hardware doesn't specify base clock "
551 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
552 }
553 /* Calculate timeout clock frequency. */
554 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
555 slot->timeout_clk = slot->max_clk / 1000;
556 } else {
557 slot->timeout_clk =
558 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
559 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
560 slot->timeout_clk *= 1000;
561 }
562 /*
563 * If the frequency wasn't in the capabilities and the hardware driver
564 * hasn't already set timeout_clk we'll probably work okay using the
565 * max timeout, but still mention it.
566 */
567 if (slot->timeout_clk == 0) {
568 device_printf(dev, "Hardware doesn't specify timeout clock "
569 "frequency, setting BROKEN_TIMEOUT quirk.\n");
570 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
571 }
572
573 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
574 slot->host.f_max = slot->max_clk;
575 slot->host.host_ocr = 0;
576 if (caps & SDHCI_CAN_VDD_330)
577 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
578 if (caps & SDHCI_CAN_VDD_300)
579 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
580 if (caps & SDHCI_CAN_VDD_180)
581 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
582 if (slot->host.host_ocr == 0) {
583 device_printf(dev, "Hardware doesn't report any "
584 "support voltages.\n");
585 }
586 slot->host.caps = MMC_CAP_4_BIT_DATA;
587 if (caps & SDHCI_CAN_DO_8BITBUS)
588 slot->host.caps |= MMC_CAP_8_BIT_DATA;
589 if (caps & SDHCI_CAN_DO_HISPD)
590 slot->host.caps |= MMC_CAP_HSPEED;
591 /* Decide if we have usable DMA. */
592 if (caps & SDHCI_CAN_DO_DMA)
593 slot->opt |= SDHCI_HAVE_DMA;
594
595 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
596 slot->opt &= ~SDHCI_HAVE_DMA;
597 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
598 slot->opt |= SDHCI_HAVE_DMA;
599
600 /*
601 * Use platform-provided transfer backend
602 * with PIO as a fallback mechanism
603 */
604 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
605 slot->opt &= ~SDHCI_HAVE_DMA;
606
607 if (bootverbose || sdhci_debug) {
608 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n",
609 slot->max_clk / 1000000,
610 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
611 (caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
612 ((caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
613 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
614 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
615 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
616 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
617 sdhci_dumpregs(slot);
618 }
619
620 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
621 callout_init(&slot->card_callout, 1);
622 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
623 return (0);
624 }
625
626 void
sdhci_start_slot(struct sdhci_slot * slot)627 sdhci_start_slot(struct sdhci_slot *slot)
628 {
629 sdhci_card_task(slot, 0);
630 }
631
632 int
sdhci_cleanup_slot(struct sdhci_slot * slot)633 sdhci_cleanup_slot(struct sdhci_slot *slot)
634 {
635 device_t d;
636
637 callout_drain(&slot->timeout_callout);
638 callout_drain(&slot->card_callout);
639 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
640
641 SDHCI_LOCK(slot);
642 d = slot->dev;
643 slot->dev = NULL;
644 SDHCI_UNLOCK(slot);
645 if (d != NULL)
646 device_delete_child(slot->bus, d);
647
648 SDHCI_LOCK(slot);
649 sdhci_reset(slot, SDHCI_RESET_ALL);
650 SDHCI_UNLOCK(slot);
651 bus_dmamap_unload(slot->dmatag, slot->dmamap);
652 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
653 bus_dma_tag_destroy(slot->dmatag);
654
655 SDHCI_LOCK_DESTROY(slot);
656
657 return (0);
658 }
659
660 int
sdhci_generic_suspend(struct sdhci_slot * slot)661 sdhci_generic_suspend(struct sdhci_slot *slot)
662 {
663 sdhci_reset(slot, SDHCI_RESET_ALL);
664
665 return (0);
666 }
667
668 int
sdhci_generic_resume(struct sdhci_slot * slot)669 sdhci_generic_resume(struct sdhci_slot *slot)
670 {
671 sdhci_init(slot);
672
673 return (0);
674 }
675
676 uint32_t
sdhci_generic_min_freq(device_t brdev,struct sdhci_slot * slot)677 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
678 {
679 if (slot->version >= SDHCI_SPEC_300)
680 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
681 else
682 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
683 }
684
685 int
sdhci_generic_update_ios(device_t brdev,device_t reqdev)686 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
687 {
688 struct sdhci_slot *slot = device_get_ivars(reqdev);
689 struct mmc_ios *ios = &slot->host.ios;
690
691 SDHCI_LOCK(slot);
692 /* Do full reset on bus power down to clear from any state. */
693 if (ios->power_mode == power_off) {
694 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
695 sdhci_init(slot);
696 }
697 /* Configure the bus. */
698 sdhci_set_clock(slot, ios->clock);
699 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
700 if (ios->bus_width == bus_width_8) {
701 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
702 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
703 } else if (ios->bus_width == bus_width_4) {
704 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
705 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
706 } else if (ios->bus_width == bus_width_1) {
707 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
708 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
709 } else {
710 panic("Invalid bus width: %d", ios->bus_width);
711 }
712 if (ios->timing == bus_timing_hs &&
713 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
714 slot->hostctrl |= SDHCI_CTRL_HISPD;
715 else
716 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
717 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
718 /* Some controllers like reset after bus changes. */
719 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
720 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
721
722 SDHCI_UNLOCK(slot);
723 return (0);
724 }
725
726 static void
sdhci_req_done(struct sdhci_slot * slot)727 sdhci_req_done(struct sdhci_slot *slot)
728 {
729 struct mmc_request *req;
730
731 if (slot->req != NULL && slot->curcmd != NULL) {
732 callout_stop(&slot->timeout_callout);
733 req = slot->req;
734 slot->req = NULL;
735 slot->curcmd = NULL;
736 req->done(req);
737 }
738 }
739
740 static void
sdhci_timeout(void * arg)741 sdhci_timeout(void *arg)
742 {
743 struct sdhci_slot *slot = arg;
744
745 if (slot->curcmd != NULL) {
746 slot_printf(slot, " Controller timeout\n");
747 sdhci_dumpregs(slot);
748 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
749 slot->curcmd->error = MMC_ERR_TIMEOUT;
750 sdhci_req_done(slot);
751 } else {
752 slot_printf(slot, " Spurious timeout - no active command\n");
753 }
754 }
755
756 static void
sdhci_set_transfer_mode(struct sdhci_slot * slot,struct mmc_data * data)757 sdhci_set_transfer_mode(struct sdhci_slot *slot,
758 struct mmc_data *data)
759 {
760 uint16_t mode;
761
762 if (data == NULL)
763 return;
764
765 mode = SDHCI_TRNS_BLK_CNT_EN;
766 if (data->len > 512)
767 mode |= SDHCI_TRNS_MULTI;
768 if (data->flags & MMC_DATA_READ)
769 mode |= SDHCI_TRNS_READ;
770 if (slot->req->stop)
771 mode |= SDHCI_TRNS_ACMD12;
772 if (slot->flags & SDHCI_USE_DMA)
773 mode |= SDHCI_TRNS_DMA;
774
775 WR2(slot, SDHCI_TRANSFER_MODE, mode);
776 }
777
778 static void
sdhci_start_command(struct sdhci_slot * slot,struct mmc_command * cmd)779 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
780 {
781 int flags, timeout;
782 uint32_t mask, state;
783
784 slot->curcmd = cmd;
785 slot->cmd_done = 0;
786
787 cmd->error = MMC_ERR_NONE;
788
789 /* This flags combination is not supported by controller. */
790 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
791 slot_printf(slot, "Unsupported response type!\n");
792 cmd->error = MMC_ERR_FAILED;
793 sdhci_req_done(slot);
794 return;
795 }
796
797 /* Read controller present state. */
798 state = RD4(slot, SDHCI_PRESENT_STATE);
799 /* Do not issue command if there is no card, clock or power.
800 * Controller will not detect timeout without clock active. */
801 if ((state & SDHCI_CARD_PRESENT) == 0 ||
802 slot->power == 0 ||
803 slot->clock == 0) {
804 cmd->error = MMC_ERR_FAILED;
805 sdhci_req_done(slot);
806 return;
807 }
808 /* Always wait for free CMD bus. */
809 mask = SDHCI_CMD_INHIBIT;
810 /* Wait for free DAT if we have data or busy signal. */
811 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
812 mask |= SDHCI_DAT_INHIBIT;
813 /* We shouldn't wait for DAT for stop commands. */
814 if (cmd == slot->req->stop)
815 mask &= ~SDHCI_DAT_INHIBIT;
816 /*
817 * Wait for bus no more then 250 ms. Typically there will be no wait
818 * here at all, but when writing a crash dump we may be bypassing the
819 * host platform's interrupt handler, and in some cases that handler
820 * may be working around hardware quirks such as not respecting r1b
821 * busy indications. In those cases, this wait-loop serves the purpose
822 * of waiting for the prior command and data transfers to be done, and
823 * SD cards are allowed to take up to 250ms for write and erase ops.
824 * (It's usually more like 20-30ms in the real world.)
825 */
826 timeout = 250;
827 while (state & mask) {
828 if (timeout == 0) {
829 slot_printf(slot, "Controller never released "
830 "inhibit bit(s).\n");
831 sdhci_dumpregs(slot);
832 cmd->error = MMC_ERR_FAILED;
833 sdhci_req_done(slot);
834 return;
835 }
836 timeout--;
837 DELAY(1000);
838 state = RD4(slot, SDHCI_PRESENT_STATE);
839 }
840
841 /* Prepare command flags. */
842 if (!(cmd->flags & MMC_RSP_PRESENT))
843 flags = SDHCI_CMD_RESP_NONE;
844 else if (cmd->flags & MMC_RSP_136)
845 flags = SDHCI_CMD_RESP_LONG;
846 else if (cmd->flags & MMC_RSP_BUSY)
847 flags = SDHCI_CMD_RESP_SHORT_BUSY;
848 else
849 flags = SDHCI_CMD_RESP_SHORT;
850 if (cmd->flags & MMC_RSP_CRC)
851 flags |= SDHCI_CMD_CRC;
852 if (cmd->flags & MMC_RSP_OPCODE)
853 flags |= SDHCI_CMD_INDEX;
854 if (cmd->data)
855 flags |= SDHCI_CMD_DATA;
856 if (cmd->opcode == MMC_STOP_TRANSMISSION)
857 flags |= SDHCI_CMD_TYPE_ABORT;
858 /* Prepare data. */
859 sdhci_start_data(slot, cmd->data);
860 /*
861 * Interrupt aggregation: To reduce total number of interrupts
862 * group response interrupt with data interrupt when possible.
863 * If there going to be data interrupt, mask response one.
864 */
865 if (slot->data_done == 0) {
866 WR4(slot, SDHCI_SIGNAL_ENABLE,
867 slot->intmask &= ~SDHCI_INT_RESPONSE);
868 }
869 /* Set command argument. */
870 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
871 /* Set data transfer mode. */
872 sdhci_set_transfer_mode(slot, cmd->data);
873 /* Start command. */
874 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
875 /* Start timeout callout. */
876 callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot);
877 }
878
879 static void
sdhci_finish_command(struct sdhci_slot * slot)880 sdhci_finish_command(struct sdhci_slot *slot)
881 {
882 int i;
883
884 slot->cmd_done = 1;
885 /* Interrupt aggregation: Restore command interrupt.
886 * Main restore point for the case when command interrupt
887 * happened first. */
888 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
889 /* In case of error - reset host and return. */
890 if (slot->curcmd->error) {
891 sdhci_reset(slot, SDHCI_RESET_CMD);
892 sdhci_reset(slot, SDHCI_RESET_DATA);
893 sdhci_start(slot);
894 return;
895 }
896 /* If command has response - fetch it. */
897 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
898 if (slot->curcmd->flags & MMC_RSP_136) {
899 /* CRC is stripped so we need one byte shift. */
900 uint8_t extra = 0;
901 for (i = 0; i < 4; i++) {
902 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
903 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
904 slot->curcmd->resp[3 - i] = val;
905 else {
906 slot->curcmd->resp[3 - i] =
907 (val << 8) | extra;
908 extra = val >> 24;
909 }
910 }
911 } else
912 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
913 }
914 /* If data ready - finish. */
915 if (slot->data_done)
916 sdhci_start(slot);
917 }
918
919 static void
sdhci_start_data(struct sdhci_slot * slot,struct mmc_data * data)920 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
921 {
922 uint32_t target_timeout, current_timeout;
923 uint8_t div;
924
925 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
926 slot->data_done = 1;
927 return;
928 }
929
930 slot->data_done = 0;
931
932 /* Calculate and set data timeout.*/
933 /* XXX: We should have this from mmc layer, now assume 1 sec. */
934 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
935 div = 0xE;
936 } else {
937 target_timeout = 1000000;
938 div = 0;
939 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
940 while (current_timeout < target_timeout && div < 0xE) {
941 ++div;
942 current_timeout <<= 1;
943 }
944 /* Compensate for an off-by-one error in the CaFe chip.*/
945 if (div < 0xE &&
946 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
947 ++div;
948 }
949 }
950 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
951
952 if (data == NULL)
953 return;
954
955 /* Use DMA if possible. */
956 if ((slot->opt & SDHCI_HAVE_DMA))
957 slot->flags |= SDHCI_USE_DMA;
958 /* If data is small, broken DMA may return zeroes instead of data, */
959 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
960 (data->len <= 512))
961 slot->flags &= ~SDHCI_USE_DMA;
962 /* Some controllers require even block sizes. */
963 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
964 ((data->len) & 0x3))
965 slot->flags &= ~SDHCI_USE_DMA;
966 /* Load DMA buffer. */
967 if (slot->flags & SDHCI_USE_DMA) {
968 if (data->flags & MMC_DATA_READ)
969 bus_dmamap_sync(slot->dmatag, slot->dmamap,
970 BUS_DMASYNC_PREREAD);
971 else {
972 memcpy(slot->dmamem, data->data,
973 (data->len < DMA_BLOCK_SIZE) ?
974 data->len : DMA_BLOCK_SIZE);
975 bus_dmamap_sync(slot->dmatag, slot->dmamap,
976 BUS_DMASYNC_PREWRITE);
977 }
978 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
979 /* Interrupt aggregation: Mask border interrupt
980 * for the last page and unmask else. */
981 if (data->len == DMA_BLOCK_SIZE)
982 slot->intmask &= ~SDHCI_INT_DMA_END;
983 else
984 slot->intmask |= SDHCI_INT_DMA_END;
985 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
986 }
987 /* Current data offset for both PIO and DMA. */
988 slot->offset = 0;
989 /* Set block size and request IRQ on 4K border. */
990 WR2(slot, SDHCI_BLOCK_SIZE,
991 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
992 /* Set block count. */
993 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
994 }
995
996 void
sdhci_finish_data(struct sdhci_slot * slot)997 sdhci_finish_data(struct sdhci_slot *slot)
998 {
999 struct mmc_data *data = slot->curcmd->data;
1000
1001 /* Interrupt aggregation: Restore command interrupt.
1002 * Auxiliary restore point for the case when data interrupt
1003 * happened first. */
1004 if (!slot->cmd_done) {
1005 WR4(slot, SDHCI_SIGNAL_ENABLE,
1006 slot->intmask |= SDHCI_INT_RESPONSE);
1007 }
1008 /* Unload rest of data from DMA buffer. */
1009 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
1010 if (data->flags & MMC_DATA_READ) {
1011 size_t left = data->len - slot->offset;
1012 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1013 BUS_DMASYNC_POSTREAD);
1014 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1015 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1016 } else
1017 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1018 BUS_DMASYNC_POSTWRITE);
1019 }
1020 slot->data_done = 1;
1021 /* If there was error - reset the host. */
1022 if (slot->curcmd->error) {
1023 sdhci_reset(slot, SDHCI_RESET_CMD);
1024 sdhci_reset(slot, SDHCI_RESET_DATA);
1025 sdhci_start(slot);
1026 return;
1027 }
1028 /* If we already have command response - finish. */
1029 if (slot->cmd_done)
1030 sdhci_start(slot);
1031 }
1032
1033 static void
sdhci_start(struct sdhci_slot * slot)1034 sdhci_start(struct sdhci_slot *slot)
1035 {
1036 struct mmc_request *req;
1037
1038 req = slot->req;
1039 if (req == NULL)
1040 return;
1041
1042 if (!(slot->flags & CMD_STARTED)) {
1043 slot->flags |= CMD_STARTED;
1044 sdhci_start_command(slot, req->cmd);
1045 return;
1046 }
1047 /* We don't need this until using Auto-CMD12 feature
1048 if (!(slot->flags & STOP_STARTED) && req->stop) {
1049 slot->flags |= STOP_STARTED;
1050 sdhci_start_command(slot, req->stop);
1051 return;
1052 }
1053 */
1054 if (sdhci_debug > 1)
1055 slot_printf(slot, "result: %d\n", req->cmd->error);
1056 if (!req->cmd->error &&
1057 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1058 sdhci_reset(slot, SDHCI_RESET_CMD);
1059 sdhci_reset(slot, SDHCI_RESET_DATA);
1060 }
1061
1062 sdhci_req_done(slot);
1063 }
1064
1065 int
sdhci_generic_request(device_t brdev,device_t reqdev,struct mmc_request * req)1066 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1067 {
1068 struct sdhci_slot *slot = device_get_ivars(reqdev);
1069
1070 SDHCI_LOCK(slot);
1071 if (slot->req != NULL) {
1072 SDHCI_UNLOCK(slot);
1073 return (EBUSY);
1074 }
1075 if (sdhci_debug > 1) {
1076 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1077 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1078 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1079 (req->cmd->data)?req->cmd->data->flags:0);
1080 }
1081 slot->req = req;
1082 slot->flags = 0;
1083 sdhci_start(slot);
1084 SDHCI_UNLOCK(slot);
1085 if (dumping) {
1086 while (slot->req != NULL) {
1087 sdhci_generic_intr(slot);
1088 DELAY(10);
1089 }
1090 }
1091 return (0);
1092 }
1093
1094 int
sdhci_generic_get_ro(device_t brdev,device_t reqdev)1095 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1096 {
1097 struct sdhci_slot *slot = device_get_ivars(reqdev);
1098 uint32_t val;
1099
1100 SDHCI_LOCK(slot);
1101 val = RD4(slot, SDHCI_PRESENT_STATE);
1102 SDHCI_UNLOCK(slot);
1103 return (!(val & SDHCI_WRITE_PROTECT));
1104 }
1105
1106 int
sdhci_generic_acquire_host(device_t brdev,device_t reqdev)1107 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1108 {
1109 struct sdhci_slot *slot = device_get_ivars(reqdev);
1110 int err = 0;
1111
1112 SDHCI_LOCK(slot);
1113 while (slot->bus_busy)
1114 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1115 slot->bus_busy++;
1116 /* Activate led. */
1117 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1118 SDHCI_UNLOCK(slot);
1119 return (err);
1120 }
1121
1122 int
sdhci_generic_release_host(device_t brdev,device_t reqdev)1123 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1124 {
1125 struct sdhci_slot *slot = device_get_ivars(reqdev);
1126
1127 SDHCI_LOCK(slot);
1128 /* Deactivate led. */
1129 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1130 slot->bus_busy--;
1131 SDHCI_UNLOCK(slot);
1132 wakeup(slot);
1133 return (0);
1134 }
1135
1136 static void
sdhci_cmd_irq(struct sdhci_slot * slot,uint32_t intmask)1137 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1138 {
1139
1140 if (!slot->curcmd) {
1141 slot_printf(slot, "Got command interrupt 0x%08x, but "
1142 "there is no active command.\n", intmask);
1143 sdhci_dumpregs(slot);
1144 return;
1145 }
1146 if (intmask & SDHCI_INT_TIMEOUT)
1147 slot->curcmd->error = MMC_ERR_TIMEOUT;
1148 else if (intmask & SDHCI_INT_CRC)
1149 slot->curcmd->error = MMC_ERR_BADCRC;
1150 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1151 slot->curcmd->error = MMC_ERR_FIFO;
1152
1153 sdhci_finish_command(slot);
1154 }
1155
1156 static void
sdhci_data_irq(struct sdhci_slot * slot,uint32_t intmask)1157 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1158 {
1159
1160 if (!slot->curcmd) {
1161 slot_printf(slot, "Got data interrupt 0x%08x, but "
1162 "there is no active command.\n", intmask);
1163 sdhci_dumpregs(slot);
1164 return;
1165 }
1166 if (slot->curcmd->data == NULL &&
1167 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1168 slot_printf(slot, "Got data interrupt 0x%08x, but "
1169 "there is no active data operation.\n",
1170 intmask);
1171 sdhci_dumpregs(slot);
1172 return;
1173 }
1174 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1175 slot->curcmd->error = MMC_ERR_TIMEOUT;
1176 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1177 slot->curcmd->error = MMC_ERR_BADCRC;
1178 if (slot->curcmd->data == NULL &&
1179 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1180 SDHCI_INT_DMA_END))) {
1181 slot_printf(slot, "Got data interrupt 0x%08x, but "
1182 "there is busy-only command.\n", intmask);
1183 sdhci_dumpregs(slot);
1184 slot->curcmd->error = MMC_ERR_INVALID;
1185 }
1186 if (slot->curcmd->error) {
1187 /* No need to continue after any error. */
1188 goto done;
1189 }
1190
1191 /* Handle PIO interrupt. */
1192 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1193 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1194 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1195 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1196 slot->flags |= PLATFORM_DATA_STARTED;
1197 } else
1198 sdhci_transfer_pio(slot);
1199 }
1200 /* Handle DMA border. */
1201 if (intmask & SDHCI_INT_DMA_END) {
1202 struct mmc_data *data = slot->curcmd->data;
1203 size_t left;
1204
1205 /* Unload DMA buffer... */
1206 left = data->len - slot->offset;
1207 if (data->flags & MMC_DATA_READ) {
1208 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1209 BUS_DMASYNC_POSTREAD);
1210 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1211 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1212 } else {
1213 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1214 BUS_DMASYNC_POSTWRITE);
1215 }
1216 /* ... and reload it again. */
1217 slot->offset += DMA_BLOCK_SIZE;
1218 left = data->len - slot->offset;
1219 if (data->flags & MMC_DATA_READ) {
1220 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1221 BUS_DMASYNC_PREREAD);
1222 } else {
1223 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1224 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1225 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1226 BUS_DMASYNC_PREWRITE);
1227 }
1228 /* Interrupt aggregation: Mask border interrupt
1229 * for the last page. */
1230 if (left == DMA_BLOCK_SIZE) {
1231 slot->intmask &= ~SDHCI_INT_DMA_END;
1232 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1233 }
1234 /* Restart DMA. */
1235 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1236 }
1237 /* We have got all data. */
1238 if (intmask & SDHCI_INT_DATA_END) {
1239 if (slot->flags & PLATFORM_DATA_STARTED) {
1240 slot->flags &= ~PLATFORM_DATA_STARTED;
1241 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1242 } else
1243 sdhci_finish_data(slot);
1244 }
1245 done:
1246 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
1247 if (slot->flags & PLATFORM_DATA_STARTED) {
1248 slot->flags &= ~PLATFORM_DATA_STARTED;
1249 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1250 } else
1251 sdhci_finish_data(slot);
1252 return;
1253 }
1254 }
1255
1256 static void
sdhci_acmd_irq(struct sdhci_slot * slot)1257 sdhci_acmd_irq(struct sdhci_slot *slot)
1258 {
1259 uint16_t err;
1260
1261 err = RD4(slot, SDHCI_ACMD12_ERR);
1262 if (!slot->curcmd) {
1263 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1264 "there is no active command.\n", err);
1265 sdhci_dumpregs(slot);
1266 return;
1267 }
1268 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1269 sdhci_reset(slot, SDHCI_RESET_CMD);
1270 }
1271
1272 void
sdhci_generic_intr(struct sdhci_slot * slot)1273 sdhci_generic_intr(struct sdhci_slot *slot)
1274 {
1275 uint32_t intmask;
1276
1277 SDHCI_LOCK(slot);
1278 /* Read slot interrupt status. */
1279 intmask = RD4(slot, SDHCI_INT_STATUS);
1280 if (intmask == 0 || intmask == 0xffffffff) {
1281 SDHCI_UNLOCK(slot);
1282 return;
1283 }
1284 if (sdhci_debug > 2)
1285 slot_printf(slot, "Interrupt %#x\n", intmask);
1286
1287 /* Handle card presence interrupts. */
1288 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1289 WR4(slot, SDHCI_INT_STATUS, intmask &
1290 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1291
1292 if (intmask & SDHCI_INT_CARD_REMOVE) {
1293 if (bootverbose || sdhci_debug)
1294 slot_printf(slot, "Card removed\n");
1295 callout_stop(&slot->card_callout);
1296 taskqueue_enqueue(taskqueue_swi_giant,
1297 &slot->card_task);
1298 }
1299 if (intmask & SDHCI_INT_CARD_INSERT) {
1300 if (bootverbose || sdhci_debug)
1301 slot_printf(slot, "Card inserted\n");
1302 callout_reset(&slot->card_callout, hz / 2,
1303 sdhci_card_delay, slot);
1304 }
1305 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1306 }
1307 /* Handle command interrupts. */
1308 if (intmask & SDHCI_INT_CMD_MASK) {
1309 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1310 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1311 }
1312 /* Handle data interrupts. */
1313 if (intmask & SDHCI_INT_DATA_MASK) {
1314 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1315 /* Dont call data_irq in case of errored command */
1316 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
1317 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1318 }
1319 /* Handle AutoCMD12 error interrupt. */
1320 if (intmask & SDHCI_INT_ACMD12ERR) {
1321 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1322 sdhci_acmd_irq(slot);
1323 }
1324 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1325 intmask &= ~SDHCI_INT_ACMD12ERR;
1326 intmask &= ~SDHCI_INT_ERROR;
1327 /* Handle bus power interrupt. */
1328 if (intmask & SDHCI_INT_BUS_POWER) {
1329 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1330 slot_printf(slot,
1331 "Card is consuming too much power!\n");
1332 intmask &= ~SDHCI_INT_BUS_POWER;
1333 }
1334 /* The rest is unknown. */
1335 if (intmask) {
1336 WR4(slot, SDHCI_INT_STATUS, intmask);
1337 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1338 intmask);
1339 sdhci_dumpregs(slot);
1340 }
1341
1342 SDHCI_UNLOCK(slot);
1343 }
1344
1345 int
sdhci_generic_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)1346 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1347 {
1348 struct sdhci_slot *slot = device_get_ivars(child);
1349
1350 switch (which) {
1351 default:
1352 return (EINVAL);
1353 case MMCBR_IVAR_BUS_MODE:
1354 *result = slot->host.ios.bus_mode;
1355 break;
1356 case MMCBR_IVAR_BUS_WIDTH:
1357 *result = slot->host.ios.bus_width;
1358 break;
1359 case MMCBR_IVAR_CHIP_SELECT:
1360 *result = slot->host.ios.chip_select;
1361 break;
1362 case MMCBR_IVAR_CLOCK:
1363 *result = slot->host.ios.clock;
1364 break;
1365 case MMCBR_IVAR_F_MIN:
1366 *result = slot->host.f_min;
1367 break;
1368 case MMCBR_IVAR_F_MAX:
1369 *result = slot->host.f_max;
1370 break;
1371 case MMCBR_IVAR_HOST_OCR:
1372 *result = slot->host.host_ocr;
1373 break;
1374 case MMCBR_IVAR_MODE:
1375 *result = slot->host.mode;
1376 break;
1377 case MMCBR_IVAR_OCR:
1378 *result = slot->host.ocr;
1379 break;
1380 case MMCBR_IVAR_POWER_MODE:
1381 *result = slot->host.ios.power_mode;
1382 break;
1383 case MMCBR_IVAR_VDD:
1384 *result = slot->host.ios.vdd;
1385 break;
1386 case MMCBR_IVAR_CAPS:
1387 *result = slot->host.caps;
1388 break;
1389 case MMCBR_IVAR_TIMING:
1390 *result = slot->host.ios.timing;
1391 break;
1392 case MMCBR_IVAR_MAX_DATA:
1393 *result = 65535;
1394 break;
1395 }
1396 return (0);
1397 }
1398
1399 int
sdhci_generic_write_ivar(device_t bus,device_t child,int which,uintptr_t value)1400 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1401 {
1402 struct sdhci_slot *slot = device_get_ivars(child);
1403
1404 switch (which) {
1405 default:
1406 return (EINVAL);
1407 case MMCBR_IVAR_BUS_MODE:
1408 slot->host.ios.bus_mode = value;
1409 break;
1410 case MMCBR_IVAR_BUS_WIDTH:
1411 slot->host.ios.bus_width = value;
1412 break;
1413 case MMCBR_IVAR_CHIP_SELECT:
1414 slot->host.ios.chip_select = value;
1415 break;
1416 case MMCBR_IVAR_CLOCK:
1417 if (value > 0) {
1418 uint32_t max_clock;
1419 uint32_t clock;
1420 int i;
1421
1422 max_clock = slot->max_clk;
1423 clock = max_clock;
1424
1425 if (slot->version < SDHCI_SPEC_300) {
1426 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1427 i <<= 1) {
1428 if (clock <= value)
1429 break;
1430 clock >>= 1;
1431 }
1432 }
1433 else {
1434 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1435 i += 2) {
1436 if (clock <= value)
1437 break;
1438 clock = max_clock / (i + 2);
1439 }
1440 }
1441
1442 slot->host.ios.clock = clock;
1443 } else
1444 slot->host.ios.clock = 0;
1445 break;
1446 case MMCBR_IVAR_MODE:
1447 slot->host.mode = value;
1448 break;
1449 case MMCBR_IVAR_OCR:
1450 slot->host.ocr = value;
1451 break;
1452 case MMCBR_IVAR_POWER_MODE:
1453 slot->host.ios.power_mode = value;
1454 break;
1455 case MMCBR_IVAR_VDD:
1456 slot->host.ios.vdd = value;
1457 break;
1458 case MMCBR_IVAR_TIMING:
1459 slot->host.ios.timing = value;
1460 break;
1461 case MMCBR_IVAR_CAPS:
1462 case MMCBR_IVAR_HOST_OCR:
1463 case MMCBR_IVAR_F_MIN:
1464 case MMCBR_IVAR_F_MAX:
1465 case MMCBR_IVAR_MAX_DATA:
1466 return (EINVAL);
1467 }
1468 return (0);
1469 }
1470
1471 MODULE_VERSION(sdhci, 1);
1472