1 /*-
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #ifndef _DEV_UART_BUS_H_
30 #define _DEV_UART_BUS_H_
31
32 #ifndef KLD_MODULE
33 #include "opt_uart.h"
34 #endif
35
36 #include <sys/serial.h>
37 #include <sys/timepps.h>
38
39 /* Drain and flush targets. */
40 #define UART_DRAIN_RECEIVER 0x0001
41 #define UART_DRAIN_TRANSMITTER 0x0002
42 #define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER
43 #define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER
44
45 /* Received character status bits. */
46 #define UART_STAT_BREAK 0x0100
47 #define UART_STAT_FRAMERR 0x0200
48 #define UART_STAT_OVERRUN 0x0400
49 #define UART_STAT_PARERR 0x0800
50
51 /* UART_IOCTL() requests */
52 #define UART_IOCTL_BREAK 1
53 #define UART_IOCTL_IFLOW 2
54 #define UART_IOCTL_OFLOW 3
55 #define UART_IOCTL_BAUD 4
56
57 /* UART quirk flag */
58 #define UART_F_BUSY_DETECT 0x1
59
60 /*
61 * UART class & instance (=softc)
62 */
63 struct uart_class {
64 KOBJ_CLASS_FIELDS;
65 struct uart_ops *uc_ops; /* Low-level console operations. */
66 u_int uc_range; /* Bus space address range. */
67 u_int uc_rclk; /* Default rclk for this device. */
68 u_int uc_rshift; /* Default regshift for this device. */
69 u_int uc_riowidth; /* Default reg io width for this device. */
70 };
71
72 struct uart_softc {
73 KOBJ_FIELDS;
74 struct uart_class *sc_class;
75 struct uart_bas sc_bas;
76 device_t sc_dev;
77
78 struct mtx sc_hwmtx_s; /* Spinlock protecting hardware. */
79 struct mtx *sc_hwmtx;
80
81 struct resource *sc_rres; /* Register resource. */
82 int sc_rrid;
83 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */
84 struct resource *sc_ires; /* Interrupt resource. */
85 void *sc_icookie;
86 int sc_irid;
87 struct callout sc_timer;
88
89 int sc_callout:1; /* This UART is opened for callout. */
90 int sc_fastintr:1; /* This UART uses fast interrupts. */
91 int sc_hwiflow:1; /* This UART has HW input flow ctl. */
92 int sc_hwoflow:1; /* This UART has HW output flow ctl. */
93 int sc_leaving:1; /* This UART is going away. */
94 int sc_opened:1; /* This UART is open for business. */
95 int sc_polled:1; /* This UART has no interrupts. */
96 int sc_txbusy:1; /* This UART is transmitting. */
97 int sc_isquelch:1; /* This UART has input squelched. */
98 int sc_testintr:1; /* This UART is under int. testing. */
99
100 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */
101
102 int sc_altbrk; /* State for alt break sequence. */
103 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */
104
105 /* Receiver data. */
106 uint16_t *sc_rxbuf;
107 int sc_rxbufsz;
108 int sc_rxput;
109 int sc_rxget;
110 int sc_rxfifosz; /* Size of RX FIFO. */
111 int sc_rxoverruns;
112
113 /* Transmitter data. */
114 uint8_t *sc_txbuf;
115 int sc_txdatasz;
116 int sc_txfifosz; /* Size of TX FIFO and buffer. */
117
118 /* Pulse capturing support (PPS). */
119 struct pps_state sc_pps;
120 int sc_pps_mode;
121 sbintime_t sc_pps_captime;
122
123 /* Upper layer data. */
124 void *sc_softih;
125 uint32_t sc_ttypend;
126 union {
127 /* TTY specific data. */
128 struct {
129 struct tty *tp;
130 } u_tty;
131 /* Keyboard specific data. */
132 struct {
133 } u_kbd;
134 } sc_u;
135 };
136
137 extern devclass_t uart_devclass;
138 extern const char uart_driver_name[];
139
140 int uart_bus_attach(device_t dev);
141 int uart_bus_detach(device_t dev);
142 int uart_bus_resume(device_t dev);
143 serdev_intr_t *uart_bus_ihand(device_t dev, int ipend);
144 int uart_bus_ipend(device_t dev);
145 int uart_bus_probe(device_t dev, int regshft, int regiowidth, int rclk, int rid, int chan, int quirks);
146 int uart_bus_sysdev(device_t dev);
147
148 void uart_sched_softih(struct uart_softc *, uint32_t);
149
150 int uart_tty_attach(struct uart_softc *);
151 int uart_tty_detach(struct uart_softc *);
152 struct mtx *uart_tty_getlock(struct uart_softc *);
153 void uart_tty_intr(void *arg);
154
155 /*
156 * Receive buffer operations.
157 */
158 static __inline int
uart_rx_empty(struct uart_softc * sc)159 uart_rx_empty(struct uart_softc *sc)
160 {
161
162 return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0);
163 }
164
165 static __inline int
uart_rx_full(struct uart_softc * sc)166 uart_rx_full(struct uart_softc *sc)
167 {
168
169 return ((sc->sc_rxput + 1 < sc->sc_rxbufsz) ?
170 (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0));
171 }
172
173 static __inline int
uart_rx_get(struct uart_softc * sc)174 uart_rx_get(struct uart_softc *sc)
175 {
176 int ptr, xc;
177
178 ptr = sc->sc_rxget;
179 if (ptr == sc->sc_rxput)
180 return (-1);
181 xc = sc->sc_rxbuf[ptr++];
182 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
183 return (xc);
184 }
185
186 static __inline int
uart_rx_next(struct uart_softc * sc)187 uart_rx_next(struct uart_softc *sc)
188 {
189 int ptr;
190
191 ptr = sc->sc_rxget;
192 if (ptr == sc->sc_rxput)
193 return (-1);
194 ptr += 1;
195 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
196 return (0);
197 }
198
199 static __inline int
uart_rx_peek(struct uart_softc * sc)200 uart_rx_peek(struct uart_softc *sc)
201 {
202 int ptr;
203
204 ptr = sc->sc_rxget;
205 return ((ptr == sc->sc_rxput) ? -1 : sc->sc_rxbuf[ptr]);
206 }
207
208 static __inline int
uart_rx_put(struct uart_softc * sc,int xc)209 uart_rx_put(struct uart_softc *sc, int xc)
210 {
211 int ptr;
212
213 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0;
214 if (ptr == sc->sc_rxget)
215 return (ENOSPC);
216 sc->sc_rxbuf[sc->sc_rxput] = xc;
217 sc->sc_rxput = ptr;
218 return (0);
219 }
220
221 #endif /* _DEV_UART_BUS_H_ */
222