1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #ifndef _I915_DRV_H_
34 #define _I915_DRV_H_
35
36 #include <dev/agp/agp_i810.h>
37 #include <dev/drm2/drm_mm.h>
38 #include <dev/drm2/i915/i915_reg.h>
39 #include <dev/drm2/i915/intel_ringbuffer.h>
40 #include <dev/drm2/i915/intel_bios.h>
41
42 /* General customization:
43 */
44
45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46
47 #define DRIVER_NAME "i915"
48 #define DRIVER_DESC "Intel Graphics"
49 #define DRIVER_DATE "20080730"
50
51 MALLOC_DECLARE(DRM_I915_GEM);
52
53 enum pipe {
54 PIPE_A = 0,
55 PIPE_B,
56 PIPE_C,
57 I915_MAX_PIPES
58 };
59 #define pipe_name(p) ((p) + 'A')
60
61 enum transcoder {
62 TRANSCODER_A = 0,
63 TRANSCODER_B,
64 TRANSCODER_C,
65 TRANSCODER_EDP = 0xF,
66 };
67 #define transcoder_name(t) ((t) + 'A')
68
69 enum plane {
70 PLANE_A = 0,
71 PLANE_B,
72 PLANE_C,
73 };
74 #define plane_name(p) ((p) + 'A')
75
76 enum port {
77 PORT_A = 0,
78 PORT_B,
79 PORT_C,
80 PORT_D,
81 PORT_E,
82 I915_MAX_PORTS
83 };
84 #define port_name(p) ((p) + 'A')
85
86 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
87
88 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
89
90 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
91 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
92 if ((intel_encoder)->base.crtc == (__crtc))
93
94 struct intel_pch_pll {
95 int refcount; /* count of number of CRTCs sharing this PLL */
96 int active; /* count of number of active CRTCs (i.e. DPMS on) */
97 bool on; /* is the PLL actually active? Disabled during modeset */
98 int pll_reg;
99 int fp0_reg;
100 int fp1_reg;
101 };
102 #define I915_NUM_PLLS 2
103
104 struct intel_ddi_plls {
105 int spll_refcount;
106 int wrpll1_refcount;
107 int wrpll2_refcount;
108 };
109
110 /* Interface history:
111 *
112 * 1.1: Original.
113 * 1.2: Add Power Management
114 * 1.3: Add vblank support
115 * 1.4: Fix cmdbuffer path, add heap destroy
116 * 1.5: Add vblank pipe configuration
117 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
118 * - Support vertical blank on secondary display pipe
119 */
120 #define DRIVER_MAJOR 1
121 #define DRIVER_MINOR 6
122 #define DRIVER_PATCHLEVEL 0
123
124 #define WATCH_COHERENCY 0
125 #define WATCH_LISTS 0
126 #define WATCH_GTT 0
127
128 #define I915_GEM_PHYS_CURSOR_0 1
129 #define I915_GEM_PHYS_CURSOR_1 2
130 #define I915_GEM_PHYS_OVERLAY_REGS 3
131 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
132
133 struct drm_i915_gem_phys_object {
134 int id;
135 drm_dma_handle_t *handle;
136 struct drm_i915_gem_object *cur_obj;
137 };
138
139 struct opregion_header;
140 struct opregion_acpi;
141 struct opregion_swsci;
142 struct opregion_asle;
143 struct drm_i915_private;
144
145 struct intel_opregion {
146 struct opregion_header __iomem *header;
147 struct opregion_acpi __iomem *acpi;
148 struct opregion_swsci __iomem *swsci;
149 struct opregion_asle __iomem *asle;
150 void __iomem *vbt;
151 u32 __iomem *lid_state;
152 };
153 #define OPREGION_SIZE (8*1024)
154
155 struct intel_overlay;
156 struct intel_overlay_error_state;
157
158 struct drm_i915_master_private {
159 drm_local_map_t *sarea;
160 struct _drm_i915_sarea *sarea_priv;
161 };
162 #define I915_FENCE_REG_NONE -1
163 #define I915_MAX_NUM_FENCES 16
164 /* 16 fences + sign bit for FENCE_REG_NONE */
165 #define I915_MAX_NUM_FENCE_BITS 5
166
167 struct drm_i915_fence_reg {
168 struct list_head lru_list;
169 struct drm_i915_gem_object *obj;
170 int pin_count;
171 };
172
173 struct sdvo_device_mapping {
174 u8 initialized;
175 u8 dvo_port;
176 u8 slave_addr;
177 u8 dvo_wiring;
178 u8 i2c_pin;
179 u8 ddc_pin;
180 };
181
182 struct intel_display_error_state;
183
184 struct drm_i915_error_state {
185 u_int ref;
186 u32 eir;
187 u32 pgtbl_er;
188 u32 ier;
189 u32 ccid;
190 u32 derrmr;
191 u32 forcewake;
192 bool waiting[I915_NUM_RINGS];
193 u32 pipestat[I915_MAX_PIPES];
194 u32 tail[I915_NUM_RINGS];
195 u32 head[I915_NUM_RINGS];
196 u32 ctl[I915_NUM_RINGS];
197 u32 ipeir[I915_NUM_RINGS];
198 u32 ipehr[I915_NUM_RINGS];
199 u32 instdone[I915_NUM_RINGS];
200 u32 acthd[I915_NUM_RINGS];
201 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
202 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
203 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
204 /* our own tracking of ring head and tail */
205 u32 cpu_ring_head[I915_NUM_RINGS];
206 u32 cpu_ring_tail[I915_NUM_RINGS];
207 u32 error; /* gen6+ */
208 u32 err_int; /* gen7 */
209 u32 instpm[I915_NUM_RINGS];
210 u32 instps[I915_NUM_RINGS];
211 u32 extra_instdone[I915_NUM_INSTDONE_REG];
212 u32 seqno[I915_NUM_RINGS];
213 u64 bbaddr;
214 u32 fault_reg[I915_NUM_RINGS];
215 u32 done_reg;
216 u32 faddr[I915_NUM_RINGS];
217 u64 fence[I915_MAX_NUM_FENCES];
218 struct timeval time;
219 struct drm_i915_error_ring {
220 struct drm_i915_error_object {
221 int page_count;
222 u32 gtt_offset;
223 u32 *pages[0];
224 } *ringbuffer, *batchbuffer;
225 struct drm_i915_error_request {
226 long jiffies;
227 u32 seqno;
228 u32 tail;
229 } *requests;
230 int num_requests;
231 } ring[I915_NUM_RINGS];
232 struct drm_i915_error_buffer {
233 u32 size;
234 u32 name;
235 u32 rseqno, wseqno;
236 u32 gtt_offset;
237 u32 read_domains;
238 u32 write_domain;
239 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
240 s32 pinned:2;
241 u32 tiling:2;
242 u32 dirty:1;
243 u32 purgeable:1;
244 s32 ring:4;
245 u32 cache_level:2;
246 } *active_bo, *pinned_bo;
247 u32 active_bo_count, pinned_bo_count;
248 struct intel_overlay_error_state *overlay;
249 struct intel_display_error_state *display;
250 };
251
252 struct drm_i915_display_funcs {
253 bool (*fbc_enabled)(struct drm_device *dev);
254 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
255 void (*disable_fbc)(struct drm_device *dev);
256 int (*get_display_clock_speed)(struct drm_device *dev);
257 int (*get_fifo_size)(struct drm_device *dev, int plane);
258 void (*update_wm)(struct drm_device *dev);
259 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
260 uint32_t sprite_width, int pixel_size);
261 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
262 struct drm_display_mode *mode);
263 void (*modeset_global_resources)(struct drm_device *dev);
264 int (*crtc_mode_set)(struct drm_crtc *crtc,
265 struct drm_display_mode *mode,
266 struct drm_display_mode *adjusted_mode,
267 int x, int y,
268 struct drm_framebuffer *old_fb);
269 void (*crtc_enable)(struct drm_crtc *crtc);
270 void (*crtc_disable)(struct drm_crtc *crtc);
271 void (*off)(struct drm_crtc *crtc);
272 void (*write_eld)(struct drm_connector *connector,
273 struct drm_crtc *crtc);
274 void (*fdi_link_train)(struct drm_crtc *crtc);
275 void (*init_clock_gating)(struct drm_device *dev);
276 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
277 struct drm_framebuffer *fb,
278 struct drm_i915_gem_object *obj);
279 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
280 int x, int y);
281 /* clock updates for mode set */
282 /* cursor updates */
283 /* render clock increase/decrease */
284 /* display clock increase/decrease */
285 /* pll clock increase/decrease */
286 };
287
288 struct drm_i915_gt_funcs {
289 void (*force_wake_get)(struct drm_i915_private *dev_priv);
290 void (*force_wake_put)(struct drm_i915_private *dev_priv);
291 };
292
293 #define DEV_INFO_FLAGS \
294 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
295 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
296 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
297 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
298 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
299 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
300 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
301 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
302 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
303 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
304 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
305 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
306 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
307 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
308 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
309 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
310 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
311 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
312 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
313 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
314 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
315 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
316 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
317 DEV_INFO_FLAG(has_llc)
318
319 struct intel_device_info {
320 u8 gen;
321 u8 is_mobile:1;
322 u8 is_i85x:1;
323 u8 is_i915g:1;
324 u8 is_i945gm:1;
325 u8 is_g33:1;
326 u8 need_gfx_hws:1;
327 u8 is_g4x:1;
328 u8 is_pineview:1;
329 u8 is_broadwater:1;
330 u8 is_crestline:1;
331 u8 is_ivybridge:1;
332 u8 is_valleyview:1;
333 u8 has_force_wake:1;
334 u8 is_haswell:1;
335 u8 has_fbc:1;
336 u8 has_pipe_cxsr:1;
337 u8 has_hotplug:1;
338 u8 cursor_needs_physical:1;
339 u8 has_overlay:1;
340 u8 overlay_needs_physical:1;
341 u8 supports_tv:1;
342 u8 has_bsd_ring:1;
343 u8 has_blt_ring:1;
344 u8 has_llc:1;
345 };
346
347 #define I915_PPGTT_PD_ENTRIES 512
348 #define I915_PPGTT_PT_ENTRIES 1024
349 struct i915_hw_ppgtt {
350 struct drm_device *dev;
351 unsigned num_pd_entries;
352 vm_page_t *pt_pages;
353 uint32_t pd_offset;
354 vm_paddr_t *pt_dma_addr;
355 vm_paddr_t scratch_page_dma_addr;
356 };
357
358
359 /* This must match up with the value previously used for execbuf2.rsvd1. */
360 #define DEFAULT_CONTEXT_ID 0
361 struct i915_hw_context {
362 uint32_t id;
363 bool is_initialized;
364 struct drm_i915_file_private *file_priv;
365 struct intel_ring_buffer *ring;
366 struct drm_i915_gem_object *obj;
367 };
368
369 enum no_fbc_reason {
370 FBC_NO_OUTPUT, /* no outputs enabled to compress */
371 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
372 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
373 FBC_MODE_TOO_LARGE, /* mode too large for compression */
374 FBC_BAD_PLANE, /* fbc not supported on plane */
375 FBC_NOT_TILED, /* buffer not tiled */
376 FBC_MULTIPLE_PIPES, /* more than one pipe active */
377 FBC_MODULE_PARAM,
378 };
379
380 enum intel_pch {
381 PCH_NONE = 0, /* No PCH present */
382 PCH_IBX, /* Ibexpeak PCH */
383 PCH_CPT, /* Cougarpoint PCH */
384 PCH_LPT, /* Lynxpoint PCH */
385 };
386
387 enum intel_sbi_destination {
388 SBI_ICLK,
389 SBI_MPHY,
390 };
391
392 #define QUIRK_PIPEA_FORCE (1<<0)
393 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
394 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
395
396 struct intel_fbdev;
397 struct intel_fbc_work;
398
399 struct intel_gmbus {
400 device_t gmbus_bridge;
401 device_t gmbus;
402 device_t bbbus_bridge;
403 device_t bbbus;
404 u32 force_bit;
405 u32 reg0;
406 u32 gpio_reg;
407 struct drm_i915_private *dev_priv;
408 };
409
410 struct i915_suspend_saved_registers {
411 u8 saveLBB;
412 u32 saveDSPACNTR;
413 u32 saveDSPBCNTR;
414 u32 saveDSPARB;
415 u32 savePIPEACONF;
416 u32 savePIPEBCONF;
417 u32 savePIPEASRC;
418 u32 savePIPEBSRC;
419 u32 saveFPA0;
420 u32 saveFPA1;
421 u32 saveDPLL_A;
422 u32 saveDPLL_A_MD;
423 u32 saveHTOTAL_A;
424 u32 saveHBLANK_A;
425 u32 saveHSYNC_A;
426 u32 saveVTOTAL_A;
427 u32 saveVBLANK_A;
428 u32 saveVSYNC_A;
429 u32 saveBCLRPAT_A;
430 u32 saveTRANSACONF;
431 u32 saveTRANS_HTOTAL_A;
432 u32 saveTRANS_HBLANK_A;
433 u32 saveTRANS_HSYNC_A;
434 u32 saveTRANS_VTOTAL_A;
435 u32 saveTRANS_VBLANK_A;
436 u32 saveTRANS_VSYNC_A;
437 u32 savePIPEASTAT;
438 u32 saveDSPASTRIDE;
439 u32 saveDSPASIZE;
440 u32 saveDSPAPOS;
441 u32 saveDSPAADDR;
442 u32 saveDSPASURF;
443 u32 saveDSPATILEOFF;
444 u32 savePFIT_PGM_RATIOS;
445 u32 saveBLC_HIST_CTL;
446 u32 saveBLC_PWM_CTL;
447 u32 saveBLC_PWM_CTL2;
448 u32 saveBLC_CPU_PWM_CTL;
449 u32 saveBLC_CPU_PWM_CTL2;
450 u32 saveFPB0;
451 u32 saveFPB1;
452 u32 saveDPLL_B;
453 u32 saveDPLL_B_MD;
454 u32 saveHTOTAL_B;
455 u32 saveHBLANK_B;
456 u32 saveHSYNC_B;
457 u32 saveVTOTAL_B;
458 u32 saveVBLANK_B;
459 u32 saveVSYNC_B;
460 u32 saveBCLRPAT_B;
461 u32 saveTRANSBCONF;
462 u32 saveTRANS_HTOTAL_B;
463 u32 saveTRANS_HBLANK_B;
464 u32 saveTRANS_HSYNC_B;
465 u32 saveTRANS_VTOTAL_B;
466 u32 saveTRANS_VBLANK_B;
467 u32 saveTRANS_VSYNC_B;
468 u32 savePIPEBSTAT;
469 u32 saveDSPBSTRIDE;
470 u32 saveDSPBSIZE;
471 u32 saveDSPBPOS;
472 u32 saveDSPBADDR;
473 u32 saveDSPBSURF;
474 u32 saveDSPBTILEOFF;
475 u32 saveVGA0;
476 u32 saveVGA1;
477 u32 saveVGA_PD;
478 u32 saveVGACNTRL;
479 u32 saveADPA;
480 u32 saveLVDS;
481 u32 savePP_ON_DELAYS;
482 u32 savePP_OFF_DELAYS;
483 u32 saveDVOA;
484 u32 saveDVOB;
485 u32 saveDVOC;
486 u32 savePP_ON;
487 u32 savePP_OFF;
488 u32 savePP_CONTROL;
489 u32 savePP_DIVISOR;
490 u32 savePFIT_CONTROL;
491 u32 save_palette_a[256];
492 u32 save_palette_b[256];
493 u32 saveDPFC_CB_BASE;
494 u32 saveFBC_CFB_BASE;
495 u32 saveFBC_LL_BASE;
496 u32 saveFBC_CONTROL;
497 u32 saveFBC_CONTROL2;
498 u32 saveIER;
499 u32 saveIIR;
500 u32 saveIMR;
501 u32 saveDEIER;
502 u32 saveDEIMR;
503 u32 saveGTIER;
504 u32 saveGTIMR;
505 u32 saveFDI_RXA_IMR;
506 u32 saveFDI_RXB_IMR;
507 u32 saveCACHE_MODE_0;
508 u32 saveMI_ARB_STATE;
509 u32 saveSWF0[16];
510 u32 saveSWF1[16];
511 u32 saveSWF2[3];
512 u8 saveMSR;
513 u8 saveSR[8];
514 u8 saveGR[25];
515 u8 saveAR_INDEX;
516 u8 saveAR[21];
517 u8 saveDACMASK;
518 u8 saveCR[37];
519 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
520 u32 saveCURACNTR;
521 u32 saveCURAPOS;
522 u32 saveCURABASE;
523 u32 saveCURBCNTR;
524 u32 saveCURBPOS;
525 u32 saveCURBBASE;
526 u32 saveCURSIZE;
527 u32 saveDP_B;
528 u32 saveDP_C;
529 u32 saveDP_D;
530 u32 savePIPEA_GMCH_DATA_M;
531 u32 savePIPEB_GMCH_DATA_M;
532 u32 savePIPEA_GMCH_DATA_N;
533 u32 savePIPEB_GMCH_DATA_N;
534 u32 savePIPEA_DP_LINK_M;
535 u32 savePIPEB_DP_LINK_M;
536 u32 savePIPEA_DP_LINK_N;
537 u32 savePIPEB_DP_LINK_N;
538 u32 saveFDI_RXA_CTL;
539 u32 saveFDI_TXA_CTL;
540 u32 saveFDI_RXB_CTL;
541 u32 saveFDI_TXB_CTL;
542 u32 savePFA_CTL_1;
543 u32 savePFB_CTL_1;
544 u32 savePFA_WIN_SZ;
545 u32 savePFB_WIN_SZ;
546 u32 savePFA_WIN_POS;
547 u32 savePFB_WIN_POS;
548 u32 savePCH_DREF_CONTROL;
549 u32 saveDISP_ARB_CTL;
550 u32 savePIPEA_DATA_M1;
551 u32 savePIPEA_DATA_N1;
552 u32 savePIPEA_LINK_M1;
553 u32 savePIPEA_LINK_N1;
554 u32 savePIPEB_DATA_M1;
555 u32 savePIPEB_DATA_N1;
556 u32 savePIPEB_LINK_M1;
557 u32 savePIPEB_LINK_N1;
558 u32 saveMCHBAR_RENDER_STANDBY;
559 u32 savePCH_PORT_HOTPLUG;
560 };
561
562 struct intel_gen6_power_mgmt {
563 struct task work;
564 u32 pm_iir;
565 /* lock - irqsave spinlock that protectects the work_struct and
566 * pm_iir. */
567 struct mtx lock;
568
569 /* The below variables an all the rps hw state are protected by
570 * dev->struct mutext. */
571 u8 cur_delay;
572 u8 min_delay;
573 u8 max_delay;
574
575 struct timeout_task delayed_resume_work;
576
577 /*
578 * Protects RPS/RC6 register access and PCU communication.
579 * Must be taken after struct_mutex if nested.
580 */
581 struct sx hw_lock;
582 };
583
584 struct intel_ilk_power_mgmt {
585 u8 cur_delay;
586 u8 min_delay;
587 u8 max_delay;
588 u8 fmax;
589 u8 fstart;
590
591 u64 last_count1;
592 unsigned long last_time1;
593 unsigned long chipset_power;
594 u64 last_count2;
595 struct timespec last_time2;
596 unsigned long gfx_power;
597 u8 corr;
598
599 int c_m;
600 int r_t;
601
602 struct drm_i915_gem_object *pwrctx;
603 struct drm_i915_gem_object *renderctx;
604 };
605
606 struct i915_dri1_state {
607 unsigned allow_batchbuffer : 1;
608 u32 __iomem *gfx_hws_cpu_addr;
609
610 unsigned int cpp;
611 int back_offset;
612 int front_offset;
613 int current_page;
614 int page_flipping;
615
616 uint32_t counter;
617 };
618
619 struct intel_l3_parity {
620 u32 *remap_info;
621 struct task error_work;
622 };
623
624 typedef struct drm_i915_private {
625 struct drm_device *dev;
626
627 const struct intel_device_info *info;
628
629 int relative_constants_mode;
630
631 /* FIXME Linux<->FreeBSD: "void *regs" on Linux. */
632 drm_local_map_t *mmio_map;
633
634 struct drm_i915_gt_funcs gt;
635 /** gt_fifo_count and the subsequent register write are synchronized
636 * with dev->struct_mutex. */
637 unsigned gt_fifo_count;
638 /** forcewake_count is protected by gt_lock */
639 unsigned forcewake_count;
640 /** gt_lock is also taken in irq contexts. */
641 struct mtx gt_lock;
642
643 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
644
645 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
646 * controller on different i2c buses. */
647 struct sx gmbus_mutex;
648
649 /**
650 * Base address of the gmbus and gpio block.
651 */
652 uint32_t gpio_mmio_base;
653
654 device_t bridge_dev;
655 struct intel_ring_buffer ring[I915_NUM_RINGS];
656 uint32_t next_seqno;
657
658 drm_dma_handle_t *status_page_dmah;
659 int mch_res_rid;
660 struct resource *mch_res;
661
662 atomic_t irq_received;
663
664 /* protects the irq masks */
665 struct mtx irq_lock;
666
667 /* DPIO indirect register protection */
668 struct sx dpio_lock;
669
670 /** Cached value of IMR to avoid reads in updating the bitfield */
671 u32 pipestat[2];
672 u32 irq_mask;
673 u32 gt_irq_mask;
674 u32 pch_irq_mask;
675
676 u32 hotplug_supported_mask;
677 struct task hotplug_work;
678
679 int num_pipe;
680 int num_pch_pll;
681
682 /* For hangcheck timer */
683 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
684 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
685 struct callout hangcheck_timer;
686 int hangcheck_count;
687 uint32_t last_acthd[I915_NUM_RINGS];
688 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
689
690 unsigned int stop_rings;
691
692 unsigned long cfb_size;
693 unsigned int cfb_fb;
694 enum plane cfb_plane;
695 int cfb_y;
696 struct intel_fbc_work *fbc_work;
697
698 struct intel_opregion opregion;
699
700 /* overlay */
701 struct intel_overlay *overlay;
702 bool sprite_scaling_enabled;
703
704 /* LVDS info */
705 int backlight_level; /* restore backlight to this value */
706 bool backlight_enabled;
707 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
708 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
709
710 /* Feature bits from the VBIOS */
711 unsigned int int_tv_support:1;
712 unsigned int lvds_dither:1;
713 unsigned int lvds_vbt:1;
714 unsigned int int_crt_support:1;
715 unsigned int lvds_use_ssc:1;
716 unsigned int display_clock_mode:1;
717 unsigned int fdi_rx_polarity_inverted:1;
718 int lvds_ssc_freq;
719 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
720 unsigned int lvds_val; /* used for checking LVDS channel mode */
721 struct {
722 int rate;
723 int lanes;
724 int preemphasis;
725 int vswing;
726
727 bool initialized;
728 bool support;
729 int bpp;
730 struct edp_power_seq pps;
731 } edp;
732 bool no_aux_handshake;
733
734 int crt_ddc_pin;
735 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
736 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
737 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
738
739 unsigned int fsb_freq, mem_freq, is_ddr3;
740
741 struct mtx error_lock;
742 /* Protected by dev->error_lock. */
743 struct drm_i915_error_state *first_error;
744 struct task error_work;
745 struct completion error_completion;
746 struct taskqueue *wq;
747
748 /* Display functions */
749 struct drm_i915_display_funcs display;
750
751 /* PCH chipset type */
752 enum intel_pch pch_type;
753 unsigned short pch_id;
754
755 unsigned long quirks;
756
757 /* Register state */
758 bool modeset_on_lid;
759
760 struct {
761 /** Bridge to intel-gtt-ko */
762 struct intel_gtt *gtt;
763 /** Memory allocator for GTT stolen memory */
764 struct drm_mm stolen;
765 /** Memory allocator for GTT */
766 struct drm_mm gtt_space;
767 /** List of all objects in gtt_space. Used to restore gtt
768 * mappings on resume */
769 struct list_head bound_list;
770 /**
771 * List of objects which are not bound to the GTT (thus
772 * are idle and not used by the GPU) but still have
773 * (presumably uncached) pages still attached.
774 */
775 struct list_head unbound_list;
776
777 /** Usable portion of the GTT for GEM */
778 unsigned long gtt_start;
779 unsigned long gtt_mappable_end;
780 unsigned long gtt_end;
781 unsigned long stolen_base; /* limited to low memory (32-bit) */
782
783 #ifdef __linux__
784 struct io_mapping *gtt_mapping;
785 #endif
786 vm_paddr_t gtt_base_addr;
787 int gtt_mtrr;
788
789 /** PPGTT used for aliasing the PPGTT with the GTT */
790 struct i915_hw_ppgtt *aliasing_ppgtt;
791
792 eventhandler_tag inactive_shrinker;
793 bool shrinker_no_lock_stealing;
794
795 /**
796 * List of objects currently involved in rendering.
797 *
798 * Includes buffers having the contents of their GPU caches
799 * flushed, not necessarily primitives. last_rendering_seqno
800 * represents when the rendering involved will be completed.
801 *
802 * A reference is held on the buffer while on this list.
803 */
804 struct list_head active_list;
805
806 /**
807 * LRU list of objects which are not in the ringbuffer and
808 * are ready to unbind, but are still in the GTT.
809 *
810 * last_rendering_seqno is 0 while an object is in this list.
811 *
812 * A reference is not held on the buffer while on this list,
813 * as merely being GTT-bound shouldn't prevent its being
814 * freed, and we'll pull it off the list in the free path.
815 */
816 struct list_head inactive_list;
817
818 /** LRU list of objects with fence regs on them. */
819 struct list_head fence_list;
820
821 /**
822 * We leave the user IRQ off as much as possible,
823 * but this means that requests will finish and never
824 * be retired once the system goes idle. Set a timer to
825 * fire periodically while the ring is running. When it
826 * fires, go retire requests.
827 */
828 struct timeout_task retire_work;
829
830 /**
831 * Are we in a non-interruptible section of code like
832 * modesetting?
833 */
834 bool interruptible;
835
836 /**
837 * Flag if the X Server, and thus DRM, is not currently in
838 * control of the device.
839 *
840 * This is set between LeaveVT and EnterVT. It needs to be
841 * replaced with a semaphore. It also needs to be
842 * transitioned away from for kernel modesetting.
843 */
844 int suspended;
845
846 /**
847 * Flag if the hardware appears to be wedged.
848 *
849 * This is set when attempts to idle the device timeout.
850 * It prevents command submission from occurring and makes
851 * every pending request fail
852 */
853 atomic_t wedged;
854
855 /** Bit 6 swizzling required for X tiling */
856 uint32_t bit_6_swizzle_x;
857 /** Bit 6 swizzling required for Y tiling */
858 uint32_t bit_6_swizzle_y;
859
860 /* storage for physical objects */
861 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
862
863 /* accounting, useful for userland debugging */
864 size_t gtt_total;
865 size_t mappable_gtt_total;
866 size_t object_memory;
867 u32 object_count;
868 } mm;
869
870 /* Kernel Modesetting */
871
872 struct sdvo_device_mapping sdvo_mappings[2];
873 /* indicate whether the LVDS_BORDER should be enabled or not */
874 unsigned int lvds_border_bits;
875 /* Panel fitter placement and size for Ironlake+ */
876 u32 pch_pf_pos, pch_pf_size;
877
878 struct drm_crtc *plane_to_crtc_mapping[3];
879 struct drm_crtc *pipe_to_crtc_mapping[3];
880 wait_queue_head_t pending_flip_queue;
881
882 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
883 struct intel_ddi_plls ddi_plls;
884
885 /* Reclocking support */
886 bool render_reclock_avail;
887 bool lvds_downclock_avail;
888 /* indicates the reduced downclock for LVDS*/
889 int lvds_downclock;
890 u16 orig_clock;
891 int child_dev_num;
892 struct child_device_config *child_dev;
893
894 bool mchbar_need_disable;
895
896 struct intel_l3_parity l3_parity;
897
898 /* gen6+ rps state */
899 struct intel_gen6_power_mgmt rps;
900
901 /* ilk-only ips/rps state. Everything in here is protected by the global
902 * mchdev_lock in intel_pm.c */
903 struct intel_ilk_power_mgmt ips;
904
905 enum no_fbc_reason no_fbc_reason;
906
907 struct drm_mm_node *compressed_fb;
908 struct drm_mm_node *compressed_llb;
909
910 unsigned long last_gpu_reset;
911
912 /* list of fbdev register on this device */
913 struct intel_fbdev *fbdev;
914
915 /*
916 * The console may be contended at resume, but we don't
917 * want it to block on it.
918 */
919 struct task console_resume_work;
920
921 struct backlight_device *backlight;
922
923 struct drm_property *broadcast_rgb_property;
924 struct drm_property *force_audio_property;
925
926 bool hw_contexts_disabled;
927 uint32_t hw_context_size;
928
929 u32 fdi_rx_config;
930
931 struct i915_suspend_saved_registers regfile;
932
933 /* Old dri1 support infrastructure, beware the dragons ya fools entering
934 * here! */
935 struct i915_dri1_state dri1;
936 } drm_i915_private_t;
937
938 /* Iterate over initialised rings */
939 #define for_each_ring(ring__, dev_priv__, i__) \
940 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
941 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
942
943 enum hdmi_force_audio {
944 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
945 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
946 HDMI_AUDIO_AUTO, /* trust EDID */
947 HDMI_AUDIO_ON, /* force turn on HDMI audio */
948 };
949
950 enum i915_cache_level {
951 I915_CACHE_NONE = 0,
952 I915_CACHE_LLC,
953 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
954 };
955
956 struct drm_i915_gem_object_ops {
957 /* Interface between the GEM object and its backing storage.
958 * get_pages() is called once prior to the use of the associated set
959 * of pages before to binding them into the GTT, and put_pages() is
960 * called after we no longer need them. As we expect there to be
961 * associated cost with migrating pages between the backing storage
962 * and making them available for the GPU (e.g. clflush), we may hold
963 * onto the pages after they are no longer referenced by the GPU
964 * in case they may be used again shortly (for example migrating the
965 * pages to a different memory domain within the GTT). put_pages()
966 * will therefore most likely be called when the object itself is
967 * being released or under memory pressure (where we attempt to
968 * reap pages for the shrinker).
969 */
970 int (*get_pages)(struct drm_i915_gem_object *);
971 void (*put_pages)(struct drm_i915_gem_object *);
972 };
973
974 struct drm_i915_gem_object {
975 struct drm_gem_object base;
976
977 const struct drm_i915_gem_object_ops *ops;
978
979 /** Current space allocated to this object in the GTT, if any. */
980 struct drm_mm_node *gtt_space;
981 struct list_head gtt_list;
982
983 /** This object's place on the active/inactive lists */
984 struct list_head ring_list;
985 struct list_head mm_list;
986 /** This object's place in the batchbuffer or on the eviction list */
987 struct list_head exec_list;
988
989 /**
990 * This is set if the object is on the active lists (has pending
991 * rendering and so a non-zero seqno), and is not set if it i s on
992 * inactive (ready to be unbound) list.
993 */
994 unsigned int active:1;
995
996 /**
997 * This is set if the object has been written to since last bound
998 * to the GTT
999 */
1000 unsigned int dirty:1;
1001
1002 /**
1003 * Fence register bits (if any) for this object. Will be set
1004 * as needed when mapped into the GTT.
1005 * Protected by dev->struct_mutex.
1006 */
1007 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1008
1009 /**
1010 * Advice: are the backing pages purgeable?
1011 */
1012 unsigned int madv:2;
1013
1014 /**
1015 * Current tiling mode for the object.
1016 */
1017 unsigned int tiling_mode:2;
1018 /**
1019 * Whether the tiling parameters for the currently associated fence
1020 * register have changed. Note that for the purposes of tracking
1021 * tiling changes we also treat the unfenced register, the register
1022 * slot that the object occupies whilst it executes a fenced
1023 * command (such as BLT on gen2/3), as a "fence".
1024 */
1025 unsigned int fence_dirty:1;
1026
1027 /** How many users have pinned this object in GTT space. The following
1028 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1029 * (via user_pin_count), execbuffer (objects are not allowed multiple
1030 * times for the same batchbuffer), and the framebuffer code. When
1031 * switching/pageflipping, the framebuffer code has at most two buffers
1032 * pinned per crtc.
1033 *
1034 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1035 * bits with absolutely no headroom. So use 4 bits. */
1036 unsigned int pin_count:4;
1037 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1038
1039 /**
1040 * Is the object at the current location in the gtt mappable and
1041 * fenceable? Used to avoid costly recalculations.
1042 */
1043 unsigned int map_and_fenceable:1;
1044
1045 /**
1046 * Whether the current gtt mapping needs to be mappable (and isn't just
1047 * mappable by accident). Track pin and fault separate for a more
1048 * accurate mappable working set.
1049 */
1050 unsigned int fault_mappable:1;
1051 unsigned int pin_mappable:1;
1052 unsigned int pin_display:1;
1053
1054 /*
1055 * Is the GPU currently using a fence to access this buffer,
1056 */
1057 unsigned int pending_fenced_gpu_access:1;
1058 unsigned int fenced_gpu_access:1;
1059
1060 unsigned int cache_level:2;
1061
1062 unsigned int has_aliasing_ppgtt_mapping:1;
1063 unsigned int has_global_gtt_mapping:1;
1064 unsigned int has_dma_mapping:1;
1065
1066 vm_page_t *pages;
1067 int pages_pin_count;
1068
1069 /**
1070 * Used for performing relocations during execbuffer insertion.
1071 */
1072 struct hlist_node exec_node;
1073 unsigned long exec_handle;
1074 struct drm_i915_gem_exec_object2 *exec_entry;
1075
1076 /**
1077 * Current offset of the object in GTT space.
1078 *
1079 * This is the same as gtt_space->start
1080 */
1081 uint32_t gtt_offset;
1082
1083 struct intel_ring_buffer *ring;
1084
1085 /** Breadcrumb of last rendering to the buffer. */
1086 uint32_t last_read_seqno;
1087 uint32_t last_write_seqno;
1088 /** Breadcrumb of last fenced GPU access to the buffer. */
1089 uint32_t last_fenced_seqno;
1090
1091 /** Current tiling stride for the object, if it's tiled. */
1092 uint32_t stride;
1093
1094 /** Record of address bit 17 of each page at last unbind. */
1095 unsigned long *bit_17;
1096
1097 /** User space pin count and filp owning the pin */
1098 uint32_t user_pin_count;
1099 struct drm_file *pin_filp;
1100
1101 /** for phy allocated objects */
1102 struct drm_i915_gem_phys_object *phys_obj;
1103
1104 /**
1105 * Number of crtcs where this object is currently the fb, but
1106 * will be page flipped away on the next vblank. When it
1107 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1108 */
1109 atomic_t pending_flip;
1110 };
1111 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1112
1113 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1114
1115 /**
1116 * Request queue structure.
1117 *
1118 * The request queue allows us to note sequence numbers that have been emitted
1119 * and may be associated with active buffers to be retired.
1120 *
1121 * By keeping this list, we can avoid having to do questionable
1122 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1123 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1124 */
1125 struct drm_i915_gem_request {
1126 /** On Which ring this request was generated */
1127 struct intel_ring_buffer *ring;
1128
1129 /** GEM sequence number associated with this request. */
1130 uint32_t seqno;
1131
1132 /** Position in the ringbuffer of the end of the request */
1133 u32 tail;
1134
1135 /** Time at which this request was emitted, in jiffies. */
1136 unsigned long emitted_jiffies;
1137
1138 /** global list entry for this request */
1139 struct list_head list;
1140
1141 struct drm_i915_file_private *file_priv;
1142 /** file_priv list entry for this request */
1143 struct list_head client_list;
1144 };
1145
1146 struct drm_i915_file_private {
1147 struct {
1148 struct mtx lock;
1149 struct list_head request_list;
1150 } mm;
1151 struct drm_gem_names context_idr;
1152 };
1153
1154 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1155
1156 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1157 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1158 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1159 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1160 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1161 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1162 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1163 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1164 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1165 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1166 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1167 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1168 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1169 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1170 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1171 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1172 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1173 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1174 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1175 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1176 (dev)->pci_device == 0x0152 || \
1177 (dev)->pci_device == 0x015a)
1178 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1179 (dev)->pci_device == 0x0106 || \
1180 (dev)->pci_device == 0x010A)
1181 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1182 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1183 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1184 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1185 ((dev)->pci_device & 0xFF00) == 0x0A00)
1186
1187 /*
1188 * The genX designation typically refers to the render engine, so render
1189 * capability related checks should use IS_GEN, while display and other checks
1190 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1191 * chips, etc.).
1192 */
1193 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1194 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1195 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1196 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1197 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1198 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1199
1200 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1201 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1202 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1203 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1204
1205 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1206 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1207
1208 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1209 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1210
1211 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1212 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1213
1214 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1215 * rows, which changed the alignment requirements and fence programming.
1216 */
1217 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1218 IS_I915GM(dev)))
1219 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1220 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1221 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1222 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1223 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1224 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1225 /* dsparb controlled by hw only */
1226 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1227
1228 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1229 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1230 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1231
1232 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1233
1234 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1235 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1236 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1237 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1238 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1239 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1240
1241 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1242 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1243 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1244 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1245 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1246
1247 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1248
1249 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1250
1251 #define GT_FREQUENCY_MULTIPLIER 50
1252
1253 /**
1254 * RC6 is a special power stage which allows the GPU to enter an very
1255 * low-voltage mode when idle, using down to 0V while at this stage. This
1256 * stage is entered automatically when the GPU is idle when RC6 support is
1257 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1258 *
1259 * There are different RC6 modes available in Intel GPU, which differentiate
1260 * among each other with the latency required to enter and leave RC6 and
1261 * voltage consumed by the GPU in different states.
1262 *
1263 * The combination of the following flags define which states GPU is allowed
1264 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1265 * RC6pp is deepest RC6. Their support by hardware varies according to the
1266 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1267 * which brings the most power savings; deeper states save more power, but
1268 * require higher latency to switch to and wake up.
1269 */
1270 #define INTEL_RC6_ENABLE (1<<0)
1271 #define INTEL_RC6p_ENABLE (1<<1)
1272 #define INTEL_RC6pp_ENABLE (1<<2)
1273
1274 extern struct drm_ioctl_desc i915_ioctls[];
1275 extern int i915_max_ioctl;
1276 extern unsigned int i915_fbpercrtc __always_unused;
1277 extern int i915_panel_ignore_lid __read_mostly;
1278 extern unsigned int i915_powersave __read_mostly;
1279 extern int i915_semaphores __read_mostly;
1280 extern unsigned int i915_lvds_downclock __read_mostly;
1281 extern int i915_lvds_channel_mode __read_mostly;
1282 extern int i915_panel_use_ssc __read_mostly;
1283 extern int i915_vbt_sdvo_panel_type __read_mostly;
1284 extern int i915_enable_rc6 __read_mostly;
1285 extern int i915_enable_fbc __read_mostly;
1286 extern int i915_enable_hangcheck __read_mostly;
1287 extern int i915_enable_ppgtt __read_mostly;
1288 extern unsigned int i915_preliminary_hw_support __read_mostly;
1289
1290 extern struct drm_driver i915_driver_info;
1291 extern struct cdev_pager_ops i915_gem_pager_ops;
1292 extern int intel_iommu_gfx_mapped;
1293
1294 const struct intel_device_info *i915_get_device_id(int device);
1295
1296 /* i915_debug.c */
1297 int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx,
1298 struct sysctl_oid *top);
1299 void i915_sysctl_cleanup(struct drm_device *dev);
1300
1301 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1302 extern int i915_resume(struct drm_device *dev);
1303 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1304 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1305
1306 /* i915_dma.c */
1307 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1308 extern void i915_kernel_lost_context(struct drm_device * dev);
1309 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1310 extern int i915_driver_unload(struct drm_device *);
1311 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1312 extern void i915_driver_lastclose(struct drm_device * dev);
1313 extern void i915_driver_preclose(struct drm_device *dev,
1314 struct drm_file *file_priv);
1315 extern void i915_driver_postclose(struct drm_device *dev,
1316 struct drm_file *file_priv);
1317 extern int i915_driver_device_is_agp(struct drm_device * dev);
1318 #ifdef CONFIG_COMPAT
1319 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1320 unsigned long arg);
1321 #endif
1322 extern int i915_emit_box(struct drm_device *dev,
1323 struct drm_clip_rect *box,
1324 int DR1, int DR4);
1325 extern int intel_gpu_reset(struct drm_device *dev);
1326 extern int i915_reset(struct drm_device *dev);
1327 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1328 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1329 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1330 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1331
1332 extern int i915_batchbuffer(struct drm_device *dev, void *data,
1333 struct drm_file *file_priv);
1334 extern int i915_cmdbuffer(struct drm_device *dev, void *data,
1335 struct drm_file *file_priv);
1336 extern int i915_irq_emit(struct drm_device *dev, void *data,
1337 struct drm_file *file_priv);
1338 extern int i915_getparam(struct drm_device *dev, void *data,
1339 struct drm_file *file_priv);
1340
1341 extern void intel_console_resume(void *context, int pending);
1342
1343 /* i915_irq.c */
1344 void i915_hangcheck_elapsed(void *data);
1345 void i915_handle_error(struct drm_device *dev, bool wedged);
1346
1347 extern void intel_irq_init(struct drm_device *dev);
1348 extern void intel_gt_init(struct drm_device *dev);
1349 extern void intel_gt_reset(struct drm_device *dev);
1350
1351 void i915_error_state_free(struct drm_i915_error_state *error);
1352
1353 void
1354 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1355
1356 void
1357 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1358
1359 void intel_enable_asle(struct drm_device *dev);
1360
1361 //#ifdef CONFIG_DEBUG_FS
1362 extern void i915_destroy_error_state(struct drm_device *dev);
1363 //#else
1364 //#define i915_destroy_error_state(x)
1365 //#endif
1366
1367 /* i915_gem.c */
1368 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1369 struct drm_file *file_priv);
1370 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1371 struct drm_file *file_priv);
1372 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1373 struct drm_file *file_priv);
1374 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1375 struct drm_file *file_priv);
1376 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1377 struct drm_file *file_priv);
1378 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1379 struct drm_file *file_priv);
1380 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1381 struct drm_file *file_priv);
1382 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1383 struct drm_file *file_priv);
1384 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1385 struct drm_file *file_priv);
1386 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1387 struct drm_file *file_priv);
1388 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1389 struct drm_file *file_priv);
1390 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1391 struct drm_file *file_priv);
1392 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1393 struct drm_file *file_priv);
1394 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1395 struct drm_file *file);
1396 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1397 struct drm_file *file);
1398 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1399 struct drm_file *file_priv);
1400 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1401 struct drm_file *file_priv);
1402 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1403 struct drm_file *file_priv);
1404 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1405 struct drm_file *file_priv);
1406 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1407 struct drm_file *file_priv);
1408 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1409 struct drm_file *file_priv);
1410 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1411 struct drm_file *file_priv);
1412 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1413 struct drm_file *file_priv);
1414 void i915_gem_load(struct drm_device *dev);
1415 int i915_gem_init_object(struct drm_gem_object *obj);
1416 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1417 const struct drm_i915_gem_object_ops *ops);
1418 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1419 size_t size);
1420 void i915_gem_free_object(struct drm_gem_object *obj);
1421 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1422 uint32_t alignment,
1423 bool map_and_fenceable,
1424 bool nonblocking);
1425 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1426 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1427 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1428 void i915_gem_lastclose(struct drm_device *dev);
1429
1430 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1431 uint32_t i915_get_gem_seqno(struct drm_device *dev);
i915_gem_object_pin_pages(struct drm_i915_gem_object * obj)1432 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1433 {
1434 /* KASSERT(obj->pages != NULL, ("pin and NULL pages")); */
1435 obj->pages_pin_count++;
1436 }
1437
i915_gem_object_unpin_pages(struct drm_i915_gem_object * obj)1438 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1439 {
1440 KASSERT(obj->pages_pin_count != 0, ("zero pages_pin_count"));
1441 obj->pages_pin_count--;
1442 }
1443
1444 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1445 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1446 struct intel_ring_buffer *to);
1447 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1448 struct intel_ring_buffer *ring);
1449
1450 int i915_gem_dumb_create(struct drm_file *file_priv,
1451 struct drm_device *dev,
1452 struct drm_mode_create_dumb *args);
1453 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1454 uint32_t handle, uint64_t *offset);
1455 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1456 uint32_t handle);
1457 /**
1458 * Returns true if seq1 is later than seq2.
1459 */
1460 static inline bool
i915_seqno_passed(uint32_t seq1,uint32_t seq2)1461 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1462 {
1463 return (int32_t)(seq1 - seq2) >= 0;
1464 }
1465
1466 extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1467
1468 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1469 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1470
1471 static inline bool
i915_gem_object_pin_fence(struct drm_i915_gem_object * obj)1472 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1473 {
1474 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1475 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1476 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1477 return true;
1478 } else
1479 return false;
1480 }
1481
1482 static inline void
i915_gem_object_unpin_fence(struct drm_i915_gem_object * obj)1483 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1484 {
1485 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1486 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1487 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1488 }
1489 }
1490
1491 void i915_gem_retire_requests(struct drm_device *dev);
1492 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1493 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1494 bool interruptible);
1495
1496 void i915_gem_reset(struct drm_device *dev);
1497 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1498 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1499 uint32_t read_domains,
1500 uint32_t write_domain);
1501 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1502 int __must_check i915_gem_init(struct drm_device *dev);
1503 int __must_check i915_gem_init_hw(struct drm_device *dev);
1504 void i915_gem_l3_remap(struct drm_device *dev);
1505 void i915_gem_init_swizzling(struct drm_device *dev);
1506 void i915_gem_init_ppgtt(struct drm_device *dev);
1507 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1508 int __must_check i915_gpu_idle(struct drm_device *dev);
1509 int __must_check i915_gem_idle(struct drm_device *dev);
1510 int i915_add_request(struct intel_ring_buffer *ring,
1511 struct drm_file *file,
1512 u32 *seqno);
1513 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1514 uint32_t seqno);
1515 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot,
1516 uint64_t *phys);
1517 int __must_check
1518 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1519 bool write);
1520 int __must_check
1521 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1522 int __must_check
1523 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1524 u32 alignment,
1525 struct intel_ring_buffer *pipelined);
1526 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
1527 int i915_gem_attach_phys_object(struct drm_device *dev,
1528 struct drm_i915_gem_object *obj,
1529 int id,
1530 int align);
1531 void i915_gem_detach_phys_object(struct drm_device *dev,
1532 struct drm_i915_gem_object *obj);
1533 void i915_gem_free_all_phys_object(struct drm_device *dev);
1534 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1535
1536 uint32_t
1537 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1538 uint32_t size,
1539 int tiling_mode);
1540
1541 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1542 enum i915_cache_level cache_level);
1543
1544 #ifdef FREEBSD_WIP
1545 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1546 struct dma_buf *dma_buf);
1547
1548 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1549 struct drm_gem_object *gem_obj, int flags);
1550 #endif /* FREEBSD_WIP */
1551
1552 int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot);
1553
1554 /* i915_gem_context.c */
1555 void i915_gem_context_init(struct drm_device *dev);
1556 void i915_gem_context_fini(struct drm_device *dev);
1557 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1558 int i915_switch_context(struct intel_ring_buffer *ring,
1559 struct drm_file *file, int to_id);
1560 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1561 struct drm_file *file);
1562 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1563 struct drm_file *file);
1564
1565 /* i915_gem_gtt.c */
1566 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1567 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1568 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1569 struct drm_i915_gem_object *obj,
1570 enum i915_cache_level cache_level);
1571 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1572 struct drm_i915_gem_object *obj);
1573
1574 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1575 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1576 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1577 enum i915_cache_level cache_level);
1578 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1579 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1580 void i915_gem_init_global_gtt(struct drm_device *dev,
1581 unsigned long start,
1582 unsigned long mappable_end,
1583 unsigned long end);
1584 int i915_gem_gtt_init(struct drm_device *dev);
1585 void i915_gem_gtt_fini(struct drm_device *dev);
i915_gem_chipset_flush(struct drm_device * dev)1586 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1587 {
1588 if (INTEL_INFO(dev)->gen < 6)
1589 intel_gtt_chipset_flush();
1590 }
1591
1592 /* i915_gem_evict.c */
1593 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1594 unsigned alignment,
1595 unsigned cache_level,
1596 bool mappable,
1597 bool nonblock);
1598 int i915_gem_evict_everything(struct drm_device *dev);
1599
1600 /* i915_gem_stolen.c */
1601 int i915_gem_init_stolen(struct drm_device *dev);
1602 void i915_gem_cleanup_stolen(struct drm_device *dev);
1603
1604 /* i915_gem_tiling.c */
1605 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1606 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1607 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1608 void i915_gem_object_do_bit_17_swizzle_page(struct drm_i915_gem_object *obj,
1609 struct vm_page *m);
1610
1611 /* i915_gem_debug.c */
1612 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1613 const char *where, uint32_t mark);
1614 #if WATCH_LISTS
1615 int i915_verify_lists(struct drm_device *dev);
1616 #else
1617 #define i915_verify_lists(dev) 0
1618 #endif
1619 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1620 int handle);
1621
1622 /* i915_suspend.c */
1623 extern int i915_save_state(struct drm_device *dev);
1624 extern int i915_restore_state(struct drm_device *dev);
1625
1626 /* intel_i2c.c */
1627 extern int intel_setup_gmbus(struct drm_device *dev);
1628 extern void intel_teardown_gmbus(struct drm_device *dev);
intel_gmbus_is_port_valid(unsigned port)1629 static inline bool intel_gmbus_is_port_valid(unsigned port)
1630 {
1631 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1632 }
1633
1634 extern device_t intel_gmbus_get_adapter(
1635 struct drm_i915_private *dev_priv, unsigned port);
1636 extern void intel_gmbus_set_speed(device_t idev, int speed);
1637 extern void intel_gmbus_force_bit(device_t idev, bool force_bit);
1638 extern bool intel_gmbus_is_forced_bit(device_t adapter);
1639 extern void intel_i2c_reset(struct drm_device *dev);
1640
1641 /* intel_opregion.c */
1642 extern int intel_opregion_setup(struct drm_device *dev);
1643 #ifdef CONFIG_ACPI
1644 extern void intel_opregion_init(struct drm_device *dev);
1645 extern void intel_opregion_fini(struct drm_device *dev);
1646 extern void intel_opregion_asle_intr(struct drm_device *dev);
1647 extern void intel_opregion_gse_intr(struct drm_device *dev);
1648 extern void intel_opregion_enable_asle(struct drm_device *dev);
1649 #else
intel_opregion_init(struct drm_device * dev)1650 static inline void intel_opregion_init(struct drm_device *dev) { return; }
intel_opregion_fini(struct drm_device * dev)1651 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
intel_opregion_asle_intr(struct drm_device * dev)1652 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
intel_opregion_gse_intr(struct drm_device * dev)1653 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
intel_opregion_enable_asle(struct drm_device * dev)1654 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1655 #endif
1656
1657 /* intel_acpi.c */
1658 #ifdef CONFIG_ACPI
1659 extern void intel_register_dsm_handler(void);
1660 extern void intel_unregister_dsm_handler(void);
1661 #else
intel_register_dsm_handler(void)1662 static inline void intel_register_dsm_handler(void) { return; }
intel_unregister_dsm_handler(void)1663 static inline void intel_unregister_dsm_handler(void) { return; }
1664 #endif /* CONFIG_ACPI */
1665
1666 /* modesetting */
1667 extern void intel_modeset_init_hw(struct drm_device *dev);
1668 extern void intel_modeset_init(struct drm_device *dev);
1669 extern void intel_modeset_gem_init(struct drm_device *dev);
1670 extern void intel_modeset_cleanup(struct drm_device *dev);
1671 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1672 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1673 bool force_restore);
1674 extern void intel_disable_fbc(struct drm_device *dev);
1675 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1676 extern void intel_init_pch_refclk(struct drm_device *dev);
1677 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1678 extern void intel_detect_pch(struct drm_device *dev);
1679 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1680 extern int intel_enable_rc6(const struct drm_device *dev);
1681
1682 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1683 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1684 struct drm_file *file);
1685
1686 /* overlay */
1687 //#ifdef CONFIG_DEBUG_FS
1688 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1689 extern void intel_overlay_print_error_state(struct sbuf *m, struct intel_overlay_error_state *error);
1690
1691 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1692 extern void intel_display_print_error_state(struct sbuf *m,
1693 struct drm_device *dev,
1694 struct intel_display_error_state *error);
1695 //#endif
1696
1697 static inline void
trace_i915_reg_rw(boolean_t rw,int reg,uint64_t val,int sz)1698 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz)
1699 {
1700
1701 CTR4(KTR_DRM_REG, "[%x/%d] %c %x", reg, sz, rw ? "w" : "r", val);
1702 }
1703
1704 /* On SNB platform, before reading ring registers forcewake bit
1705 * must be set to prevent GT core from power down and stale values being
1706 * returned.
1707 */
1708 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1709 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1710 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1711
1712 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1713 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1714
1715 #define __i915_read(x, y) \
1716 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1717
1718 __i915_read(8, 8)
1719 __i915_read(16, 16)
1720 __i915_read(32, 32)
1721 __i915_read(64, 64)
1722 #undef __i915_read
1723
1724 #define __i915_write(x, y) \
1725 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1726
1727 __i915_write(8, 8)
1728 __i915_write(16, 16)
1729 __i915_write(32, 32)
1730 __i915_write(64, 64)
1731 #undef __i915_write
1732
1733 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1734 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1735
1736 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1737 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1738 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg))
1739 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
1740
1741 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1742 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1743 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg))
1744 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
1745
1746 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1747 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1748
1749 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1750 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1751
1752 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1753
1754 #endif
1755