1 /*-
2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #include "en.h"
29
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
32
33 #ifndef ETH_DRIVER_VERSION
34 #define ETH_DRIVER_VERSION "3.6.0"
35 #endif
36 #define DRIVER_RELDATE "December 2020"
37
38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
39 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
40
41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
42
43 struct mlx5e_channel_param {
44 struct mlx5e_rq_param rq;
45 struct mlx5e_sq_param sq;
46 struct mlx5e_cq_param rx_cq;
47 struct mlx5e_cq_param tx_cq;
48 };
49
50 struct media {
51 u32 subtype;
52 u64 baudrate;
53 };
54
55 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
56
57 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
58 .subtype = IFM_1000_CX_SGMII,
59 .baudrate = IF_Mbps(1000ULL),
60 },
61 [MLX5E_1000BASE_KX][MLX5E_KX] = {
62 .subtype = IFM_1000_KX,
63 .baudrate = IF_Mbps(1000ULL),
64 },
65 [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
66 .subtype = IFM_10G_CX4,
67 .baudrate = IF_Gbps(10ULL),
68 },
69 [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
70 .subtype = IFM_10G_KX4,
71 .baudrate = IF_Gbps(10ULL),
72 },
73 [MLX5E_10GBASE_KR][MLX5E_KR] = {
74 .subtype = IFM_10G_KR,
75 .baudrate = IF_Gbps(10ULL),
76 },
77 [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
78 .subtype = IFM_20G_KR2,
79 .baudrate = IF_Gbps(20ULL),
80 },
81 [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
82 .subtype = IFM_40G_CR4,
83 .baudrate = IF_Gbps(40ULL),
84 },
85 [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
86 .subtype = IFM_40G_KR4,
87 .baudrate = IF_Gbps(40ULL),
88 },
89 [MLX5E_56GBASE_R4][MLX5E_R] = {
90 .subtype = IFM_56G_R4,
91 .baudrate = IF_Gbps(56ULL),
92 },
93 [MLX5E_10GBASE_CR][MLX5E_CR1] = {
94 .subtype = IFM_10G_CR1,
95 .baudrate = IF_Gbps(10ULL),
96 },
97 [MLX5E_10GBASE_SR][MLX5E_SR] = {
98 .subtype = IFM_10G_SR,
99 .baudrate = IF_Gbps(10ULL),
100 },
101 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
102 .subtype = IFM_10G_ER,
103 .baudrate = IF_Gbps(10ULL),
104 },
105 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
106 .subtype = IFM_10G_LR,
107 .baudrate = IF_Gbps(10ULL),
108 },
109 [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
110 .subtype = IFM_40G_SR4,
111 .baudrate = IF_Gbps(40ULL),
112 },
113 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
114 .subtype = IFM_40G_LR4,
115 .baudrate = IF_Gbps(40ULL),
116 },
117 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
118 .subtype = IFM_40G_ER4,
119 .baudrate = IF_Gbps(40ULL),
120 },
121 [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
122 .subtype = IFM_100G_CR4,
123 .baudrate = IF_Gbps(100ULL),
124 },
125 [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
126 .subtype = IFM_100G_SR4,
127 .baudrate = IF_Gbps(100ULL),
128 },
129 [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
130 .subtype = IFM_100G_KR4,
131 .baudrate = IF_Gbps(100ULL),
132 },
133 [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
134 .subtype = IFM_100G_LR4,
135 .baudrate = IF_Gbps(100ULL),
136 },
137 [MLX5E_100BASE_TX][MLX5E_TX] = {
138 .subtype = IFM_100_TX,
139 .baudrate = IF_Mbps(100ULL),
140 },
141 [MLX5E_1000BASE_T][MLX5E_T] = {
142 .subtype = IFM_1000_T,
143 .baudrate = IF_Mbps(1000ULL),
144 },
145 [MLX5E_10GBASE_T][MLX5E_T] = {
146 .subtype = IFM_10G_T,
147 .baudrate = IF_Gbps(10ULL),
148 },
149 [MLX5E_25GBASE_CR][MLX5E_CR] = {
150 .subtype = IFM_25G_CR,
151 .baudrate = IF_Gbps(25ULL),
152 },
153 [MLX5E_25GBASE_KR][MLX5E_KR] = {
154 .subtype = IFM_25G_KR,
155 .baudrate = IF_Gbps(25ULL),
156 },
157 [MLX5E_25GBASE_SR][MLX5E_SR] = {
158 .subtype = IFM_25G_SR,
159 .baudrate = IF_Gbps(25ULL),
160 },
161 [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
162 .subtype = IFM_50G_CR2,
163 .baudrate = IF_Gbps(50ULL),
164 },
165 [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
166 .subtype = IFM_50G_KR2,
167 .baudrate = IF_Gbps(50ULL),
168 },
169 };
170
171 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
172 [MLX5E_SGMII_100M][MLX5E_SGMII] = {
173 .subtype = IFM_100_SGMII,
174 .baudrate = IF_Mbps(100),
175 },
176 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
177 .subtype = IFM_1000_KX,
178 .baudrate = IF_Mbps(1000),
179 },
180 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
181 .subtype = IFM_1000_CX_SGMII,
182 .baudrate = IF_Mbps(1000),
183 },
184 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
185 .subtype = IFM_1000_CX,
186 .baudrate = IF_Mbps(1000),
187 },
188 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
189 .subtype = IFM_1000_LX,
190 .baudrate = IF_Mbps(1000),
191 },
192 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
193 .subtype = IFM_1000_SX,
194 .baudrate = IF_Mbps(1000),
195 },
196 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
197 .subtype = IFM_1000_T,
198 .baudrate = IF_Mbps(1000),
199 },
200 [MLX5E_5GBASE_R][MLX5E_T] = {
201 .subtype = IFM_5000_T,
202 .baudrate = IF_Mbps(5000),
203 },
204 [MLX5E_5GBASE_R][MLX5E_KR] = {
205 .subtype = IFM_5000_KR,
206 .baudrate = IF_Mbps(5000),
207 },
208 [MLX5E_5GBASE_R][MLX5E_KR1] = {
209 .subtype = IFM_5000_KR1,
210 .baudrate = IF_Mbps(5000),
211 },
212 [MLX5E_5GBASE_R][MLX5E_KR_S] = {
213 .subtype = IFM_5000_KR_S,
214 .baudrate = IF_Mbps(5000),
215 },
216 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
217 .subtype = IFM_10G_ER,
218 .baudrate = IF_Gbps(10ULL),
219 },
220 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
221 .subtype = IFM_10G_KR,
222 .baudrate = IF_Gbps(10ULL),
223 },
224 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
225 .subtype = IFM_10G_LR,
226 .baudrate = IF_Gbps(10ULL),
227 },
228 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
229 .subtype = IFM_10G_SR,
230 .baudrate = IF_Gbps(10ULL),
231 },
232 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
233 .subtype = IFM_10G_T,
234 .baudrate = IF_Gbps(10ULL),
235 },
236 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
237 .subtype = IFM_10G_AOC,
238 .baudrate = IF_Gbps(10ULL),
239 },
240 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
241 .subtype = IFM_10G_CR1,
242 .baudrate = IF_Gbps(10ULL),
243 },
244 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
245 .subtype = IFM_40G_CR4,
246 .baudrate = IF_Gbps(40ULL),
247 },
248 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
249 .subtype = IFM_40G_KR4,
250 .baudrate = IF_Gbps(40ULL),
251 },
252 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
253 .subtype = IFM_40G_LR4,
254 .baudrate = IF_Gbps(40ULL),
255 },
256 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
257 .subtype = IFM_40G_SR4,
258 .baudrate = IF_Gbps(40ULL),
259 },
260 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
261 .subtype = IFM_40G_ER4,
262 .baudrate = IF_Gbps(40ULL),
263 },
264
265 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
266 .subtype = IFM_25G_CR,
267 .baudrate = IF_Gbps(25ULL),
268 },
269 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
270 .subtype = IFM_25G_KR,
271 .baudrate = IF_Gbps(25ULL),
272 },
273 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
274 .subtype = IFM_25G_SR,
275 .baudrate = IF_Gbps(25ULL),
276 },
277 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
278 .subtype = IFM_25G_ACC,
279 .baudrate = IF_Gbps(25ULL),
280 },
281 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
282 .subtype = IFM_25G_AOC,
283 .baudrate = IF_Gbps(25ULL),
284 },
285 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
286 .subtype = IFM_25G_CR1,
287 .baudrate = IF_Gbps(25ULL),
288 },
289 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
290 .subtype = IFM_25G_CR_S,
291 .baudrate = IF_Gbps(25ULL),
292 },
293 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
294 .subtype = IFM_5000_KR1,
295 .baudrate = IF_Gbps(25ULL),
296 },
297 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
298 .subtype = IFM_25G_KR_S,
299 .baudrate = IF_Gbps(25ULL),
300 },
301 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
302 .subtype = IFM_25G_LR,
303 .baudrate = IF_Gbps(25ULL),
304 },
305 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
306 .subtype = IFM_25G_T,
307 .baudrate = IF_Gbps(25ULL),
308 },
309 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
310 .subtype = IFM_50G_CR2,
311 .baudrate = IF_Gbps(50ULL),
312 },
313 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
314 .subtype = IFM_50G_KR2,
315 .baudrate = IF_Gbps(50ULL),
316 },
317 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
318 .subtype = IFM_50G_SR2,
319 .baudrate = IF_Gbps(50ULL),
320 },
321 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
322 .subtype = IFM_50G_LR2,
323 .baudrate = IF_Gbps(50ULL),
324 },
325 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
326 .subtype = IFM_50G_LR,
327 .baudrate = IF_Gbps(50ULL),
328 },
329 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
330 .subtype = IFM_50G_SR,
331 .baudrate = IF_Gbps(50ULL),
332 },
333 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
334 .subtype = IFM_50G_CP,
335 .baudrate = IF_Gbps(50ULL),
336 },
337 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
338 .subtype = IFM_50G_FR,
339 .baudrate = IF_Gbps(50ULL),
340 },
341 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
342 .subtype = IFM_50G_KR_PAM4,
343 .baudrate = IF_Gbps(50ULL),
344 },
345 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
346 .subtype = IFM_100G_CR4,
347 .baudrate = IF_Gbps(100ULL),
348 },
349 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
350 .subtype = IFM_100G_KR4,
351 .baudrate = IF_Gbps(100ULL),
352 },
353 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
354 .subtype = IFM_100G_LR4,
355 .baudrate = IF_Gbps(100ULL),
356 },
357 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
358 .subtype = IFM_100G_SR4,
359 .baudrate = IF_Gbps(100ULL),
360 },
361 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
362 .subtype = IFM_100G_SR2,
363 .baudrate = IF_Gbps(100ULL),
364 },
365 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
366 .subtype = IFM_100G_CP2,
367 .baudrate = IF_Gbps(100ULL),
368 },
369 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
370 .subtype = IFM_100G_KR2_PAM4,
371 .baudrate = IF_Gbps(100ULL),
372 },
373 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
374 .subtype = IFM_200G_DR4,
375 .baudrate = IF_Gbps(200ULL),
376 },
377 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
378 .subtype = IFM_200G_LR4,
379 .baudrate = IF_Gbps(200ULL),
380 },
381 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
382 .subtype = IFM_200G_SR4,
383 .baudrate = IF_Gbps(200ULL),
384 },
385 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
386 .subtype = IFM_200G_FR4,
387 .baudrate = IF_Gbps(200ULL),
388 },
389 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
390 .subtype = IFM_200G_CR4_PAM4,
391 .baudrate = IF_Gbps(200ULL),
392 },
393 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
394 .subtype = IFM_200G_KR4_PAM4,
395 .baudrate = IF_Gbps(200ULL),
396 },
397 };
398
399 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
400
401 static void
mlx5e_update_carrier(struct mlx5e_priv * priv)402 mlx5e_update_carrier(struct mlx5e_priv *priv)
403 {
404 struct mlx5_core_dev *mdev = priv->mdev;
405 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
406 u32 eth_proto_oper;
407 int error;
408 u8 port_state;
409 u8 is_er_type;
410 u8 i, j;
411 bool ext;
412 struct media media_entry = {};
413
414 port_state = mlx5_query_vport_state(mdev,
415 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
416
417 if (port_state == VPORT_STATE_UP) {
418 priv->media_status_last |= IFM_ACTIVE;
419 } else {
420 priv->media_status_last &= ~IFM_ACTIVE;
421 priv->media_active_last = IFM_ETHER;
422 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
423 return;
424 }
425
426 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
427 MLX5_PTYS_EN, 1);
428 if (error) {
429 priv->media_active_last = IFM_ETHER;
430 priv->ifp->if_baudrate = 1;
431 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
432 error);
433 return;
434 }
435
436 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
437 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
438 eth_proto_oper);
439
440 i = ilog2(eth_proto_oper);
441
442 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
443 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
444 mlx5e_mode_table[i][j];
445 if (media_entry.baudrate != 0)
446 break;
447 }
448
449 if (media_entry.subtype == 0) {
450 mlx5_en_err(priv->ifp,
451 "Could not find operational media subtype\n");
452 return;
453 }
454
455 switch (media_entry.subtype) {
456 case IFM_10G_ER:
457 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
458 if (error != 0) {
459 mlx5_en_err(priv->ifp,
460 "query port pddr failed: %d\n", error);
461 }
462 if (error != 0 || is_er_type == 0)
463 media_entry.subtype = IFM_10G_LR;
464 break;
465 case IFM_40G_LR4:
466 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
467 if (error != 0) {
468 mlx5_en_err(priv->ifp,
469 "query port pddr failed: %d\n", error);
470 }
471 if (error == 0 && is_er_type != 0)
472 media_entry.subtype = IFM_40G_ER4;
473 break;
474 }
475 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
476 priv->ifp->if_baudrate = media_entry.baudrate;
477
478 if_link_state_change(priv->ifp, LINK_STATE_UP);
479 }
480
481 static void
mlx5e_media_status(struct ifnet * dev,struct ifmediareq * ifmr)482 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
483 {
484 struct mlx5e_priv *priv = dev->if_softc;
485
486 ifmr->ifm_status = priv->media_status_last;
487 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last |
488 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
489 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
490
491 }
492
493 static u32
mlx5e_find_link_mode(u32 subtype,bool ext)494 mlx5e_find_link_mode(u32 subtype, bool ext)
495 {
496 u32 i;
497 u32 j;
498 u32 link_mode = 0;
499 u32 speeds_num = 0;
500 struct media media_entry = {};
501
502 switch (subtype) {
503 case IFM_10G_LR:
504 subtype = IFM_10G_ER;
505 break;
506 case IFM_40G_ER4:
507 subtype = IFM_40G_LR4;
508 break;
509 }
510
511 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
512 MLX5E_LINK_SPEEDS_NUMBER;
513
514 for (i = 0; i != speeds_num; i++) {
515 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
516 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
517 mlx5e_mode_table[i][j];
518 if (media_entry.baudrate == 0)
519 continue;
520 if (media_entry.subtype == subtype) {
521 link_mode |= MLX5E_PROT_MASK(i);
522 }
523 }
524 }
525
526 return (link_mode);
527 }
528
529 static int
mlx5e_set_port_pause_and_pfc(struct mlx5e_priv * priv)530 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
531 {
532 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
533 priv->params.rx_pauseframe_control,
534 priv->params.tx_pauseframe_control,
535 priv->params.rx_priority_flow_control,
536 priv->params.tx_priority_flow_control));
537 }
538
539 static int
mlx5e_set_port_pfc(struct mlx5e_priv * priv)540 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
541 {
542 int error;
543
544 if (priv->gone != 0) {
545 error = -ENXIO;
546 } else if (priv->params.rx_pauseframe_control ||
547 priv->params.tx_pauseframe_control) {
548 mlx5_en_err(priv->ifp,
549 "Global pauseframes must be disabled before enabling PFC.\n");
550 error = -EINVAL;
551 } else {
552 error = mlx5e_set_port_pause_and_pfc(priv);
553 }
554 return (error);
555 }
556
557 static int
mlx5e_media_change(struct ifnet * dev)558 mlx5e_media_change(struct ifnet *dev)
559 {
560 struct mlx5e_priv *priv = dev->if_softc;
561 struct mlx5_core_dev *mdev = priv->mdev;
562 u32 eth_proto_cap;
563 u32 link_mode;
564 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
565 int was_opened;
566 int locked;
567 int error;
568 bool ext;
569
570 locked = PRIV_LOCKED(priv);
571 if (!locked)
572 PRIV_LOCK(priv);
573
574 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
575 error = EINVAL;
576 goto done;
577 }
578
579 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
580 MLX5_PTYS_EN, 1);
581 if (error != 0) {
582 mlx5_en_err(dev, "Query port media capability failed\n");
583 goto done;
584 }
585
586 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
587 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
588
589 /* query supported capabilities */
590 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
591 eth_proto_capability);
592
593 /* check for autoselect */
594 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
595 link_mode = eth_proto_cap;
596 if (link_mode == 0) {
597 mlx5_en_err(dev, "Port media capability is zero\n");
598 error = EINVAL;
599 goto done;
600 }
601 } else {
602 link_mode = link_mode & eth_proto_cap;
603 if (link_mode == 0) {
604 mlx5_en_err(dev, "Not supported link mode requested\n");
605 error = EINVAL;
606 goto done;
607 }
608 }
609 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
610 /* check if PFC is enabled */
611 if (priv->params.rx_priority_flow_control ||
612 priv->params.tx_priority_flow_control) {
613 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
614 error = EINVAL;
615 goto done;
616 }
617 }
618 /* update pauseframe control bits */
619 priv->params.rx_pauseframe_control =
620 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
621 priv->params.tx_pauseframe_control =
622 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
623
624 /* check if device is opened */
625 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
626
627 /* reconfigure the hardware */
628 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
629 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
630 error = -mlx5e_set_port_pause_and_pfc(priv);
631 if (was_opened)
632 mlx5_set_port_status(mdev, MLX5_PORT_UP);
633
634 done:
635 if (!locked)
636 PRIV_UNLOCK(priv);
637 return (error);
638 }
639
640 static void
mlx5e_update_carrier_work(struct work_struct * work)641 mlx5e_update_carrier_work(struct work_struct *work)
642 {
643 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
644 update_carrier_work);
645
646 PRIV_LOCK(priv);
647 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
648 mlx5e_update_carrier(priv);
649 PRIV_UNLOCK(priv);
650 }
651
652 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \
653 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
654
655 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \
656 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
657
658 static void
mlx5e_update_pcie_counters(struct mlx5e_priv * priv)659 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
660 {
661 struct mlx5_core_dev *mdev = priv->mdev;
662 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
663 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
664 void *out;
665 void *in;
666 int err;
667
668 /* allocate firmware request structures */
669 in = mlx5_vzalloc(sz);
670 out = mlx5_vzalloc(sz);
671 if (in == NULL || out == NULL)
672 goto free_out;
673
674 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
675 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
676 if (err != 0)
677 goto free_out;
678
679 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
680 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
681
682 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
683 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
684 if (err != 0)
685 goto free_out;
686
687 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
688
689 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
690 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
691 if (err != 0)
692 goto free_out;
693
694 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
695
696 free_out:
697 /* free firmware request structures */
698 kvfree(in);
699 kvfree(out);
700 }
701
702 /*
703 * This function reads the physical port counters from the firmware
704 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
705 * macros. The output is converted from big-endian 64-bit values into
706 * host endian ones and stored in the "priv->stats.pport" structure.
707 */
708 static void
mlx5e_update_pport_counters(struct mlx5e_priv * priv)709 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
710 {
711 struct mlx5_core_dev *mdev = priv->mdev;
712 struct mlx5e_pport_stats *s = &priv->stats.pport;
713 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
714 u32 *in;
715 u32 *out;
716 const u64 *ptr;
717 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
718 unsigned x;
719 unsigned y;
720 unsigned z;
721
722 /* allocate firmware request structures */
723 in = mlx5_vzalloc(sz);
724 out = mlx5_vzalloc(sz);
725 if (in == NULL || out == NULL)
726 goto free_out;
727
728 /*
729 * Get pointer to the 64-bit counter set which is located at a
730 * fixed offset in the output firmware request structure:
731 */
732 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
733
734 MLX5_SET(ppcnt_reg, in, local_port, 1);
735
736 /* read IEEE802_3 counter group using predefined counter layout */
737 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
738 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
739 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
740 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
741 s->arg[y] = be64toh(ptr[x]);
742
743 /* read RFC2819 counter group using predefined counter layout */
744 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
745 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
746 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
747 s->arg[y] = be64toh(ptr[x]);
748
749 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
750 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
751 s_debug->arg[y] = be64toh(ptr[x]);
752
753 /* read RFC2863 counter group using predefined counter layout */
754 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
755 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
756 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
757 s_debug->arg[y] = be64toh(ptr[x]);
758
759 /* read physical layer stats counter group using predefined counter layout */
760 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
761 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
762 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
763 s_debug->arg[y] = be64toh(ptr[x]);
764
765 /* read Extended Ethernet counter group using predefined counter layout */
766 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
767 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
768 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
769 s_debug->arg[y] = be64toh(ptr[x]);
770
771 /* read Extended Statistical Group */
772 if (MLX5_CAP_GEN(mdev, pcam_reg) &&
773 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
774 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
775 /* read Extended Statistical counter group using predefined counter layout */
776 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
777 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
778
779 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
780 s_debug->arg[y] = be64toh(ptr[x]);
781 }
782
783 /* read PCIE counters */
784 mlx5e_update_pcie_counters(priv);
785
786 /* read per-priority counters */
787 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
788
789 /* iterate all the priorities */
790 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
791 MLX5_SET(ppcnt_reg, in, prio_tc, z);
792 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
793
794 /* read per priority stats counter group using predefined counter layout */
795 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
796 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
797 s->arg[y] = be64toh(ptr[x]);
798 }
799
800 free_out:
801 /* free firmware request structures */
802 kvfree(in);
803 kvfree(out);
804 }
805
806 static void
mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv * priv)807 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
808 {
809 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
810 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
811
812 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
813 return;
814
815 MLX5_SET(query_vnic_env_in, in, opcode,
816 MLX5_CMD_OP_QUERY_VNIC_ENV);
817 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
818 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
819
820 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
821 return;
822
823 priv->stats.vport.rx_steer_missed_packets =
824 MLX5_GET64(query_vnic_env_out, out,
825 vport_env.nic_receive_steering_discard);
826 }
827
828 /*
829 * This function is called regularly to collect all statistics
830 * counters from the firmware. The values can be viewed through the
831 * sysctl interface. Execution is serialized using the priv's global
832 * configuration lock.
833 */
834 static void
mlx5e_update_stats_locked(struct mlx5e_priv * priv)835 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
836 {
837 struct mlx5_core_dev *mdev = priv->mdev;
838 struct mlx5e_vport_stats *s = &priv->stats.vport;
839 struct mlx5e_sq_stats *sq_stats;
840 #if (__FreeBSD_version < 1100000)
841 struct ifnet *ifp = priv->ifp;
842 #endif
843
844 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
845 u32 *out;
846 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
847 u64 tso_packets = 0;
848 u64 tso_bytes = 0;
849 u64 tx_queue_dropped = 0;
850 u64 tx_defragged = 0;
851 u64 tx_offload_none = 0;
852 u64 lro_packets = 0;
853 u64 lro_bytes = 0;
854 u64 sw_lro_queued = 0;
855 u64 sw_lro_flushed = 0;
856 u64 rx_csum_none = 0;
857 u64 rx_wqe_err = 0;
858 u64 rx_packets = 0;
859 u64 rx_bytes = 0;
860 u32 rx_out_of_buffer = 0;
861 int error;
862 int i;
863 int j;
864
865 out = mlx5_vzalloc(outlen);
866 if (out == NULL)
867 goto free_out;
868
869 /* Collect firts the SW counters and then HW for consistency */
870 for (i = 0; i < priv->params.num_channels; i++) {
871 struct mlx5e_channel *pch = priv->channel + i;
872 struct mlx5e_rq *rq = &pch->rq;
873 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
874
875 /* collect stats from LRO */
876 rq_stats->sw_lro_queued = rq->lro.lro_queued;
877 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
878 sw_lro_queued += rq_stats->sw_lro_queued;
879 sw_lro_flushed += rq_stats->sw_lro_flushed;
880 lro_packets += rq_stats->lro_packets;
881 lro_bytes += rq_stats->lro_bytes;
882 rx_csum_none += rq_stats->csum_none;
883 rx_wqe_err += rq_stats->wqe_err;
884 rx_packets += rq_stats->packets;
885 rx_bytes += rq_stats->bytes;
886
887 for (j = 0; j < priv->num_tc; j++) {
888 sq_stats = &pch->sq[j].stats;
889
890 tso_packets += sq_stats->tso_packets;
891 tso_bytes += sq_stats->tso_bytes;
892 tx_queue_dropped += sq_stats->dropped;
893 tx_queue_dropped += sq_stats->enobuf;
894 tx_defragged += sq_stats->defragged;
895 tx_offload_none += sq_stats->csum_offload_none;
896 }
897 }
898
899 /* update counters */
900 s->tso_packets = tso_packets;
901 s->tso_bytes = tso_bytes;
902 s->tx_queue_dropped = tx_queue_dropped;
903 s->tx_defragged = tx_defragged;
904 s->lro_packets = lro_packets;
905 s->lro_bytes = lro_bytes;
906 s->sw_lro_queued = sw_lro_queued;
907 s->sw_lro_flushed = sw_lro_flushed;
908 s->rx_csum_none = rx_csum_none;
909 s->rx_wqe_err = rx_wqe_err;
910 s->rx_packets = rx_packets;
911 s->rx_bytes = rx_bytes;
912
913 mlx5e_grp_vnic_env_update_stats(priv);
914
915 /* HW counters */
916 memset(in, 0, sizeof(in));
917
918 MLX5_SET(query_vport_counter_in, in, opcode,
919 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
920 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
921 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
922
923 memset(out, 0, outlen);
924
925 /* get number of out-of-buffer drops first */
926 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
927 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
928 &rx_out_of_buffer) == 0) {
929 s->rx_out_of_buffer = rx_out_of_buffer;
930 }
931
932 /* get port statistics */
933 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
934 #define MLX5_GET_CTR(out, x) \
935 MLX5_GET64(query_vport_counter_out, out, x)
936
937 s->rx_error_packets =
938 MLX5_GET_CTR(out, received_errors.packets);
939 s->rx_error_bytes =
940 MLX5_GET_CTR(out, received_errors.octets);
941 s->tx_error_packets =
942 MLX5_GET_CTR(out, transmit_errors.packets);
943 s->tx_error_bytes =
944 MLX5_GET_CTR(out, transmit_errors.octets);
945
946 s->rx_unicast_packets =
947 MLX5_GET_CTR(out, received_eth_unicast.packets);
948 s->rx_unicast_bytes =
949 MLX5_GET_CTR(out, received_eth_unicast.octets);
950 s->tx_unicast_packets =
951 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
952 s->tx_unicast_bytes =
953 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
954
955 s->rx_multicast_packets =
956 MLX5_GET_CTR(out, received_eth_multicast.packets);
957 s->rx_multicast_bytes =
958 MLX5_GET_CTR(out, received_eth_multicast.octets);
959 s->tx_multicast_packets =
960 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
961 s->tx_multicast_bytes =
962 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
963
964 s->rx_broadcast_packets =
965 MLX5_GET_CTR(out, received_eth_broadcast.packets);
966 s->rx_broadcast_bytes =
967 MLX5_GET_CTR(out, received_eth_broadcast.octets);
968 s->tx_broadcast_packets =
969 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
970 s->tx_broadcast_bytes =
971 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
972
973 s->tx_packets = s->tx_unicast_packets +
974 s->tx_multicast_packets + s->tx_broadcast_packets;
975 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
976 s->tx_broadcast_bytes;
977
978 /* Update calculated offload counters */
979 s->tx_csum_offload = s->tx_packets - tx_offload_none;
980 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
981 }
982
983 /* Get physical port counters */
984 mlx5e_update_pport_counters(priv);
985
986 s->tx_jumbo_packets =
987 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
988 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
989 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
990 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
991
992 #if (__FreeBSD_version < 1100000)
993 /* no get_counters interface in fbsd 10 */
994 ifp->if_ipackets = s->rx_packets;
995 ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
996 priv->stats.pport.out_of_range_len +
997 priv->stats.pport.too_long_errors +
998 priv->stats.pport.check_seq_err +
999 priv->stats.pport.alignment_err;
1000 ifp->if_iqdrops = s->rx_out_of_buffer;
1001 ifp->if_opackets = s->tx_packets;
1002 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1003 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1004 ifp->if_ibytes = s->rx_bytes;
1005 ifp->if_obytes = s->tx_bytes;
1006 ifp->if_collisions =
1007 priv->stats.pport.collisions;
1008 #endif
1009
1010 free_out:
1011 kvfree(out);
1012
1013 /* Update diagnostics, if any */
1014 if (priv->params_ethtool.diag_pci_enable ||
1015 priv->params_ethtool.diag_general_enable) {
1016 error = mlx5_core_get_diagnostics_full(mdev,
1017 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1018 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1019 if (error != 0)
1020 mlx5_en_err(priv->ifp,
1021 "Failed reading diagnostics: %d\n", error);
1022 }
1023
1024 /* Update FEC, if any */
1025 error = mlx5e_fec_update(priv);
1026 if (error != 0 && error != EOPNOTSUPP) {
1027 mlx5_en_err(priv->ifp,
1028 "Updating FEC failed: %d\n", error);
1029 }
1030
1031 /* Update temperature, if any */
1032 if (priv->params_ethtool.hw_num_temp != 0) {
1033 error = mlx5e_hw_temperature_update(priv);
1034 if (error != 0 && error != EOPNOTSUPP) {
1035 mlx5_en_err(priv->ifp,
1036 "Updating temperature failed: %d\n", error);
1037 }
1038 }
1039 }
1040
1041 static void
mlx5e_update_stats_work(struct work_struct * work)1042 mlx5e_update_stats_work(struct work_struct *work)
1043 {
1044 struct mlx5e_priv *priv;
1045
1046 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1047 PRIV_LOCK(priv);
1048 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1049 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1050 mlx5e_update_stats_locked(priv);
1051 PRIV_UNLOCK(priv);
1052 }
1053
1054 static void
mlx5e_update_stats(void * arg)1055 mlx5e_update_stats(void *arg)
1056 {
1057 struct mlx5e_priv *priv = arg;
1058
1059 queue_work(priv->wq, &priv->update_stats_work);
1060
1061 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv);
1062 }
1063
1064 static void
mlx5e_async_event_sub(struct mlx5e_priv * priv,enum mlx5_dev_event event)1065 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1066 enum mlx5_dev_event event)
1067 {
1068 switch (event) {
1069 case MLX5_DEV_EVENT_PORT_UP:
1070 case MLX5_DEV_EVENT_PORT_DOWN:
1071 queue_work(priv->wq, &priv->update_carrier_work);
1072 break;
1073
1074 default:
1075 break;
1076 }
1077 }
1078
1079 static void
mlx5e_async_event(struct mlx5_core_dev * mdev,void * vpriv,enum mlx5_dev_event event,unsigned long param)1080 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1081 enum mlx5_dev_event event, unsigned long param)
1082 {
1083 struct mlx5e_priv *priv = vpriv;
1084
1085 mtx_lock(&priv->async_events_mtx);
1086 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1087 mlx5e_async_event_sub(priv, event);
1088 mtx_unlock(&priv->async_events_mtx);
1089 }
1090
1091 static void
mlx5e_enable_async_events(struct mlx5e_priv * priv)1092 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1093 {
1094 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1095 }
1096
1097 static void
mlx5e_disable_async_events(struct mlx5e_priv * priv)1098 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1099 {
1100 mtx_lock(&priv->async_events_mtx);
1101 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1102 mtx_unlock(&priv->async_events_mtx);
1103 }
1104
1105 static const char *mlx5e_rq_stats_desc[] = {
1106 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1107 };
1108
1109 static int
mlx5e_create_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1110 mlx5e_create_rq(struct mlx5e_channel *c,
1111 struct mlx5e_rq_param *param,
1112 struct mlx5e_rq *rq)
1113 {
1114 struct mlx5e_priv *priv = c->priv;
1115 struct mlx5_core_dev *mdev = priv->mdev;
1116 char buffer[16];
1117 void *rqc = param->rqc;
1118 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1119 int wq_sz;
1120 int err;
1121 int i;
1122 u32 nsegs, wqe_sz;
1123
1124 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1125 if (err != 0)
1126 goto done;
1127
1128 /* Create DMA descriptor TAG */
1129 if ((err = -bus_dma_tag_create(
1130 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1131 1, /* any alignment */
1132 0, /* no boundary */
1133 BUS_SPACE_MAXADDR, /* lowaddr */
1134 BUS_SPACE_MAXADDR, /* highaddr */
1135 NULL, NULL, /* filter, filterarg */
1136 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1137 nsegs, /* nsegments */
1138 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1139 0, /* flags */
1140 NULL, NULL, /* lockfunc, lockfuncarg */
1141 &rq->dma_tag)))
1142 goto done;
1143
1144 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1145 &rq->wq_ctrl);
1146 if (err)
1147 goto err_free_dma_tag;
1148
1149 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1150
1151 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1152 if (err != 0)
1153 goto err_rq_wq_destroy;
1154
1155 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1156
1157 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
1158 if (err)
1159 goto err_rq_wq_destroy;
1160
1161 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1162 for (i = 0; i != wq_sz; i++) {
1163 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1164 int j;
1165
1166 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1167 if (err != 0) {
1168 while (i--)
1169 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1170 goto err_rq_mbuf_free;
1171 }
1172
1173 /* set value for constant fields */
1174 for (j = 0; j < rq->nsegs; j++)
1175 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1176 }
1177
1178 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1179 if (priv->params.rx_cq_moderation_mode < 2) {
1180 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1181 } else {
1182 void *cqc = container_of(param,
1183 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1184
1185 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1186 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1187 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1188 break;
1189 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1190 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1191 break;
1192 default:
1193 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1194 break;
1195 }
1196 }
1197
1198 rq->ifp = c->ifp;
1199 rq->channel = c;
1200 rq->ix = c->ix;
1201
1202 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1203 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1204 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1205 rq->stats.arg);
1206 return (0);
1207
1208 err_rq_mbuf_free:
1209 free(rq->mbuf, M_MLX5EN);
1210 tcp_lro_free(&rq->lro);
1211 err_rq_wq_destroy:
1212 mlx5_wq_destroy(&rq->wq_ctrl);
1213 err_free_dma_tag:
1214 bus_dma_tag_destroy(rq->dma_tag);
1215 done:
1216 return (err);
1217 }
1218
1219 static void
mlx5e_destroy_rq(struct mlx5e_rq * rq)1220 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1221 {
1222 int wq_sz;
1223 int i;
1224
1225 /* destroy all sysctl nodes */
1226 sysctl_ctx_free(&rq->stats.ctx);
1227
1228 /* free leftover LRO packets, if any */
1229 tcp_lro_free(&rq->lro);
1230
1231 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1232 for (i = 0; i != wq_sz; i++) {
1233 if (rq->mbuf[i].mbuf != NULL) {
1234 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1235 m_freem(rq->mbuf[i].mbuf);
1236 }
1237 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1238 }
1239 free(rq->mbuf, M_MLX5EN);
1240 mlx5_wq_destroy(&rq->wq_ctrl);
1241 bus_dma_tag_destroy(rq->dma_tag);
1242 }
1243
1244 static int
mlx5e_enable_rq(struct mlx5e_rq * rq,struct mlx5e_rq_param * param)1245 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1246 {
1247 struct mlx5e_channel *c = rq->channel;
1248 struct mlx5e_priv *priv = c->priv;
1249 struct mlx5_core_dev *mdev = priv->mdev;
1250
1251 void *in;
1252 void *rqc;
1253 void *wq;
1254 int inlen;
1255 int err;
1256
1257 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1258 sizeof(u64) * rq->wq_ctrl.buf.npages;
1259 in = mlx5_vzalloc(inlen);
1260 if (in == NULL)
1261 return (-ENOMEM);
1262
1263 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1264 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1265
1266 memcpy(rqc, param->rqc, sizeof(param->rqc));
1267
1268 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1269 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1270 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1271 if (priv->counter_set_id >= 0)
1272 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1273 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1274 PAGE_SHIFT);
1275 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1276
1277 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1278 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1279
1280 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1281
1282 kvfree(in);
1283
1284 return (err);
1285 }
1286
1287 static int
mlx5e_modify_rq(struct mlx5e_rq * rq,int curr_state,int next_state)1288 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1289 {
1290 struct mlx5e_channel *c = rq->channel;
1291 struct mlx5e_priv *priv = c->priv;
1292 struct mlx5_core_dev *mdev = priv->mdev;
1293
1294 void *in;
1295 void *rqc;
1296 int inlen;
1297 int err;
1298
1299 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1300 in = mlx5_vzalloc(inlen);
1301 if (in == NULL)
1302 return (-ENOMEM);
1303
1304 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1305
1306 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1307 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1308 MLX5_SET(rqc, rqc, state, next_state);
1309
1310 err = mlx5_core_modify_rq(mdev, in, inlen);
1311
1312 kvfree(in);
1313
1314 return (err);
1315 }
1316
1317 static void
mlx5e_disable_rq(struct mlx5e_rq * rq)1318 mlx5e_disable_rq(struct mlx5e_rq *rq)
1319 {
1320 struct mlx5e_channel *c = rq->channel;
1321 struct mlx5e_priv *priv = c->priv;
1322 struct mlx5_core_dev *mdev = priv->mdev;
1323
1324 mlx5_core_destroy_rq(mdev, rq->rqn);
1325 }
1326
1327 static int
mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq * rq)1328 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1329 {
1330 struct mlx5e_channel *c = rq->channel;
1331 struct mlx5e_priv *priv = c->priv;
1332 struct mlx5_wq_ll *wq = &rq->wq;
1333 int i;
1334
1335 for (i = 0; i < 1000; i++) {
1336 if (wq->cur_sz >= priv->params.min_rx_wqes)
1337 return (0);
1338
1339 msleep(4);
1340 }
1341 return (-ETIMEDOUT);
1342 }
1343
1344 static int
mlx5e_open_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1345 mlx5e_open_rq(struct mlx5e_channel *c,
1346 struct mlx5e_rq_param *param,
1347 struct mlx5e_rq *rq)
1348 {
1349 int err;
1350
1351 err = mlx5e_create_rq(c, param, rq);
1352 if (err)
1353 return (err);
1354
1355 err = mlx5e_enable_rq(rq, param);
1356 if (err)
1357 goto err_destroy_rq;
1358
1359 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1360 if (err)
1361 goto err_disable_rq;
1362
1363 c->rq.enabled = 1;
1364
1365 return (0);
1366
1367 err_disable_rq:
1368 mlx5e_disable_rq(rq);
1369 err_destroy_rq:
1370 mlx5e_destroy_rq(rq);
1371
1372 return (err);
1373 }
1374
1375 static void
mlx5e_close_rq(struct mlx5e_rq * rq)1376 mlx5e_close_rq(struct mlx5e_rq *rq)
1377 {
1378 mtx_lock(&rq->mtx);
1379 rq->enabled = 0;
1380 callout_stop(&rq->watchdog);
1381 mtx_unlock(&rq->mtx);
1382
1383 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1384 }
1385
1386 static void
mlx5e_close_rq_wait(struct mlx5e_rq * rq)1387 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1388 {
1389
1390 mlx5e_disable_rq(rq);
1391 mlx5e_close_cq(&rq->cq);
1392 cancel_work_sync(&rq->dim.work);
1393 mlx5e_destroy_rq(rq);
1394 }
1395
1396 void
mlx5e_free_sq_db(struct mlx5e_sq * sq)1397 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1398 {
1399 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1400 int x;
1401
1402 for (x = 0; x != wq_sz; x++) {
1403 if (sq->mbuf[x].mbuf != NULL) {
1404 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1405 m_freem(sq->mbuf[x].mbuf);
1406 }
1407 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1408 }
1409 free(sq->mbuf, M_MLX5EN);
1410 }
1411
1412 int
mlx5e_alloc_sq_db(struct mlx5e_sq * sq)1413 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1414 {
1415 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1416 int err;
1417 int x;
1418
1419 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1420
1421 /* Create DMA descriptor MAPs */
1422 for (x = 0; x != wq_sz; x++) {
1423 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1424 if (err != 0) {
1425 while (x--)
1426 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1427 free(sq->mbuf, M_MLX5EN);
1428 return (err);
1429 }
1430 }
1431 return (0);
1432 }
1433
1434 static const char *mlx5e_sq_stats_desc[] = {
1435 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1436 };
1437
1438 void
mlx5e_update_sq_inline(struct mlx5e_sq * sq)1439 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1440 {
1441 sq->max_inline = sq->priv->params.tx_max_inline;
1442 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1443
1444 /*
1445 * Check if trust state is DSCP or if inline mode is NONE which
1446 * indicates CX-5 or newer hardware.
1447 */
1448 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1449 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1450 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1451 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1452 else
1453 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1454 } else {
1455 sq->min_insert_caps = 0;
1456 }
1457 }
1458
1459 static void
mlx5e_refresh_sq_inline_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)1460 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1461 {
1462 int i;
1463
1464 for (i = 0; i != priv->num_tc; i++) {
1465 mtx_lock(&c->sq[i].lock);
1466 mlx5e_update_sq_inline(&c->sq[i]);
1467 mtx_unlock(&c->sq[i].lock);
1468 }
1469 }
1470
1471 void
mlx5e_refresh_sq_inline(struct mlx5e_priv * priv)1472 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1473 {
1474 int i;
1475
1476 /* check if channels are closed */
1477 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1478 return;
1479
1480 for (i = 0; i < priv->params.num_channels; i++)
1481 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1482 }
1483
1484 static int
mlx5e_create_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1485 mlx5e_create_sq(struct mlx5e_channel *c,
1486 int tc,
1487 struct mlx5e_sq_param *param,
1488 struct mlx5e_sq *sq)
1489 {
1490 struct mlx5e_priv *priv = c->priv;
1491 struct mlx5_core_dev *mdev = priv->mdev;
1492 char buffer[16];
1493 void *sqc = param->sqc;
1494 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1495 int err;
1496
1497 /* Create DMA descriptor TAG */
1498 if ((err = -bus_dma_tag_create(
1499 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1500 1, /* any alignment */
1501 0, /* no boundary */
1502 BUS_SPACE_MAXADDR, /* lowaddr */
1503 BUS_SPACE_MAXADDR, /* highaddr */
1504 NULL, NULL, /* filter, filterarg */
1505 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1506 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1507 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1508 0, /* flags */
1509 NULL, NULL, /* lockfunc, lockfuncarg */
1510 &sq->dma_tag)))
1511 goto done;
1512
1513 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1514 if (err)
1515 goto err_free_dma_tag;
1516
1517 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1518 &sq->wq_ctrl);
1519 if (err)
1520 goto err_unmap_free_uar;
1521
1522 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1523 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1524
1525 err = mlx5e_alloc_sq_db(sq);
1526 if (err)
1527 goto err_sq_wq_destroy;
1528
1529 sq->mkey_be = cpu_to_be32(priv->mr.key);
1530 sq->ifp = priv->ifp;
1531 sq->priv = priv;
1532 sq->tc = tc;
1533
1534 mlx5e_update_sq_inline(sq);
1535
1536 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1537 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1538 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1539 sq->stats.arg);
1540
1541 return (0);
1542
1543 err_sq_wq_destroy:
1544 mlx5_wq_destroy(&sq->wq_ctrl);
1545
1546 err_unmap_free_uar:
1547 mlx5_unmap_free_uar(mdev, &sq->uar);
1548
1549 err_free_dma_tag:
1550 bus_dma_tag_destroy(sq->dma_tag);
1551 done:
1552 return (err);
1553 }
1554
1555 static void
mlx5e_destroy_sq(struct mlx5e_sq * sq)1556 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1557 {
1558 /* destroy all sysctl nodes */
1559 sysctl_ctx_free(&sq->stats.ctx);
1560
1561 mlx5e_free_sq_db(sq);
1562 mlx5_wq_destroy(&sq->wq_ctrl);
1563 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1564 bus_dma_tag_destroy(sq->dma_tag);
1565 }
1566
1567 int
mlx5e_enable_sq(struct mlx5e_sq * sq,struct mlx5e_sq_param * param,int tis_num)1568 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1569 int tis_num)
1570 {
1571 void *in;
1572 void *sqc;
1573 void *wq;
1574 int inlen;
1575 int err;
1576
1577 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1578 sizeof(u64) * sq->wq_ctrl.buf.npages;
1579 in = mlx5_vzalloc(inlen);
1580 if (in == NULL)
1581 return (-ENOMEM);
1582
1583 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1584 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1585
1586 memcpy(sqc, param->sqc, sizeof(param->sqc));
1587
1588 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1589 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1590 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1591 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1592 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1593
1594 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1595 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1596 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1597 PAGE_SHIFT);
1598 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1599
1600 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1601 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1602
1603 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1604
1605 kvfree(in);
1606
1607 return (err);
1608 }
1609
1610 int
mlx5e_modify_sq(struct mlx5e_sq * sq,int curr_state,int next_state)1611 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1612 {
1613 void *in;
1614 void *sqc;
1615 int inlen;
1616 int err;
1617
1618 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1619 in = mlx5_vzalloc(inlen);
1620 if (in == NULL)
1621 return (-ENOMEM);
1622
1623 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1624
1625 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1626 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1627 MLX5_SET(sqc, sqc, state, next_state);
1628
1629 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1630
1631 kvfree(in);
1632
1633 return (err);
1634 }
1635
1636 void
mlx5e_disable_sq(struct mlx5e_sq * sq)1637 mlx5e_disable_sq(struct mlx5e_sq *sq)
1638 {
1639
1640 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1641 }
1642
1643 static int
mlx5e_open_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1644 mlx5e_open_sq(struct mlx5e_channel *c,
1645 int tc,
1646 struct mlx5e_sq_param *param,
1647 struct mlx5e_sq *sq)
1648 {
1649 int err;
1650
1651 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1652
1653 /* ensure the TX completion event factor is not zero */
1654 if (sq->cev_factor == 0)
1655 sq->cev_factor = 1;
1656
1657 err = mlx5e_create_sq(c, tc, param, sq);
1658 if (err)
1659 return (err);
1660
1661 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1662 if (err)
1663 goto err_destroy_sq;
1664
1665 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1666 if (err)
1667 goto err_disable_sq;
1668
1669 WRITE_ONCE(sq->running, 1);
1670
1671 return (0);
1672
1673 err_disable_sq:
1674 mlx5e_disable_sq(sq);
1675 err_destroy_sq:
1676 mlx5e_destroy_sq(sq);
1677
1678 return (err);
1679 }
1680
1681 static void
mlx5e_sq_send_nops_locked(struct mlx5e_sq * sq,int can_sleep)1682 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1683 {
1684 /* fill up remainder with NOPs */
1685 while (sq->cev_counter != 0) {
1686 while (!mlx5e_sq_has_room_for(sq, 1)) {
1687 if (can_sleep != 0) {
1688 mtx_unlock(&sq->lock);
1689 msleep(4);
1690 mtx_lock(&sq->lock);
1691 } else {
1692 goto done;
1693 }
1694 }
1695 /* send a single NOP */
1696 mlx5e_send_nop(sq, 1);
1697 atomic_thread_fence_rel();
1698 }
1699 done:
1700 /* Check if we need to write the doorbell */
1701 if (likely(sq->doorbell.d64 != 0)) {
1702 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1703 sq->doorbell.d64 = 0;
1704 }
1705 }
1706
1707 void
mlx5e_sq_cev_timeout(void * arg)1708 mlx5e_sq_cev_timeout(void *arg)
1709 {
1710 struct mlx5e_sq *sq = arg;
1711
1712 mtx_assert(&sq->lock, MA_OWNED);
1713
1714 /* check next state */
1715 switch (sq->cev_next_state) {
1716 case MLX5E_CEV_STATE_SEND_NOPS:
1717 /* fill TX ring with NOPs, if any */
1718 mlx5e_sq_send_nops_locked(sq, 0);
1719
1720 /* check if completed */
1721 if (sq->cev_counter == 0) {
1722 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1723 return;
1724 }
1725 break;
1726 default:
1727 /* send NOPs on next timeout */
1728 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1729 break;
1730 }
1731
1732 /* restart timer */
1733 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1734 }
1735
1736 void
mlx5e_drain_sq(struct mlx5e_sq * sq)1737 mlx5e_drain_sq(struct mlx5e_sq *sq)
1738 {
1739 int error;
1740 struct mlx5_core_dev *mdev= sq->priv->mdev;
1741
1742 /*
1743 * Check if already stopped.
1744 *
1745 * NOTE: Serialization of this function is managed by the
1746 * caller ensuring the priv's state lock is locked or in case
1747 * of rate limit support, a single thread manages drain and
1748 * resume of SQs. The "running" variable can therefore safely
1749 * be read without any locks.
1750 */
1751 if (READ_ONCE(sq->running) == 0)
1752 return;
1753
1754 /* don't put more packets into the SQ */
1755 WRITE_ONCE(sq->running, 0);
1756
1757 /* serialize access to DMA rings */
1758 mtx_lock(&sq->lock);
1759
1760 /* teardown event factor timer, if any */
1761 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1762 callout_stop(&sq->cev_callout);
1763
1764 /* send dummy NOPs in order to flush the transmit ring */
1765 mlx5e_sq_send_nops_locked(sq, 1);
1766 mtx_unlock(&sq->lock);
1767
1768 /* wait till SQ is empty or link is down */
1769 mtx_lock(&sq->lock);
1770 while (sq->cc != sq->pc &&
1771 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1772 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1773 mtx_unlock(&sq->lock);
1774 msleep(1);
1775 sq->cq.mcq.comp(&sq->cq.mcq);
1776 mtx_lock(&sq->lock);
1777 }
1778 mtx_unlock(&sq->lock);
1779
1780 /* error out remaining requests */
1781 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1782 if (error != 0) {
1783 mlx5_en_err(sq->ifp,
1784 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1785 }
1786
1787 /* wait till SQ is empty */
1788 mtx_lock(&sq->lock);
1789 while (sq->cc != sq->pc &&
1790 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1791 mtx_unlock(&sq->lock);
1792 msleep(1);
1793 sq->cq.mcq.comp(&sq->cq.mcq);
1794 mtx_lock(&sq->lock);
1795 }
1796 mtx_unlock(&sq->lock);
1797 }
1798
1799 static void
mlx5e_close_sq_wait(struct mlx5e_sq * sq)1800 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1801 {
1802
1803 mlx5e_drain_sq(sq);
1804 mlx5e_disable_sq(sq);
1805 mlx5e_destroy_sq(sq);
1806 }
1807
1808 static int
mlx5e_create_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)1809 mlx5e_create_cq(struct mlx5e_priv *priv,
1810 struct mlx5e_cq_param *param,
1811 struct mlx5e_cq *cq,
1812 mlx5e_cq_comp_t *comp,
1813 int eq_ix)
1814 {
1815 struct mlx5_core_dev *mdev = priv->mdev;
1816 struct mlx5_core_cq *mcq = &cq->mcq;
1817 int eqn_not_used;
1818 int irqn;
1819 int err;
1820 u32 i;
1821
1822 param->wq.buf_numa_node = 0;
1823 param->wq.db_numa_node = 0;
1824
1825 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1826 if (err)
1827 return (err);
1828
1829 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1830 &cq->wq_ctrl);
1831 if (err)
1832 return (err);
1833
1834 mcq->cqe_sz = 64;
1835 mcq->set_ci_db = cq->wq_ctrl.db.db;
1836 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1837 *mcq->set_ci_db = 0;
1838 *mcq->arm_db = 0;
1839 mcq->vector = eq_ix;
1840 mcq->comp = comp;
1841 mcq->event = mlx5e_cq_error_event;
1842 mcq->irqn = irqn;
1843 mcq->uar = &priv->cq_uar;
1844
1845 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1846 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1847
1848 cqe->op_own = 0xf1;
1849 }
1850
1851 cq->priv = priv;
1852
1853 return (0);
1854 }
1855
1856 static void
mlx5e_destroy_cq(struct mlx5e_cq * cq)1857 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1858 {
1859 mlx5_wq_destroy(&cq->wq_ctrl);
1860 }
1861
1862 static int
mlx5e_enable_cq(struct mlx5e_cq * cq,struct mlx5e_cq_param * param,int eq_ix)1863 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1864 {
1865 struct mlx5_core_cq *mcq = &cq->mcq;
1866 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1867 void *in;
1868 void *cqc;
1869 int inlen;
1870 int irqn_not_used;
1871 int eqn;
1872 int err;
1873
1874 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1875 sizeof(u64) * cq->wq_ctrl.buf.npages;
1876 in = mlx5_vzalloc(inlen);
1877 if (in == NULL)
1878 return (-ENOMEM);
1879
1880 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1881
1882 memcpy(cqc, param->cqc, sizeof(param->cqc));
1883
1884 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1885 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1886
1887 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1888
1889 MLX5_SET(cqc, cqc, c_eqn, eqn);
1890 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1891 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1892 PAGE_SHIFT);
1893 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1894
1895 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out));
1896
1897 kvfree(in);
1898
1899 if (err)
1900 return (err);
1901
1902 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1903
1904 return (0);
1905 }
1906
1907 static void
mlx5e_disable_cq(struct mlx5e_cq * cq)1908 mlx5e_disable_cq(struct mlx5e_cq *cq)
1909 {
1910
1911 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1912 }
1913
1914 int
mlx5e_open_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)1915 mlx5e_open_cq(struct mlx5e_priv *priv,
1916 struct mlx5e_cq_param *param,
1917 struct mlx5e_cq *cq,
1918 mlx5e_cq_comp_t *comp,
1919 int eq_ix)
1920 {
1921 int err;
1922
1923 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1924 if (err)
1925 return (err);
1926
1927 err = mlx5e_enable_cq(cq, param, eq_ix);
1928 if (err)
1929 goto err_destroy_cq;
1930
1931 return (0);
1932
1933 err_destroy_cq:
1934 mlx5e_destroy_cq(cq);
1935
1936 return (err);
1937 }
1938
1939 void
mlx5e_close_cq(struct mlx5e_cq * cq)1940 mlx5e_close_cq(struct mlx5e_cq *cq)
1941 {
1942 mlx5e_disable_cq(cq);
1943 mlx5e_destroy_cq(cq);
1944 }
1945
1946 static int
mlx5e_open_tx_cqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)1947 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1948 struct mlx5e_channel_param *cparam)
1949 {
1950 int err;
1951 int tc;
1952
1953 for (tc = 0; tc < c->priv->num_tc; tc++) {
1954 /* open completion queue */
1955 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1956 &mlx5e_tx_cq_comp, c->ix);
1957 if (err)
1958 goto err_close_tx_cqs;
1959 }
1960 return (0);
1961
1962 err_close_tx_cqs:
1963 for (tc--; tc >= 0; tc--)
1964 mlx5e_close_cq(&c->sq[tc].cq);
1965
1966 return (err);
1967 }
1968
1969 static void
mlx5e_close_tx_cqs(struct mlx5e_channel * c)1970 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1971 {
1972 int tc;
1973
1974 for (tc = 0; tc < c->priv->num_tc; tc++)
1975 mlx5e_close_cq(&c->sq[tc].cq);
1976 }
1977
1978 static int
mlx5e_open_sqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)1979 mlx5e_open_sqs(struct mlx5e_channel *c,
1980 struct mlx5e_channel_param *cparam)
1981 {
1982 int err;
1983 int tc;
1984
1985 for (tc = 0; tc < c->priv->num_tc; tc++) {
1986 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1987 if (err)
1988 goto err_close_sqs;
1989 }
1990
1991 return (0);
1992
1993 err_close_sqs:
1994 for (tc--; tc >= 0; tc--)
1995 mlx5e_close_sq_wait(&c->sq[tc]);
1996
1997 return (err);
1998 }
1999
2000 static void
mlx5e_close_sqs_wait(struct mlx5e_channel * c)2001 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2002 {
2003 int tc;
2004
2005 for (tc = 0; tc < c->priv->num_tc; tc++)
2006 mlx5e_close_sq_wait(&c->sq[tc]);
2007 }
2008
2009 static void
mlx5e_chan_static_init(struct mlx5e_priv * priv,struct mlx5e_channel * c,int ix)2010 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2011 {
2012 int tc;
2013
2014 /* setup priv and channel number */
2015 c->priv = priv;
2016 c->ix = ix;
2017 c->ifp = priv->ifp;
2018
2019 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2020
2021 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2022
2023 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2024 struct mlx5e_sq *sq = c->sq + tc;
2025
2026 mtx_init(&sq->lock, "mlx5tx",
2027 MTX_NETWORK_LOCK " TX", MTX_DEF);
2028 mtx_init(&sq->comp_lock, "mlx5comp",
2029 MTX_NETWORK_LOCK " TX", MTX_DEF);
2030
2031 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2032 }
2033 }
2034
2035 static void
mlx5e_chan_static_destroy(struct mlx5e_channel * c)2036 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2037 {
2038 int tc;
2039
2040 callout_drain(&c->rq.watchdog);
2041
2042 mtx_destroy(&c->rq.mtx);
2043
2044 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2045 callout_drain(&c->sq[tc].cev_callout);
2046 mtx_destroy(&c->sq[tc].lock);
2047 mtx_destroy(&c->sq[tc].comp_lock);
2048 }
2049 }
2050
2051 static int
mlx5e_open_channel(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam,struct mlx5e_channel * c)2052 mlx5e_open_channel(struct mlx5e_priv *priv,
2053 struct mlx5e_channel_param *cparam,
2054 struct mlx5e_channel *c)
2055 {
2056 int i, err;
2057
2058 /* zero non-persistant data */
2059 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2060 for (i = 0; i != priv->num_tc; i++)
2061 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2062
2063 /* open transmit completion queue */
2064 err = mlx5e_open_tx_cqs(c, cparam);
2065 if (err)
2066 goto err_free;
2067
2068 /* open receive completion queue */
2069 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2070 &mlx5e_rx_cq_comp, c->ix);
2071 if (err)
2072 goto err_close_tx_cqs;
2073
2074 err = mlx5e_open_sqs(c, cparam);
2075 if (err)
2076 goto err_close_rx_cq;
2077
2078 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2079 if (err)
2080 goto err_close_sqs;
2081
2082 /* poll receive queue initially */
2083 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2084
2085 return (0);
2086
2087 err_close_sqs:
2088 mlx5e_close_sqs_wait(c);
2089
2090 err_close_rx_cq:
2091 mlx5e_close_cq(&c->rq.cq);
2092
2093 err_close_tx_cqs:
2094 mlx5e_close_tx_cqs(c);
2095
2096 err_free:
2097 return (err);
2098 }
2099
2100 static void
mlx5e_close_channel(struct mlx5e_channel * c)2101 mlx5e_close_channel(struct mlx5e_channel *c)
2102 {
2103 mlx5e_close_rq(&c->rq);
2104 }
2105
2106 static void
mlx5e_close_channel_wait(struct mlx5e_channel * c)2107 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2108 {
2109 mlx5e_close_rq_wait(&c->rq);
2110 mlx5e_close_sqs_wait(c);
2111 mlx5e_close_tx_cqs(c);
2112 }
2113
2114 static int
mlx5e_get_wqe_sz(struct mlx5e_priv * priv,u32 * wqe_sz,u32 * nsegs)2115 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2116 {
2117 u32 r, n;
2118
2119 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2120 MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2121 if (r > MJUM16BYTES)
2122 return (-ENOMEM);
2123
2124 if (r > MJUM9BYTES)
2125 r = MJUM16BYTES;
2126 else if (r > MJUMPAGESIZE)
2127 r = MJUM9BYTES;
2128 else if (r > MCLBYTES)
2129 r = MJUMPAGESIZE;
2130 else
2131 r = MCLBYTES;
2132
2133 /*
2134 * n + 1 must be a power of two, because stride size must be.
2135 * Stride size is 16 * (n + 1), as the first segment is
2136 * control.
2137 */
2138 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2139 ;
2140
2141 if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2142 return (-ENOMEM);
2143
2144 *wqe_sz = r;
2145 *nsegs = n;
2146 return (0);
2147 }
2148
2149 static void
mlx5e_build_rq_param(struct mlx5e_priv * priv,struct mlx5e_rq_param * param)2150 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2151 struct mlx5e_rq_param *param)
2152 {
2153 void *rqc = param->rqc;
2154 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2155 u32 wqe_sz, nsegs;
2156
2157 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2158 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2159 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2160 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2161 nsegs * sizeof(struct mlx5_wqe_data_seg)));
2162 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2163 MLX5_SET(wq, wq, pd, priv->pdn);
2164
2165 param->wq.buf_numa_node = 0;
2166 param->wq.db_numa_node = 0;
2167 param->wq.linear = 1;
2168 }
2169
2170 static void
mlx5e_build_sq_param(struct mlx5e_priv * priv,struct mlx5e_sq_param * param)2171 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2172 struct mlx5e_sq_param *param)
2173 {
2174 void *sqc = param->sqc;
2175 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2176
2177 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2178 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2179 MLX5_SET(wq, wq, pd, priv->pdn);
2180
2181 param->wq.buf_numa_node = 0;
2182 param->wq.db_numa_node = 0;
2183 param->wq.linear = 1;
2184 }
2185
2186 static void
mlx5e_build_common_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2187 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2188 struct mlx5e_cq_param *param)
2189 {
2190 void *cqc = param->cqc;
2191
2192 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2193 }
2194
2195 static void
mlx5e_get_default_profile(struct mlx5e_priv * priv,int mode,struct net_dim_cq_moder * ptr)2196 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2197 {
2198
2199 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2200
2201 /* apply LRO restrictions */
2202 if (priv->params.hw_lro_en &&
2203 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2204 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2205 }
2206 }
2207
2208 static void
mlx5e_build_rx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2209 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2210 struct mlx5e_cq_param *param)
2211 {
2212 struct net_dim_cq_moder curr;
2213 void *cqc = param->cqc;
2214
2215 /*
2216 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2217 * format is more beneficial for FreeBSD use case.
2218 *
2219 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2220 * in mlx5e_decompress_cqe.
2221 */
2222 if (priv->params.cqe_zipping_en) {
2223 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2224 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2225 }
2226
2227 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2228
2229 switch (priv->params.rx_cq_moderation_mode) {
2230 case 0:
2231 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2232 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2233 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2234 break;
2235 case 1:
2236 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2237 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2238 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2239 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2240 else
2241 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2242 break;
2243 case 2:
2244 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2245 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2246 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2247 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2248 break;
2249 case 3:
2250 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2251 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2252 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2253 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2254 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2255 else
2256 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2257 break;
2258 default:
2259 break;
2260 }
2261
2262 mlx5e_dim_build_cq_param(priv, param);
2263
2264 mlx5e_build_common_cq_param(priv, param);
2265 }
2266
2267 static void
mlx5e_build_tx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2268 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2269 struct mlx5e_cq_param *param)
2270 {
2271 void *cqc = param->cqc;
2272
2273 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2274 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2275 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2276
2277 switch (priv->params.tx_cq_moderation_mode) {
2278 case 0:
2279 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2280 break;
2281 default:
2282 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2283 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2284 else
2285 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2286 break;
2287 }
2288
2289 mlx5e_build_common_cq_param(priv, param);
2290 }
2291
2292 static void
mlx5e_build_channel_param(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam)2293 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2294 struct mlx5e_channel_param *cparam)
2295 {
2296 memset(cparam, 0, sizeof(*cparam));
2297
2298 mlx5e_build_rq_param(priv, &cparam->rq);
2299 mlx5e_build_sq_param(priv, &cparam->sq);
2300 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2301 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2302 }
2303
2304 static int
mlx5e_open_channels(struct mlx5e_priv * priv)2305 mlx5e_open_channels(struct mlx5e_priv *priv)
2306 {
2307 struct mlx5e_channel_param *cparam;
2308 int err;
2309 int i;
2310 int j;
2311
2312 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2313
2314 mlx5e_build_channel_param(priv, cparam);
2315 for (i = 0; i < priv->params.num_channels; i++) {
2316 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2317 if (err)
2318 goto err_close_channels;
2319 }
2320
2321 for (j = 0; j < priv->params.num_channels; j++) {
2322 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2323 if (err)
2324 goto err_close_channels;
2325 }
2326 free(cparam, M_MLX5EN);
2327 return (0);
2328
2329 err_close_channels:
2330 while (i--) {
2331 mlx5e_close_channel(&priv->channel[i]);
2332 mlx5e_close_channel_wait(&priv->channel[i]);
2333 }
2334 free(cparam, M_MLX5EN);
2335 return (err);
2336 }
2337
2338 static void
mlx5e_close_channels(struct mlx5e_priv * priv)2339 mlx5e_close_channels(struct mlx5e_priv *priv)
2340 {
2341 int i;
2342
2343 for (i = 0; i < priv->params.num_channels; i++)
2344 mlx5e_close_channel(&priv->channel[i]);
2345 for (i = 0; i < priv->params.num_channels; i++)
2346 mlx5e_close_channel_wait(&priv->channel[i]);
2347 }
2348
2349 static int
mlx5e_refresh_sq_params(struct mlx5e_priv * priv,struct mlx5e_sq * sq)2350 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2351 {
2352
2353 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2354 uint8_t cq_mode;
2355
2356 switch (priv->params.tx_cq_moderation_mode) {
2357 case 0:
2358 case 2:
2359 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2360 break;
2361 default:
2362 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2363 break;
2364 }
2365
2366 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2367 priv->params.tx_cq_moderation_usec,
2368 priv->params.tx_cq_moderation_pkts,
2369 cq_mode));
2370 }
2371
2372 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2373 priv->params.tx_cq_moderation_usec,
2374 priv->params.tx_cq_moderation_pkts));
2375 }
2376
2377 static int
mlx5e_refresh_rq_params(struct mlx5e_priv * priv,struct mlx5e_rq * rq)2378 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2379 {
2380
2381 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2382 uint8_t cq_mode;
2383 uint8_t dim_mode;
2384 int retval;
2385
2386 switch (priv->params.rx_cq_moderation_mode) {
2387 case 0:
2388 case 2:
2389 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2390 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2391 break;
2392 default:
2393 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2394 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2395 break;
2396 }
2397
2398 /* tear down dynamic interrupt moderation */
2399 mtx_lock(&rq->mtx);
2400 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2401 mtx_unlock(&rq->mtx);
2402
2403 /* wait for dynamic interrupt moderation work task, if any */
2404 cancel_work_sync(&rq->dim.work);
2405
2406 if (priv->params.rx_cq_moderation_mode >= 2) {
2407 struct net_dim_cq_moder curr;
2408
2409 mlx5e_get_default_profile(priv, dim_mode, &curr);
2410
2411 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2412 curr.usec, curr.pkts, cq_mode);
2413
2414 /* set dynamic interrupt moderation mode and zero defaults */
2415 mtx_lock(&rq->mtx);
2416 rq->dim.mode = dim_mode;
2417 rq->dim.state = 0;
2418 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2419 mtx_unlock(&rq->mtx);
2420 } else {
2421 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2422 priv->params.rx_cq_moderation_usec,
2423 priv->params.rx_cq_moderation_pkts,
2424 cq_mode);
2425 }
2426 return (retval);
2427 }
2428
2429 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2430 priv->params.rx_cq_moderation_usec,
2431 priv->params.rx_cq_moderation_pkts));
2432 }
2433
2434 static int
mlx5e_refresh_channel_params_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)2435 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2436 {
2437 int err;
2438 int i;
2439
2440 err = mlx5e_refresh_rq_params(priv, &c->rq);
2441 if (err)
2442 goto done;
2443
2444 for (i = 0; i != priv->num_tc; i++) {
2445 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2446 if (err)
2447 goto done;
2448 }
2449 done:
2450 return (err);
2451 }
2452
2453 int
mlx5e_refresh_channel_params(struct mlx5e_priv * priv)2454 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2455 {
2456 int i;
2457
2458 /* check if channels are closed */
2459 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2460 return (EINVAL);
2461
2462 for (i = 0; i < priv->params.num_channels; i++) {
2463 int err;
2464
2465 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2466 if (err)
2467 return (err);
2468 }
2469 return (0);
2470 }
2471
2472 static int
mlx5e_open_tis(struct mlx5e_priv * priv,int tc)2473 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2474 {
2475 struct mlx5_core_dev *mdev = priv->mdev;
2476 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2477 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2478
2479 memset(in, 0, sizeof(in));
2480
2481 MLX5_SET(tisc, tisc, prio, tc);
2482 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2483
2484 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2485 }
2486
2487 static void
mlx5e_close_tis(struct mlx5e_priv * priv,int tc)2488 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2489 {
2490 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2491 }
2492
2493 static int
mlx5e_open_tises(struct mlx5e_priv * priv)2494 mlx5e_open_tises(struct mlx5e_priv *priv)
2495 {
2496 int num_tc = priv->num_tc;
2497 int err;
2498 int tc;
2499
2500 for (tc = 0; tc < num_tc; tc++) {
2501 err = mlx5e_open_tis(priv, tc);
2502 if (err)
2503 goto err_close_tises;
2504 }
2505
2506 return (0);
2507
2508 err_close_tises:
2509 for (tc--; tc >= 0; tc--)
2510 mlx5e_close_tis(priv, tc);
2511
2512 return (err);
2513 }
2514
2515 static void
mlx5e_close_tises(struct mlx5e_priv * priv)2516 mlx5e_close_tises(struct mlx5e_priv *priv)
2517 {
2518 int num_tc = priv->num_tc;
2519 int tc;
2520
2521 for (tc = 0; tc < num_tc; tc++)
2522 mlx5e_close_tis(priv, tc);
2523 }
2524
2525 static int
mlx5e_open_rqt(struct mlx5e_priv * priv)2526 mlx5e_open_rqt(struct mlx5e_priv *priv)
2527 {
2528 struct mlx5_core_dev *mdev = priv->mdev;
2529 u32 *in;
2530 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2531 void *rqtc;
2532 int inlen;
2533 int err;
2534 int sz;
2535 int i;
2536
2537 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2538
2539 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2540 in = mlx5_vzalloc(inlen);
2541 if (in == NULL)
2542 return (-ENOMEM);
2543 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2544
2545 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2546 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2547
2548 for (i = 0; i < sz; i++) {
2549 int ix = i;
2550 #ifdef RSS
2551 ix = rss_get_indirection_to_bucket(ix);
2552 #endif
2553 /* ensure we don't overflow */
2554 ix %= priv->params.num_channels;
2555
2556 /* apply receive side scaling stride, if any */
2557 ix -= ix % (int)priv->params.channels_rsss;
2558
2559 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2560 }
2561
2562 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2563
2564 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2565 if (!err)
2566 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2567
2568 kvfree(in);
2569
2570 return (err);
2571 }
2572
2573 static void
mlx5e_close_rqt(struct mlx5e_priv * priv)2574 mlx5e_close_rqt(struct mlx5e_priv *priv)
2575 {
2576 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2577 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2578
2579 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2580 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2581
2582 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2583 }
2584
2585 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */
2586
2587 static void
mlx5e_get_rss_key(void * key_ptr)2588 mlx5e_get_rss_key(void *key_ptr)
2589 {
2590 #ifdef RSS
2591 rss_getkey(key_ptr);
2592 #else
2593 static const u32 rsskey[] = {
2594 cpu_to_be32(0xD181C62C),
2595 cpu_to_be32(0xF7F4DB5B),
2596 cpu_to_be32(0x1983A2FC),
2597 cpu_to_be32(0x943E1ADB),
2598 cpu_to_be32(0xD9389E6B),
2599 cpu_to_be32(0xD1039C2C),
2600 cpu_to_be32(0xA74499AD),
2601 cpu_to_be32(0x593D56D9),
2602 cpu_to_be32(0xF3253C06),
2603 cpu_to_be32(0x2ADC1FFC),
2604 };
2605 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE);
2606 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE);
2607 #endif
2608 }
2609
2610 static void
mlx5e_build_tir_ctx(struct mlx5e_priv * priv,u32 * tirc,int tt)2611 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2612 {
2613 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2614 __be32 *hkey;
2615
2616 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2617
2618 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2619
2620 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2621 MLX5_HASH_FIELD_SEL_DST_IP)
2622
2623 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2624 MLX5_HASH_FIELD_SEL_DST_IP |\
2625 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2626 MLX5_HASH_FIELD_SEL_L4_DPORT)
2627
2628 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2629 MLX5_HASH_FIELD_SEL_DST_IP |\
2630 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2631
2632 if (priv->params.hw_lro_en) {
2633 MLX5_SET(tirc, tirc, lro_enable_mask,
2634 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2635 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2636 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2637 (priv->params.lro_wqe_sz -
2638 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2639 /* TODO: add the option to choose timer value dynamically */
2640 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2641 MLX5_CAP_ETH(priv->mdev,
2642 lro_timer_supported_periods[2]));
2643 }
2644
2645 /* setup parameters for hashing TIR type, if any */
2646 switch (tt) {
2647 case MLX5E_TT_ANY:
2648 MLX5_SET(tirc, tirc, disp_type,
2649 MLX5_TIRC_DISP_TYPE_DIRECT);
2650 MLX5_SET(tirc, tirc, inline_rqn,
2651 priv->channel[0].rq.rqn);
2652 break;
2653 default:
2654 MLX5_SET(tirc, tirc, disp_type,
2655 MLX5_TIRC_DISP_TYPE_INDIRECT);
2656 MLX5_SET(tirc, tirc, indirect_table,
2657 priv->rqtn);
2658 MLX5_SET(tirc, tirc, rx_hash_fn,
2659 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2660 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2661
2662 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >=
2663 MLX5E_RSS_KEY_SIZE);
2664 #ifdef RSS
2665 /*
2666 * The FreeBSD RSS implementation does currently not
2667 * support symmetric Toeplitz hashes:
2668 */
2669 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2670 #else
2671 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2672 #endif
2673 mlx5e_get_rss_key(hkey);
2674 break;
2675 }
2676
2677 switch (tt) {
2678 case MLX5E_TT_IPV4_TCP:
2679 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2680 MLX5_L3_PROT_TYPE_IPV4);
2681 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2682 MLX5_L4_PROT_TYPE_TCP);
2683 #ifdef RSS
2684 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2685 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2686 MLX5_HASH_IP);
2687 } else
2688 #endif
2689 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2690 MLX5_HASH_ALL);
2691 break;
2692
2693 case MLX5E_TT_IPV6_TCP:
2694 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2695 MLX5_L3_PROT_TYPE_IPV6);
2696 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2697 MLX5_L4_PROT_TYPE_TCP);
2698 #ifdef RSS
2699 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2700 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2701 MLX5_HASH_IP);
2702 } else
2703 #endif
2704 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2705 MLX5_HASH_ALL);
2706 break;
2707
2708 case MLX5E_TT_IPV4_UDP:
2709 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2710 MLX5_L3_PROT_TYPE_IPV4);
2711 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2712 MLX5_L4_PROT_TYPE_UDP);
2713 #ifdef RSS
2714 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2715 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2716 MLX5_HASH_IP);
2717 } else
2718 #endif
2719 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2720 MLX5_HASH_ALL);
2721 break;
2722
2723 case MLX5E_TT_IPV6_UDP:
2724 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2725 MLX5_L3_PROT_TYPE_IPV6);
2726 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2727 MLX5_L4_PROT_TYPE_UDP);
2728 #ifdef RSS
2729 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2730 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2731 MLX5_HASH_IP);
2732 } else
2733 #endif
2734 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2735 MLX5_HASH_ALL);
2736 break;
2737
2738 case MLX5E_TT_IPV4_IPSEC_AH:
2739 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2740 MLX5_L3_PROT_TYPE_IPV4);
2741 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2742 MLX5_HASH_IP_IPSEC_SPI);
2743 break;
2744
2745 case MLX5E_TT_IPV6_IPSEC_AH:
2746 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2747 MLX5_L3_PROT_TYPE_IPV6);
2748 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2749 MLX5_HASH_IP_IPSEC_SPI);
2750 break;
2751
2752 case MLX5E_TT_IPV4_IPSEC_ESP:
2753 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2754 MLX5_L3_PROT_TYPE_IPV4);
2755 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2756 MLX5_HASH_IP_IPSEC_SPI);
2757 break;
2758
2759 case MLX5E_TT_IPV6_IPSEC_ESP:
2760 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2761 MLX5_L3_PROT_TYPE_IPV6);
2762 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2763 MLX5_HASH_IP_IPSEC_SPI);
2764 break;
2765
2766 case MLX5E_TT_IPV4:
2767 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2768 MLX5_L3_PROT_TYPE_IPV4);
2769 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2770 MLX5_HASH_IP);
2771 break;
2772
2773 case MLX5E_TT_IPV6:
2774 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2775 MLX5_L3_PROT_TYPE_IPV6);
2776 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2777 MLX5_HASH_IP);
2778 break;
2779
2780 default:
2781 break;
2782 }
2783 }
2784
2785 static int
mlx5e_open_tir(struct mlx5e_priv * priv,int tt)2786 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2787 {
2788 struct mlx5_core_dev *mdev = priv->mdev;
2789 u32 *in;
2790 void *tirc;
2791 int inlen;
2792 int err;
2793
2794 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2795 in = mlx5_vzalloc(inlen);
2796 if (in == NULL)
2797 return (-ENOMEM);
2798 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2799
2800 mlx5e_build_tir_ctx(priv, tirc, tt);
2801
2802 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2803
2804 kvfree(in);
2805
2806 return (err);
2807 }
2808
2809 static void
mlx5e_close_tir(struct mlx5e_priv * priv,int tt)2810 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2811 {
2812 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2813 }
2814
2815 static int
mlx5e_open_tirs(struct mlx5e_priv * priv)2816 mlx5e_open_tirs(struct mlx5e_priv *priv)
2817 {
2818 int err;
2819 int i;
2820
2821 for (i = 0; i < MLX5E_NUM_TT; i++) {
2822 err = mlx5e_open_tir(priv, i);
2823 if (err)
2824 goto err_close_tirs;
2825 }
2826
2827 return (0);
2828
2829 err_close_tirs:
2830 for (i--; i >= 0; i--)
2831 mlx5e_close_tir(priv, i);
2832
2833 return (err);
2834 }
2835
2836 static void
mlx5e_close_tirs(struct mlx5e_priv * priv)2837 mlx5e_close_tirs(struct mlx5e_priv *priv)
2838 {
2839 int i;
2840
2841 for (i = 0; i < MLX5E_NUM_TT; i++)
2842 mlx5e_close_tir(priv, i);
2843 }
2844
2845 /*
2846 * SW MTU does not include headers,
2847 * HW MTU includes all headers and checksums.
2848 */
2849 static int
mlx5e_set_dev_port_mtu(struct ifnet * ifp,int sw_mtu)2850 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2851 {
2852 struct mlx5e_priv *priv = ifp->if_softc;
2853 struct mlx5_core_dev *mdev = priv->mdev;
2854 int hw_mtu;
2855 int err;
2856
2857 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2858
2859 err = mlx5_set_port_mtu(mdev, hw_mtu);
2860 if (err) {
2861 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
2862 sw_mtu, err);
2863 return (err);
2864 }
2865
2866 /* Update vport context MTU */
2867 err = mlx5_set_vport_mtu(mdev, hw_mtu);
2868 if (err) {
2869 mlx5_en_err(ifp,
2870 "Failed updating vport context with MTU size, err=%d\n",
2871 err);
2872 }
2873
2874 ifp->if_mtu = sw_mtu;
2875
2876 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2877 if (err || !hw_mtu) {
2878 /* fallback to port oper mtu */
2879 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2880 }
2881 if (err) {
2882 mlx5_en_err(ifp,
2883 "Query port MTU, after setting new MTU value, failed\n");
2884 return (err);
2885 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2886 err = -E2BIG,
2887 mlx5_en_err(ifp,
2888 "Port MTU %d is smaller than ifp mtu %d\n",
2889 hw_mtu, sw_mtu);
2890 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2891 err = -EINVAL;
2892 mlx5_en_err(ifp,
2893 "Port MTU %d is bigger than ifp mtu %d\n",
2894 hw_mtu, sw_mtu);
2895 }
2896 priv->params_ethtool.hw_mtu = hw_mtu;
2897
2898 return (err);
2899 }
2900
2901 int
mlx5e_open_locked(struct ifnet * ifp)2902 mlx5e_open_locked(struct ifnet *ifp)
2903 {
2904 struct mlx5e_priv *priv = ifp->if_softc;
2905 int err;
2906 u16 set_id;
2907
2908 /* check if already opened */
2909 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2910 return (0);
2911
2912 #ifdef RSS
2913 if (rss_getnumbuckets() > priv->params.num_channels) {
2914 mlx5_en_info(ifp,
2915 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
2916 rss_getnumbuckets(), priv->params.num_channels);
2917 }
2918 #endif
2919 err = mlx5e_open_tises(priv);
2920 if (err) {
2921 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
2922 return (err);
2923 }
2924 err = mlx5_vport_alloc_q_counter(priv->mdev,
2925 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2926 if (err) {
2927 mlx5_en_err(priv->ifp,
2928 "mlx5_vport_alloc_q_counter failed: %d\n", err);
2929 goto err_close_tises;
2930 }
2931 /* store counter set ID */
2932 priv->counter_set_id = set_id;
2933
2934 err = mlx5e_open_channels(priv);
2935 if (err) {
2936 mlx5_en_err(ifp,
2937 "mlx5e_open_channels failed, %d\n", err);
2938 goto err_dalloc_q_counter;
2939 }
2940 err = mlx5e_open_rqt(priv);
2941 if (err) {
2942 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
2943 goto err_close_channels;
2944 }
2945 err = mlx5e_open_tirs(priv);
2946 if (err) {
2947 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
2948 goto err_close_rqls;
2949 }
2950 err = mlx5e_open_flow_table(priv);
2951 if (err) {
2952 mlx5_en_err(ifp,
2953 "mlx5e_open_flow_table failed, %d\n", err);
2954 goto err_close_tirs;
2955 }
2956 err = mlx5e_add_all_vlan_rules(priv);
2957 if (err) {
2958 mlx5_en_err(ifp,
2959 "mlx5e_add_all_vlan_rules failed, %d\n", err);
2960 goto err_close_flow_table;
2961 }
2962 set_bit(MLX5E_STATE_OPENED, &priv->state);
2963
2964 mlx5e_update_carrier(priv);
2965 mlx5e_set_rx_mode_core(priv);
2966
2967 return (0);
2968
2969 err_close_flow_table:
2970 mlx5e_close_flow_table(priv);
2971
2972 err_close_tirs:
2973 mlx5e_close_tirs(priv);
2974
2975 err_close_rqls:
2976 mlx5e_close_rqt(priv);
2977
2978 err_close_channels:
2979 mlx5e_close_channels(priv);
2980
2981 err_dalloc_q_counter:
2982 mlx5_vport_dealloc_q_counter(priv->mdev,
2983 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2984
2985 err_close_tises:
2986 mlx5e_close_tises(priv);
2987
2988 return (err);
2989 }
2990
2991 static void
mlx5e_open(void * arg)2992 mlx5e_open(void *arg)
2993 {
2994 struct mlx5e_priv *priv = arg;
2995
2996 PRIV_LOCK(priv);
2997 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2998 mlx5_en_err(priv->ifp,
2999 "Setting port status to up failed\n");
3000
3001 mlx5e_open_locked(priv->ifp);
3002 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3003 PRIV_UNLOCK(priv);
3004 }
3005
3006 int
mlx5e_close_locked(struct ifnet * ifp)3007 mlx5e_close_locked(struct ifnet *ifp)
3008 {
3009 struct mlx5e_priv *priv = ifp->if_softc;
3010
3011 /* check if already closed */
3012 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3013 return (0);
3014
3015 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3016
3017 mlx5e_set_rx_mode_core(priv);
3018 mlx5e_del_all_vlan_rules(priv);
3019 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3020 mlx5e_close_flow_table(priv);
3021 mlx5e_close_tirs(priv);
3022 mlx5e_close_rqt(priv);
3023 mlx5e_close_channels(priv);
3024 mlx5_vport_dealloc_q_counter(priv->mdev,
3025 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3026 mlx5e_close_tises(priv);
3027
3028 return (0);
3029 }
3030
3031 #if (__FreeBSD_version >= 1100000)
3032 static uint64_t
mlx5e_get_counter(struct ifnet * ifp,ift_counter cnt)3033 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3034 {
3035 struct mlx5e_priv *priv = ifp->if_softc;
3036 u64 retval;
3037
3038 /* PRIV_LOCK(priv); XXX not allowed */
3039 switch (cnt) {
3040 case IFCOUNTER_IPACKETS:
3041 retval = priv->stats.vport.rx_packets;
3042 break;
3043 case IFCOUNTER_IERRORS:
3044 retval = priv->stats.pport.in_range_len_errors +
3045 priv->stats.pport.out_of_range_len +
3046 priv->stats.pport.too_long_errors +
3047 priv->stats.pport.check_seq_err +
3048 priv->stats.pport.alignment_err;
3049 break;
3050 case IFCOUNTER_IQDROPS:
3051 retval = priv->stats.vport.rx_out_of_buffer;
3052 break;
3053 case IFCOUNTER_OPACKETS:
3054 retval = priv->stats.vport.tx_packets;
3055 break;
3056 case IFCOUNTER_OERRORS:
3057 retval = priv->stats.port_stats_debug.out_discards;
3058 break;
3059 case IFCOUNTER_IBYTES:
3060 retval = priv->stats.vport.rx_bytes;
3061 break;
3062 case IFCOUNTER_OBYTES:
3063 retval = priv->stats.vport.tx_bytes;
3064 break;
3065 case IFCOUNTER_IMCASTS:
3066 retval = priv->stats.vport.rx_multicast_packets;
3067 break;
3068 case IFCOUNTER_OMCASTS:
3069 retval = priv->stats.vport.tx_multicast_packets;
3070 break;
3071 case IFCOUNTER_OQDROPS:
3072 retval = priv->stats.vport.tx_queue_dropped;
3073 break;
3074 case IFCOUNTER_COLLISIONS:
3075 retval = priv->stats.pport.collisions;
3076 break;
3077 default:
3078 retval = if_get_counter_default(ifp, cnt);
3079 break;
3080 }
3081 /* PRIV_UNLOCK(priv); XXX not allowed */
3082 return (retval);
3083 }
3084 #endif
3085
3086 static void
mlx5e_set_rx_mode(struct ifnet * ifp)3087 mlx5e_set_rx_mode(struct ifnet *ifp)
3088 {
3089 struct mlx5e_priv *priv = ifp->if_softc;
3090
3091 queue_work(priv->wq, &priv->set_rx_mode_work);
3092 }
3093
3094 static int
mlx5e_ioctl(struct ifnet * ifp,u_long command,caddr_t data)3095 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3096 {
3097 struct mlx5e_priv *priv;
3098 struct ifreq *ifr;
3099 struct ifdownreason *ifdr;
3100 struct ifi2creq i2c;
3101 struct ifrsskey *ifrk;
3102 struct ifrsshash *ifrh;
3103 int error = 0;
3104 int mask = 0;
3105 int size_read = 0;
3106 int module_status;
3107 int module_num;
3108 int max_mtu;
3109 uint8_t read_addr;
3110
3111 priv = ifp->if_softc;
3112
3113 /* check if detaching */
3114 if (priv == NULL || priv->gone != 0)
3115 return (ENXIO);
3116
3117 switch (command) {
3118 case SIOCSIFMTU:
3119 ifr = (struct ifreq *)data;
3120
3121 PRIV_LOCK(priv);
3122 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3123
3124 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3125 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3126 int was_opened;
3127
3128 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3129 if (was_opened)
3130 mlx5e_close_locked(ifp);
3131
3132 /* set new MTU */
3133 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3134
3135 if (was_opened)
3136 mlx5e_open_locked(ifp);
3137 } else {
3138 error = EINVAL;
3139 mlx5_en_err(ifp,
3140 "Invalid MTU value. Min val: %d, Max val: %d\n",
3141 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3142 }
3143 PRIV_UNLOCK(priv);
3144 break;
3145 case SIOCSIFFLAGS:
3146 if ((ifp->if_flags & IFF_UP) &&
3147 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3148 mlx5e_set_rx_mode(ifp);
3149 break;
3150 }
3151 PRIV_LOCK(priv);
3152 if (ifp->if_flags & IFF_UP) {
3153 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3154 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3155 mlx5e_open_locked(ifp);
3156 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3157 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3158 }
3159 } else {
3160 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3161 mlx5_set_port_status(priv->mdev,
3162 MLX5_PORT_DOWN);
3163 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3164 mlx5e_close_locked(ifp);
3165 mlx5e_update_carrier(priv);
3166 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3167 }
3168 }
3169 PRIV_UNLOCK(priv);
3170 break;
3171 case SIOCADDMULTI:
3172 case SIOCDELMULTI:
3173 mlx5e_set_rx_mode(ifp);
3174 break;
3175 case SIOCSIFMEDIA:
3176 case SIOCGIFMEDIA:
3177 case SIOCGIFXMEDIA:
3178 ifr = (struct ifreq *)data;
3179 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3180 break;
3181 case SIOCSIFCAP:
3182 ifr = (struct ifreq *)data;
3183 PRIV_LOCK(priv);
3184 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3185
3186 if (mask & IFCAP_TXCSUM) {
3187 ifp->if_capenable ^= IFCAP_TXCSUM;
3188 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3189
3190 if (IFCAP_TSO4 & ifp->if_capenable &&
3191 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3192 mask &= ~IFCAP_TSO4;
3193 ifp->if_capenable &= ~IFCAP_TSO4;
3194 ifp->if_hwassist &= ~CSUM_IP_TSO;
3195 mlx5_en_err(ifp,
3196 "tso4 disabled due to -txcsum.\n");
3197 }
3198 }
3199 if (mask & IFCAP_TXCSUM_IPV6) {
3200 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3201 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3202
3203 if (IFCAP_TSO6 & ifp->if_capenable &&
3204 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3205 mask &= ~IFCAP_TSO6;
3206 ifp->if_capenable &= ~IFCAP_TSO6;
3207 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3208 mlx5_en_err(ifp,
3209 "tso6 disabled due to -txcsum6.\n");
3210 }
3211 }
3212 if (mask & IFCAP_RXCSUM)
3213 ifp->if_capenable ^= IFCAP_RXCSUM;
3214 if (mask & IFCAP_RXCSUM_IPV6)
3215 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3216 if (mask & IFCAP_TSO4) {
3217 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3218 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3219 mlx5_en_err(ifp, "enable txcsum first.\n");
3220 error = EAGAIN;
3221 goto out;
3222 }
3223 ifp->if_capenable ^= IFCAP_TSO4;
3224 ifp->if_hwassist ^= CSUM_IP_TSO;
3225 }
3226 if (mask & IFCAP_TSO6) {
3227 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3228 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3229 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3230 error = EAGAIN;
3231 goto out;
3232 }
3233 ifp->if_capenable ^= IFCAP_TSO6;
3234 ifp->if_hwassist ^= CSUM_IP6_TSO;
3235 }
3236 if (mask & IFCAP_VLAN_HWTSO)
3237 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3238 if (mask & IFCAP_VLAN_HWFILTER) {
3239 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3240 mlx5e_disable_vlan_filter(priv);
3241 else
3242 mlx5e_enable_vlan_filter(priv);
3243
3244 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3245 }
3246 if (mask & IFCAP_VLAN_HWTAGGING)
3247 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3248 if (mask & IFCAP_WOL_MAGIC)
3249 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3250
3251 VLAN_CAPABILITIES(ifp);
3252 /* turn off LRO means also turn of HW LRO - if it's on */
3253 if (mask & IFCAP_LRO) {
3254 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3255 bool need_restart = false;
3256
3257 ifp->if_capenable ^= IFCAP_LRO;
3258
3259 /* figure out if updating HW LRO is needed */
3260 if (!(ifp->if_capenable & IFCAP_LRO)) {
3261 if (priv->params.hw_lro_en) {
3262 priv->params.hw_lro_en = false;
3263 need_restart = true;
3264 }
3265 } else {
3266 if (priv->params.hw_lro_en == false &&
3267 priv->params_ethtool.hw_lro != 0) {
3268 priv->params.hw_lro_en = true;
3269 need_restart = true;
3270 }
3271 }
3272 if (was_opened && need_restart) {
3273 mlx5e_close_locked(ifp);
3274 mlx5e_open_locked(ifp);
3275 }
3276 }
3277 out:
3278 PRIV_UNLOCK(priv);
3279 break;
3280
3281 case SIOCGI2C:
3282 ifr = (struct ifreq *)data;
3283
3284 /*
3285 * Copy from the user-space address ifr_data to the
3286 * kernel-space address i2c
3287 */
3288 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3289 if (error)
3290 break;
3291
3292 if (i2c.len > sizeof(i2c.data)) {
3293 error = EINVAL;
3294 break;
3295 }
3296
3297 PRIV_LOCK(priv);
3298 /* Get module_num which is required for the query_eeprom */
3299 error = mlx5_query_module_num(priv->mdev, &module_num);
3300 if (error) {
3301 mlx5_en_err(ifp,
3302 "Query module num failed, eeprom reading is not supported\n");
3303 error = EINVAL;
3304 goto err_i2c;
3305 }
3306 /* Check if module is present before doing an access */
3307 module_status = mlx5_query_module_status(priv->mdev, module_num);
3308 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3309 error = EINVAL;
3310 goto err_i2c;
3311 }
3312 /*
3313 * Currently 0XA0 and 0xA2 are the only addresses permitted.
3314 * The internal conversion is as follows:
3315 */
3316 if (i2c.dev_addr == 0xA0)
3317 read_addr = MLX5_I2C_ADDR_LOW;
3318 else if (i2c.dev_addr == 0xA2)
3319 read_addr = MLX5_I2C_ADDR_HIGH;
3320 else {
3321 mlx5_en_err(ifp,
3322 "Query eeprom failed, Invalid Address: %X\n",
3323 i2c.dev_addr);
3324 error = EINVAL;
3325 goto err_i2c;
3326 }
3327 error = mlx5_query_eeprom(priv->mdev,
3328 read_addr, MLX5_EEPROM_LOW_PAGE,
3329 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3330 (uint32_t *)i2c.data, &size_read);
3331 if (error) {
3332 mlx5_en_err(ifp,
3333 "Query eeprom failed, eeprom reading is not supported\n");
3334 error = EINVAL;
3335 goto err_i2c;
3336 }
3337
3338 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3339 error = mlx5_query_eeprom(priv->mdev,
3340 read_addr, MLX5_EEPROM_LOW_PAGE,
3341 (uint32_t)(i2c.offset + size_read),
3342 (uint32_t)(i2c.len - size_read), module_num,
3343 (uint32_t *)(i2c.data + size_read), &size_read);
3344 }
3345 if (error) {
3346 mlx5_en_err(ifp,
3347 "Query eeprom failed, eeprom reading is not supported\n");
3348 error = EINVAL;
3349 goto err_i2c;
3350 }
3351
3352 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3353 err_i2c:
3354 PRIV_UNLOCK(priv);
3355 break;
3356 case SIOCGIFDOWNREASON:
3357 ifdr = (struct ifdownreason *)data;
3358 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3359 PRIV_LOCK(priv);
3360 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL,
3361 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3362 PRIV_UNLOCK(priv);
3363 if (error == 0)
3364 ifdr->ifdr_reason = IFDR_REASON_MSG;
3365 break;
3366
3367 case SIOCGIFRSSKEY:
3368 ifrk = (struct ifrsskey *)data;
3369 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ;
3370 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE;
3371 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE);
3372 mlx5e_get_rss_key(ifrk->ifrk_key);
3373 break;
3374
3375 case SIOCGIFRSSHASH:
3376 ifrh = (struct ifrsshash *)data;
3377 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ;
3378 ifrh->ifrh_types =
3379 RSS_TYPE_IPV4 |
3380 RSS_TYPE_TCP_IPV4 |
3381 RSS_TYPE_UDP_IPV4 |
3382 RSS_TYPE_IPV6 |
3383 RSS_TYPE_TCP_IPV6 |
3384 RSS_TYPE_UDP_IPV6;
3385 break;
3386
3387 default:
3388 error = ether_ioctl(ifp, command, data);
3389 break;
3390 }
3391 return (error);
3392 }
3393
3394 static int
mlx5e_check_required_hca_cap(struct mlx5_core_dev * mdev)3395 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3396 {
3397 /*
3398 * TODO: uncoment once FW really sets all these bits if
3399 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3400 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3401 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3402 * -ENOTSUPP;
3403 */
3404
3405 /* TODO: add more must-to-have features */
3406
3407 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3408 return (-ENODEV);
3409
3410 return (0);
3411 }
3412
3413 static u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev * mdev)3414 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3415 {
3416 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN;
3417 const int max_size = MLX5E_MAX_TX_INLINE;
3418 const int bf_buf_size =
3419 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) -
3420 (sizeof(struct mlx5e_tx_wqe) - 2);
3421
3422 /* verify against driver limits */
3423 if (bf_buf_size > max_size)
3424 return (max_size);
3425 else if (bf_buf_size < min_size)
3426 return (min_size);
3427 else
3428 return (bf_buf_size);
3429 }
3430
3431 static int
mlx5e_build_ifp_priv(struct mlx5_core_dev * mdev,struct mlx5e_priv * priv,int num_comp_vectors)3432 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3433 struct mlx5e_priv *priv,
3434 int num_comp_vectors)
3435 {
3436 int err;
3437
3438 /*
3439 * TODO: Consider link speed for setting "log_sq_size",
3440 * "log_rq_size" and "cq_moderation_xxx":
3441 */
3442 priv->params.log_sq_size =
3443 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3444 priv->params.log_rq_size =
3445 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3446 priv->params.rx_cq_moderation_usec =
3447 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3448 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3449 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3450 priv->params.rx_cq_moderation_mode =
3451 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3452 priv->params.rx_cq_moderation_pkts =
3453 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3454 priv->params.tx_cq_moderation_usec =
3455 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3456 priv->params.tx_cq_moderation_pkts =
3457 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3458 priv->params.min_rx_wqes =
3459 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3460 priv->params.rx_hash_log_tbl_sz =
3461 (order_base_2(num_comp_vectors) >
3462 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3463 order_base_2(num_comp_vectors) :
3464 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3465 priv->params.num_tc = 1;
3466 priv->params.default_vlan_prio = 0;
3467 priv->counter_set_id = -1;
3468 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3469
3470 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3471 if (err)
3472 return (err);
3473
3474 /*
3475 * hw lro is currently defaulted to off. when it won't anymore we
3476 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3477 */
3478 priv->params.hw_lro_en = false;
3479 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3480
3481 /*
3482 * CQE zipping is currently defaulted to off. when it won't
3483 * anymore we will consider the HW capability:
3484 * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3485 */
3486 priv->params.cqe_zipping_en = false;
3487
3488 priv->mdev = mdev;
3489 priv->params.num_channels = num_comp_vectors;
3490 priv->params.channels_rsss = 1;
3491 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3492 priv->queue_mapping_channel_mask =
3493 roundup_pow_of_two(num_comp_vectors) - 1;
3494 priv->num_tc = priv->params.num_tc;
3495 priv->default_vlan_prio = priv->params.default_vlan_prio;
3496
3497 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3498 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3499 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3500
3501 return (0);
3502 }
3503
3504 static int
mlx5e_create_mkey(struct mlx5e_priv * priv,u32 pdn,struct mlx5_core_mr * mkey)3505 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3506 struct mlx5_core_mr *mkey)
3507 {
3508 struct ifnet *ifp = priv->ifp;
3509 struct mlx5_core_dev *mdev = priv->mdev;
3510 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3511 void *mkc;
3512 u32 *in;
3513 int err;
3514
3515 in = mlx5_vzalloc(inlen);
3516 if (in == NULL) {
3517 mlx5_en_err(ifp, "failed to allocate inbox\n");
3518 return (-ENOMEM);
3519 }
3520
3521 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3522 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3523 MLX5_SET(mkc, mkc, lw, 1);
3524 MLX5_SET(mkc, mkc, lr, 1);
3525
3526 MLX5_SET(mkc, mkc, pd, pdn);
3527 MLX5_SET(mkc, mkc, length64, 1);
3528 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3529
3530 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3531 if (err)
3532 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3533 err);
3534
3535 kvfree(in);
3536 return (err);
3537 }
3538
3539 static const char *mlx5e_vport_stats_desc[] = {
3540 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3541 };
3542
3543 static const char *mlx5e_pport_stats_desc[] = {
3544 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3545 };
3546
3547 static void
mlx5e_priv_static_init(struct mlx5e_priv * priv,const uint32_t channels)3548 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3549 {
3550 uint32_t x;
3551
3552 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3553 sx_init(&priv->state_lock, "mlx5state");
3554 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3555 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3556 for (x = 0; x != channels; x++)
3557 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3558 }
3559
3560 static void
mlx5e_priv_static_destroy(struct mlx5e_priv * priv,const uint32_t channels)3561 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3562 {
3563 uint32_t x;
3564
3565 for (x = 0; x != channels; x++)
3566 mlx5e_chan_static_destroy(&priv->channel[x]);
3567 callout_drain(&priv->watchdog);
3568 mtx_destroy(&priv->async_events_mtx);
3569 sx_destroy(&priv->state_lock);
3570 }
3571
3572 static int
sysctl_firmware(SYSCTL_HANDLER_ARGS)3573 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3574 {
3575 /*
3576 * %d.%d%.d the string format.
3577 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3578 * We need at most 5 chars to store that.
3579 * It also has: two "." and NULL at the end, which means we need 18
3580 * (5*3 + 3) chars at most.
3581 */
3582 char fw[18];
3583 struct mlx5e_priv *priv = arg1;
3584 int error;
3585
3586 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3587 fw_rev_sub(priv->mdev));
3588 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3589 return (error);
3590 }
3591
3592 static void
mlx5e_disable_tx_dma(struct mlx5e_channel * ch)3593 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3594 {
3595 int i;
3596
3597 for (i = 0; i < ch->priv->num_tc; i++)
3598 mlx5e_drain_sq(&ch->sq[i]);
3599 }
3600
3601 static void
mlx5e_reset_sq_doorbell_record(struct mlx5e_sq * sq)3602 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3603 {
3604
3605 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3606 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3607 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3608 sq->doorbell.d64 = 0;
3609 }
3610
3611 void
mlx5e_resume_sq(struct mlx5e_sq * sq)3612 mlx5e_resume_sq(struct mlx5e_sq *sq)
3613 {
3614 int err;
3615
3616 /* check if already enabled */
3617 if (READ_ONCE(sq->running) != 0)
3618 return;
3619
3620 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3621 MLX5_SQC_STATE_RST);
3622 if (err != 0) {
3623 mlx5_en_err(sq->ifp,
3624 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3625 }
3626
3627 sq->cc = 0;
3628 sq->pc = 0;
3629
3630 /* reset doorbell prior to moving from RST to RDY */
3631 mlx5e_reset_sq_doorbell_record(sq);
3632
3633 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3634 MLX5_SQC_STATE_RDY);
3635 if (err != 0) {
3636 mlx5_en_err(sq->ifp,
3637 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3638 }
3639
3640 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3641 WRITE_ONCE(sq->running, 1);
3642 }
3643
3644 static void
mlx5e_enable_tx_dma(struct mlx5e_channel * ch)3645 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3646 {
3647 int i;
3648
3649 for (i = 0; i < ch->priv->num_tc; i++)
3650 mlx5e_resume_sq(&ch->sq[i]);
3651 }
3652
3653 static void
mlx5e_disable_rx_dma(struct mlx5e_channel * ch)3654 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3655 {
3656 struct mlx5e_rq *rq = &ch->rq;
3657 int err;
3658
3659 mtx_lock(&rq->mtx);
3660 rq->enabled = 0;
3661 callout_stop(&rq->watchdog);
3662 mtx_unlock(&rq->mtx);
3663
3664 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3665 if (err != 0) {
3666 mlx5_en_err(rq->ifp,
3667 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3668 }
3669
3670 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3671 msleep(1);
3672 rq->cq.mcq.comp(&rq->cq.mcq);
3673 }
3674
3675 /*
3676 * Transitioning into RST state will allow the FW to track less ERR state queues,
3677 * thus reducing the recv queue flushing time
3678 */
3679 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3680 if (err != 0) {
3681 mlx5_en_err(rq->ifp,
3682 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3683 }
3684 }
3685
3686 static void
mlx5e_enable_rx_dma(struct mlx5e_channel * ch)3687 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3688 {
3689 struct mlx5e_rq *rq = &ch->rq;
3690 int err;
3691
3692 rq->wq.wqe_ctr = 0;
3693 mlx5_wq_ll_update_db_record(&rq->wq);
3694 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3695 if (err != 0) {
3696 mlx5_en_err(rq->ifp,
3697 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3698 }
3699
3700 rq->enabled = 1;
3701
3702 rq->cq.mcq.comp(&rq->cq.mcq);
3703 }
3704
3705 void
mlx5e_modify_tx_dma(struct mlx5e_priv * priv,uint8_t value)3706 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3707 {
3708 int i;
3709
3710 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3711 return;
3712
3713 for (i = 0; i < priv->params.num_channels; i++) {
3714 if (value)
3715 mlx5e_disable_tx_dma(&priv->channel[i]);
3716 else
3717 mlx5e_enable_tx_dma(&priv->channel[i]);
3718 }
3719 }
3720
3721 void
mlx5e_modify_rx_dma(struct mlx5e_priv * priv,uint8_t value)3722 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3723 {
3724 int i;
3725
3726 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3727 return;
3728
3729 for (i = 0; i < priv->params.num_channels; i++) {
3730 if (value)
3731 mlx5e_disable_rx_dma(&priv->channel[i]);
3732 else
3733 mlx5e_enable_rx_dma(&priv->channel[i]);
3734 }
3735 }
3736
3737 static void
mlx5e_add_hw_stats(struct mlx5e_priv * priv)3738 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3739 {
3740 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3741 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3742 sysctl_firmware, "A", "HCA firmware version");
3743
3744 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3745 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3746 "Board ID");
3747 }
3748
3749 static int
mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)3750 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3751 {
3752 struct mlx5e_priv *priv = arg1;
3753 uint8_t temp[MLX5E_MAX_PRIORITY];
3754 uint32_t tx_pfc;
3755 int err;
3756 int i;
3757
3758 PRIV_LOCK(priv);
3759
3760 tx_pfc = priv->params.tx_priority_flow_control;
3761
3762 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3763 temp[i] = (tx_pfc >> i) & 1;
3764
3765 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3766 if (err || !req->newptr)
3767 goto done;
3768 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3769 if (err)
3770 goto done;
3771
3772 priv->params.tx_priority_flow_control = 0;
3773
3774 /* range check input value */
3775 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3776 if (temp[i] > 1) {
3777 err = ERANGE;
3778 goto done;
3779 }
3780 priv->params.tx_priority_flow_control |= (temp[i] << i);
3781 }
3782
3783 /* check if update is required */
3784 if (tx_pfc != priv->params.tx_priority_flow_control)
3785 err = -mlx5e_set_port_pfc(priv);
3786 done:
3787 if (err != 0)
3788 priv->params.tx_priority_flow_control= tx_pfc;
3789 PRIV_UNLOCK(priv);
3790
3791 return (err);
3792 }
3793
3794 static int
mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)3795 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3796 {
3797 struct mlx5e_priv *priv = arg1;
3798 uint8_t temp[MLX5E_MAX_PRIORITY];
3799 uint32_t rx_pfc;
3800 int err;
3801 int i;
3802
3803 PRIV_LOCK(priv);
3804
3805 rx_pfc = priv->params.rx_priority_flow_control;
3806
3807 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3808 temp[i] = (rx_pfc >> i) & 1;
3809
3810 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3811 if (err || !req->newptr)
3812 goto done;
3813 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3814 if (err)
3815 goto done;
3816
3817 priv->params.rx_priority_flow_control = 0;
3818
3819 /* range check input value */
3820 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3821 if (temp[i] > 1) {
3822 err = ERANGE;
3823 goto done;
3824 }
3825 priv->params.rx_priority_flow_control |= (temp[i] << i);
3826 }
3827
3828 /* check if update is required */
3829 if (rx_pfc != priv->params.rx_priority_flow_control) {
3830 err = -mlx5e_set_port_pfc(priv);
3831 if (err == 0 && priv->sw_is_port_buf_owner)
3832 err = mlx5e_update_buf_lossy(priv);
3833 }
3834 done:
3835 if (err != 0)
3836 priv->params.rx_priority_flow_control= rx_pfc;
3837 PRIV_UNLOCK(priv);
3838
3839 return (err);
3840 }
3841
3842 static void
mlx5e_setup_pauseframes(struct mlx5e_priv * priv)3843 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3844 {
3845 #if (__FreeBSD_version < 1100000)
3846 char path[96];
3847 #endif
3848 int error;
3849
3850 /* enable pauseframes by default */
3851 priv->params.tx_pauseframe_control = 1;
3852 priv->params.rx_pauseframe_control = 1;
3853
3854 /* disable ports flow control, PFC, by default */
3855 priv->params.tx_priority_flow_control = 0;
3856 priv->params.rx_priority_flow_control = 0;
3857
3858 #if (__FreeBSD_version < 1100000)
3859 /* compute path for sysctl */
3860 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3861 device_get_unit(priv->mdev->pdev->dev.bsddev));
3862
3863 /* try to fetch tunable, if any */
3864 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3865
3866 /* compute path for sysctl */
3867 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3868 device_get_unit(priv->mdev->pdev->dev.bsddev));
3869
3870 /* try to fetch tunable, if any */
3871 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3872 #endif
3873
3874 /* register pauseframe SYSCTLs */
3875 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3876 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3877 &priv->params.tx_pauseframe_control, 0,
3878 "Set to enable TX pause frames. Clear to disable.");
3879
3880 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3881 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3882 &priv->params.rx_pauseframe_control, 0,
3883 "Set to enable RX pause frames. Clear to disable.");
3884
3885 /* register priority flow control, PFC, SYSCTLs */
3886 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3887 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3888 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3889 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3890
3891 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3892 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3893 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3894 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3895
3896 PRIV_LOCK(priv);
3897
3898 /* range check */
3899 priv->params.tx_pauseframe_control =
3900 priv->params.tx_pauseframe_control ? 1 : 0;
3901 priv->params.rx_pauseframe_control =
3902 priv->params.rx_pauseframe_control ? 1 : 0;
3903
3904 /* update firmware */
3905 error = mlx5e_set_port_pause_and_pfc(priv);
3906 if (error == -EINVAL) {
3907 mlx5_en_err(priv->ifp,
3908 "Global pauseframes must be disabled before enabling PFC.\n");
3909 priv->params.rx_priority_flow_control = 0;
3910 priv->params.tx_priority_flow_control = 0;
3911
3912 /* update firmware */
3913 (void) mlx5e_set_port_pause_and_pfc(priv);
3914 }
3915 PRIV_UNLOCK(priv);
3916 }
3917
3918 static void
mlx5e_ifm_add(struct mlx5e_priv * priv,int type)3919 mlx5e_ifm_add(struct mlx5e_priv *priv, int type)
3920 {
3921 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL);
3922 ifmedia_add(&priv->media, type | IFM_ETHER |
3923 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3924 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL);
3925 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL);
3926 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL);
3927 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
3928 IFM_ETH_RXPAUSE, 0, NULL);
3929 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
3930 IFM_ETH_TXPAUSE, 0, NULL);
3931 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
3932 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3933 }
3934
3935 static void *
mlx5e_create_ifp(struct mlx5_core_dev * mdev)3936 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3937 {
3938 struct ifnet *ifp;
3939 struct mlx5e_priv *priv;
3940 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3941 u8 connector_type;
3942 struct sysctl_oid_list *child;
3943 int ncv = mdev->priv.eq_table.num_comp_vectors;
3944 char unit[16];
3945 int err;
3946 int i,j;
3947 u32 eth_proto_cap;
3948 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
3949 bool ext = 0;
3950 u32 speeds_num;
3951 struct media media_entry = {};
3952
3953 if (mlx5e_check_required_hca_cap(mdev)) {
3954 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3955 return (NULL);
3956 }
3957 /*
3958 * Try to allocate the priv and make room for worst-case
3959 * number of channel structures:
3960 */
3961 priv = malloc(sizeof(*priv) +
3962 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3963 M_MLX5EN, M_WAITOK | M_ZERO);
3964
3965 ifp = priv->ifp = if_alloc(IFT_ETHER);
3966 if (ifp == NULL) {
3967 mlx5_core_err(mdev, "if_alloc() failed\n");
3968 goto err_free_priv;
3969 }
3970 /* setup all static fields */
3971 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
3972
3973 ifp->if_softc = priv;
3974 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3975 ifp->if_mtu = ETHERMTU;
3976 ifp->if_init = mlx5e_open;
3977 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3978 ifp->if_ioctl = mlx5e_ioctl;
3979 ifp->if_transmit = mlx5e_xmit;
3980 ifp->if_qflush = if_qflush;
3981 #if (__FreeBSD_version >= 1100000)
3982 ifp->if_get_counter = mlx5e_get_counter;
3983 #endif
3984 ifp->if_snd.ifq_maxlen = ifqmaxlen;
3985 /*
3986 * Set driver features
3987 */
3988 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3989 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3990 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3991 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3992 ifp->if_capabilities |= IFCAP_LRO;
3993 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3994 ifp->if_capabilities |= IFCAP_HWSTATS;
3995
3996 /* set TSO limits so that we don't have to drop TX packets */
3997 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3998 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3999 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4000
4001 ifp->if_capenable = ifp->if_capabilities;
4002 ifp->if_hwassist = 0;
4003 if (ifp->if_capenable & IFCAP_TSO)
4004 ifp->if_hwassist |= CSUM_TSO;
4005 if (ifp->if_capenable & IFCAP_TXCSUM)
4006 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4007 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4008 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4009
4010 /* ifnet sysctl tree */
4011 sysctl_ctx_init(&priv->sysctl_ctx);
4012 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4013 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
4014 if (priv->sysctl_ifnet == NULL) {
4015 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4016 goto err_free_sysctl;
4017 }
4018 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4019 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4020 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
4021 if (priv->sysctl_ifnet == NULL) {
4022 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4023 goto err_free_sysctl;
4024 }
4025
4026 /* HW sysctl tree */
4027 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4028 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4029 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
4030 if (priv->sysctl_hw == NULL) {
4031 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4032 goto err_free_sysctl;
4033 }
4034
4035 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4036 if (err) {
4037 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4038 goto err_free_sysctl;
4039 }
4040
4041 /* reuse mlx5core's watchdog workqueue */
4042 priv->wq = mdev->priv.health.wq_watchdog;
4043
4044 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4045 if (err) {
4046 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4047 goto err_free_wq;
4048 }
4049 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4050 if (err) {
4051 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4052 goto err_unmap_free_uar;
4053 }
4054 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4055 if (err) {
4056 mlx5_en_err(ifp,
4057 "mlx5_alloc_transport_domain failed, %d\n", err);
4058 goto err_dealloc_pd;
4059 }
4060 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4061 if (err) {
4062 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4063 goto err_dealloc_transport_domain;
4064 }
4065 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4066
4067 /* check if we should generate a random MAC address */
4068 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4069 is_zero_ether_addr(dev_addr)) {
4070 random_ether_addr(dev_addr);
4071 mlx5_en_err(ifp, "Assigned random MAC address\n");
4072 }
4073
4074 /* set default MTU */
4075 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4076
4077 /* Set default media status */
4078 priv->media_status_last = IFM_AVALID;
4079 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX;
4080
4081 /* setup default pauseframes configuration */
4082 mlx5e_setup_pauseframes(priv);
4083
4084 /* Setup supported medias */
4085 //TODO: If we failed to query ptys is it ok to proceed??
4086 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4087 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4088 ptys_extended_ethernet);
4089 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4090 eth_proto_capability);
4091 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4092 connector_type = MLX5_GET(ptys_reg, out,
4093 connector_type);
4094 } else {
4095 eth_proto_cap = 0;
4096 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4097 }
4098
4099 ifmedia_init(&priv->media, IFM_IMASK,
4100 mlx5e_media_change, mlx5e_media_status);
4101
4102 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4103 for (i = 0; i != speeds_num; i++) {
4104 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4105 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4106 mlx5e_mode_table[i][j];
4107 if (media_entry.baudrate == 0)
4108 continue;
4109 if (MLX5E_PROT_MASK(i) & eth_proto_cap)
4110 mlx5e_ifm_add(priv, media_entry.subtype);
4111 }
4112 }
4113
4114 mlx5e_ifm_add(priv, IFM_AUTO);
4115
4116 /* Set autoselect by default */
4117 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4118 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4119 ether_ifattach(ifp, dev_addr);
4120
4121 /* Register for VLAN events */
4122 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4123 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4124 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4125 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4126
4127 /* Link is down by default */
4128 if_link_state_change(ifp, LINK_STATE_DOWN);
4129
4130 mlx5e_enable_async_events(priv);
4131
4132 mlx5e_add_hw_stats(priv);
4133
4134 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4135 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4136 priv->stats.vport.arg);
4137
4138 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4139 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4140 priv->stats.pport.arg);
4141
4142 mlx5e_create_ethtool(priv);
4143
4144 mtx_lock(&priv->async_events_mtx);
4145 mlx5e_update_stats(priv);
4146 mtx_unlock(&priv->async_events_mtx);
4147
4148 return (priv);
4149
4150 err_dealloc_transport_domain:
4151 mlx5_dealloc_transport_domain(mdev, priv->tdn);
4152
4153 err_dealloc_pd:
4154 mlx5_core_dealloc_pd(mdev, priv->pdn);
4155
4156 err_unmap_free_uar:
4157 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4158
4159 err_free_wq:
4160 flush_workqueue(priv->wq);
4161
4162 err_free_sysctl:
4163 sysctl_ctx_free(&priv->sysctl_ctx);
4164 if (priv->sysctl_debug)
4165 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4166 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4167 if_free(ifp);
4168
4169 err_free_priv:
4170 free(priv, M_MLX5EN);
4171 return (NULL);
4172 }
4173
4174 static void
mlx5e_destroy_ifp(struct mlx5_core_dev * mdev,void * vpriv)4175 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4176 {
4177 struct mlx5e_priv *priv = vpriv;
4178 struct ifnet *ifp = priv->ifp;
4179
4180 /* don't allow more IOCTLs */
4181 priv->gone = 1;
4182
4183 /* XXX wait a bit to allow IOCTL handlers to complete */
4184 pause("W", hz);
4185
4186 /* stop watchdog timer */
4187 callout_drain(&priv->watchdog);
4188
4189 if (priv->vlan_attach != NULL)
4190 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4191 if (priv->vlan_detach != NULL)
4192 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4193
4194 /* make sure device gets closed */
4195 PRIV_LOCK(priv);
4196 mlx5e_close_locked(ifp);
4197 PRIV_UNLOCK(priv);
4198
4199 /* unregister device */
4200 ifmedia_removeall(&priv->media);
4201 ether_ifdetach(ifp);
4202
4203 /* destroy all remaining sysctl nodes */
4204 sysctl_ctx_free(&priv->stats.vport.ctx);
4205 sysctl_ctx_free(&priv->stats.pport.ctx);
4206 if (priv->sysctl_debug)
4207 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4208 sysctl_ctx_free(&priv->sysctl_ctx);
4209
4210 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4211 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4212 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4213 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4214 mlx5e_disable_async_events(priv);
4215 flush_workqueue(priv->wq);
4216 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4217 if_free(ifp);
4218 free(priv, M_MLX5EN);
4219 }
4220
4221 static void *
mlx5e_get_ifp(void * vpriv)4222 mlx5e_get_ifp(void *vpriv)
4223 {
4224 struct mlx5e_priv *priv = vpriv;
4225
4226 return (priv->ifp);
4227 }
4228
4229 static struct mlx5_interface mlx5e_interface = {
4230 .add = mlx5e_create_ifp,
4231 .remove = mlx5e_destroy_ifp,
4232 .event = mlx5e_async_event,
4233 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4234 .get_dev = mlx5e_get_ifp,
4235 };
4236
4237 void
mlx5e_init(void)4238 mlx5e_init(void)
4239 {
4240 mlx5_register_interface(&mlx5e_interface);
4241 }
4242
4243 void
mlx5e_cleanup(void)4244 mlx5e_cleanup(void)
4245 {
4246 mlx5_unregister_interface(&mlx5e_interface);
4247 }
4248
4249 static void
mlx5e_show_version(void __unused * arg)4250 mlx5e_show_version(void __unused *arg)
4251 {
4252
4253 printf("%s", mlx5e_version);
4254 }
4255 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4256
4257 module_init_order(mlx5e_init, SI_ORDER_SIXTH);
4258 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH);
4259
4260 #if (__FreeBSD_version >= 1100000)
4261 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4262 #endif
4263 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4264 MODULE_VERSION(mlx5en, 1);
4265