1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010-2011 Aleksandr Rybalko <ray@ddteam.net> 5 * Copyright (c) 2009-2010 Alexander Egorenkov <egorenar@gmail.com> 6 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _IF_RTVAR_H_ 32 #define _IF_RTVAR_H_ 33 34 #include <sys/param.h> 35 #include <sys/sysctl.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/taskqueue.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 #include <sys/rman.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include "opt_if_rt.h" 60 61 #define RT_SOFTC_LOCK(sc) mtx_lock(&(sc)->lock) 62 #define RT_SOFTC_UNLOCK(sc) mtx_unlock(&(sc)->lock) 63 #define RT_SOFTC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED) 64 65 #define RT_SOFTC_TX_RING_LOCK(ring) mtx_lock(&(ring)->lock) 66 #define RT_SOFTC_TX_RING_UNLOCK(ring) mtx_unlock(&(ring)->lock) 67 #define RT_SOFTC_TX_RING_ASSERT_LOCKED(ring) \ 68 mtx_assert(&(ring)->lock, MA_OWNED) 69 70 #define RT_SOFTC_TX_RING_COUNT 4 71 #define RT_SOFTC_RX_RING_COUNT 4 72 73 #ifndef IF_RT_RING_DATA_COUNT 74 #define IF_RT_RING_DATA_COUNT 128 75 #endif 76 77 #define RT_SOFTC_RX_RING_DATA_COUNT IF_RT_RING_DATA_COUNT 78 79 #define RT_SOFTC_MAX_SCATTER 10 80 81 #define RT_SOFTC_TX_RING_DATA_COUNT (IF_RT_RING_DATA_COUNT/4) 82 #define RT_SOFTC_TX_RING_DESC_COUNT \ 83 (RT_SOFTC_TX_RING_DATA_COUNT * RT_SOFTC_MAX_SCATTER) 84 85 #define RT_TXDESC_SDL1_BURST (1 << 15) 86 #define RT_TXDESC_SDL1_LASTSEG (1 << 14) 87 #define RT_TXDESC_SDL0_DDONE (1 << 15) 88 #define RT_TXDESC_SDL0_LASTSEG (1 << 14) 89 struct rt_txdesc 90 { 91 uint32_t sdp0; 92 uint16_t sdl1; 93 uint16_t sdl0; 94 uint32_t sdp1; 95 uint8_t vid; 96 #define TXDSCR_INS_VLAN_TAG 0x80 97 #define TXDSCR_VLAN_PRIO_MASK 0x70 98 #define TXDSCR_VLAN_IDX_MASK 0x0f 99 uint8_t pppoe; 100 #define TXDSCR_USR_DEF_FLD 0x80 101 #define TXDSCR_INS_PPPOE_HDR 0x10 102 #define TXDSCR_PPPOE_SID_MASK 0x0f 103 uint8_t qn; 104 #define TXDSCR_QUEUE_MASK 0x07 105 uint8_t dst; 106 #define TXDSCR_IP_CSUM_GEN 0x80 107 #define TXDSCR_UDP_CSUM_GEN 0x40 108 #define TXDSCR_TCP_CSUM_GEN 0x20 109 #define TXDSCR_DST_PORT_MASK 0x07 110 #define TXDSCR_DST_PORT_CPU 0x00 111 #define TXDSCR_DST_PORT_GDMA1 0x01 112 #define TXDSCR_DST_PORT_GDMA2 0x02 113 #define TXDSCR_DST_PORT_PPE 0x06 114 #define TXDSCR_DST_PORT_DISC 0x07 115 } __packed; 116 117 #define RT_RXDESC_SDL0_DDONE (1 << 15) 118 119 #define RT305X_RXD_SRC_L4_CSUM_FAIL (1 << 28) 120 #define RT305X_RXD_SRC_IP_CSUM_FAIL (1 << 29) 121 #define MT7620_RXD_SRC_L4_CSUM_FAIL (1 << 22) 122 #define MT7620_RXD_SRC_IP_CSUM_FAIL (1 << 25) 123 #define MT7621_RXD_SRC_L4_CSUM_FAIL (1 << 23) 124 #define MT7621_RXD_SRC_IP_CSUM_FAIL (1 << 26) 125 126 struct rt_rxdesc 127 { 128 uint32_t sdp0; 129 uint16_t sdl1; 130 uint16_t sdl0; 131 uint32_t sdp1; 132 #if 0 133 uint16_t foe; 134 #define RXDSXR_FOE_ENTRY_VALID 0x40 135 #define RXDSXR_FOE_ENTRY_MASK 0x3f 136 uint8_t ai; 137 #define RXDSXR_AI_COU_REASON 0xff 138 #define RXDSXR_AI_PARSER_RSLT_MASK 0xff 139 uint8_t src; 140 #define RXDSXR_SRC_IPFVLD 0x80 141 #define RXDSXR_SRC_L4FVLD 0x40 142 #define RXDSXR_SRC_IP_CSUM_FAIL 0x20 143 #define RXDSXR_SRC_L4_CSUM_FAIL 0x10 144 #define RXDSXR_SRC_AIS 0x08 145 #define RXDSXR_SRC_PORT_MASK 0x07 146 #endif 147 uint32_t word3; 148 } __packed; 149 150 struct rt_softc_rx_data 151 { 152 bus_dmamap_t dma_map; 153 struct mbuf *m; 154 }; 155 156 struct rt_softc_rx_ring 157 { 158 bus_dma_tag_t desc_dma_tag; 159 bus_dmamap_t desc_dma_map; 160 bus_addr_t desc_phys_addr; 161 struct rt_rxdesc *desc; 162 bus_dma_tag_t data_dma_tag; 163 bus_dmamap_t spare_dma_map; 164 struct rt_softc_rx_data data[RT_SOFTC_RX_RING_DATA_COUNT]; 165 int cur; 166 int qid; 167 }; 168 169 struct rt_softc_tx_data 170 { 171 bus_dmamap_t dma_map; 172 struct mbuf *m; 173 }; 174 175 struct rt_softc_tx_ring 176 { 177 struct mtx lock; 178 bus_dma_tag_t desc_dma_tag; 179 bus_dmamap_t desc_dma_map; 180 bus_addr_t desc_phys_addr; 181 struct rt_txdesc *desc; 182 int desc_queued; 183 int desc_cur; 184 int desc_next; 185 bus_dma_tag_t seg0_dma_tag; 186 bus_dmamap_t seg0_dma_map; 187 bus_addr_t seg0_phys_addr; 188 uint8_t *seg0; 189 bus_dma_tag_t data_dma_tag; 190 struct rt_softc_tx_data data[RT_SOFTC_TX_RING_DATA_COUNT]; 191 int data_queued; 192 int data_cur; 193 int data_next; 194 int qid; 195 }; 196 197 struct rt_softc 198 { 199 device_t dev; 200 struct mtx lock; 201 uint32_t flags; 202 203 int mem_rid; 204 struct resource *mem; 205 int irq_rid; 206 struct resource *irq; 207 void *irqh; 208 209 bus_space_tag_t bst; 210 bus_space_handle_t bsh; 211 212 struct ifnet *ifp; 213 int if_flags; 214 struct ifmedia rt_ifmedia; 215 216 uint32_t mac_rev; 217 uint8_t mac_addr[ETHER_ADDR_LEN]; 218 device_t rt_miibus; 219 220 uint32_t intr_enable_mask; 221 uint32_t intr_disable_mask; 222 uint32_t intr_pending_mask; 223 224 struct task rx_done_task; 225 int rx_process_limit; 226 struct task tx_done_task; 227 struct task periodic_task; 228 struct callout periodic_ch; 229 unsigned long periodic_round; 230 struct taskqueue *taskqueue; 231 232 struct rt_softc_rx_ring rx_ring[RT_SOFTC_RX_RING_COUNT]; 233 struct rt_softc_tx_ring tx_ring[RT_SOFTC_TX_RING_COUNT]; 234 int tx_ring_mgtqid; 235 236 struct callout tx_watchdog_ch; 237 int tx_timer; 238 239 /* statistic counters */ 240 unsigned long interrupts; 241 unsigned long tx_coherent_interrupts; 242 unsigned long rx_coherent_interrupts; 243 unsigned long rx_interrupts[RT_SOFTC_RX_RING_COUNT]; 244 unsigned long rx_delay_interrupts; 245 unsigned long tx_interrupts[RT_SOFTC_TX_RING_COUNT]; 246 unsigned long tx_delay_interrupts; 247 unsigned long tx_data_queue_full[RT_SOFTC_TX_RING_COUNT]; 248 unsigned long tx_watchdog_timeouts; 249 unsigned long tx_defrag_packets; 250 unsigned long no_tx_desc_avail; 251 unsigned long rx_mbuf_alloc_errors; 252 unsigned long rx_mbuf_dmamap_errors; 253 unsigned long tx_queue_not_empty[2]; 254 255 unsigned long rx_bytes; 256 unsigned long rx_packets; 257 unsigned long rx_crc_err; 258 unsigned long rx_phy_err; 259 unsigned long rx_dup_packets; 260 unsigned long rx_fifo_overflows; 261 unsigned long rx_short_err; 262 unsigned long rx_long_err; 263 unsigned long tx_bytes; 264 unsigned long tx_packets; 265 unsigned long tx_skip; 266 unsigned long tx_collision; 267 268 int phy_addr; 269 270 #ifdef IF_RT_DEBUG 271 int debug; 272 #endif 273 274 uint32_t rt_chipid; 275 /* chip specific registers config */ 276 int rx_ring_count; 277 uint32_t csum_fail_l4; 278 uint32_t csum_fail_ip; 279 uint32_t int_rx_done_mask; 280 uint32_t int_tx_done_mask; 281 uint32_t delay_int_cfg; 282 uint32_t fe_int_status; 283 uint32_t fe_int_enable; 284 uint32_t pdma_glo_cfg; 285 uint32_t pdma_rst_idx; 286 uint32_t gdma1_base; 287 uint32_t tx_base_ptr[RT_SOFTC_TX_RING_COUNT]; 288 uint32_t tx_max_cnt[RT_SOFTC_TX_RING_COUNT]; 289 uint32_t tx_ctx_idx[RT_SOFTC_TX_RING_COUNT]; 290 uint32_t tx_dtx_idx[RT_SOFTC_TX_RING_COUNT]; 291 uint32_t rx_base_ptr[RT_SOFTC_RX_RING_COUNT]; 292 uint32_t rx_max_cnt[RT_SOFTC_RX_RING_COUNT]; 293 uint32_t rx_calc_idx[RT_SOFTC_RX_RING_COUNT]; 294 uint32_t rx_drx_idx[RT_SOFTC_RX_RING_COUNT]; 295 }; 296 297 #ifdef IF_RT_DEBUG 298 enum 299 { 300 RT_DEBUG_RX = 0x00000001, 301 RT_DEBUG_TX = 0x00000002, 302 RT_DEBUG_INTR = 0x00000004, 303 RT_DEBUG_STATE = 0x00000008, 304 RT_DEBUG_STATS = 0x00000010, 305 RT_DEBUG_PERIODIC = 0x00000020, 306 RT_DEBUG_WATCHDOG = 0x00000040, 307 RT_DEBUG_ANY = 0xffffffff 308 }; 309 310 #define RT_DPRINTF(sc, m, fmt, ...) \ 311 do { if ((sc)->debug & (m)) \ 312 device_printf(sc->dev, fmt, ## __VA_ARGS__); } while (0) 313 #else 314 #define RT_DPRINTF(sc, m, fmt, ...) 315 #endif /* #ifdef IF_RT_DEBUG */ 316 317 #endif /* #ifndef _IF_RTVAR_H_ */ 318